AD9222ABCPZ-65

FEATURES FUNCTIONAL BLOCK DIAGRAM 8 ADCs integrated into 1 package 114 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 80 dBc Excellent linearity: DNL = ±0.3 LSB (typical), INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar IEEE 1596.3) Data and frame clock outputs 325 MHz full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode PDWN AVDD DRVDD AD9222 DRGND 12 VIN + A VIN – A ADC VIN + B VIN – B ADC VIN + C VIN – C ADC VIN + D VIN – D ADC VIN + E VIN – E ADC VIN + F VIN – F ADC VIN + G VIN – G ADC VIN + H VIN – H ADC SERIAL LVDS D+A D–A SERIAL LVDS D+B D–B SERIAL LVDS D+C D–C SERIAL LVDS D+D D–D SERIAL LVDS D+E D–E SERIAL LVDS D+F D–F SERIAL LVDS D+G D–G SERIAL LVDS D+H D–H 12 12 12 12 12 12 12 VREF SENSE FCO + 0.5V APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment GENERAL DESCRIPTION The AD9222 is an octal, 12-bit, 40/50/65 MSPS analog-todigital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. REFT REFB REF SELECT RBIAS SERIAL PORT INTERFACE AGND CSB SDIO/ ODM SCLK/ DTP DATA RATE MULTIPLIER CLK+ CLK– FCO – DCO + DCO – 05967-001 Data Sheet Octal, 12-Bit, 40/50/65 MSPS Serial LVDS 1.8 V A/D Converter AD9222 Figure 1. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI). The AD9222 is available in an RoHS compliant, 64-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Small Footprint. Eight ADCs are contained in a small, space-saving package. Low power of 114 mW/channel at 65 MSPS. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9212 (10-bit) and AD9252 (14-bit). Rev. F Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved. AD9222 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 21 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 24 General Description ......................................................................... 1 Serial Port Interface (SPI) .............................................................. 33 Functional Block Diagram .............................................................. 1 Hardware Interface ..................................................................... 34 Product Highlights ........................................................................... 1 Memory Map .................................................................................. 36 Revision History ............................................................................... 2 Reading the Memory Map Table .............................................. 36 Specifications..................................................................................... 3 Reserved Locations .................................................................... 36 AC Specifications.......................................................................... 4 Default Values ............................................................................. 36 Digital Specifications ................................................................... 5 Logic Levels ................................................................................. 36 Switching Specifications .............................................................. 6 Evaluation Board ............................................................................ 40 Timing Diagrams .............................................................................. 7 Power Supplies ............................................................................ 40 Absolute Maximum Ratings ............................................................ 9 Input Signals................................................................................ 40 Thermal Impedance ..................................................................... 9 Output Signals ............................................................................ 40 ESD Caution .................................................................................. 9 Default Operation and Jumper Selection Settings ................. 41 Pin Configuration and Function Descriptions ........................... 10 Alternative Analog Input Drive Configuration...................... 42 Equivalent Circuits ......................................................................... 12 Outline Dimensions ....................................................................... 59 Typical Performance Characteristics ........................................... 14 Ordering Guide .......................................................................... 59 Theory of Operation ...................................................................... 21 REVISION HISTORY 12/11—Rev E to Rev. F Changes to Figure 86 ...................................................................... 41 Changes to Ordering Guide .......................................................... 59 11/11—Rev. D to Rev. E Changes to Output Signals Section .............................................. 41 Changes to Figure 86 ...................................................................... 41 Changes to Ordering Guide .......................................................... 60 4/10—Rev. C to Rev. D Changes to Address 16 in Table 16............................................... 38 Updated Outline Dimensions ....................................................... 59 Changes to Ordering Guide .......................................................... 59 1/10—Rev. B to Rev. C Updated Outline Dimensions ....................................................... 59 Changes to Ordering Guide .......................................................... 60 7/09—Rev. A to Rev. B Changes to Figure 5 ........................................................................ 10 Changes to Figure 61 and Figure 62............................................. 23 Changes to Figure 79 and Figure 80............................................. 31 Updated Outline Dimensions ....................................................... 59 Changes to Ordering Guide .......................................................... 59 8/07—Rev. 0 to Rev. A Added 65 MSPS Models .................................................... Universal Changes to Features.......................................................................... 1 Changes to Product Highlights....................................................... 1 Changes to Figure 2 to Figure 4 .......................................................7 Added Figure 21 to Figure 24, Figure 27, Figure 28, Figure 30, Figure 32, Figure 37, Figure 38, Figure 40, Figure 42, Figure 44, Figure 46, Figure 48, and Figure 51.............................................. 15 Added Figure 56 and Figure 58 .................................................... 22 Added Figure 70 ............................................................................. 25 Added Figure 72 ............................................................................. 26 Added Figure 74 ............................................................................. 27 Added Figure 76 and Figure 78 .................................................... 28 Changes to Digital Outputs and Timing Section ....................... 28 Changes to Table 9 Endnote.......................................................... 29 Added Table 10 ............................................................................... 30 Changes to RBIAS Pin Section ..................................................... 31 Deleted Figure 56 and Figure 57................................................... 27 Changes to Table 15 ....................................................................... 35 Change to Input Signals Section ................................................... 40 Change to Output Signals Section................................................ 40 Changes to Figure 86...................................................................... 40 Changes to Default Operation and Jumper Selection Settings Section ............................................................................... 41 Changes to Alternative Analog Input Configuration Section......... 42 Added Figure 88 and Figure 89 .................................................... 42 Change to Figure 92 ....................................................................... 45 Changes to Table 17 ....................................................................... 54 Updated Outline Dimensions ....................................................... 59 Changes to Ordering Guide .......................................................... 60 9/06—Revision 0: Initial Version Rev. F | Page 2 of 60 Data Sheet AD9222 SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation @ 1.0 mA (VREF = 1 V) Input Resistance ANALOG INPUTS Differential Input Voltage Range (VREF = 1 V) Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation 2 CROSSTALK CROSSTALK (Overrange Condition) 3 Temp Min 12 Full Full Full Full Full Full Full AD9222-40 Typ Max Min 12 Guaranteed ±1 ±8 ±3 ±8 ±0.4 ±1.2 ±0.3 ±0.7 ±0.25 ±0.5 ±0.4 ±1 AD9222-50 Typ Max Min 12 Guaranteed ±1 ±8 ±3 ±8 ±1.5 ±2.5 ±0.3 ±0.7 ±0.3 ±0.65 ±0.4 ±1 AD9222-65 Typ Max Guaranteed ±1 ±8 ±3 ±8 ±3.5 ±5 ±0.4 ±0.8 ±0.25 ±0.6 ±0.4 ±1 ±2 ±17 ±21 Full Full Full ±2 3 6 Full 2 2 2 V p-p Full Full Full AVDD/2 7 325 AVDD/2 7 325 AVDD/2 7 325 V pF MHz Full Full Full Full 1.7 1.7 ±30 1.8 1.8 338 51 700 1.9 1.9 348.5 53.6 722 2 83 −90 −90 11 ±2 3 6 1.7 1.7 ±2 ±17 ±21 mV mV % FS % FS LSB LSB Full Full Full Full Full Full Full Full ±2 ±17 ±21 Unit Bits ±30 1.8 1.8 357.5 53.5 740 1.9 1.9 367.5 56.2 760 2 89 −90 −90 11 ±2 3 6 1.7 1.7 ppm/°C ppm/°C ppm/°C ±30 mV mV kΩ 1.8 1.8 450 56.6 910 1.9 1.9 470 60.5 950.5 V V mA mA mW 2 100 −90 −90 11 mW mW dB dB See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. This can be controlled via SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. 1 2 Rev. F | Page 3 of 60 AD9222 Data Sheet AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST HARMONIC (Second or Third) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 AND AIN2 = −7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz fIN1 = 70 MHz, fIN2 = 71 MHz 1 Temp Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Min AD9222-40 Typ Max 69.5 68.7 11.25 73 70.3 70.3 69.9 68.8 68.5 11.38 11.38 11.32 11.14 11.25 85 85 80 76 −85 −85 −80 −76 Full Full Full Full −92 −92 −92 −90 25°C 25°C 80.0 77.0 AD9222-50 Typ Max 69.5 70.0 70.0 69.5 68.0 Full Full Full Full Min 73 −74 −80 70.4 70.3 70.0 69.0 68.5 70.0 70.0 69.8 68.5 66.8 11.4 11.38 11.33 11.17 11.1 85 84 83 77 −85 −84 −83 −77 −92 −92 −92 −90 80.0 77.0 Min 70.5 −73 −80 AD9222-65 Typ Max 70.3 70.0 69.8 69.5 dB dB dB dB 69.5 69.4 69.3 69 dB dB dB dB 11.4 11.34 11.30 11.25 Bits Bits Bits Bits 83 80 80 75 dBc dBc dBc dBc −83 −80 −80 −75 −90 −90 −90 −85 −70.5 −80 80.0 75.0 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. Rev. F | Page 4 of 60 Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc Data Sheet AD9222 DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. Parameter 1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM) 3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D + x, D − x), (Low Power, Reduced Signal Option)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) 1 2 3 Temp Min Full Full 25°C 25°C 250 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 AD9222-40 Typ Max Min CMOS/LVDS/LVPECL CMOS/LVDS/LVPECL 250 1.2 20 1.5 1.2 20 1.5 3.6 0.3 1.2 30 0.5 3.6 0.3 3.6 0.3 1.2 DRVDD + 0.3 0.3 247 1.125 LVDS 454 1.375 Offset binary 150 1.10 DRVDD +0.3 0.3 V V kΩ pF 250 1.30 Offset binary V V LVDS 247 1.125 LVDS 250 1.30 Offset binary V V kΩ pF 0.05 LVDS 454 1.375 Offset binary 3.6 0.3 1.79 0.05 mV p-p V kΩ pF V V kΩ pF 30 2 1.79 LVDS 150 1.10 1.2 0 Unit 3.6 0.3 70 0.5 DRVDD + 0.3 0.3 0.05 Full Full 1.2 30 2 1.79 247 1.125 1.2 30 0.5 3.6 0.3 1.2 0 AD9222-65 Typ Max CMOS/LVDS/LVPECL 250 1.2 20 1.5 70 0.5 30 2 Full Full Min 30 0.5 70 0.5 Full Full AD9222-50 Typ Max 454 1.375 Offset binary mV V LVDS 150 1.10 250 1.30 Offset binary mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed. This is specified for LVDS and LVPECL only. This is specified for 13 SDIO pins sharing the same connection. Rev. F | Page 5 of 60 AD9222 Data Sheet SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. Min Full Full Full Full 40 Full Full Full Full Full 1.5 Min AD9222-50 Typ Max Full DCO to FCO Delay (tFRAME)4 Full Data to Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency Full ±50 25°C 25°C Full 600 375 8 600 375 8 600 375 8 ns μs CLK cycles APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) 25°C 25°C 750