AD9512UCPZ-EP

1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Five Outputs AD9512-EP Enhanced Product FEATURES FUNCTIONAL BLOCK DIAGRAM VS FUNCTION DSYNC DSYNCB SYNCB, RESETB PDB DETECT SYNC GND RSET VREF AD9512-EP PROGRAMMABLE DIVIDERS AND PHASE ADJUST SYNC STATUS LVPECL OUT0 /1, /2, /3... /31, /32 OUT0B LVPECL OUT1 /1, /2, /3... /31, /32 CLK1 OUT1B LVPECL CLK1B ENHANCED PRODUCT FEATURES OUT2 /1, /2, /3... /31, /32 OUT2B CLK2 Supports defense and aerospace applications (AQEC standard) Military temperature range (−55°C to +85°C) Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Enhanced product change notification Qualification data available on request SYNC STATUS LVDS/CMOS CLK2B OUT3 /1, /2, /3... /31, /32 OUT3B SCLK SDIO SDO SERIAL CONTROL PORT LVDS/CMOS /1, /2, /3... /31, /32 CSB OUT4 OUT4B 10463-001 Two 1.6 GHz, differential clock inputs 5 programmable dividers, 1 to 32, all integers 3 independent 1.2 GHz LVPECL outputs Additive output jitter 225 fs rms 2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter: 275 fs rms Serial control port Space-saving 48-lead LFCSP Figure 1. APPLICATIONS Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs Defense and aerospace applications GENERAL DESCRIPTION The AD9512-EP provides a multi-output clock distribution in a design that emphasizes low jitter and low phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements can also benefit from this device. There are five independent clock outputs. Three outputs are LVPECL (1.2 GHz), and two are selectable as either LVDS (800 MHz) or CMOS (250 MHz) levels. Each output has a programmable divider that can be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output can be varied by means of a divider phase select function that serves as a coarse timing adjustment. Rev. A The AD9512-EP is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9512-EP is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. The temperature range is −55°C to +85°C. Additional application and technical information can be found in the AD9512 data sheet. Note that the delay block element that exists in Channel 4 of the AD9512 standard product is not supported in this AD9512-EP version. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9512-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Clock Output Additive Time Jitter..............................................8 Enhanced Product Features ............................................................ 1 Serial Control Port ..................................................................... 10 Applications ....................................................................................... 1 FUNCTION Pin ......................................................................... 10 Functional Block Diagram .............................................................. 1 SYNC STATUS Pin .................................................................... 11 General Description ......................................................................... 1 Power............................................................................................ 11 Revision History ............................................................................... 2 Absolute Maximum Ratings ......................................................... 12 Specifications..................................................................................... 3 Thermal Resistance .................................................................... 12 Clock Inputs .................................................................................. 3 Pin Configuration and Function Descriptions........................... 13 Clock Outputs ............................................................................... 3 Typical Performance Characteristics ........................................... 15 Timing Characteristics ................................................................ 4 Outline Dimensions ....................................................................... 18 Clock Output Phase Noise .......................................................... 5 Ordering Guide .......................................................................... 18 REVISION HISTORY 11/2018—Rev. 0 to Rev. A Changes to Figure 2 ........................................................................ 13 Updated Outline Dimensions ....................................................... 18 Changes to Ordering Guide .......................................................... 18 3/2012—Revision 0: Initial Version Rev. A | Page 2 of 18 Enhanced Product AD9512-EP SPECIFICATIONS The typical value is given for VS = 3.3 V ± 5%; TA = 25°C, RSET = 4.12 kΩ, unless otherwise noted. Minimum and maximum values are given over full VS and TA (−55°C to +85°C) variation. CLOCK INPUTS Table 1. Parameter CLOCK INPUTS (CLK1, CLK2) 1 Input Frequency Input Sensitivity Min Typ 0 Input Common-Mode Range, VCMR Input Sensitivity, Single-Ended Input Resistance Input Capacitance Unit 1.6 GHz mV p-p 150 2 Input Level Input Common-Mode Voltage, VCM Max 1.45 1.5 1.3 4.0 1.6 1.6 150 4.8 2 23 V p-p 1.7 1.7 1.8 V V V mV p-p kΩ pF 5.6 Test Conditions/Comments Jitter performance can be improved with higher slew rates (greater swing). Larger swings turn on the protection diodes and can degrade jitter performance. Self-biased; enables ac coupling; at full temperature range. At −40°C to +85°C. With 200 mV p-p signal applied; dc-coupled. CLK2 ac-coupled; CLK2B ac bypassed to RF ground. Self-biased. CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input. With a 50 Ω termination, this is −12.5 dBm. 3 With a 50 Ω termination, this is +10 dBm. 1 2 CLOCK OUTPUTS Table 2. Parameter LVPECL CLOCK OUTPUTS OUT0, OUT1, OUT2; Differential Output Frequency Output High Voltage (VOH) Output Low Voltage (VOL) Output Differential Voltage (VOD) LVDS CLOCK OUTPUTS OUT3, OUT4; Differential Output Frequency Differential Output Voltage (VOD) Delta VOD Output Offset Voltage (VOS) Min Typ Max Unit VS − 1.22 VS − 2.10 660 VS − 0.98 VS − 1.80 810 1200 VS − 0.93 VS − 1.67 965 MHz V V mV 250 360 1.05 1.125 1.23 1.23 Delta VOS Short-Circuit Current (ISA, ISB) CMOS CLOCK OUTPUTS OUT3, OUT4 Output Frequency Output Voltage High (VOH) Output Voltage Low (VOL) 14 800 450 25 1.375 1.375 25 24 250 VS − 0.1 0.1 Rev. A | Page 3 of 18 MHz mV mV V V mV mA MHz V V Test Conditions/Comments Termination = 50 Ω to VS − 2 V Output level 0x3D (0x3E) (0x3F)[3:2] = 10b See Figure 10 Termination = 100 Ω differential; default Output level 0x40 (0x41)[2:1] = 01b 3.5 mA termination current See Figure 11 At full temperature range At −40°C to +85°C Output shorted to GND Single-ended measurements; B outputs: inverted, termination open With 5 pF load each output; see Figure 12 At 1 mA load At 1 mA load AD9512-EP Enhanced Product TIMING CHARACTERISTICS Table 3. Parameter LVPECL Output Rise Time, tRP Output Fall Time, tFP PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT 1 Divide = Bypass Divide = 2 to 32 Variation with Temperature OUTPUT SKEW, LVPECL OUTPUTS OUT1 to OUT0 on Same Device, tSKP 2 OUT1 to OUT2 on Same Device, tSKP2 OUT0 to OUT2 on Same Device, tSKP2 All LVPECL OUT Across Multiple Devices, tSKP_AB 3 Same LVPECL OUT Across Multiple Devices, tSKP_AB3 LVDS Output Rise Time, tRL Output Fall Time, tFL PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT1 OUT3 to OUT4 Divide = Bypass Divide = 2 to 32 Variation with Temperature OUTPUT SKEW, LVDS OUTPUTS OUT3 to OUT4 on Same Device, tSKV2 All LVDS OUTs Across Multiple Devices, tSKV_AB3 Same LVDS OUT Across Multiple Devices, tSKV_AB3 CMOS Output Rise Time, tRC Output Fall Time, tFC PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT1 Divide = Bypass Divide = 2 to 32 Variation with Temperature OUTPUT SKEW, CMOS OUTPUTS OUT3 to OUT4 on Same Device, tSKC2 All CMOS OUT Across Multiple Devices, tSKC_AB3 Same CMOS OUT Across Multiple Devices, tSKC_AB3 LVPECL-TO-LVDS OUT Output Skew, tSKP_V LVPECL-TO-CMOS OUT Output Skew, tSKP_C Min Typ Max Unit 130 130 180 180 ps ps 320 335 360 375 490 490 545 545 0.5 635 635 695 695 ps ps ps ps ps/°C 70 15 45 100 45 65 140 80 90 275 130 ps ps Ps ps ps 200 210 350 350 ps ps 1.33 1.33 1.38 1.38 0.9 1.59 1.59 1.64 1.64 ns ns ns ns ps/°C +270 450 325 ps ps ps 681 646 865 992 ps ps 1.0 1.02 1.05 1.07 1.39 1.39 1.44 1.44 1 1.71 1.71 1.76 1.76 ns ns ns ns ps/°C −140 +145 +300 650 500 ps ps ps 0.73 0.92 1.14 ns 0.87 1.14 1.43 ns 0.97 0.99 1.02 1.04 −85 Rev. A | Page 4 of 18 Test Conditions/Comments Termination = 50 Ω to VS − 2 V Output level 0x3D (0x3E) (0x3F)[3:2] = 10b 20% to 80%, measured differentially 80% to 20%, measured differentially At full temperature range At −40°C to +85°C At full temperature range At −40°C to +85°C Termination = 100 Ω differential Output level 0x40 (0x41) [2:1] = 01b 3.5 mA termination current 20% to 80%, measured differentially 80% to 20%, measured differentially At full temperature range At −40°C to +85°C At full temperature range At −40°C to +85°C B outputs are inverted; termination = open 20% to 80%; CLOAD = 3 pF 80% to 20%; CLOAD = 3 pF At full temperature range At −40°C to +85°C At full temperature range At −40°C to +85°C Everything the same; different logic type LVPECL to LVDS on same device Everything the same; different logic type LVPECL to CMOS on same device Enhanced Product Parameter LVDS-TO-CMOS OUT Output Skew, tSKV_C 1 2 3 AD9512-EP Min Typ Max Unit 158 353 506 ps Test Conditions/Comments Everything the same; different logic type LVDS to CMOS on same device The measurements are for CLK1. For CLK2, add approximately 25 ps. This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature. This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature. CLOCK OUTPUT PHASE NOISE Table 4. Parameter CLK1-TO-LVPECL ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset >1 MHz Offset CLK1 = 622.08 MHz, OUT = 38.88 MHz Divide Ratio = 16 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset >1 MHz Offset CLK1 = 491.52 MHz, OUT = 61.44 MHz Divide Ratio = 8 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset >1 MHz Offset CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset >1 MHz Offset Min Typ Max Unit Test Conditions/Comments Input slew rate > 1 V/ns −125 −132 −140 −148 −153 −154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −128 −140 −148 −155 −161 −161 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −135 −145 −158 −165 −165 −166 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −131 −142 −153 −160 −165 −165 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −125 −132 −140 −151 −157 −158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. A | Page 5 of 18 AD9512-EP Parameter CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset >1 MHz Offset CLK1-TO-LVDS ADDITIVE PHASE NOISE CLK1 = 622.08 MHz, OUT = 622.08 MHz Divide Ratio = 1 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset at 1 MHz Offset >10 MHz Offset CLK1 = 622.08 MHz, OUT = 155.52 MHz Divide Ratio = 4 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset at 1 MHz Offset >10 MHz Offset CLK1 = 491.52 MHz, OUT = 245.76 MHz Divide Ratio = 2 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset at 1 MHz Offset >10 MHz Offset CLK1 = 491.52 MHz, OUT = 122.88 MHz Divide Ratio = 4 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset t 1 MHz Offset >10 MHz Offset CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset at 1 MHz Offset >10 MHz Offset Enhanced Product Min Typ Max Unit −138 −144 −154 −163 −164 −165 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −100 −110 −118 −129 −135 −140 −148 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −112 −122 −132 −142 −148 −152 −155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −108 −118 −128 −138 −145 −148 −154 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −118 −129 −136 −147 −153 −156 −158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −108 −118 −128 −138 −145 −148 −155 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. A | Page 6 of 18 Test Conditions/Comments Enhanced Product Parameter CLK1 = 245.76 MHz, OUT = 122.88 MHz Divide Ratio = 2 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset at 1 MHz Offset >10 MHz Offset CLK1-TO-CMOS ADDITIVE PHASE NOISE CLK1 = 245.76 MHz, OUT = 245.76 MHz Divide Ratio = 1 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset at 1 MHz Offset > 10 MHz Offset CLK1 = 245.76 MHz, OUT = 61.44 MHz Divide Ratio = 4 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset at 1 MHz Offset >10 MHz Offset CLK1 = 78.6432 MHz, OUT = 78.6432 MHz Divide Ratio = 1 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset at 1 MHz Offset >10 MHz Offset CLK1 = 78.6432 MHz, OUT = 39.3216 MHz Divide Ratio = 2 at 10 Hz Offset at 100 Hz Offset at 1 kHz Offset at 10 kHz Offset at 100 kHz Offset >1 MHz Offset AD9512-EP Min Typ Max Unit −118 −127 −137 −147 −154 −156 −158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −110 −121 −130 −140 −145 −149 −156 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −122 −132 −143 −152 −158 −160 −162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −122 −132 −140 −150 −155 −158 −160 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −128 −136 −146 −155 −161 −162 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. A | Page 7 of 18 Test Conditions/Comments AD9512-EP Enhanced Product CLOCK OUTPUT ADDITIVE TIME JITTER Table 5. Parameter LVPECL OUTPUT ADDITIVE TIME JITTER CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 622.08 MHz Divide Ratio = 1 CLK1 = 622.08 MHz Any LVPECL (OUT0 to OUT2) = 155.52 MHz Divide Ratio = 4 CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 100 MHz Both LVDS (OUT3, OUT4) = 100 MHz CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Both LVDS (OUT3, OUT4) = 50 MHz CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off) CLK1 = 400 MHz Any LVPECL (OUT0 to OUT2) = 100 MHz Divide Ratio = 4 Other LVPECL = 50 MHz Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On) LVDS OUTPUT ADDITIVE TIME JITTER CLK1 = 400 MHz Min Typ Max Unit Test Conditions/Comments 40 fs rms BW = 12 kHz to 20 MHz (OC-12) 55 fs rms BW = 12 kHz to 20 MHz (OC-3) 215 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz 215 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz 222 225 225 fs rms fs rms fs rms Interferer(s) Interferer(s) Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) 264 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz 319 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CLK1 = 400 MHz 395 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 LVDS (OUT4) = 50 MHz All LVPECL = 50 MHz Interferer(s) Interferer(s) Rev. A | Page 8 of 18 Enhanced Product Parameter CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 LVDS (OUT3) = 50 MHz All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs Off ) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs Off ) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT3) = 100 MHz Divide Ratio = 4 CMOS (OUT4) = 50 MHz (B Outputs On) All LVPECL = 50 MHz CLK1 = 400 MHz LVDS (OUT4) = 100 MHz Divide Ratio = 4 CMOS (OUT3) = 50 MHz (B Outputs On) All LVPECL = 50 MHz CMOS OUTPUT ADDITIVE TIME JITTER CLK1 = 400 MHz Both CMOS (OUT3, OUT4) = 100 MHz (B Output On) Divide Ratio = 4 CLK1 = 400 MHz CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz LVDS (OUT4) = 50 MHz CLK1 = 400 MHz CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz CMOS (OUT4) = 50 MHz (B Output Off ) CLK1 = 400 MHz AD9512-EP Min Typ 395 Max 367 367 548 548 Unit fs rms fs rms fs rms fs rms fs rms Test Conditions/Comments Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) 275 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz 400 fs rms Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz 374 555 CMOS (OUT3) = 100 MHz (B Output On) Divide Ratio = 4 All LVPECL = 50 MHz CMOS (OUT4) = 50 MHz (B Output On) fs rms fs rms Interferer(s) Interferer(s) Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Calculated from SNR of ADC method; fC = 100 MHz with AIN = 170 MHz Interferer(s) Interferer(s) Rev. A | Page 9 of 18 AD9512-EP Enhanced Product SERIAL CONTROL PORT Table 6. Parameter CSB, SCLK (INPUTS) Min Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO (WHEN INPUT) Input Logic 1 Voltage Input Logic 0 Voltage Input Logic 1 Current Input Logic 0 Current Input Capacitance SDIO, SDO (OUTPUTS) Output Logic 1 Voltage Output Logic 0 Voltage TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High, tPWH Pulse Width Low, tPWL SDIO to SCLK Setup, tDS SCLK to SDIO Hold, tDH SCLK to Valid SDIO and SDO, tDV CSB to SCLK Setup and Hold, tS, tH CSB Minimum Pulse Width High, tPWH 2.0 Typ Max 0.8 110 1 2 2.0 0.8 10 10 2 2.7 0.4 25 16 16 2 1 6 2 3 Unit Test Conditions/Comments CSB and SCLK have 30 kΩ internal pull-down resistors V V µA µA pF V V nA nA pF V V MHz ns ns ns ns ns ns ns FUNCTION PIN Table 7. Parameter INPUT CHARACTERISTICS Min Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance RESET TIMING Pulse Width Low SYNC TIMING Pulse Width Low 2.0 Typ Max 0.8 110 1 2 Unit Test Conditions/Comments The FUNCTION pin has a 30 kΩ internal pull-down resistor. This pin is normally held high. Do not let input float. V V µA µA pF 50 ns 1.5 High speed clock cycles Rev. A | Page 10 of 18 High speed clock is CLK1 or CLK2, whichever is being used for distribution. Enhanced Product AD9512-EP SYNC STATUS PIN Table 8. Parameter OUTPUT CHARACTERISTICS Output Voltage High (VOH) Output Voltage Low (VOL) Min Typ Max Unit 0.4 V V 2.7 Test Conditions/Comments POWER Table 9. Parameter POWER-UP DEFAULT MODE POWER DISSIPATION Min Typ 550 POWER DISSIPATION Max 600 Unit mW 800 mW 850 mW Full Sleep Power-Down 35 60 mW Power-Down (PDB) 60 80 mW POWER DELTA CLK1, CLK2 Power-Down Divider, DIV 2 to 32 to Bypass LVPECL Output Power-Down (PD2, PD3) 10 23 50 15 27 65 25 33 75 mW mW mW LVDS Output Power-Down CMOS Output Power-Down (Static) CMOS Output Power-Down (Dynamic) 80 56 115 92 70 150 110 85 190 mW mW mW CMOS Output Power-Down (Dynamic) 125 165 210 mW Rev. A | Page 11 of 18 Test Conditions/Comments Power-up default state; does not include power dissipated in output load resistors. No clock. All outputs on. Three LVPECL outputs at 800 MHz, two CMOS out at 62 MHz (5 pF load). Does not include power dissipated in external resistors. All outputs on. Three LVPECL outputs at 800 MHz, two CMOS out at 125 MHz (5 pF load). Does not include power dissipated in external resistors. Maximum sleep is entered by setting 0x0A[1:0] = 01b and 0x58[4] = 1b. This powers off all band gap references. Does not include power dissipated in terminations. Set FUNCTION pin for PDB operation by setting 0x58[6:5] = 11b. Pull PDB low. Does not include power dissipated in terminations. For each divider. For each output. Does not include dissipation in termination (PD2 only). For each output. For each output. Static (no clock). For each CMOS output, single-ended. Clocking at 62 MHz with 5 pF load. For each CMOS output, single-ended. Clocking at 125 MHz with 5 pF load. AD9512-EP Enhanced Product ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 10. Parameter VS DSYNC/DSYNCB RSET CLK1, CLK1B, CLK2, CLK2B CLK1 CLK2 SCLK, SDIO, SDO, CSB OUT0, OUT1, OUT2, OUT3, OUT4 FUNCTION SYNC STATUS Junction Temperature Storage Temperature Range Lead Temperature (10 sec) With Respect to GND GND GND GND CLK1B CLK2B GND GND GND GND Table 11. Thermal Resistance 1 Rating −0.3 V to +3.6 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V −1.2 V to +1.2 V −1.2 V to +1.2 V −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V Package Type CP-48-13 1 θJA 28.5 Unit °C/W Thermal impedance measurements were taken on a 4-layer board in still air, in accordance with EIA/JESD51-7. ESD CAUTION −0.3 V to VS + 0.3 V −0.3 V to VS + 0.3 V 150°C −65°C to +150°C 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 12 of 18 Enhanced Product AD9512-EP 48 47 46 45 44 43 42 41 40 39 38 37 VS VS GND RSET VS GND OUT0 OUT0B VS VS GND GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 AD9512-EP TOP VIEW (Not to Scale) 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 VS OUT3 OUT3B VS VS OUT4 OUT4B VS VS OUT1 OUT1B VS NOTES 1. DNC = DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO FUNCTION PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND, GND. 10463-002 SYNC STATUS SCLK SDIO SDO CSB VS GND OUT2B OUT2 VS VS GND 13 14 15 16 17 18 19 20 21 22 23 24 DSYNC DSYNCB VS VS DNC VS CLK2 CLK2B VS CLK1 CLK1B FUNCTION Figure 2. Pin Configuration Table 12. Pin Function Descriptions Pin No. 1 2 3, 4, 6, 9, 18, 22, 23, 25, 28, 29, 32, 33, 36, 39, 40, 44, 47, 48 5 7 8 10 11 12 13 14 15 16 17 19, 24, 37, 38, 43, 46 20 21 26 27 30 31 34 Mnemonic DSYNC DSYNCB VS Description Detect Sync. Used for multichip synchronization. Detect Sync Complement. Used for multichip synchronization. Power Supply (3.3 V). DNC CLK2 CLK2B CLK1 CLK1B FUNCTION SYNC STATUS SCLK SDIO SDO CSB GND Do Not Connect. Do not connect to this pin. Clock Input. Complementary Clock Input. Used in conjunction with CLK2. Clock Input. Complementary Clock Input. Used in conjunction with CLK1. Multipurpose Input. Can be programmed as a reset (RESETB), sync (SYNCB), or power-down (PDB) pin. Output Used to Monitor the Status of Multichip Synchronization. Serial Data Clock. Serial Data I/O. Serial Data Output. Serial Port Chip Select. Ground. OUT2B OUT2 OUT1B OUT1 OUT4B OUT4 OUT3B Complementary LVPECL Output. LVPECL Output. Complementary LVPECL Output. LVPECL Output. Complementary LVDS/Inverted CMOS Output. LVDS/CMOS Output. Complementary LVDS/Inverted CMOS Output. Rev. A | Page 13 of 18 AD9512-EP Pin No. 35 41 42 45 Enhanced Product Mnemonic OUT3 OUT0B OUT0 RSET EPAD Description LVDS/CMOS Output. Complementary LVPECL Output. LVPECL Output. Current Set Resistor to Ground. Nominal value = 4.12 kΩ. Exposed paddle. The exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND. Rev. A | Page 14 of 18 Enhanced Product AD9512-EP TYPICAL PERFORMANCE CHARACTERISTICS 0.7 0.6 DEFAULT – 3 LVPECL + 2 LVDS (DIV ON) 0.6 POWER (W) POWER (W) 0.5 3 LVPECL + 2 LVDS (DIV BYPASSED) 3 LVPECL + 2 CMOS (DIV ON) 0.5 0.4 0.3 0 400 800 OUTPUT FREQUENCY (MHz) 0.4 0 40 60 80 100 120 OUTPUT FREQUENCY (MHz) Figure 5. Power vs. Frequency—LVPECL, CMOS Figure 3. Power vs. Frequency—LVPECL, LVDS CLK2 (EVAL BOARD) CLK1 (EVAL BOARD) 3GHz 20 5MHz 5MHz 10463-004 10463-006 3GHz Figure 6. CLK2 Smith Chart (Evaluation Board) Figure 4. CLK1 Smith Chart (Evaluation Board) Rev. A | Page 15 of 18 10463-005 2 LVDS (DIV ON) 10463-003 3 LVPECL (DIV ON) AD9512-EP Enhanced Product DIFFERENTIAL SWING (V p-p) 1.8 1.7 1.6 1.5 1.4 HORIZ 500ps/DIV 1.2 100 600 1100 10463-010 VERT 500mV/DIV 10463-007 1.3 1600 OUTPUT FREQUENCY (MHz) Figure 7. LVPECL Differential Output at 800 MHz Figure 10. LVPECL Differential Output Swing vs. Frequency HORIZ 500ps/DIV 700 650 600 550 500 100 300 500 700 10463-011 VERT 100mV/DIV 10463-008 DIFFERENTIAL SWING (mV p-p) 750 900 OUTPUT FREQUENCY (MHz) Figure 8. LVDS Differential Output at 800 MHz Figure 11. LVDS Differential Output Swing vs. Frequency 3.5 2pF 3.0 OUTPUT (VPK) 2.5 10pF 2.0 1.5 1.0 20pF HORIZ 1ns/DIV 0 0 100 200 300 400 OUTPUT FREQUENCY (MHz) Figure 9. CMOS Single-Ended Output at 250 MHz with 10 pF Load 500 600 10463-012 VERT 500mV/DIV 10463-009 0.5 Figure 12. CMOS Single-Ended Output Swing vs. Frequency and Load Rev. A | Page 16 of 18 AD9512-EP –110 –120 –120 –130 –130 –140 –140 –150 –150 –160 –160 1k 10k 100k 1M 10M OFFSET (Hz) –170 10 –90 –100 –100 –110 –110 L(f) (dBc/Hz) –90 –120 –130 –150 –150 –160 –160 10k 100k 1M 10M –170 10 –110 –120 –120 L(f) (dBc/Hz) –110 –130 –140 –160 –160 10k 100k 1M 10M 10k 100k 1M 10M –140 –150 OFFSET (Hz) 1k –130 –150 10463-015 L(f) (dBc/Hz) –100 1k 100 Figure 17. Additive Phase Noise—LVDS DIV2, 122.88 MHz –100 100 10M OFFSET (Hz) Figure 14. Additive Phase Noise—LVDS DIV1, 245.76 MHz –170 10 1M –130 –140 OFFSET (Hz) 100k –120 –140 10463-014 L(f) (dBc/Hz) –80 1k 10k Figure 16. Additive Phase Noise—LVPECL DIV1, 622.08 MHz –80 100 1k OFFSET (Hz) Figure 13. Additive Phase Noise—LVPECL DIV1, 245.76 MHz Distribution Section Only –170 10 100 10463-017 100 Figure 15. Additive Phase Noise—CMOS DIV1, 245.76 MHz –170 10 100 1k 10k 100k 1M 10M OFFSET (Hz) Figure 18. Additive Phase Noise—CMOS DIV4, 61.44 MHz Rev. A | Page 17 of 18 10463-018 –170 10 10463-016 L(f) (dBc/Hz) –110 10463-013 L(f) (dBc/Hz) Enhanced Product AD9512-EP Enhanced Product OUTLINE DIMENSIONS DETAIL A (JEDEC 95) 7.10 7.00 SQ 6.90 0.30 0.25 0.18 37 36 48 1 0.50 BSC 5.70 5.60 SQ 5.50 EXPOSED PAD TOP VIEW 0.80 0.75 0.70 END VIEW PKG-004452 SEATING PLANE 0.50 0.40 0.30 24 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF P IN 1 IN D IC AT O R AR E A OP T IO N S (SEE DETAIL A) 13 BOTTOM VIEW 0.20 MIN 5.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4. 08-21-2018-A PIN 1 INDICATOR Figure 19. 48-Lead Lead Frame Chip Scale Package [LFCSP] 7 mm × 7 mm Body and 0.75 mm Package Height (CP-48-13) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9512UCPZ-EP AD9512UCPZ-EP-R7 1 Temperature Range −55°C to +85°C −55°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP] 48-Lead Lead Frame Chip Scale Package [LFCSP] Z = RoHS Compliant Part. ©2012–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D10463-0-11/18(A) Rev. A | Page 18 of 18 Package Option CP-48-13 CP-48-13