AD9559/PCBZ

Dual PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator AD9559 Data Sheet FEATURES Pin program function for easy frequency translation configuration Software controlled power-down 72-lead (10 mm × 10 mm) LFCSP package Supports GR-1244 Stratum 3 stability in holdover mode Supports smooth reference switchover with virtually no disturbance on output phase Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems Supports ITU-T G.8262 synchronous Ethernet slave clocks Supports ITU-T G.823, G.824, G.825, and G.8261 Auto/manual holdover and reference switchover Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications Dual digital PLL architecture with four reference inputs (single-ended or differential) 4x2 crosspoint allows any reference input to drive either PLL Input reference frequencies from 2 kHz to 1250 MHz Reference validation and frequency monitoring (2 ppm) Programmable input reference switchover priority 20-bit programmable input reference divider 4 pairs of clock output pins with each pair configurable as a single differential LVDS/HSTL output or as 2 single-ended CMOS outputs Output frequencies: 262 kHz to 1250 MHz Programmable 17-bit integer and 23-bit fractional feedback divider in digital PLL Programmable digital loop filter covering loop bandwidths from 0.1 Hz to 2 kHz Low noise system clock multiplier Optional crystal resonator for system clock input On-chip EEPROM to store multiple power-up profiles APPLICATIONS Network synchronization, including synchronous Ethernet and SDH to OTN mapping/demapping Cleanup of reference clock jitter SONET/SDH clocks up to OC-192, including FEC Stratum 3 holdover, jitter cleanup, and phase transient control Wireless base station controllers Cable infrastructure Data communications GENERAL DESCRIPTION The AD9559 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9559 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9559 continuously generates a low jitter output clock even when all reference inputs have failed. The AD9559 operates over an industrial temperature range of −40°C to +85°C. If a single DPLL version of this part is needed, refer to the AD9557. FUNCTIONAL BLOCK DIAGRAM CHANNEL 0A DIVIDER AD9559 ANALOG PLL 0 ÷3 TO ÷11 HF DIVIDER 0 CHANNEL 0B DIVIDER DIGITAL PLL 1 ANALOG PLL 1 ÷3 TO ÷11 HF DIVIDER 1 CHANNEL 1A DIVIDER CLOCK MULTIPLIER EEPROM SERIAL INTERFACE (SPI OR I2C) STATUS AND CONTROL PINS CHANNEL 1B DIVIDER 10644-001 REFERENCE INPUT MONITOR AND MUX DIGITAL PLL 0 STABLE SOURCE Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9559 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Digital PLL (DPLL) Core .......................................................... 34 Applications ....................................................................................... 1 Loop Control State Machine ..................................................... 36 General Description ......................................................................... 1 System Clock (SYSCLK) ................................................................ 37 Functional Block Diagram .............................................................. 1 SYSCLK Inputs ........................................................................... 37 Revision History ............................................................................... 3 SYSCLK Multiplier ..................................................................... 37 Specifications..................................................................................... 4 Output PLL (APLL) ....................................................................... 39 Supply Voltage ............................................................................... 4 APLL Configuration .................................................................. 39 Supply Current .............................................................................. 4 APLL Calibration ....................................................................... 39 Power Dissipation ......................................................................... 5 Clock Distribution.......................................................................... 40 System Clock Inputs (XOA, XOB) ............................................. 5 Clock Dividers ............................................................................ 40 Reference Inputs ........................................................................... 6 Output Enable ............................................................................. 40 Reference Monitors ...................................................................... 7 Output Mode and Power-Down .............................................. 40 Reference Switchover Specifications .......................................... 7 Clock Distribution Synchronization ........................................ 41 Distribution Clock Outputs ........................................................ 8 Status and Control .......................................................................... 42 Time Duration of Digital Functions ........................................ 10 Multifunction Pins (M0 to M5) ............................................... 42 Digital PLL (DPLL_0 and DPLL_1) ........................................ 10 IRQ Function .............................................................................. 42 Analog PLL (APLL_0 and APLL_1) ........................................ 10 Watchdog Timer ......................................................................... 43 Digital PLL Lock Detection ...................................................... 10 EEPROM ..................................................................................... 43 Holdover Specifications ............................................................. 10 Serial Control Port ......................................................................... 49 Serial Port Specifications—SPI Mode...................................... 11 SPI/I²C Port Selection................................................................ 49 Serial Port Specifications—I C Mode ...................................... 12 SPI Serial Port Operation .......................................................... 49 Logic Inputs (RESET, M5 to M0)............................................. 12 I²C Serial Port Operation .......................................................... 53 Logic Outputs (M5 to M0) ........................................................ 12 Programming the I/O Registers ................................................... 56 Jitter Generation ......................................................................... 13 Buffered/Active Registers .......................................................... 56 Absolute Maximum Ratings .......................................................... 16 Write Detect Registers ............................................................... 56 ESD Caution ................................................................................ 16 Autoclear Registers..................................................................... 56 Pin Configuration and Function Descriptions ........................... 17 Register Access Restrictions...................................................... 56 Typical Performance Characteristics ........................................... 20 Thermal Performance .................................................................... 57 Input/Output Termination Recommendations .......................... 26 Power Supply Partitions ................................................................. 58 Getting Started ................................................................................ 27 3.3 V Supplies.............................................................................. 58 Chip Power Monitor and Startup ............................................. 27 1.8 V Supplies.............................................................................. 58 Multifunction Pins at Reset/Power-Up ................................... 27 Bypass Capacitors for Pin 21 and Pin 33................................. 58 Device Register Programming Using a Register Setup File .. 27 Register Map ................................................................................... 59 Register Programming Overview............................................. 28 Register Map Bit Descriptions ...................................................... 72 Theory of Operation ...................................................................... 31 Serial Control Port Configuration (Register 0x0000 to Register 0x0005) ......................................................................... 72 2 Overview...................................................................................... 31 Reference Input Physical Connections .................................... 32 Reference Monitors .................................................................... 32 Reference Input Block ................................................................ 32 Reference Switchover ................................................................. 33 Clock Part Family ID (Register 0x000C and Register 0x000D) 72 User Scratchpad (Register 0x000E and Register 0x000F) ..... 73 General Configuration (Register 0x0100 to Register 0x0109) .. 73 IRQ Mask (Register 0x010A to Register 0x112) .................... 74 Rev. C | Page 2 of 120 Data Sheet AD9559 System Clock (Register 0x0200 to Register 0x0207) ..............76 Reference Input A (Register 0x0300 to Register 0x031A) .....77 Reference Input B (Register 0x0320 to Register 0x033A)......78 Reference Input C (Register 0x0340 to Register 0x035A) .....79 Reference Input D (Register 0x0360 to Register 0x037A) .....81 DPLL_0 Controls (Register 0x0400 to Register 0x0415) .......82 DPLL_1 Settings for Reference Input A (REFA) (Register 0x055A to Register 0x0566) ....................................................... 98 DPLL_1 Settings for Reference Input B (REFB) (Register 0x0567 to Register 0x0573)........................................................ 99 Digital Loop Filter Coefficients (Register 0x0800 to Register 0x0817) .......................................................................................100 APLL_0 Configuration (Register 0x0420 to Register 0x0423) .. 84 Common Operational Controls (Register 0x0A00 to Register 0x0A0E) ......................................................................................101 PLL_0 Output Sync and Clock Distribution (Register 0x0424 to Register 0x042E) .....................................................................85 PLL_0 Operational Controls (Register 0x0A20 to Register 0x0A24) ......................................................................................104 DPLL_0 Settings for Reference Input A (REFA) (Register 0x0440 to Register 0x044C) .......................................................87 PLL_1 Operational Controls (Register 0x0A40 to Register 0x0A44) ......................................................................................106 DPLL_0 Settings for Reference Input B (REFB) (Register 0x044D to Register 0x0459) .......................................................88 Status ReadBack (Register 0x0D00 to Register 0x0D05) .....107 DPLL_0 Settings for Reference Input C (REFC) (Register 0x045A to Register 0x0466) .......................................................89 PLL_0 Read-Only Status (Register 0x0D20 to Register 0x0D2A) .....................................................................................110 DPLL_0 Settings for Reference Input D (REFD) (Register 0x0467 to Register 0x0473) ........................................................90 DPLL_1 Controls (Register 0x0500 to Register 0x0515) .......91 APLL_1 Configuration (Register 0x0520 to Register 0x0523)...93 PLL_1 Output Sync and Clock Distribution (Register 0x0524 to Register 0x052E) .....................................................................94 DPLL_1 Settings for Reference Input C (REFC) (Register 0x0540 to Register 0x054C) .......................................................96 IRQ Monitor (Register 0x0D08 to Register 0x0D10) ..........108 PLL_1 Read-Only Status (Register 0x0D40 to Register 0x0D4A) .....................................................................................112 EEPROM Control (Register 0x0E00 to Register 0x0E03) ...113 EEPROM Storage Sequence (Register 0x0E10 to Register 0x0E3C) ......................................................................................113 Outline Dimensions ......................................................................120 Ordering Guide .........................................................................120 DPLL_1 Settings for Reference Input D (REFD) (Register 0x054D to Register 0x0559) .......................................................97 REVISION HISTORY 5/13—Rev. B to Rev. C Changes to Table 25 ........................................................................49 3/13—Rev. A to Rev. B Changes to Device Register Programming Using a Register Setup File Section ............................................................................27 Changed 101100 to 1101100, Table 25 .........................................49 12/12—Rev. 0 to Rev. A Change to Features Section .............................................................. 1 Changes to DPLL Overview Section, Figure 35, and Figure 36 ...........................................................................................34 Changes to EEPROM Upload Section and Manual EEPROM Download Section ...........................................................................45 Changes to Table 25 ........................................................................49 Changes to Table 34 ........................................................................ 63 Changes to Table 91 ........................................................................ 87 Changes to Table 92, Table 96, and Table 97 ............................... 88 Changes to Table 101 and Table 102 ............................................. 89 Changes to Table 106 and Table 107 ............................................. 90 Changes to Table 126 ...................................................................... 97 Changes to Table 127, Table 131, and Table 132 ......................... 97 Changes to Table 136 and Table 137 ............................................. 98 Changes to Table 141 and Table 142 ............................................. 99 Changes to Table 179 ....................................................................113 Updated Outline Dimensions......................................................120 7/12—Revision 0: Initial Version Rev. C | Page 3 of 120 AD9559 Data Sheet SPECIFICATIONS Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ) values apply for VDD3 = 3.3 V; VDD = 1.8 V; TA= 25°C, unless otherwise noted. SUPPLY VOLTAGE Table 1. Parameter SUPPLY VOLTAGE VDD3 VDD Min Typ Max Unit 3.135 1.71 3.30 1.80 3.465 1.89 V V Test Conditions/Comments SUPPLY CURRENT The test conditions for the maximum (max) supply current are at the maximum supply voltage found in Table 1. The test conditions for the typical (typ) supply current are at the typical supply voltage found in Table 1. The test conditions for the minimum (min) supply current are at the minimum supply voltage found in Table 1. Table 2. Parameter SUPPLY CURRENT FOR TYPICAL CONFIGURATION Min Typ Max Unit IVDD3 IVDD SUPPLY CURRENT FOR ALL BLOCKS RUNNING CONFIGURATION IVDD3 IVDD 34 253 42 316 50 380 mA mA Test Conditions/Comments Typical values are for the Typical Configuration parameter listed in Table 3 Maximum values are for the All Blocks Running parameter listed in Table 3 75 256 94 320 113 384 mA mA Rev. C | Page 4 of 120 Data Sheet AD9559 POWER DISSIPATION Table 3. Parameter POWER DISSIPATION Typical Configuration Min Typ Max Unit Test Conditions/Comments 0.57 0.71 0.85 W All Blocks Running 0.71 0.89 1.1 W 75 110 mW 171 214 257 mW System clock: 49.152 MHz crystal; two DPLLs active; two 19.44 MHz input references in differential mode; two HSTL drivers at 644.53125 MHz; two 3.3 V CMOS drivers at 161.1328125 MHz and 80 pF capacitive load on CMOS output System clock: 49.152 MHz crystal; two DPLLs active, all input references in differential mode; two HSTL drivers at 750 MHz; four 3.3 V CMOS drivers at 250 MHz and 80 pF capacitive load on CMOS outputs Typical configuration with no external pull-up or pulldown resistors; about 2/3 of this power is on VDD3 Typical configuration; table values show the change in power due to the indicated operation This power delta is computed relative to the typical configuration; the blocks powered down include one reference input, one DPLL, one APLL, one P divider, two channel dividers, one HSTL driver, and one CMOS driver; roughly 2/3 of the power savings is on the 1.8 V supply 19 25 5 25 32 6.6 31 39 8 mW mW mW Additional current draw is in the VDD3 domain only Additional current draw is in the VDD3 domain only Additional current draw is in the VDD3 domain only 12 14 14 18 17 21 21 27 22 28 28 36 mW mW mW mW Additional current draw is in the VDD domain only Additional current draw is in the VDD domain only A single 1.8 V CMOS output with an 80 pF load A single 3.3 V CMOS output with an 80 pF load Min Typ Max Unit Test Conditions/Comments 750 805 MHz VCO range may place limitations on nonstandard system clock input frequencies 150 255 MHz 4 400 MHz V/μs Full Power-Down Incremental Power Dissipation Complete DPLL/APLL On/Off Input Reference On/Off Differential Without Divide-by-2 Differential With Divide-by-2 Single-Ended (Without Divide-by-2) Output Distribution Driver On/Off LVDS (at 750 MHz) HSTL (at 750 MHz) 1.8 V CMOS (at 250 MHz) 3.3 V CMOS (at 250 MHz) SYSTEM CLOCK INPUTS (XOA, XOB) Table 4. Parameter SYSTEM CLOCK MULTIPLIER PLL Output Frequency Range Phase Frequency Detector (PFD) Rate Frequency Multiplication Range SYSTEM CLOCK REFERENCE INPUT PATH Input Frequency Range Minimum Input Slew Rate Common-Mode Voltage Differential Input Voltage Sensitivity 10 50 Assumes valid system clock and PFD rates 1.05 250 1.16 1.27 V mV p-p 45 46 47 50 50 50 3 4.1 55 54 53 % % % pF kΩ System Clock Input Doubler Duty Cycle System Clock input = 50 MHz System Clock input = 20 MHz System Clock input = 16 MHz to 20 MHz Input Capacitance Input Resistance Rev. C | Page 5 of 120 Minimum limit imposed for jitter performance; jitter performance affected if sine wave input ≤ 20 MHz Internally generated Minimum voltage across pins required to ensure switching between logic states; the instantaneous voltage on either pin must not exceed supply rails; single-ended input can be accommodated by ac grounding complementary input; 1 V p-p recommended for optimal jitter performance Amount of duty cycle variation that can be tolerated on the system clock input to use the doubler Single-ended, each pin AD9559 Parameter CRYSTAL RESONATOR PATH Crystal Resonator Frequency Range Maximum Crystal Motional Resistance Data Sheet Min Typ 10 Max Unit Test Conditions/Comments 50 100 MHz Ω Fundamental mode, AT cut crystal Max Unit Test Conditions/Comments REFERENCE INPUTS Table 5. Parameter DIFFERENTIAL OPERATION Frequency Range Sinusoidal Input LVPECL Input LVDS Input Minimum Input Slew Rate Common-Mode Input Voltage AC-Coupled DC-Coupled Differential Input Voltage Sensitivity fIN < 800 MHz fIN = 800 MHz to 1050 MHz fIN = 1050 MHz to 1250 MHz Differential Input Voltage Hysteresis Input Resistance Input Capacitance Minimum Pulse Width High LVPECL LVDS Minimum Pulse Width Low LVPECL LVDS SINGLE-ENDED OPERATION Frequency Range (CMOS) Minimum Input Slew Rate Input Voltage High (VIH) 1.2 V to 1.5 V Threshold Setting 1.8 V to 2.5 V Threshold Setting 3.0 V to 3.3 V Threshold Setting Input Voltage Low (VIL) 1.2 V to 1.5 V Threshold Setting 1.8 V to 2.5 V Threshold Setting 3.0 V to 3.3 V Threshold Setting Input Resistance Input Capacitance Minimum Pulse Width High Minimum Pulse Width Low Min Typ The reference input divide-by-2 block must be engaged for fIN > 705 MHz 10 0.002 0.002 40 1.9 1.0 750 1250 750 2 2.1 2.4 240 320 400 55 21 3 100 MHz MHz MHz V/μs V V mV ps ps 390 640 ps ps 300 1.0 1.4 2.0 47 3 1.5 1.5 MHz V/μs V V V 0.35 0.5 1.0 Internally generated Minimum differential voltage across pins required to ensure switching between logic levels; instantaneous voltage on either pin must not exceed the supply rails mV mV mV mV kΩ pF 390 640 0.002 40 Minimum limit imposed for jitter performance V V V kΩ pF ns ns Rev. C | Page 6 of 120 Minimum limit imposed for jitter performance Data Sheet AD9559 REFERENCE MONITORS Table 6. Parameter REFERENCE MONITORS Reference Monitor Loss of Reference Detection Time Frequency Out-of Range Limits Validation Timer 1 Min Typ Max Unit Test Conditions/Comments 1.15 DPLL PFD period Δf/fREF (ppm) Nominal phase detector period = R/fREF 1 2 105 0.001 65.535 sec Programmable (lower bound subject to quality of the system clock (SYSCLK)); SYSCLK accuracy must be less than the lower bound Programmable in 1 ms increments fREF is the frequency of the active reference; R is the frequency division factor determined by the R divider. REFERENCE SWITCHOVER SPECIFICATIONS Table 7. Parameter REFERENCE SWITCHOVER SPECIFICATIONS Maximum Output Phase Perturbation (Phase Build-Out Switchover) Min Typ Max Unit ±55 ±55 ±100 ±100 ps ps 10 DPLL PFD period 50 Hz DPLL Loop Bandwidth Peak Steady State Time Required to Switch to a New Reference Phase Build-Out Switchover Rev. C | Page 7 of 120 Test Conditions/Comments Assumes a jitter-free reference; satisfies Telcordia GR-1244-CORE requirements; base loop filter selection bit set to 1b for all active references Test conditions: 19.44 MHz to 174.70308 MHz; DPLL BW = 50 Hz; 49.152 MHz signal generator used for system clock source Calculated using the nominal phase detector period (NPDP = R/fREF); the total time required is the time plus the reference validation time, plus the time required to lock to the new reference AD9559 Data Sheet DISTRIBUTION CLOCK OUTPUTS Table 8. Parameter HSTL MODE Output Frequency OUT0A, OUT0A and OUT0B, OUT0B OUT1A, OUT1A and OUT1B, OUT1B Rise/Fall Time (20% to 80%) 1 Duty Cycle Up to fOUT = 700 MHz Up to fOUT = 750 MHz Up to fOUT = 1250 MHz Differential Output Voltage Swing Common-Mode Output Voltage Reference Input-to-Output Delay Variation over Temperature Static Phase Offset Variation from Active Reference to Output over Voltage Extremes LVDS MODE Output Frequency OUT0A, OUT0A and OUT0B, OUT0B OUT1A, OUT1A and OUT1B, OUT1B Rise/Fall Time (20% to 80%)1 Duty Cycle Up to fOUT = 750 MHz Up to fOUT = 800 MHz Up to fOUT = 1250 MHz Differential Output Voltage Swing Balanced, VOD Min Typ Max Unit Test Conditions/Comments 140 1250 1250 250 MHz MHz ps 100 Ω termination across the output pair 53 54 % % % mV 0.262 0.302 44 43 700 750 48 48 43 925 850 3.2 Short-Circuit Output Current CMOS MODE Output Frequency 1.8 V Supply OUT0A, OUT0A and OUT0B, OUT0B OUT1A, OUT1A and OUT1B, OUT1B 3.3 V Supply (OUT0A and OUT1A) Strong Drive Strength Setting OUT0A, OUT0A OUT1A, OUT1A Weak Drive Strength Setting OUT0A, OUT0A OUT1A, OUT1A 1000 0.875 0.262 0.302 mV ps/°C ps/mV Magnitude of voltage across pins; output driver static Output driver static HSTL mode; DPLL locked to same input reference at all times; stable system clock source (non-XTAL) Valid for HSTL, LVDS, and 1.8 V CMOS output driver modes 1250 1250 280 MHz MHz ps 53 53.5 % % % 454 mV 50 mV 1.25 1.375 50 V mV 10 24 mA Output driver static Voltage difference between pins; output driver static Output driver static 0.262 0.302 250 250 MHz MHz 10 pF load 10 pF load 0.262 0.302 250 250 MHz MHz 10 pF load 10 pF load 0.262 0.302 25 25 MHz MHz 10 pF load 10 pF load 185 43 42.5 48 48 43 247 Unbalanced, ΔVOD Offset Voltage Common Mode, VOS Common-Mode Difference, ΔVOS 1200 1.125 Rev. C | Page 8 of 120 100 Ω termination across the output pair Voltage swing between output pins; output driver static Absolute difference between voltage swing of normal pin and inverted pin; output driver static Data Sheet Parameter Rise/Fall Time (20% to 80%)1 1.8 V Mode 3.3 V Strong Mode 3.3 V Weak Mode Duty Cycle 1.8 V Mode 3.3 V Strong Mode 3.3 V Weak Mode Output Voltage High (VOH) VDD3 = 3.3 V, IOH = 10 mA VDD3 = 3.3 V, IOH = 1 mA VDD3 = 1.8 V, IOH = 1 mA Output Voltage Low (VOL) VDD3 = 3.3 V, IOL = 10 mA VDD3 = 3.3 V, IOL = 1 mA VDD3 = 1.8 V, IOL = 1 mA OUTPUT TIMING SKEW Between OUT0A, OUT0A and OUT0B, OUT0B or OUT1A, OUT1A and OUT1B, OUT1B Additional Delay on One Driver by Changing Its Logic Type HSTL to LVDS 1 AD9559 Min 47 Typ Max Unit Test Conditions/Comments 1.5 0.4 8 3 0.6 ns ns ns 10 pF load 10 pF load 10 pF load % % % 10 pF load 10 pF load 10 pF load Output driver static; strong drive strength 50 51 51 56 VDD3 − 0.3 VDD3 − 0.1 VDD − 0.2 V V V Output driver static; strong drive strength 0.3 0.1 0.1 V V V 116 265 ps 0 +15 +35 ps HSTL to 1.8 V CMOS −5 0 +5 ps OUT0B, OUT0B HSTL to OUT0B, OUT0B 3.3 V CMOS, Strong Mode OUT1B, OUT1B HSTL to OUT1B, OUT1B 3.3 V CMOS, Strong Mode −765 −280 +250 ns Positive value indicates that the LVDS edge is delayed relative to HSTL Positive value indicates that the CMOS edge is delayed relative to HSTL The CMOS edge is delayed relative to HSTL −765 −280 +250 ns The CMOS edge is delayed relative to HSTL The listed values are for the slower edge (rising or falling). Rev. C | Page 9 of 120 10 pF load HSTL mode on both drivers; rising edge only; any divide value AD9559 Data Sheet TIME DURATION OF DIGITAL FUNCTIONS Table 9. Parameter TIME DURATION OF DIGITAL FUNCTIONS EEPROM-to-Register Download Time Min Typ Max Unit Test Conditions/Comments 16 25 ms 180 ms Uses default EEPROM storage sequence (see Register 0x0E10 to Register 0x0E4F) Uses default EEPROM storage sequence (see Register 0x0E10 to Register 0x0E4F Time from power-down exit to system clock lock detect; system clock stability timer setting should be added to calculate the time needed for system clock stable Register-to-EEPROM Upload Time Power-Down Exit Time ms 1 DIGITAL PLL (DPLL_0 AND DPLL_1) Table 10. Parameter DIGITAL PLL Phase Frequency Detector (PFD) Input Frequency Range Loop Bandwidth Phase Margin Closed Loop Peaking Min Typ Max Unit Test Conditions/Comments 2 100 kHz 0.1 2000 Hz 45