PCA9559PW,112

PCA9559 2 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch Rev. 5.0 — 25 October 2021 1 Product data sheet General description PCA9559 is a 20-pin CMOS device consisting of one 6-bit non-volatile EEPROM registers, 5 hardware pin inputs and a 5-bit multiplexed output with one latched EEPROM bit. It is used for DIP switch-free or jumper-less system configuration and supports Mobile and Desktop VID Configuration, where 2 preset values (1 sets of internal non-volatile registers and 1 set of external hardware pins) set processor voltage for operation in either performance or deep sleep modes. The PCA9559 is also useful in server and telecom/networking applications when used to replace DIP switches or jumpers, since 2 the settings can be easily changed via I C/SMBus without having to power down the equipment to open the cabinet. The non-volatile memory retains the most current setting selected before the power is turned off. The PCA9559 typically resides between the CPU and Voltage Regulator Module (VRM) when used for CPU VID (Voltage IDentification code) configuration. It is used to bypass the CPU-defined VID values and provide a different set of VID values to the VRM, if an increase in the CPU voltage is desired. An increase in CPU voltage combined with an increase in CPU frequency leads to a performance boost of up to 7.5%. Lower CPU voltage reduces power consumption. 2 The PCA9559 has 2 address pins allowing up to 4 devices to be placed on the same I Cbus or SMBus. 2 Features and benefits • • • • • • • • • • 5-bit 2-to-1 multiplexer, 1-bit latch DIP switch 6-bit internal non-volatile register 2 Internal non-volatile register programmable and readable via I C-bus Override input forces all outputs to logic 0 5 open drain multiplexed outputs 1 open drain non-multiplexed (latched) output 5 V and 2.5 V tolerant inputs/outputs Useful for ‘jumperless’ configuration of PC motherboards 2 2 address pins, allowing up to 4 devices on the I C-bus ESD protection exceeds 2000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101 • Latch-up testing is done to JESDEC Standard JESD78 which exceeds 100 mA. NXP Semiconductors 2 PCA9559 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch 3 Ordering information Table 1. Ordering information Type number PCA9559PW Topside marking Package Name Description Version PCA9559 TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 3.1 Ordering options Table 2. Ordering options [1] Type number Orderable part number Package Packing method PCA9559PW PCA9559PW,118 TSSOP20 REEL 13" Q1 NDP [1] Minimum order quantity Temperature 2500 Tamb = -40 °C to +85 °C Standard packing quantities and other packaging data are available at www.nxp.com/packages/. PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 2 / 20 PCA9559 NXP Semiconductors 2 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch 4 Block diagram PCA9559 11 18 MUX_SELECT 10-30 kΩ OVERRIDE_N 4 A0 3 A1 6-BIT EEPROM 100-150 kΩ 2 SDA 20 10 5 6 7 8 VDD INPUT FILTER POWER-ON RESET NMO SELECT 17 NON_MUXED_OUT 0 16 MUX_OUT A GND 15 MUX_OUT B WRITE OE PROTECT MUX_IN A MUX_IN B 5-BIT 2 to 1 DEMULTIPLEXER 19 LATCH SCL 2 I C/SMBus CONTROL LOGIC 1 MUX_OUT C MUX_OUT D MUX_OUT E 14 13 12 MUX_IN C MUX_IN D 1 9 MUX_IN E 10-30 kΩ SW00400 Figure 1. Block diagram of PCA9559 PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 3 / 20 NXP Semiconductors 2 PCA9559 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch 5 Pinning information 5.1 Pinning SCL 1 20 VCC SDA 2 19 WP A1 3 18 OVERRIDE_N A0 4 17 NON_MUXED_OUT MUX_IN A 5 MUX_IN B 6 PCA9559 16 MUX_OUT A 15 MUX_OUT B MUX_IN C 7 14 MUX_OUT C MUX_IN D 8 13 MUX_OUT D MUX_IN E 9 12 MUX_OUT E GND 10 11 MUX_SELECT aaa-044311 Figure 2. Pin configuration for TSSOP20 5.2 Pin description Table 3. Pin description Symbol Pin Description SCL 1 serial I C-bus clock line SDA 2 serial bidirectional I C-bus data line A1 3 address 1 A0 4 address 0 MUX_IN_A 5 external input A to multiplexer MUX_IN_B 6 external input B to multiplexer MUX_IN_C 7 external input C to multiplexer MUX_IN_D 8 external input D to multiplexer MUX_IN_E 9 external input E to multiplexer GND 10 ground MUX_SELECT 11 selects MUX_IN inputs or register contents for MUX_OUT outputs MUX_OUT_E 12 open-drain multiplexed output E MUX_OUT_D 13 open-drain multiplexed output D MUX_OUT_C 14 open-drain multiplexed output C MUX_OUT_B 15 open-drain multiplexed output B MUX_OUT_A 16 open-drain multiplexed output A NON-MUXED_OUT 17 open-drain output from non-volatile memory OVERRIDE_N 18 forces all outputs to logic 0 WP 19 non-volatile register write-protect VCC 20 supply voltage (3.0 V to 3.6 V) PCA9559 Product data sheet 2 2 All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 4 / 20 NXP Semiconductors 2 PCA9559 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch 6 Functional description When the MUX_SELECT signal is logic 0, the multiplexer will select the data from the non-volatile register to drive on the MUX_OUT pins. When the MUX_SELECT signal is logic 1, the multiplexer will select the MUX_IN lines to drive on the MUX_OUT pins. The MUX_SELECT signal is also used to latch the NON_MUXED_OUT signal which outputs data from the non-volatile register. The NON_MUXED_OUT signal latch is transparent when MUX_SELECT is in a logic 0 state, and will latch data when MUX_SELECT is in a logic 1 state. When the active-LOW OVERRIDE_N signal is set to logic 0 and the MUX_SELECT signal is at a logic 0, all outputs will be driven to logic 0. This information is summarized in Table 4. The Write Protect (WP) input is used to control the ability to write the contents of the 62 bit non-volatile register. If the WP signal is logic 0, the I C-bus will be able to write the contents of the non-volatile register. If the WP signal is logic 1, data will not be allowed to be written into the non-volatile register. The factory default for the contents of the non-volatile register are all logic 0. These 2 stored values can be read or written using the I C-bus (described in Section 6.1). The OVERRIDE_N, WP, MUX_IN, and MUX_SELECT signals have internal pull-up resistors. See Section 11 and Section 10 for hysteresis and signal spike suppression figures. Table 4. Function table OVERRIDE_N MUX_SELECT MUX_OUT OUTPUTS 0 0 0 1 All 0s MUX_IN inputs 1 0 1 1 From non-volatile register MUX_IN inputs [1] NON_MUXED_OUT OUTPUT All 0s latched NON[1] MUXED_OUT From non-volatile register From non-volatile register NON_MUXED_OUT state will be the value present on the output at the time of the MUX_SELECT input transitioned from a logic 0 to a logic 1 state. 2 6.1 I C-bus interface 2 Communicating with this device is initiated by sending a valid address on the I C-bus. The address format has 5 fixed bits and two user-programmable bits followed by a 1-bit read/write value which determines the direction of the data transfer. MSB 1 LSB 0 0 1 fixed 1 A1 A0 R/W hardware selectable 002aah287 2 Figure 3. I C address byte Following the address and acknowledge bit are 8 data bits which, depending on the read/ write bit in the address, will read data from or write data to the non-volatile register. Data will be written to the register if the read/write bit is logic 0 and the WP input is logic 0. PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 5 / 20 PCA9559 NXP Semiconductors 2 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch Data will be read from the register if the bit is logic 1. The four high-order bits are latched outputs, while the four low order bits are multiplexed outputs (Figure 4). NOTE: To ensure data integrity, the non-volatile register must be internally write protected 2 when VCC to the I C-bus is powered down or VCC to the component is dropped below normal operating levels. MSB LSB 0 0 NONMUX MUXED DATA E DATA MUX DATA D MUX DATA C MUX DATA B MUX DATA A aaa-044312 2 Figure 4. I C data byte 6.2 Power-on reset When power is applied to VCC, an internal Power-On Reset (POR) holds the PCA9559 in a reset state until VCC has reached VPOR. At that point, the reset condition is released 2 and the PCA9559 volatile registers and I C/SMBus state machine will initialize to their default states. The MUX_OUT and NON_MUXED_OUT pin values depend on: • The OVERRIDE # and MUX_SELECT logic levels • The previously stored values in the EEPROM registers/current MUX_IN pin values as shown in Table 1. 7 Limiting values [1] [2] Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage VI input voltage VO output voltage Tstg storage temperature [1] [2] [3] Conditions [3] [3] Min Max Unit -0.5 +4.6 V -1.5 VCC + 1.5 V -0.5 VCC + 1.5 V -60 +150 °C Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 8 Recommended operating conditions Table 6. Operating conditions Symbol Parameter VCC supply voltage VIL LOW-level input voltage PCA9559 Product data sheet Conditions SCL, SDA; IOL = 3 mA All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 Min Max Unit 3.0 3.6 V -0.5 +0.9 V © NXP B.V. 2021. All rights reserved. 6 / 20 PCA9559 NXP Semiconductors 2 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch Table 6. Operating conditions...continued Symbol Parameter Conditions Min Max Unit VIH HIGH-level input voltage SCL, SDA; IOL = 3 mA 2.7 4.0 V VOL LOW-level output voltage SCL, SDA IOL = 3 mA - 0.4 V IOL = 6 mA - 0.6 V VIL LOW-level input voltage OVERRIDE_N, MUX_IN, MUX_SELECT -0.5 +0.8 V VIH HIGH-level input voltage OVERRIDE_N, MUX_IN, MUX_SELECT 2.0 4.0 V IOL LOW-level output current MUX_OUT, NON_MUXED_ OUT - 8 mA IOH HIGH-level output current MUX_OUT, NON_MUXED_ OUT - 100 μA Δt/ΔV input transition rise and fall rate 0 10 ns/V Tamb ambient temperature 0 70 °C 9 Thermal characteristics Table 7. Thermal characteristics Symbol Parameter Conditions Typ Unit Rth(j-a) thermal resistance from junction to ambient TSSOP20 package 146 °C/W 10 Static characteristics Table 8. Static characteristics VHYS is the hysteresis of Schmitt-Trigger inputs Symbol Parameter Conditions Min Typ Max Unit 3 - 3.8 V all inputs = 0 V - - 10 mA all inputs = VCC - - 600 μA - 1.9 2.6 V Supply VCC supply voltage IDD supply current VPOR operating mode power-on reset voltage no load; VI = VCC or GND Input SCL; input/output SDA VIL LOW-level input voltage -0.5 - +0.8 V VIH HIGH-level input voltage 2 - VCC = 0.5 V IOL LOW-level output current VOL = 0.4 V 3 - - mA VOL = 0.6 V 6 - - mA ILIH HIGH-level input leakage current VI = VCC -1.5 - -12 μA ILIL LOW-level input leakage current VI = GND -7 - -32 μA PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 7 / 20 PCA9559 NXP Semiconductors 2 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch Table 8. Static characteristics...continued VHYS is the hysteresis of Schmitt-Trigger inputs Symbol Parameter Ci input capacitance Conditions Min Typ Max Unit - - 10 pF OVERRIDE_N, WP, MUX_SELECT ILIH HIGH-level input leakage current VI = VCC -20 - -100 μA ILIL LOW-level input leakage current VI = GND -86 - -267 μA Ci input capacitance - - 10 pF MUX_IN_A, MUX_IN_B, MUX_IN_C, MUX_IN_D, MUX_IN_E ILIH HIGH-level input leakage current VI = VCC -0.166 - -0.75 mA ILIL LOW-level input leakage current VI = GND -0.72 - -2 mA Ci input capacitance 10 pF - Inputs A0, A1 ILIH HIGH-level input leakage current VI = VCC -1 - +1 μA IIL LOW-level input current VI = GND -1 - +1 μA Ci input capacitance - - 10 pF IOL = 100 μA - - 0.4 V IOL = 2 mA - - 0.7 V IOL = 100 μA - - 0.4 V IOL = 2 mA - - 0.7 V Min Typ Max Unit MUX_OUT E ⇒ A VOL LOW-level output voltage NON-MUX_OUT VOL LOW-level output voltage 11 Dynamic characteristics Table 9. Dynamic characteristics Symbol Parameter Conditions MUX_IN ⇒ MUX_OUT tPLH LOW to HIGH propagation delay - 28 37 ns tPHL HIGH to LOW propagation delay - 16 21 ns Select ⇒ MUX_OUT tPLH LOW to HIGH propagation delay - 30 39 ns tPHL HIGH to LOW propagation delay - 17 22 ns OVERRIDE_N ⇒ NON-MUX_OUT tPLH LOW to HIGH propagation delay - 34 43 ns tPHL HIGH to LOW propagation delay - 19 25 ns OVERRIDE_N ⇒ MUX_OUT tPLH LOW to HIGH propagation delay - 31 41 ns tPHL HIGH to LOW propagation delay - 21 27 ns PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 8 / 20 PCA9559 NXP Semiconductors 2 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch Table 9. Dynamic characteristics...continued Symbol Parameter Conditions Min Typ Max Unit tr rise time output 1.0 - 3 ns/V tf fall time output 1.0 - 3 ns/V PF Pull-up resistor for outputs 1.0 - - ns/V CL load capacitance - - - pF test load on outputs 2 I C-bus fSCL SCL clock frequency 10 - 400 kHz tBUF bus free time between a STOP and START condition 1.3 - - µs tHD;STA hold time (repeated) START condition 600 - - ns tLOW LOW period of the SCL clock 1.3 - - µs tHIGH HIGH period of the SCL clock 600 - -12 ns tSU;STA set-up time for a repeated START condition 600 - -32 ns tHD;DAT data hold time 0 - 10 ns tSU;DAT data set-up time 100 - -100 ns tSP pulse width of spikes that must be suppressed by the input filters 0 - 50 ns tSU;STO set-up time for STOP condition 600 - 10 ns tr rise time of both SDA and SCL signals 10 - 400 pF bus 20 - 300 ns tf fall time of both SDA and SCL signals 10 - 400 pF bus 20 - 300 ns CL tW load capacitance [1] write cycle time for each bus line - 15 400 - pF ms [1] After this period, the first clock pulse is generated 2 WRITE CYCLE time can only be measured indirectly during the write cycle. During this time, the device will not acknowledge its I C Address. 0.7 × VDD SDA 0.3 × VDD tr tBUF tf tHD;STA tSP tLOW 0.7 × VDD SCL 0.3 × VDD P S tHD;STA tHD;DAT tHIGH tSU;DAT Sr tSU;STA tSU;STO P 002aaa986 Figure 5. Definition of timing PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 9 / 20 PCA9559 NXP Semiconductors 2 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch MUX input VM VM tPLZ tPHL MUX output VM VO VOL + 0.3 V VOL 002aah292 Figure 6. Open-drain output enable and disable times 12 Non-volatile storage specifications Table 10. Non-volatile storage specifications Parameter Specification memory cell data retention 10 years (minimum) number of memory cell write cycles 100,000 cycles (minimum) 2 Application note AN250, "I C DIP Switch" provides additional information on memory cell data retention and the minimum number of write cycles. 13 Test information VO VDD PULSE GENERATOR VI DUT RT VO RL CL 002aah293 RL = load resistor; 1 kΩ. CL = load capacitance; includes jig and probe capacitance; 10 pF. RT = termination resistance; should be equal to Zo of pulse generators. Figure 7. Test circuit for open-drain outputs PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 10 / 20 PCA9559 NXP Semiconductors 2 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch 14 Package outline TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm D SOT360-1 E A X c HE y v M A Z 11 20 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Figure 8. Package outline SOT360-1 (TSSOP20) PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 11 / 20 NXP Semiconductors 2 PCA9559 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch 15 Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”. 15.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 15.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: • Through-hole components • Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: • • • • • • Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 15.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 15.4 Reflow soldering Key characteristics in reflow soldering are: PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 12 / 20 NXP Semiconductors 2 PCA9559 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 9) than a SnPb process, thus reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 11 and Table 12 Table 11. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 ≥ 350 < 2.5 235 220 ≥ 2.5 220 220 Table 12. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (°C) Volume (mm³) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 9. PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 13 / 20 NXP Semiconductors 2 PCA9559 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Figure 9. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 14 / 20 PCA9559 NXP Semiconductors 2 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch 16 Soldering: PCB footprints Footprint information for reflow soldering of TSSOP20 package SOT360-1 Hx Gx P2 (0.125) Hy Gy (0.125) By Ay C D2 (4x) D1 P1 Generic footprint pattern Refer to the package outline drawing for actual layout solder land occupied area DIMENSIONS in mm P1 P2 Ay By C D1 D2 Gx Gy Hx Hy 0.650 0.750 7.200 4.500 1.350 0.400 0.600 6.900 5.300 7.300 7.450 sot360-1_fr Figure 10. PCB footprint for SOT360-1 (TSSOP20); reflow soldering PCA9559 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 15 / 20 PCA9559 NXP Semiconductors 2 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch 17 Abbreviations Table 13. Abbreviations Acronym Description CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor CPU Central Processing Unit DIP Dual In-line Package EEPROM Electrically Erasable Programmable Read-Only Memory ESD ElectroStatic Discharge HBM Human Body Model 2 I C-bus Inter-Integrated Circuit bus PCB Printed-Circuit Board SMBus System Management Bus VID Voltage IDentification code VRM Voltage Regulator Module 18 Revision history Table 14. Revision history Document ID Release date Data sheet status Change notice Supersedes PCA9559 v.5 20211025 Product data sheet - PCA9559 v.4 Modifications: • The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Section 2: MM is removed from data sheet during update as no longer required. • Removed PCA9959PW,112; tube pack method was discontinued DN86 July 2017. PCA9559 v.4 20030627 PCA9559 Product data sheet Product data sheet - All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 PCA9559 v.3 © NXP B.V. 2021. All rights reserved. 16 / 20 NXP Semiconductors 2 PCA9559 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch 19 Legal information 19.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] [2] [3] Please consult the most recently issued document before initiating or completing a design. The term 'short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 19.2 Definitions Draft — A draft status on a document indicates that the content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included in a draft version of a document and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. 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PCA9559 Product data sheet Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 17 / 20 NXP Semiconductors 2 PCA9559 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Suitability for use in non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. PCA9559 Product data sheet Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 19.4 Trademarks Notice: All referenced brands, product names, service names, and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. I2C-bus — logo is a trademark of NXP B.V. All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 18 / 20 NXP Semiconductors 2 PCA9559 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch Tables Tab. 1. Tab. 2. Tab. 3. Tab. 4. Tab. 5. Tab. 6. Tab. 7. Ordering information ..........................................2 Ordering options ................................................2 Pin description ...................................................4 Function table ....................................................5 Limiting values .................................................. 6 Operating conditions ......................................... 6 Thermal characteristics ..................................... 7 Tab. 8. Tab. 9. Tab. 10. Tab. 11. Tab. 12. Tab. 13. Tab. 14. Static characteristics ......................................... 7 Dynamic characteristics .................................... 8 Non-volatile storage specifications .................. 10 SnPb eutectic process (from J-STD-020D) ..... 13 Lead-free process (from J-STD-020D) ............ 13 Abbreviations ...................................................16 Revision history ...............................................16 Fig. 7. Fig. 8. Fig. 9. Test circuit for open-drain outputs ................... 10 Package outline SOT360-1 (TSSOP20) ..........11 Temperature profiles for large and small components ..................................................... 14 PCB footprint for SOT360-1 (TSSOP20); reflow soldering ............................................... 15 Figures Fig. 1. Fig. 2. Fig. 3. Fig. 4. Fig. 5. Fig. 6. Block diagram of PCA9559 ...............................3 Pin configuration for TSSOP20 ......................... 4 I2C address byte ...............................................5 I2C data byte .................................................... 6 Definition of timing ............................................ 9 Open-drain output enable and disable times ................................................................ 10 PCA9559 Product data sheet Fig. 10. All information provided in this document is subject to legal disclaimers. Rev. 5.0 — 25 October 2021 © NXP B.V. 2021. All rights reserved. 19 / 20 NXP Semiconductors 2 PCA9559 5-bit multiplexed/1-bit latched 6-bit I C-bus EEPROM DIP switch Contents 1 2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 18 19 General description ............................................ 1 Features and benefits .........................................1 Ordering information .......................................... 2 Ordering options ................................................ 2 Block diagram ..................................................... 3 Pinning information ............................................ 4 Pinning ............................................................... 4 Pin description ................................................... 4 Functional description ........................................5 I2C-bus interface ............................................... 5 Power-on reset .................................................. 6 Limiting values .................................................... 6 Recommended operating conditions ................ 6 Thermal characteristics ......................................7 Static characteristics .......................................... 7 Dynamic characteristics .....................................8 Non-volatile storage specifications .................10 Test information ................................................ 10 Package outline .................................................11 Soldering of SMD packages .............................12 Introduction to soldering .................................. 12 Wave and reflow soldering .............................. 12 Wave soldering ................................................ 12 Reflow soldering .............................................. 12 Soldering: PCB footprints ................................ 15 Abbreviations .................................................... 16 Revision history ................................................ 16 Legal information .............................................. 17 © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 October 2021 Document identifier: PCA9559