AD9648TCPZ-125-EP

14-Bit, 125 MSPS, 1.8 V Dual Analog-to-Digital Converter AD9648-EP Enhanced Product FEATURES FUNCTIONAL BLOCK DIAGRAM AVDD ADC VIN–A VREF SENSE RBIAS VIN–B ADC VIN+B D13A D0A DCOA DRVDD DIVIDE 1 TO 8 DUTY CYCLE STABILIZER MODE CONTROLS SYNC DCS PDWN DFS OEB ORB D13B D0B DCOB NOTES 1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY; SEE FIGURE 7 FOR LVDS PIN NAMES. Figure 1. PRODUCT HIGHLIGHTS 1. APPLICATIONS Communications Diversity radio systems Multimode digital receivers GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA I/Q demodulation systems Smart antenna systems Broadband data applications Battery-powered instruments Handheld scope meters Portable medical imaging Ultrasound Radar/LIDAR AD9648-EP REF SELECT CMOS/LVDS OUTPUT BUFFER VCM ORA 13386-001 Supports defense and aerospace applications (AQEC standard) Military temperature range: −55°C to +125°C Controlled manufacturing baseline Qualification data available on request Rev. B PROGRAMMING DATA VIN+A CMOS/LVDS OUTPUT BUFFER SPI CLK+ CLK– ENHANCED PRODUCT FEATURES SDIO SCLK CSB AGND MUX OPTION 1.8 V analog supply operation 1.8 V CMOS or LVDS outputs SNR = 74.5 dBFS at 70 MHz SFDR = 91 dBc at 70 MHz Low power: 106 mW/channel at 125 MSPS Differential analog input with 650 MHz bandwidth IF sampling frequencies to 200 MHz On-chip voltage reference and sample-and-hold circuit 2 V p-p differential analog input DNL = ±0.5 LSB at 25°C Serial port control options Offset binary, gray code, or twos complement data format Optional clock duty cycle stabilizer Integer 1-to-8 input clock divider Data output multiplex option Built-in selectable digital test pattern generation Energy-saving power-down modes Data clock out with programmable clock and data alignment 2. 3. 4. The AD9648-EP operates from a single 1.8 V analog power supply and features a separate digital output driver supply to accommodate 1.8 V CMOS or LVDS logic families. The sample-and-hold circuit maintains excellent performance for input frequencies up to 200 MHz and is designed for low cost, low power, and ease of use. A standard serial port interface supports various product features and functions, such as data output formatting, internal clock divider, power-down, DCO/data timing and offset adjustments. The AD9648-EP is packaged in a 64-lead, RoHS-compliant LFCSP that is pin-compatible with the AD9650/AD9269/ AD9268 16-bit ADC, the AD9258 14-bit ADC, the AD9628/ AD9231 12-bit ADCs, and the AD9608/AD9204 10-bit ADCs, enabling a simple migration path between 10-bit and 16-bit converters sampling from 20 MSPS to 125 MSPS. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9648-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Digital Specifications ....................................................................6 Enhanced Product Features ............................................................ 1 Switching Specifications .................................................................7 Applications ....................................................................................... 1 Timing Specifications ...................................................................8 Functional Block Diagram .............................................................. 1 Absolute Maximum Ratings ......................................................... 10 Product Highlights ........................................................................... 1 Thermal Characteristics ............................................................ 10 Revision History ............................................................................... 2 ESD Caution................................................................................ 10 General Description ......................................................................... 3 Pin Configurations and Function Descriptions ......................... 11 Specifications..................................................................................... 4 Outline Dimensions ....................................................................... 17 DC Specifications ........................................................................... 4 Ordering Guide .......................................................................... 17 AC Specifications ........................................................................... 5 REVISION HISTORY 1/16—Rev. A to Rev. B Change to Product Highlights Section .......................................... 1 Changes to General Description Section ...................................... 3 Change to Differential Nonlinearity (DNL) Parameter, Table 1 ................................................................................................ 4 Changes to Signal-to-Noise-Ratio (SNR) Parameter, Signal-toNoise and Distortion (SINAD) Parameter, and Worst Other (Harmonic or Spur) Parameter, Table 2 ........................................ 5 Changes to Table 6 .......................................................................... 10 12/15—Rev. 0 to Rev. A Changes to Figure 3 ...........................................................................8 Changes to Figure 4 ...........................................................................9 9/15—Revision 0: Initial Version Rev. B | Page 2 of 17 Enhanced Product AD9648-EP GENERAL DESCRIPTION The AD9648-EP is a monolithic, dual-channel, 1.8 V supply, 14-bit, 125 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range. The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Output logic levels of 1.8 V CMOS or LVDS are supported. Output data can also be multiplexed onto a single output bus. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). The AD9648-EP is available in a 64-lead RoHS-compliant LFCSP and is specified over the −55°C to +125°C temperature range. Additional information, including Typical Performance Characteristics at 125 MSPS, can be found in the AD9648 data sheet. Rev. B | Page 3 of 17 AD9648-EP Enhanced Product SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL)1 Integral Nonlinearity (INL)1 MATCHING CHARACTERISTIC Offset Error Gain Error TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation Error at 1.0 mA INPUT REFERRED NOISE VREF = 1.0 V ANALOG INPUT Input Span, VREF = 1.0 V Input Capacitance2 Input Resistance (Differential) Input Common-Mode Voltage Input Common-Mode Range POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD1 IDRVDD (1.8 V CMOS)1 IDRVDD(1.8 V LVDS)1 POWER CONSUMPTION DC Input Sine Wave Input (DRVDD = 1.8 V CMOS Output Mode) Sine Wave Input (DRVDD = 1.8 V LVDS Output Mode) Standby Power3 Power-Down Power 1 2 3 Temperature Full Full Full Full Full 25°C Full 25°C Min 14 −0.8 −6.3 −0.7 Typ Guaranteed −0.3 ±1.3 Unit Bits +0.2 +6.3 +1.3 % FSR % FSR LSB LSB LSB LSB ±0.5 −2.6 +2.6 ±1.0 Full Full ±0.01 ±0.5 Full Full ±2 ±50 Full Full Max 0.98 1.00 2 ±0.8 ±7.0 % FSR % FSR ppm/°C ppm/°C 1.02 V mV 25°C 0.98 LSB rms Full Full Full Full Full 2 5 7.5 0.9 0.5 1.3 V p-p pF kΩ V V Full Full 1.7 1.7 1.8 1.8 1.9 1.9 V V Full Full Full 95 22.5 65.0 100 23.8 66.4 mA mA mA Full Full Full Full Full 155.5 211.5 288 120 2.0 Measure with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit. Input capacitance refers to the effective capacitance between one differential input pin and AGND. Standby power is measured with a dc input and with the CLK± pins active (1.8 V CMOS mode). Rev. B | Page 4 of 17 223 300 mW mW mW mW mW Enhanced Product AD9648-EP AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless otherwise noted. Table 2. Parameter1 SIGNAL-TO-NOISE-RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz Temperature 25°C 25°C 25°C Full 25°C 25°C fIN = 100 MHz fIN = 200 MHz SIGNAL-TO-NOISE AND DISTORTION (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz 25°C 25°C 25°C Full 25°C 25°C fIN = 100 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz WORST SECOND OR THIRD HARMONIC fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz WORST OTHER (HARMONIC OR SPUR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 100 MHz fIN = 200 MHz TWO-TONE SFDR fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS ) CROSSTALK2 ANALOG INPUT BANDWIDTH 1 2 Max 75.0 74.7 74.5 Unit dBFS dBFS dBFS dBFS dBFS dBFS 72.5 73.9 71.5 73.9 73.4 73.3 72.8 70.3 12 11.9 11.9 11.8 11.4 Bits Bits Bits Bits Bits 25°C 25°C 25°C Full 25°C 25°C −96 −90 −91 dBc dBc dBc dBc dBc dBc 25°C 25°C 25°C Full 25°C 25°C 96 90 91 72.3 11.8 −82 −90 −84 dBc dBc dBc dBc dBc dBc 82 90 84 25°C 25°C 25°C Full 25°C 25°C −97 −97 −97 −92 −90 dBc dBc dBc dBc dBc dBc 25°C Full 25°C 84 −95 650 dBc dB MHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions. Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel. Rev. B | Page 5 of 17 Typ dBFS dBFS dBFS dBFS dBFS dBFS 25°C 25°C Full 25°C 25°C fIN = 100 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz Min −89 AD9648-EP Enhanced Product DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 3. Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Current Low Level Input Current Input Capacitance Input Resistance LOGIC INPUT (CSB)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT (SCLK/DFS/SYNC)2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 1.8 V) Low Level Input Current Input Resistance Input Capacitance LOGIC INPUT/OUTPUT (SDIO/DCS)1 High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Resistance Input Capacitance LOGIC INPUTS (OEB, PDWN)2 High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = 1.8 V) Low Level Input Current Input Resistance Input Capacitance Temperature Min Full Full Full Full Full Full Full Full CMOS/LVDS/LVPECL 0.9 0.3 3.6 AGND − 0.3 AVDD + 0.2 0.9 1.4 −10 +10 −10 +10 4 8 10 12 Full Full Full Full Full Full 1.22 0 −10 40 Full Full Full Full Full Full 1.22 0 −92 −10 Full Full Full Full Full Full 1.22 0 −10 38 Full Full Full Full Full Full 1.22 0 −90 −10 Rev. B | Page 6 of 17 Typ Max V V p-p V V µA µA pF kΩ DRVDD + 0.2 0.6 +10 132 V V µA µA kΩ pF DRVDD + 0.2 0.6 −135 +10 V V µA µA kΩ pF DRVDD + 0.2 0.6 +10 128 V V µA µA kΩ pF DRVDD + 0.2 0.6 −134 +10 V V µA µA kΩ pF 26 2 26 2 26 5 26 5 Unit Enhanced Product Parameter DIGITAL OUTPUTS CMOS Mode—DRVDD = 1.8 V High Level Output Voltage IOH = 50 µA IOH = 0.5 mA Low Level Output Voltage IOL = 1.6 mA IOL = 50 µA LVDS Mode—DRVDD = 1.8 V Differential Output Voltage (VOD), ANSI Mode Output Offset Voltage (VOS), ANSI Mode Differential Output Voltage (VOD), Reduced Swing Mode Output Offset Voltage (VOS), Reduced Swing Mode 1 2 AD9648-EP Temperature Min Full Full 1.79 1.75 Typ Max V V Full Full Full Full Full Full 290 1.15 160 1.15 Unit 345 1.25 200 1.25 0.2 0.05 V V 400 1.35 230 1.35 mV V mV V Pull up. Pull down. SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, and DCS enabled, unless otherwise noted. Table 4. Parameter CLOCK INPUT PARAMETERS Input Clock Rate Conversion Rate1 DCS Enabled DCS Disabled CLK Period—Divide-by-1 Mode (tCLK) CLK Pulse Width High (tCH) Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) DATA OUTPUT PARAMETERS CMOS Mode (DRVDD = 1.8 V) Data Propagation Delay (tPD) DCO Propagation Delay (tDCO)2 DCO to Data Skew (tSKEW) LVDS Mode (DRVDD = 1.8 V) Data Propagation Delay (tPD) DCO Propagation Delay (tDCO)2 DCO to Data Skew (tSKEW) CMOS Mode Pipeline Delay (Latency) LVDS Mode Pipeline Delay (Latency) Channel A/Channel B Wake-Up Time (Power Down)3 Wake-Up Time (Standby) Out-of-Range Recovery Time Temperature Min Typ Full Full Full Full Full Full Full 20 10 Full Full Full 1.8 2.0 −1.2 Full Full Full Full Full Full Full Full 1 Conversion rate is the clock rate after the divider. Additional DCO delay can be added by writing to Bits[2:0] in SPI Register 0x17 (see the standard AD9648 datasheet). 3 Wake-up time is defined as the time required to return to normal operation from power-down mode. 2 Rev. B | Page 7 of 17 Max Unit 1000 MHz 125 125 MSPS MSPS ns ns ns ps rms 4.4 4.4 +1.0 ns ns ns 8 4 1.0 0.137 −0.20 2.9 3.1 −0.1 2.4 2.4 +0.03 16 16/16.5 350 250 2 +0.25 ns ns ns Cycles Cycles µs ns Cycles AD9648-EP Enhanced Product TIMING SPECIFICATIONS Table 5. Parameter SYNC TIMING REQUIREMENTS tSSYNC tHSYNC SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO tDIS_SDIO Description Limit Unit SYNC to rising edge of CLK+ setup time SYNC to rising edge of CLK+ hold time 0.24 0.40 ns typ ns typ Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK SCLK pulse width high SCLK pulse width low Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge 2 2 40 2 2 10 10 10 ns min ns min ns min ns min ns min ns min ns min ns min 10 ns min Timing Diagrams N–1 N+4 tA N+5 N N+3 VIN N+1 tCH N+2 tCLK CLK+ CLK– tDCO DCOA/DCOB tSKEW N – 17 N – 16 N – 15 N – 14 N – 13 N – 12 13386-002 CH A/CH B DATA tPD Figure 2. CMOS Default Output Mode Data Output Timing N–1 N+4 tA N+5 N N+3 VIN N+1 tCH N+2 tCLK CLK+ CLK– t DCO DCOA/DCOB t SKEW CH A CH B CH A CH B CH A CH B CH A CH B CH A N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 CH A DATA CH B CH A CH B CH A CH B CH A CH B CH A CH B N – 16 N – 16 N – 15 N – 15 N – 14 N – 14 N – 13 N – 13 N – 12 Figure 3. CMOS Interleaved Output Mode Data Output Timing Rev. B | Page 8 of 17 13386-003 t PD CH B DATA Enhanced Product AD9648-EP N–1 N+4 tA N+5 N N+3 VIN N+1 tCH N+2 tCLK CLK+ CLK– tDCO DCO+ DCO– tSKEW D0+ (LSB) PARALLEL INTERLEAVED MODE D0– (LSB) D13+ (MSB) D13– (MSB) D1+/0+ (LSB) CHANNEL MULTIPLEXED MODE D1–/D0– (LSB) CHANNEL A D13+/D12+ (MSB) D13–/D12– (MSB) D1+/D0+ (LSB) CHANNEL MULTIPLEXED MODE D1–/D0– (LSB) CHANNEL B D13+/D12+ (MSB) D13–/D12– (MSB) CH A N – 16 CH B N – 16 CH A N – 15 CH B N – 15 CH A N – 14 CH B N – 14 CH A N – 13 CH B N – 13 CH A N – 12 CH A N – 16 CH B N – 16 CH A N – 15 CH B N – 15 CH A N – 14 CH B N – 14 CH A N – 13 CH B N – 13 CH A N – 12 CH A0 N – 16 CH A1 N – 16 CH A0 N – 15 CH A1 N – 15 CH A0 N – 14 CH A1 N – 14 CH A0 N – 13 CH A1 N – 13 CH A0 N – 12 CH A12 N – 16 CH A13 N – 16 CH A12 N – 15 CH A13 N – 15 CH A12 N – 14 CH A13 N – 14 CH A12 N – 13 CH A13 N – 13 CH A12 N – 12 CH B0 N – 16 CH B1 N – 16 CH B0 N – 15 CH B1 N – 15 CH B0 N – 14 CH B1 N – 14 CH B0 N – 13 CH B1 N – 13 CH B0 N – 12 CH B12 N – 16 CH B13 N – 16 CH B12 N – 15 CH B13 N – 15 CH B12 N – 14 CH B13 N – 14 CH A12 N – 13 CH A13 N – 13 CH A12 N – 12 Figure 4. LVDS Modes for Data Output Timing CLK+ tHSYNC 13386-005 tSSYNC SYNC Figure 5. SYNC Input Timing Requirements Rev. B | Page 9 of 17 13386-004 tPD AD9648-EP Enhanced Product ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical AVDD to AGND DRVDD to AGND VIN+A/VIN+B, VIN−A/VIN−B to AGND CLK+, CLK− to AGND SYNC to DRVDD VCM to AGND RBIAS to AGND CSB to AGND SCLK/DFS to AGND SDIO/DCS to AGND OEB PDWN D0A/D0B through D13A/D13B to AGND DCOA/DCOB to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Under Bias Storage Temperature Range (Ambient) Rating −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to AVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −0.3 V to DRVDD + 0.2 V −55°C to +125°C 150°C The exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the printed circuit board (PCB) increases the reliability of the solder joints and maximizes the thermal capability of the package. Table 7. Thermal Resistance Package Type 64-Lead LFCSP 9 mm × 9 mm (CP-64-4) Airflow Velocity (m/sec) 0 1.0 2.5 θJA1, 2 22.3 19.5 17.5 θJC1, 3 1.4 N/A N/A θJB1, 4 11.8 N/A N/A ΨJT1,2 0.1 0.2 0.2 Unit °C/W °C/W °C/W 1 Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 2 3 Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown Table 7, airflow improves heat dissipation, which reduces θJA. In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces θJA. ESD CAUTION −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 10 of 17 Enhanced Product AD9648-EP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD9648-EP PARALLEL CMOS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS ORA D13A (MSB) D12A D11A D10A D9A DRVDD D8A D7A D6A D5A NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE DEVICE. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 13386-006 D10B D11B DRVDD D12B D13B (MSB) ORB DCOB DCOA NC NC D0A (LSB) DRVDD D1A D2A D3A D4A 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK+ CLK– SYNC NC NC D0B (LSB) D1B D2B D3B DRVDD D4B D5B D6B D7B D8B D9B Figure 6. Parallel CMOS Pin Configuration (Top View) Table 8. Pin Function Descriptions (Parallel CMOS Mode) Pin No. Mnemonic ADC Power Supplies 10, 19, 28, 37 DRVDD 49, 50, 53, 54, AVDD 59, 60, 63, 64 4, 5, 25, 26 NC 0 AGND, Exposed Pad ADC Analog 51 52 62 61 55 56 58 57 1 2 Digital Input 3 Type Description Supply Supply Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). Ground No Connect. Do not connect to these pins. The exposed thermal pad on the bottom of the package provides the analog ground for the device. This exposed pad must be connected to ground for proper operation. VIN+A VIN−A VIN+B VIN−B VREF SENSE RBIAS VCM CLK+ CLK− Input Input Input Input Input/Output Input Input/Output Output Input Input Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Reference Mode Selection. External Reference Bias Resistor. Connect to a 10 kΩ (1% tolerance) resistor to ground. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. SYNC Input Digital Synchronization Pin. Slave mode only. Rev. B | Page 11 of 17 AD9648-EP Pin No. Mnemonic Digital Outputs 27 D0A (LSB) 29 D1A 30 D2A 31 D3A 32 D4A 33 D5A 34 D6A 35 D7A 36 D8A 38 D9A 39 D10A 40 D11A 41 D12A 42 D13A (MSB) 43 ORA 6 D0B (LSB) 7 D1B 8 D2B 9 D3B 11 D4B 12 D5B 13 D6B 14 D7B 15 D8B 16 D9B 17 D10B 18 D11B 20 D12B 21 D13B (MSB) 22 ORB 24 DCOA 23 DCOB SPI Control 45 SCLK/DFS 44 SDIO/DCS 46 CSB ADC Configuration 47 OEB 48 PDWN Enhanced Product Type Description Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A CMOS Output Data. Channel A Overrange Output. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B CMOS Output Data. Channel B Overrange Output Channel A Data Clock Output. Channel B Data Clock Output. Input Input/Output Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). Input Input Output Enable Input (Active Low). Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. B | Page 12 of 17 AD9648-EP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD Enhanced Product 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD9648-EP INTERLEAVED PARALLEL LVDS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS OR+ OR– D13+ (MSB) D13– (MSB) D12+ D12– DRVDD D11+ D11– D10+ D10– NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE DEVICE. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 13386-007 D4– D4+ DRVDD D5– D5+ D6– D6+ DCO– DCO+ D7– D7+ DRVDD D8– D8+ D9– D9+ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK+ CLK– SYNC NC NC NC NC D0– (LSB) D0+ (LSB) DRVDD D1– D1+ D2– D2+ D3– D3+ Figure 7. Interleaved Parallel LVDS Pin Configuration (Top View) Table 9. Pin Function Descriptions (Interleaved Parallel LVDS Mode) Pin No. Mnemonic ADC Power Supplies 10, 19, 28, 37 DRVDD 49, 50, 53, 54, AVDD 59, 60, 63, 64 4, 5, 6, 7 NC 0 AGND, Exposed Pad ADC Analog 51 VIN+A 52 VIN−A 62 VIN+B 61 VIN−B 55 VREF 56 SENSE 58 RBIAS 57 VCM 1 CLK+ 2 CLK− Digital Input 3 SYNC Type Description Supply Supply Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). Ground No Connect. Do not connect to these pins. The exposed thermal pad on the bottom of the package provides the analog ground for the device. This exposed pad must be connected to ground for proper operation. Input Input Input Input Input/Output Input Input/Output Output Input Input Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Reference Mode Selection. External Reference Bias Resistor. Connect to a 10 kΩ (1% tolerance) resistor to ground. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. Input Digital Synchronization Pin. Slave mode only. Rev. B | Page 13 of 17 AD9648-EP Pin No. Mnemonic Digital Outputs 9 D0+ (LSB) 8 D0− (LSB) 12 D1+ 11 D1− 14 D2+ 13 D2− 16 D3+ 15 D3− 18 D4+ 17 D4− 21 D5+ 20 D5− 23 D6+ 22 D6− 27 D7+ 26 D7− 30 D8+ 29 D8− 32 D9+ 31 D9− 34 D10+ 33 D10− 36 D11+ 35 D11− 39 D12+ 38 D12− 41 D13+ (MSB) 40 D13− (MSB) 43 OR+ 42 OR− 25 DCO+ 24 DCO− SPI Control 45 SCLK/DFS 44 SDIO/DCS 46 CSB ADC Configuration 47 OEB 48 PDWN Enhanced Product Type Description Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Channel A/Channel B LVDS Output Data 0—True. Channel A/Channel B LVDS Output Data 0—Complement. Channel A/Channel B LVDS Output Data 1—True. Channel A/Channel B LVDS Output Data 1—Complement. Channel A/Channel B LVDS Output Data 2—True. Channel A/Channel B LVDS Output Data 2—Complement. Channel A/Channel B LVDS Output Data 3—True. Channel A/Channel B LVDS Output Data 3—Complement. Channel A/Channel B LVDS Output Data 4—True. Channel A/Channel B LVDS Output Data 4—Complement. Channel A/Channel B LVDS Output Data 5—True. Channel A/Channel B LVDS Output Data 5—Complement. Channel A/Channel B LVDS Output Data 6—True. Channel A/Channel B LVDS Output Data 6—Complement. Channel A/Channel B LVDS Output Data 7—True. Channel A/Channel B LVDS Output Data 7—Complement. Channel A/Channel B LVDS Output Data 8—True. Channel A/Channel B LVDS Output Data 8—Complement. Channel A/Channel B LVDS Output Data 9—True. Channel A/Channel B LVDS Output Data 9—Complement. Channel A/Channel B LVDS Output Data 10—True. Channel A/Channel B LVDS Output Data 10—Complement. Channel A/Channel B LVDS Output Data 11—True. Channel A/Channel B LVDS Output Data 11—Complement. Channel A/Channel B LVDS Output Data 12—True. Channel A/Channel B LVDS Output Data 12—Complement. Channel A/Channel B LVDS Output Data 13—True. Channel A/Channel B LVDS Output Data 13—Complement. Channel A/Channel B LVDS Overrange Output—True. Channel A/Channel B LVDS Overrange Output—Complement. Channel A/Channel B LVDS Data Clock Output—True. Channel A/Channel B LVDS Data Clock Output—Complement. Input Input/Output Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). Input Input Output Enable Input (Active Low). Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. B | Page 14 of 17 AD9648-EP 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVDD AVDD VIN+B VIN–B AVDD AVDD RBIAS VCM SENSE VREF AVDD AVDD VIN–A VIN+A AVDD AVDD Enhanced Product 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AD9648-EP CHANNEL MULTIPLEXED LVDS TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PDWN OEB CSB SCLK/DFS SDIO/DCS OR+ OR– A D13+/D12+ (MSB) A D13–/D12– (MSB) A D11+/D10+ A D11–/D10– DRVDD A D9+/D8+ A D9–/D8– A D7+/D6+ A D7–/D6– NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE DEVICE. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 13386-008 B D9–/D8– B D9+/D8+ DRVDD B D11–/D10– B D11+/D10+ B D13–/D12– (MSB) B D13+/D12+ (MSB) DCO– DCO+ A D1–/D0– (LSB) A D1+/D0+ (LSB) DRVDD A D3–/D2– A D3+/D2+ A D5–/D4– A D5+/D4+ 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CLK+ CLK– SYNC NC NC NC NC B D1–/D0– (LSB) B D1+/D0+ (LSB) DRVDD B D3–/D2– B D3+/D2+ B D5–/D4– B D5+/D4+ B D7–/D6– B D7+/D6+ Figure 8. Channel Multiplexed LVDS Pin Configuration (Top View) Table 10 Pin Function Descriptions (Channel Multiplexed Parallel LVDS Mode) Pin No. Mnemonic ADC Power Supplies 10, 19, 28, 37 DRVDD 49, 50, 53, 54, AVDD 59, 60, 63, 64 4, 5, 6, 7 NC 0 AGND, Exposed Pad ADC Analog 51 52 62 61 55 56 58 57 1 2 Digital Input 3 Type Description Supply Supply Digital Output Driver Supply (1.8 V Nominal). Analog Power Supply (1.8 V Nominal). Ground Do Not Connect. The exposed thermal pad on the bottom of the package provides the analog ground for the device. This exposed pad must be connected to ground for proper operation. VIN+A VIN−A VIN+B VIN−B VREF SENSE RBIAS Input Input Input Input Input/Output Input Input/Output VCM CLK+ CLK− Output Input Input Differential Analog Input Pin (+) for Channel A. Differential Analog Input Pin (−) for Channel A. Differential Analog Input Pin (+) for Channel B. Differential Analog Input Pin (−) for Channel B. Voltage Reference Input/Output. Reference Mode Selection. External Reference Bias Resistor. Connect to a 10 kΩ (1% tolerance) resistor to ground. Common-Mode Level Bias Output for Analog Inputs. ADC Clock Input—True. ADC Clock Input—Complement. SYNC Input Digital Synchronization Pin. Slave mode only. Rev. B | Page 15 of 17 AD9648-EP Pin No. Mnemonic Digital Outputs 8 B D1−/D0− (LSB) 9 B D1+/D0+ (LSB) 11 B D3−/D2− 12 B D3+/D2+ 13 B D5−/D4− 14 B D5+/D4+ 15 B D7−/D6− 16 B D7+/D6+ 17 B D9−/D8− 18 B D9+/D8+ 20 B D11−/D10− 21 B D11+/D10+ 22 B D13−/D12− (MSB) 23 B D13+/D12+ (MSB) 26 A D1−/D0− (LSB) 27 A D1+/D0+ (LSB) 29 A D3−/D2− 30 A D3+/D2+ 32 A D5+/D4+ 31 A D5−/D4− 34 A D7+/D6+ 33 A D7−/D6− 36 A D9+/D8+ 35 A D9−/D8− 39 A D11+/D10+ 38 A D11−/D10− 41 A D13+/D12+ (MSB) 40 A D13−/D12− (MSB) 43 OR+ 42 OR− 25 DCO+ 24 DCO− SPI Control 45 SCLK/DFS 44 SDIO/DCS 46 CSB ADC Configuration 47 OEB 48 PDWN Enhanced Product Type Description Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Channel B LVDS Output Data 1/Data 0—Complement. Channel B LVDS Output Data 1/Data 0—True. Channel B LVDS Output Data 3/Data 2—Complement. Channel B LVDS Output Data 3/Data 2—True. Channel B LVDS Output Data 5/Data 4—Complement. Channel B LVDS Output Data 5/Data 4—True. Channel B LVDS Output Data 7/Data 6—Complement. Channel B LVDS Output Data 7/Data 6—True. Channel B LVDS Output Data 9/Data 8—Complement. Channel B LVDS Output Data 9/Data 8—True. Channel B LVDS Output Data 11/Data 10—Complement. Channel B LVDS Output Data 11/Data 10—True. Channel B LVDS Output Data 13/Data 12—Complement. Channel B LVDS Output Data 13/Data 12—True. Channel A LVDS Output Data 1/Data 0—Complement. Channel A LVDS Output Data 1/Data 0—True. Channel A LVDS Output Data 3/Data 2—Complement. Channel A LVDS Output Data 3/Data 2—True. Channel A LVDS Output Data 5/Data 4—True. Channel A LVDS Output Data 5/Data 4—Complement. Channel A LVDS Output Data 7/Data 6—True. Channel A LVDS Output Data 7/Data 6—Complement. Channel A LVDS Output Data 9/Data 8—True. Channel A LVDS Output Data 9/Data 8—Complement. Channel A LVDS Output Data 11/Data 10—True. Channel A LVDS Output Data 11/Data 10—Complement. Channel A LVDS Output Data 13/Data 12—True. Channel A LVDS Output Data 13/Data 12—Complement. Channel A/Channel B LVDS Overrange Output—True. Channel A/Channel B LVDS Overrange Output—Complement. Channel A/Channel B LVDS Data Clock Output—True. Channel A/Channel B LVDS Data Clock Output—Complement. Input Input/Output Input SPI Serial Clock/Data Format Select Pin in External Pin Mode. SPI Serial Data I/O/Duty Cycle Stabilizer Pin in External Pin Mode. SPI Chip Select (Active Low). Input Input Output Enable Input (Active Low). Power-Down Input in External Pin Mode. In SPI mode, this input can be configured as power-down or standby. Rev. B | Page 16 of 17 Enhanced Product AD9648-EP OUTLINE DIMENSIONS 9.10 9.00 SQ 8.90 0.30 0.25 0.18 PIN 1 INDICATOR PIN 1 INDICATOR 64 49 1 48 0.50 BSC EXPOSED PAD 6.30 6.20 SQ 6.10 33 16 PKG-004559 0.80 0.75 0.70 0.45 0.40 0.35 32 17 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE 0.20 MIN 7.50 REF FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-WMMD 06-06-2014-A TOP VIEW Figure 9. 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 9 mm × 9 mm Body, Very Very Thin Quad (CP-64-17) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9648TCPZ-125-EP AD9648TCPZ125EPRL7 1 Temperature Range −55°C to +125°C −55°C to +125°C Package Description 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. ©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13386-0-1/16(B) Rev. B | Page 17 of 17 Package Option CP-64-17 CP-64-17