16-Bit, 310 MSPS, 3.3 V/1.8 V Dual
Analog-to-Digital Converter (ADC)
AD9652
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD3
AVDD
SDIO
SCLK
CSB
DRVDD
SPI
AD9652
OR+, OR–
PROGRAMMING DATA
VIN+A
VREF
SENSE
VCM
DDR DATA
INTERLEAVER
LVDS OUTPUT
DRIVER
ADC
VIN–A
REF
SELECT
16
D15± (MSB)
TO
D0± (LSB)*
DIVIDE 1
TO 8
CLK+
DUTY CYCLE
STABILIZER
DCO+
CLK–
DCO
GENERATION
DCO–
RBIAS
VIN–B
VIN+B
ADC
MULTICHIP
SYNC
AGND
SYNC
PDWN
*THESE PINS ARE FOR CHANNEL A AND CHANNEL B.
12169-001
High dynamic range
SNR = 75.0 dBFS at 70 MHz (AIN = −1 dBFS)
SFDR = 87 dBc at 70 MHz (AIN = −1 dBFS)
Noise spectral density (NSD) = −156.7 dBFS/Hz input noise
at −1 dBFS at 70 MHz
NSD = −157.6 dBFS/Hz for small signal at −7 dBFS at 70 MHz
90 dB channel isolation/crosstalk
On-chip dithering (improves small signal linearity)
Excellent IF sampling performance
SNR = 73.7 dBFS at 170 MHz (AIN = −1 dBFS)
SFDR = 85 dBc at 170 MHz (AIN = −1 dBFS)
Full power bandwidth of 465 MHz
On-chip 3.3 V buffer
Programmable input span of 2 V p-p to 2.5 V p-p (default)
Differential clock input receiver with 1, 2, 4, and 8 integer
inputs (clock divider input accepts up to 1.24 GHz)
Internal ADC clock duty cycle stabilizer
SYNC input allows multichip synchronization
Total power consumption: 2.16 W
3.3 V and 1.8 V supply voltages
DDR LVDS (ANSI-644 levels) outputs
Serial port control
Energy saving power-down modes
Figure 1.
APPLICATIONS
Military radar and communications
Multimode digital receivers (3G or 4G)
Test and instrumentation
Smart antenna systems
GENERAL DESCRIPTION
The AD9652 is a dual, 16-bit analog-to-digital converter (ADC)
with sampling speeds of up to 310 MSPS. It is designed to
support demanding, high speed signal processing applications
that require exceptional dynamic range over a wide input
frequency range (up to 465 MHz). Its exceptional low noise
floor of −157.6 dBFS and large signal spurious-free dynamic
range (SFDR) performance (exceeding 85 dBFS, typical) allows
low level signals to be resolved in the presence of large signals.
The dual ADC cores feature a multistage, pipelined architecture
with integrated output error correction logic. A high performance
on-chip buffer and internal voltage reference simplify the interface to external driving circuitry while preserving the exceptional
performance of the ADC.
The AD9652 can support input clock frequencies of up to
1.24 GHz with a 1, 2, 4, and 8 integer clock divider to generate
the ADC sample clock. A duty cycle stabilizer is provided to
compensate for variations in the ADC clock duty cycle.
Rev. C
The 16-bit output data (with an overrange bit) from each ADC
is interleaved onto a single LVDS output port along with a
double data rate (DDR) clock. Programming for setup and control
are accomplished using a 3-wire SPI-compatible serial interface.
The AD9652 is available in a 144-ball CSP_BGA and is
specified over the industrial temperature range of −40°C to
+85°C. This product is protected by pending U.S. patents.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
Integrated dual, 16-bit, 310 MSPS ADCs.
On-chip buffer simplifies ADC driver interface.
Operation from 3.3 V and 1.8 V supplies and a separate
digital output driver supply accommodating LVDS outputs.
Proprietary differential input maintains excellent signal-tonoise ratio (SNR) performance for input frequencies of up
to 485 MHz.
SYNC input allows synchronization of multiple devices.
Three-wire, 3.3 V or 1.8 V SPI port for register programming
and readback.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9652
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage Reference ....................................................................... 23
Applications ....................................................................................... 1
Clock Input Considerations ...................................................... 23
Functional Block Diagram .............................................................. 1
Power Dissipation and Standby Mode .................................... 25
General Description ......................................................................... 1
Internal Background Calibration ............................................. 25
Product Highlights ........................................................................... 1
Digital Outputs ........................................................................... 26
Revision History ............................................................................... 2
ADC Overrange.......................................................................... 26
Specifications..................................................................................... 3
Fast Threshold Detection (FDA/FDB) ........................................ 28
ADC DC Specifications ............................................................... 3
Serial Port Interface ........................................................................ 29
ADC AC Specifications ............................................................... 4
Configuration Using the SPI ..................................................... 29
Digital Specifications ................................................................... 5
Hardware Interface..................................................................... 29
Switching Specifications .............................................................. 7
Configuration Without the SPI ................................................ 29
Timing Specifications .................................................................. 7
SPI Accessible Features .............................................................. 30
Absolute Maximum Ratings............................................................ 9
Memory Map .................................................................................. 31
Thermal Characteristics .............................................................. 9
Reading the Memory Map Register Table............................... 31
ESD Caution .................................................................................. 9
Memory Map Register Table ..................................................... 32
Pin Configuration and Function Descriptions ........................... 10
Applications Information .............................................................. 35
Typical Performance Characteristics ........................................... 13
Design Guidelines ...................................................................... 35
Equivalent Circuits ......................................................................... 19
Outline Dimensions ....................................................................... 36
Theory of Operation ...................................................................... 20
Ordering Guide .......................................................................... 36
ADC Architecture ...................................................................... 20
Analog Input Considerations.................................................... 20
REVISION HISTORY
1/2018—Rev. B to Rev. C
Changes to Transfer Register Map Section ................................. 31
Changes to Table 17 ........................................................................ 34
Changes to Ordering Guide .......................................................... 36
5/2014—Rev. 0 to Rev. A
Changes to Supply Current, Clock Divider = 1 Parameter and
Power Consumption, Clock Divider = 1 Parameter, Table 1 .......3
4/2014—Revision 0: Initial Version
1/2017—Rev. A to Rev. B
Changes to DCO± to Data Skew (tSKEW) Parameter, Table 4 ............. 7
Changes to Clock Input Options Section .................................... 24
Rev. C | Page 2 of 36
Data Sheet
AD9652
SPECIFICATIONS
ADC DC SPECIFICATIONS
AVDD3 = 3.3 V, AVDD = AVDD_CLK = 1.8 V, SPIVDD = DRVDD = 1.8 V, sample rate = 310 MSPS (clock input = 1240 MHz, AD9652
divided by 4), VIN = −1.0 dBFS differential input, 2.5 V p-p full-scale input range, duty cycle stabilizer (DCS) enabled, dither disabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL) 1
Integral Nonlinearity (INL)1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
INPUT REFERRED NOISE
VREF = 1.25 V
ANALOG INPUT
Input Span (for VREF = 1.25 V)
Input Capacitance 2
Input Resistance 3
Input Common-Mode Voltage
POWER SUPPLIES
Supply Voltage
AVDD3
AVDD
AVDD_CLK
DRVDD
SPIVDD
Supply Current, Clock Divider = 1
IAVDD3
IAVDD
IAVDD_CLK
IDRVDD
ISPIVDD
POWER CONSUMPTION
Clock Divider = 1
Normal Operation1
Standby Power 4
Power-Down Power
Temperature
Full
Min
Typ
16
Max
Unit
Bits
Full
Full
Full
Full
Full
Guaranteed
1.5
−0.3
−0.76/+1.1
−4.5/+4.5
mV
% FSR
LSB
LSB
Full
Full
±0.7
±0.1
mV
%FSR
Full
Full
±0.8
±16
ppm/°C
ppm/°C
25°C
3.7
LSB rms
Full
Full
Full
Full
2.5
5.8
27
2.0
2.4
V p-p
pF
kΩ
V
3.3
1.8
1.8
1.8
1.8
3.45
1.9
1.9
1.9
3.6
V
V
V
V
V
Full
Full
Full
Full
Full
3.15
1.7
1.7
1.7
1.7
Full
Full
Full
Full
Full
145
701
56
180
0.005
Full
Full
Full
2160
80
1
Measured with a low input frequency, full-scale sine wave.
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Input resistance refers to the effective resistance between one differential input pin and AGND.
4
Standby power is measured with a dc input and the CLK± pins inactive (that is, set to AVDD or AGND).
1
2
Rev. C | Page 3 of 36
mA
mA
mA
mA
mA
2236
mW
mW
mW
AD9652
Data Sheet
ADC AC SPECIFICATIONS
AVDD3 = 3.3 V, AVDD = AVDD_CLK = 1.8 V, SPIVDD = DRVDD = 1.8 V, sample rate = 310 MSPS (clock input = 1240 MHz, AD9652
divided by 4), VIN = −1.0 dBFS differential input, 2.5 V p-p full-scale input range, DCS enabled, dither disabled, unless otherwise noted.
Table 2.
Parameter1
DIFFERENTIAL INPUT VOLTAGE
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 30 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled)
fIN = 170 MHz (Use Nyquist 2 Settings)
fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled)
fIN = 305 MHz (Use Nyquist 2 Settings)
fIN = 400 MHz (Use Nyquist 3 Settings)
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 30 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled)
fIN = 170 MHz (Use Nyquist 2 Settings)
fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled)
fIN = 305 MHz (Use Nyquist 2 Settings)
fIN = 400 MHz (Use Nyquist 3 Settings)
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled)
fIN = 170 MHz (Use Nyquist 2 Settings)
fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled)
fIN = 305 MHz (Use Nyquist 2 Settings)
fIN = 400 MHz (Use Nyquist 3 Settings)
WORST SECOND OR THIRD HARMONIC
fIN = 30 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled)
fIN = 170 MHz (Use Nyquist 2 Settings)
fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled)
fIN = 305 MHz (Use Nyquist 2 Settings)
fIN = 400 MHz (Use Nyquist 3 Settings)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 30 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings. with Dither Enabled)
fIN = 170 MHz (Use Nyquist 2 Settings)
fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled)
fIN = 305 MHz (Use Nyquist 2 Settings)
fIN = 400 MHz (Use Nyquist 3 Settings)
Temperature
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Rev. C | Page 4 of 36
Min
VREF = 1 V
Typ
Max
2.0
74.0
73.6
VREF = 1.25 V, Default
Min
Typ
Max
2.5
74.0
73.3
73.1
72.1
71.2
70.1
67.9
72.8
73.5
73.8
73.2
74.2
74.6
12.0
11.9
12.0
12.1
12.0
11.8
11.6
11.1
10.6
−96
−90
−94
−87
−92
−87
−87
−89
−80
−89
−85
−85
−86
−77
92
84
87
89
80
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
74.0
72.6
71.7
68.5
65.8
11.8
11.7
11.5
96
90
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
74.3
73.7
72.0
70.7
68.0
73.0
72.0
71.1
11.8
12
75.4
75.0
83
83
94
87
89
85
85
86
77
Unit
V p-p
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Bits
−83
−83
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
Data Sheet
AD9652
Parameter1
WORST OTHER (NOT INCLUDING 2nd or 3rd HARMONIC)
fIN = 30 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings)
fIN = 70 MHz (Use Nyquist 1 Settings, with Dither Enabled)
fIN = 170 MHz (Use Nyquist 2 Settings)
fIN = 170 MHz (Use Nyquist 2 Settings, with Dither Enabled)
fIN = 305 MHz (Use Nyquist 2 Settings)
fIN = 400 MHz (Use Nyquist 3 Settings)
TWO-TONE SFDR
fIN = 70.1 MHz (−7 dBFS ), 72.1 MHz (−7 dBFS )
fIN = 184.12 MHz (−7 dBFS ), 187.12 MHz (−7 dBFS )
CROSSTALK2
FULL POWER BANDWIDTH3
NOISE BANDWIDTH4
Temperature
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
Min
VREF = 1 V
Typ
Max
VREF = 1.25 V, Default
Min
Typ
Max
Unit
−101
−99
−102
−98
−100
−91
−90
−98
−92
−100
−90
−95
−97
−91
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
90
485
650
93
83
90
485
650
dBc
dBc
dB
MHz
MHz
−90
−86
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
3
Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved.
4
Noise bandwidth is the −3 dB bandwidth for the ADC inputs across which noise can enter the ADC and is not attenuated internally.
2
DIGITAL SPECIFICATIONS
AVDD3 = 3.3 V, AVDD = AVDD_CLK = 1.8 V, SPIVDD = DRVDD = 1.8 V, sample rate = 310 MSPS (clock input = 1240 MHz, AD9652
divided by 4), VIN = −1.0 dBFS differential input, 2.5 V p-p full-scale input range, DCS enabled, dither disabled, unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+,
CLK−)
Logic Compliance
Differential Input Voltage
Input Voltage Range
Internal Common-Mode Bias
Input Common-Mode Range
High Level Input Current
Low Level Input Current
Input Capacitance1
Input Resistance1
SYNC INPUT
Logic Compliance
Internal Bias
Input Voltage Range
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Capacitance
Input Resistance
Test Conditions/Comments
Rev. C | Page 5 of 36
Temperature
Min
Typ
Max
Unit
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS/LVPECL
0.3
3.6
AGND
AVDD_CLK
0.9
0.9
1.4
+10
+145
−155
−15
5
10
V p-p
V
V
V
μA
μA
pF
kΩ
Full
Full
Full
Full
Full
Full
Full
Full
CMOS/LVDS
0.9
AGND
AVDD_CLK
1.2
AVDD_CLK
AGND
0.6
−15
+110
−105
+15
1.5
16
V
V
V
V
μA
μA
pF
kΩ
AD9652
Parameter
LOGIC INPUT (CSB)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUT (SCLK)3
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO)2
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
LOGIC INPUTS (PDWN)3
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
LVDS Data and OR± Outputs
ANSI Mode
Differential Output Voltage
(VOD)
Output Offset Voltage (VOS)
Reduced Swing Mode
Differential Output Voltage
(VOD)
Output Offset Voltage (VOS)
Data Sheet
Test Conditions/Comments
Temperature
Min
Full
Full
Full
Full
Full
Full
1.22
0
−65
−135
Full
Full
Full
Full
Full
Full
1.22
0
0
−60
Full
Full
Full
Full
Full
Full
1.22
0
−65
−135
Full
Full
Full
Full
Full
Full
1.22
0
−80
−145
Full
310
Full
Typ
Max
Unit
SPIVDD
0.6
+65
0
V
V
μA
μA
kΩ
pF
SPIVDD
0.6
110
+50
V
V
μA
μA
kΩ
pF
SPIVDD
0.6
+70
0
V
V
μA
μA
kΩ
pF
DRVDD
0.6
+190
+130
V
V
μA
μA
kΩ
pF
350
450
mV
1.15
1.22
1.35
V
Full
150
200
280
mV
Full
1.15
1.22
1.35
V
26
2
26
2
26
5
26
5
Assumes nominal 100 Ω differential
termination
Maximum setting, default
Minimum setting
1
Input capacitance/resistance refers to the effective capacitance/resistance between one differential input pin and AGND.
Internal weak pull-up.
3
Internal weak pull-down.
2
Rev. C | Page 6 of 36
Data Sheet
AD9652
SWITCHING SPECIFICATIONS
Table 4.
Parameter
CLOCK INPUT PARAMETERS (CLK±)
Input Clock Rate
Conversion Rate 1
Period—Divide by 1 Mode (tCLK)
Pulse Width High (tCH), Minimum
Divide by 1 Mode
Divide by 2 Mode Through Divide by 8 Mode
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
DATA OUTPUT PARAMETERS
LVDS Mode
Data Propagation Delay (tPD)
DCO± Propagation Delay (tDCO)
DCO± to Data Skew (tSKEW)
Pipeline Delay (Latency)
Wake-Up Time
Test Conditions/Comments
DCS enabled
DCS disabled
From standby
From power-down
Out of Range Recovery Time
1
2
Temperature
Min
Full
Full
Full
80
80
3.2
Typ
Max
Unit
1240
310
MHz
MSPS
ns
Full
Full
Full
Full
Full
0.8
1.3
0.8
1.0
0.1
ns
ns
ns
ns
ps rms
Full
Full
Full
Full
Full
Full
Full
290
290
−280
26
100
1
3
ps
ps
ps 2
Cycles
µs
sec
Cycles
−80
−480
Conversion rate is the clock rate after the divider.
Data transitions prior to DCO± edge transition.
TIMING SPECIFICATIONS
Table 5.
Parameter
SYNC TIMING REQUIREMENTS
tSSYNC
tHSYNC
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
tDIS_SDIO
tSPI_RST
Test Conditions/Comments
Min
SYNC to the rising edge of CLK+ setup time
SYNC to the rising edge of CLK+ hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK is in a logic high state
Minimum period that SCLK is in a logic low state
Time required for the SDIO pin to switch from an input to an output relative
to the SCLK falling edge (not shown in Timing Diagrams)
Time required for the SDIO pin to switch from an output to an input relative
to the SCLK rising edge (not shown in Timing Diagrams)
Time required after power-up, hard or soft reset until SPI access is available
(not shown in Timing Diagrams)
Rev. C | Page 7 of 36
Typ
0.1
0.1
Max
Unit
ns
ns
2
2
40
2
2
10
10
10
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
500
µs
AD9652
Data Sheet
Timing Diagrams
tA
N–1
N+4
N
VIN±x
N+1
tCH
N+2
tCLK
CLK+
CLK–
tDCO
DCO–
DCO+
tSKEW
tPD
CH A CH B CH A CH B CH A CH B CH A CH B CH A
N – 26 N – 26 N – 25 N – 25 N – 24 N – 24 N – 23 N – 23 N – 22
D0± (LSB)
CHANNEL A
AND
CHANNEL B
D15± (MSB)
12169-002
PARALLEL
INTERLEAVED
N+5
N+3
CH A CH B CH A CH B CH A CH B CH A CH B CH A
N – 26 N – 26 N – 25 N – 25 N – 24 N – 24 N – 23 N – 23 N – 22
Figure 2. LVDS Data Output Timing
CLK±
tSSYNC
12169-003
tHSYNC
SYNC
Figure 3. SYNC Timing Inputs
tHIGH
tDS
tS
tDH
tCLK
tH
tLOW
CSB
SDIO DON’T CARE
DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 4. Serial Port Interface Timing Diagram
Rev. C | Page 8 of 36
D4
D3
D2
D1
D0
DON’T CARE
12169-049
SCLK DON’T CARE
Data Sheet
AD9652
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
Electrical
AVDD3 to AGND
AVDD_CLK to AGND
AVDD to AGND
DRVDD to AGND
SPIVDD to AGND
VIN+A/VIN+B, VIN−A/VIN−B to AGND
CLK+, CLK− to AGND
SYNC to AGND
VCM to AGND
CSB to AGND
SCLK to AGND
SDIO to AGND
PDWN to AGND
OR+/OR− to AGND
D0± Through D15± to AGND
DCO± to AGND
Environmental
Operating Temperature Range
(Ambient)
Maximum Junction Temperature
Under Bias
Storage Temperature Range
(Ambient)
Rating
−0.3 V to +3.6 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +3.6 V
1.2 V to 3.0 V
−0.3 V to AVDD_CLK +
0.2 V
−0.3 V to AVDD_CLK +
0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to SPIVDD + 0.3 V
−0.3 V to SPIVDD + 0.3 V
−0.3 V to SPIVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−40°C to +85°C
Typical θJA is specified for both a 4-layer printed circuit board
(PCB) with a solid ground plane from the JEDEC 51-2 and an
8-layer PCB. The 8-layer PCB has 2 oz copper layers (M1 and
M8), 1 oz copper inner layers, and vias connecting to layers M2,
M5, and M7.
As shown in Table 7, airflow increases heat dissipation, which
reduces θJA. In addition, metal in direct contact with the
package leads from metal traces, through holes, ground, and
power planes, reduces the θJA.
Table 7. Thermal Resistance
Package Type
144-Ball CSP_BGA
10 mm × 10 mm
(BC-144-6)
1
2
Airflow
Velocity
(m/sec)
0
1.0
0
1.0
Board Type
8-layer PCB
8-layer PCB
JEDEC1
JEDEC1
Per JEDEC JESD51-7, plus JEDEC 25-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
ESD CAUTION
125°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 9 of 36
θJA 2
15.8
13.9
21.7
19.2
Unit
°C/W
°C/W
°C/W
°C/W
AD9652
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9652
1
2
3
4
5
6
7
8
9
10
11
12
A
RBIAS
VCM
AVDD3
VIN+B
VIN–B
AVDD3
AVDD3
VIN–A
VIN+A
AVDD3
SENSE
VREF
B
AGND
AVDD3
AVDD3
AGND
AGND
AVDD3
AVDD3
AGND
AGND
AVDD3
AVDD3
AGND
C
AGND
AGND
AVDD
AGND
AGND
AVDD_
CLK
AVDD_
CLK
AGND
AGND
AVDD
AGND
AGND
D
CLK–
AGND
AVDD
AGND
AGND
AVDD_
CLK
AVDD_
CLK
AGND
AGND
AVDD
AGND
CSB
E
CLK+
AGND
AVDD
AGND
AGND
AVDD_
CLK
AVDD_
CLK
AGND
AGND
AVDD
AGND
SDIO
F
TEST
AGND
AVDD
AGND
AGND
AVDD_
CLK
AVDD_
CLK
AGND
AGND
AVDD
AGND
SCLK
G
SYNC
AGND
AVDD
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AGND
OR+
H
PDWN
AGND
AVDD
AGND
AGND
AVDD
AVDD
AGND
AGND
AVDD
AGND
OR–
J
D0–
D0+
DRGND
DRGND
DRGND
DRGND
DRGND
DC0+
DRGND
DRGND
D15+
D15–
K
D1–
D1+
DRVDD
DRVDD
SPIVDD
DRVDD
DRVDD
DC0–
DRVDD
DRVDD
D14+
D14–
L
D2+
D3+
D4+
D5+
D6+
D7+
D8+
D9+
D10+
D11+
D12+
D13+
M
D2–
D3–
D4–
D5–
D6–
D7–
D8–
D9–
D10–
D11–
D12–
D13–
12169-004
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
ADC Power Supplies
K5
K3, K4, K6, K7, K9, K10
A3, A6, A7, A10, B2, B3, B6, B7,
B10, B11
C6, C7, D6, D7, E6, E7, F6, F7
C3, C10, D3, D10, E3, E10, F3,
F10, G3, G6, G7, G10, H3, H6,
H7, H10
B1, B4, B5, B8, B9, B12, C1, C2,
C4, C5, C8, C9, C11, C12, D2,
D4, D5, D8, D9, D11, E2, E4,
E5, E8, E9, E11, F2, F4, F5, F8,
F9, F11, G2, G4, G5, G8, G9,
G11, H2, H4, H5, H8, H9, H11
J3
J4
J5
Mnemonic
Type
Description
SPIVDD
DRVDD
AVDD3
Supply
Supply
Supply
Serial Interface Logic Voltage Supply (1.8 V Typical, 3.3 V Optional)
Digital Output Driver Supply (1.8 V Nominal).
3.3 V Analog Power Supply (3.3 V Nominal).
AVDD_CLK
AVDD
Supply
Supply
1.8 V Analog Power Supply for Clock Circuitry (1.8 V Nominal).
1.8 V Analog Power Supply (1.8 V Nominal).
AGND
Analog
Ground
Analog Ground Reference for AVDD3, AVDD_CLK, and AVDD.
DRGND
DRGND
DRGND
Digital Ground
Digital Ground
Digital Ground
Digital and Output Driver Ground Reference.
Digital and Output Driver Ground Reference.
Digital and Output Driver Ground Reference.
Rev. C | Page 10 of 36
Data Sheet
Pin No.
J6
J7
J9
J10
ADC Analog
A9
A8
A4
A5
A2
A1
A12
A11
E1
D1
Digital Inputs
F1
G1
H1
Digital Outputs
J2
J1
K2
K1
L1
M1
L2
M2
L3
M3
L4
M4
L5
M5
L6
M6
L7
M7
L8
M8
L9
M9
L10
M10
L11
M11
L12
M12
K11
AD9652
Mnemonic
DRGND
DRGND
DRGND
DRGND
Type
Digital Ground
Digital Ground
Digital Ground
Digital Ground
Description
Digital and Output Driver Ground Reference.
Digital and Output Driver Ground Reference.
Digital and Output Driver Ground Reference.
Digital and Output Driver Ground Reference.
VIN+A
VIN−A
VIN+B
VIN−B
VCM
Input
Input
Input
Input
Output
RBIAS
Output
VREF
SENSE
CLK+
CLK−
Input/Output
Input
Input
Input
Differential Analog Input Pin (+) for Channel A.
Differential Analog Input Pin (−) for Channel A.
Differential Analog Input Pin (+) for Channel B.
Differential Analog Input Pin (−) for Channel B.
Common-Mode Level Bias Output for Analog Inputs. Decouple
this pin to ground using a 0.1 μF capacitor.
External Bias Resister Connection. A 10 kΩ resister must be
connected between this pin and analog ground (AGND).
Voltage Reference Input/Output.
Reference Mode Selection (See Table 12).
ADC Clock Input (True).
ADC Clock Input (Complement).
TEST
Input
SYNC
PDWN
Input
Input
Pull-Down. Unused digital input, pull to ground through a 50 Ω
resistor.
Digital Input Clock Synchronization Pin. Tie low if unused.
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as power-down
or standby (see Register 0x08 in Table 17).
D0+
D0−
D1+
D1−
D2+
D2−
D3+
D3−
D4+
D4−
D5+
D5−
D6+
D6−
D7+
D7−
D8+
D8−
D9+
D9−
D10+
D10−
D11+
D11−
D12+
D12−
D13+
D13−
D14+
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Channel A/Channel B LVDS Output Data 0 (True, LSB).
Channel A/Channel B LVDS Output Data 0 (Complement, LSB).
Channel A/Channel B LVDS Output Data 1 (True).
Channel A/Channel B LVDS Output Data 1 (Complement).
Channel A/Channel B LVDS Output Data 2 (True).
Channel A/Channel B LVDS Output Data 2 (Complement).
Channel A/Channel B LVDS Output Data 3 (True).
Channel A/Channel B LVDS Output Data 3 (Complement).
Channel A/Channel B LVDS Output Data 4 (True).
Channel A/Channel B LVDS Output Data 4 (Complement).
Channel A/Channel B LVDS Output Data 5 (True).
Channel A/Channel B LVDS Output Data 5 (Complement).
Channel A/Channel B LVDS Output Data 6 (True).
Channel A/Channel B LVDS Output Data 6 (Complement).
Channel A/Channel B LVDS Output Data 7 (True).
Channel A/Channel B LVDS Output Data 7 (Complement).
Channel A/Channel B LVDS Output Data 8 (True).
Channel A/Channel B LVDS Output Data 8 (Complement).
Channel A/Channel B LVDS Output Data 9 (True).
Channel A/Channel B LVDS Output Data 9 (Complement).
Channel A/Channel B LVDS Output Data 10 (True).
Channel A/Channel B LVDS Output Data 10 (Complement).
Channel A/Channel B LVDS Output Data 11 (True).
Channel A/Channel B LVDS Output Data 11 (Complement).
Channel A/Channel B LVDS Output Data 12 (True).
Channel A/Channel B LVDS Output Data 12 (Complement).
Channel A/Channel B LVDS Output Data 13 (True).
Channel A/Channel B LVDS Output Data 13 (Complement).
Channel A/Channel B LVDS Output Data 14 (True).
Rev. C | Page 11 of 36
AD9652
Pin No.
K12
J11
J12
G12
H12
J8
K8
SPI Control
F12
E12
D12
Data Sheet
Mnemonic
D14−
D15+
D15−
OR+
OR−
DCO+
DCO−
Type
Output
Output
Output
Output
Output
Output
Output
Description
Channel A/Channel B LVDS Output Data 14 (Complement).
Channel A/Channel B LVDS Output Data 15 (True, MSB).
Channel A/Channel B LVDS Output Data 15 (Complement, MSB).
Channel A/Channel B LVDS Overrange (True).
Channel A/Channel B LVDS Overrange (Complement).
Channel A/Channel B LVDS Data Clock Output (True).
Channel A/Channel B LVDS Data Clock Output (Complement).
SCLK
SDIO
CSB
Input
Input/Output
Input
SPI Serial Clock.
SPI Serial Data Input/Output.
SPI Chip Select (Active Low). This pin must be pulled high at
power-up.
Rev. C | Page 12 of 36
Data Sheet
AD9652
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD3 = 3.3 V, AVDD = AVDD_CLK = 1.8 V, SPIVDD = DRVDD = 1.8 V, sample rate = 310 MSPS (clock input = 1240 MHz, AD9652
divide by 4), VIN = −1.0 dBFS differential, VREF = 1.25 V, DCS enabled, dither disabled, unless otherwise noted.
0
0
AIN = –1dBFS
SNRFS = 75.0dB
SFDR = 89dBc
–20
–40
–80
–100
–120
–120
0
20
40
60
80
100
120
140
–140
0
0
60
80
100
120
140
–80
–60
–80
–100
–100
–120
–120
20
40
60
80
100
120
140
fIN (MHz)
20
40
60
80
100
120
140
fIN (MHz)
0
AIN = –1dBFS
SNRFS = 73.2dB
SFDR = 88dBc
–20
0
Figure 10. Single Tone FFT with fIN = 70.1 MHz at −7 dBFS with Dither
(NSD = −157.1 dBFS/Hz)
Figure 7. Single Tone FFT with fIN = 70.1 MHz at −7 dBFS
(NSD = −157.6 dBFS/Hz)
0
–140
12169-007
0
12169-008
AMPLITUDE (dB)
–40
–60
AIN = –1dBFS
SNRFS = 72.9dB
SFDR = 88dBc
–20
–40
–60
–80
–60
–80
–100
–100
–120
–120
20
40
60
80
100
120
140
fIN (MHz)
Figure 8. Single Tone FFT with fIN = 185 MHz. at −1 dBFS
(NSD = −155.2 dBFS/Hz), Register 0x22A = 0x01
12169-009
–140
0
0
20
40
60
80
fIN (MHz)
100
120
140
12169-010
AMPLITUDE (dB)
–40
–140
40
AIN = –7dBFS
SNRFS = 75.2dB
SFDR = 94.4dBc
–20
–40
–140
20
Figure 9. Single Tone FFT with fIN = 70.1 MHz with Dither
(NSD = −156.3 dBFS/Hz)
AIN = –7dBFS
SNRFS = 75.7dB
SFDR = 91.9dBc
–20
0
fIN (MHz)
Figure 6. Single Tone Fast Fourier Transform (FFT) with fIN = 70.1 MHz
(NSD = −156.7 dBFS/Hz)
AMPLITUDE (dB)
–80
–100
fIN (MHz)
AMPLITUDE (dB)
–60
12169-006
AMPLITUDE (dB)
–60
12169-005
AMPLITUDE (dB)
–40
–140
AIN = –1dBFS
SNRFS = 74.4dB
SFDR = 90dBc
–20
Figure 11. Single Tone FFT with fIN = 185 MHz at −1 dBFS with Dither
(NSD = −154.9 dBFS/Hz), Register 0x22A = 0x01
Rev. C | Page 13 of 36
AD9652
0
Data Sheet
0
AIN = –7dBFS
SNRFS = 75dB
SFDR = 92dBc
–20
–20
–40
AMPLITUDE (dB)
–80
–60
–80
–100
–100
–120
–120
20
40
60
80
100
120
140
fIN (MHz)
Figure 12. Single Tone FFT with fIN = 185 MHz at −7 dBFS
(NSD = −156.9 dBFS/Hz), Register 0x22A = 0x01
0
–140
12169-011
0
100
120
140
AIN = –1dBFS
SNRFS = 69.5dB
SFDR = 91.6dBc
–40
MAGNITUDE (dB)
–60
–80
–100
–100
–120
–120
50
100
150
fIN (MHz)
–140
12169-200
0
150
Figure 16. FFT fIN = 305 MHz, AIN = −1 dBFS, Dither On,
Register 0x22A = 0x01
0
AIN = –7dBFS
SNRFS = 72.7dB
SFDR = 90.7dBc
–20
100
50
fIN (MHz)
Figure 13. FFT fIN = 305 MHz, AIN = −1 dBFS, Dither Off,
Register 0x22A = 0x01
0
0
12169-201
MAGNITUDE (dB)
80
–20
–80
AIN = –7dBFS
SNRFS = 72.8dB
SFDR = 90.7dBc
–20
–40
MAGNITUDE (dB)
–40
MAGNITUDE (dB)
60
0
–60
–60
–80
–60
–80
–100
–120
–120
0
50
100
150
fIN (MHz)
12169-204
–100
–140
40
Figure 15. Single Tone FFT with fIN = 185 MHz at −7 dBFS with Dither
(NSD = −156.4 dBFS/Hz), Register 0x22A = 0x01
–40
–140
20
fIN (MHz)
AIN = –1dBFS
SNRFS = 69.7dB
SFDR = 86.9dBc
–20
0
12169-012
–60
Figure 14. FFT fIN = 305 MHz, AIN = −7 dBFS, Dither Off,
Register 0x22A = 0x01
–140
0
50
100
150
fIN (MHz)
Figure 17. FFT fIN = 305 MHz, AIN = −7 dBFS, Dither On,
Register 0x22A = 0x01
Rev. C | Page 14 of 36
12169-205
AMPLITUDE (dB)
–40
–140
AIN = –7dBFS
SNRFS = 74.5dB
SFDR = 93dBc
Data Sheet
AD9652
0
0
AIN = –1dBFS
SNRFS = 68.0dB
SFDR = 75.7dBc
–20
–20
–40
–60
–80
–60
–80
–100
–100
–120
–120
50
100
–140
12169-202
0
150
fIN (MHz)
0
–40
–80
–60
–80
–100
–100
–120
–120
150
–140
–40
–20
0
20
AIN (–dBFS)
SNR (dB)
80
60
40
62
12169-014
–60
68
100
SNRFS (dB), –40°C
SNRFS (dB), +25°C
SNRFS (dB), +85°C
SFDR (dBFS), –40°C
SFDR (dBFS), +25°C
SFDR (dBFS), +85°C
SFDR (dBc), –40°C
SFDR (dBc), +25°C
SFDR (dBc), +85°C
64
40
62
70
66
60
64
60
–80
72
SFDR (dB)
80
120
74
100
SNRFS (dB), –40°C
SNRFS (dB), +25°C
SNRFS (dB), +85°C
SFDR (dBFS), –40°C
SFDR (dBFS), +25°C
SFDR (dBFS), +85°C
SFDR (dBc), –40°C
SFDR (dBc), +25°C
SFDR (dBc), +85°C
140
76
120
74
66
150
78
140
76
68
100
Figure 22. FFT fIN = 400 MHz, AIN = −7 dBFS, Dither On,
Register 0x22A = 0x02
78
70
50
fIN (MHz)
Figure 19. FFT fIN = 400 MHz, AIN = −7 dBFS, Dither Off,
Register 0x22A = 0x02
72
0
Figure 20. Single Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 90.1 MHz, VREF = 1.25 V, Over Temperature, Dither Off
60
–80
–60
–40
–20
0
20
AIN (–dBFS)
Figure 23. Single Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 90.1 MHz, VREF = 1.25 V, Over Temperature, Dither On
Rev. C | Page 15 of 36
SFDR (dB)
100
12169-114
50
12169-206
0
12169-207
MAGNITUDE (dB)
MAGNITUDE (dB)
–60
fIN (MHz)
SNR (dB)
150
AIN = –7dBFS
SNRFS = 71.9dB
SFDR = 80.2dBc
–20
–40
–140
100
Figure 21. FFT fIN = 400 MHz, AIN = −1 dBFS, Dither On,
Register 0x22A = 0x02
AIN = –7dBFS
SNRFS = 71.7dB
SFDR = 81.3dBc
–20
50
fIN (MHz)
Figure 18. FFT fIN = 400 MHz, AIN = −1 dBFS, Dither Off,
Register 0x22A = 0x02
0
0
12169-203
MAGNITUDE (dB)
MAGNITUDE (dB)
–40
–140
AIN = –1dBFS
SNRFS = 68.0dB
SFDR = 75.0dBc
AD9652
Data Sheet
60
64
–60
–40
–20
0
20
–60
–40
–20
0
20
AIN (–dBFS)
Figure 27. Single Tone SNR/SFDR vs. Input Amplitude (AIN) with fIN =
90.1 MHz, VREF = 1.0 V, Over Temperature, Dither On
106
74
102
72
70
98
70
98
68
94
68
94
66
90
66
90
64
86
64
86
74
72
62
82
58
0
50
100
150
200
250
300
350
400
450
500
110
SNRFS
(NYQUIST SETTING 1)
SNRFS
(NYQUIST SETTING 2)
SNRFS
(NYQUIST SETTING 3)
106
102
62
78
60
74
58
70
550
56
12169-116
SFDR
(NYQUIST SETTING 1)
SFDR
(NYQUIST SETTING 2)
SFDR
(NYQUIST SETTING 3)
60
56
SNR (dB)
76
SNRFS
(NYQUIST SETTING 1)
SNRFS
(NYQUIST SETTING 2)
SNRFS
(NYQUIST SETTING 3)
SFDR (dBc)
110
76
fIN (MHz)
82
SFDR
(NYQUIST SETTING 1)
SFDR
(NYQUIST SETTING 2)
SFDR
(NYQUIST SETTING 3)
0
50
100
150
200
78
74
250
300
350
400
450
500
70
550
fIN (MHz)
Figure 25. Single Tone SNR/SFDR vs. Input Frequency (fIN),
Amplitude = −1 dBFS, VREF = 1.25 V
Figure 28. Single Tone SNR/SFDR vs. Input Frequency (fIN),
Amplitude =−1 dBFS, VREF = 1.0 V
106
74
102
72
98
70
68
94
68
94
66
90
66
90
64
86
64
86
62
82
SNRFS
(NYQUIST SETTING 1)
SNRFS
(NYQUIST SETTING 2)
SNRFS
(NYQUIST SETTING 3)
72
70
SFDR
(NYQUIST SETTING 1)
SFDR
(NYQUIST SETTING 2)
SFDR
(NYQUIST SETTING 3)
60
58
56
0
50
100
150
200
250
300
350
400
450
500
78
60
74
58
70
550
56
fIN (MHz)
110
106
SNRFS
(NYQUIST SETTING 1)
SNRFS
(NYQUIST SETTING 2)
SNRFS
(NYQUIST SETTING 3)
102
98
62
12169-017
74
SNR (dB)
76
SFDR (dBc)
110
76
SFDR (dB)
40
60
–80
Figure 24. Single Tone SNR/SFDR vs. Input Amplitude (AIN) with
fIN = 90.1 MHz, VREF = 1.0 V, Over Temperature, Dither Off
SNR (dB)
60
62
AIN (–dBFS)
SNR (dB)
80
64
12169-015
60
–80
68
66
40
62
70
SFDR (dB)
66
100
SNRFS (dB), –40°C
SNRFS (dB), +25°C
SNRFS (dB), +85°C
SFDR (dBFS), –40°C
SFDR (dBFS), +25°C
SFDR (dBFS), +85°C
SFDR (dBc), –40°C
SFDR (dBc), +25°C
SFDR (dBc), +85°C
12169-016
68
80
SNR (dB)
70
72
100
SNRFS (dB), –40°C
SNRFS (dB), +25°C
SNRFS (dB), +85°C
SFDR (dBFS), –40°C
SFDR (dBFS), +25°C
SFDR (dBFS), +85°C
SFDR (dBc), –40°C
SFDR (dBc), +25°C
SFDR (dBc), +85°C
120
74
SFDR (dB)
72
SNR (dB)
76
120
74
140
Figure 26. Single Tone SNR/SFDR vs. Input Frequency (fIN),
Amplitude = −7 dBFS, VREF = 1.25 V
82
SFDR
(NYQUIST SETTING 1)
SFDR
(NYQUIST SETTING 2)
SFDR
(NYQUIST SETTING 3)
0
50
100
150
200
78
74
250
300
350
400
450
500
70
550
fIN (MHz)
Figure 29. Single Tone SNR/SFDR vs. Input Frequency (fIN),
Amplitude = −7 dBFS, VREF = 1.0 V
Rev. C | Page 16 of 36
SFDR (dBc)
76
78
12169-115
140
12169-117
78
AD9652
105
–20
100
–20
100
–40
95
–40
95
–80
–100
–120
–80
–60
–40
–20
0
90
SFDR (dBFS)
IMD2 (dBc)
IMD3 (dBc)
IMD2 (dBFS)
IMD3 (dBFS)
85
–80
80
–100
75
–120
–80
INPUT AMPLITUDE (dBFS)
Figure 30. Two Tone SFDR/Intermodulation Distortion (IMD) vs. Input
Amplitude, for fIN = 70.1 MHz and 72.1 MHz, Dither Disabled
85
80
–60
–40
–20
0
75
INPUT AMPLITUDE (dBFS)
Figure 33. Two Tone SFDR/IMD vs. Input Amplitude, for fIN = 70.1 MHz and
72.1 MHz, Dither Enabled
105
–20
100
–20
100
–40
95
–40
95
–60
90
SFDR (dBFS)
IMD2 (dBc)
IMD3 (dBc)
IMD2 (dBFS)
IMD3 (dBFS)
–80
–100
–120
–80
–60
–40
–20
0
–80
80
–100
75
–120
–80
Figure 31. Two Tone SFDR/IMD vs. Input Amplitude, for fIN = 184 MHz and
187 MHz, Dither Disabled, Register 0x22A = 0x01
–60
–40
–20
0
75
70000
60000
Figure 32. Two Tone FFT with fIN = 89.1 MHz and 92.1 MHz, VREF = 1.25 V
Rev. C | Page 17 of 36
Figure 35. Grounded Input Histogram
N + 20
N + 18
N + 16
12169-026
CODES
N + 14
N + 12
N+8
0
N + 10
150
N+6
125
N+4
fIN (MHz)
100
N
75
N +2
50
N–2
25
N–4
0
N–6
10000
N–8
–120
N – 10
20000
N – 12
–100
N – 16
30000
N – 14
–80
40000
N – 18
–60
N – 20
NUMBER OF HITS
50000
12169-331
AMPLITUDE (dB)
80
Figure 34. Two Tone SFDR/IMD vs. Input Amplitude, for fIN = 184 MHz and
187 MHz, Dither Enabled, Register 0x22A = 0x01
–40
–140
85
INPUT AMPLITUDE (dBFS)
AIN1 = AIN2 = –7dBFS
SFDR = 87dBc (94dBFS)
IMD2 = –92dBc (–99dBFS)
IMD3 = –87dBc (–94dBFS)
–20
90
SFDR (dBFS)
IMD2 (dBc)
IMD3 (dBc)
IMD2 (dBFS)
IMD3 (dBFS)
85
INPUT AMPLITUDE (dBFS)
0
–60
SFDR (dBFS)
0
IMD (dB)
105
SFDR (dBFS)
0
12169-330
IMD (dB)
–60
12169-332
90
SFDR (dBFS)
IMD2 (dBc)
IMD3 (dBc)
IMD2 (dBFS)
IMD3 (dBFS)
12169-333
–60
SFDR (dBFS)
0
IMD (dB)
105
SFDR (dBFS)
0
12169-329
IMD (dB)
Data Sheet
AD9652
Data Sheet
100
100
95
90
85
SFDR (VREF = 1.25V)
80
SNRFS (VREF = 1.25V)
75
70
80
160
200
240
85
SFDR (VREF = 1.25V)
80
SNRFS (VREF = 1.25V)
75
SNRFS (VREF = 1V)
120
SFDR (VREF = 1V)
90
280
320
70
80
ENCODE RATE (MHz)
SNRFS (VREF = 1V)
120
160
200
240
280
12169-338
SNRFS/SFDR (dB/dBc)
SFDR (VREF = 1V)
12169-335
SNRFS/SFDR (dB/dBc)
95
320
ENCODE RATE (MHz)
Figure 36. Encode Rate Sweep, fIN = 90.1 MHz at −7 dBFS,
VREF = 1.25 V and 1.0 V
Figure 39. Encode Rate Sweep, fIN = 90.1 MHz at −1 dBFS,
VREF = 1.25 V and 1.0 V
1.0
6
0.8
0.6
3
0.2
INL (LSB)
DNL (LSB)
0.4
0
–0.2
0
–0.4
–3
–0.6
0
10000
20000
30000
40000
50000
60000
CODES
–6
12169-024
–1.0
0
10000
20000
30000
40000
50000
60000
CODES
Figure 37. DNL with Dither Off, fIN = 30 MHz
12169-124
–0.8
Figure 40. INL with Dither Off, fIN = 30 MHz
1.0
6
0.8
0.6
3
INL (LSB)
0.2
0
–0.2
0
–0.4
–3
–0.6
–1.0
0
10000
20000
30000
40000
50000
CODES
60000
–6
0
10000
20000
30000
40000
50000
CODES
Figure 41. INL with Dither On, fIN = 30 MHz
Figure 38. DNL with Dither On, fIN = 30 MHz
Rev. C | Page 18 of 36
60000
12169-125
–0.8
12169-025
DNL (LSB)
0.4
Data Sheet
AD9652
EQUIVALENT CIRCUITS
SPIVDD
AVDD3
350Ω
SCLK
VIN±x
12169-027
27kΩ
12169-339
26kΩ
Figure 42. Equivalent Analog Input Circuit
Figure 47. Equivalent SCLK Input Circuit
AVDD_CLK
AVDD
0.9V
10kΩ
26kΩ
350Ω
CSB
CLK–
12169-028
CLK+
10kΩ
12169-032
AVDD
SPIVDD
Figure 48. Equivalent CSB Input Circuit
Figure 43. Equivalent Clock Circuit
DRVDD
AVDD_CLK
DATAOUT+
SYNC
V+
0.9V
16kΩ
0.9V
12169-029
V–
12169-033
DATAOUT–
Figure 44. Equivalent LVDS Output Circuit (DCO±, OR±, and D0± to D15±)
Figure 49. Equivalent SYNC Input Circuit
AVDD
SPIVDD
26kΩ
SENSE
350Ω
12168-208
350Ω
12169-030
SDIO
AVDD_CLK
V–
V+
Figure 50. Equivalent SENSE Circuit
Figure 45. Equivalent SDIO Circuit
AVDD
350Ω
VREF
6kΩ
12169-209
26kΩ
12169-300
PDWN
Figure 46. Equivalent PDWN Input Circuit
Figure 51. Equivalent VREF Circuit
Rev. C | Page 19 of 36
AD9652
Data Sheet
THEORY OF OPERATION
The AD9652 is a dual, 16-bit ADC with sampling speeds of up
to 310 MSPS. The AD9652 is designed to support communications
and instrumentation applications where high performance and
wide bandwidth are desired.
The dual ADC design can be used for diversity receivers, where
the ADCs operate identically on the same carrier but from two
separate antennae. The ADCs can also be operated with independent analog inputs. The user can sample frequencies from dc
to 310 MHz using appropriate low-pass or band-pass filtering at
the ADC inputs with little loss in ADC performance. A typical
operation of 485 MHz at the analog input is permitted but occurs
at the expense of increased ADC noise and distortion.
Synchronization capability is provided to allow synchronized
timing between multiple devices.
Programming and control of the AD9652 are accomplished
using a 3-wire, SPI-compatible serial interface.
ADC ARCHITECTURE
The AD9652 consists of a dual, buffered front-end sample-andhold circuit, followed by a pipelined switched-capacitor ADC.
The AD9652 uses a unique architecture that utilizes the benefits
of pipelined converters, as well as a novel input circuit to
maximize performance of the first stage.
The quantized outputs from each stage are combined to produce
a 16-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate on a new input sample,
and the remaining stages to operate on the preceding samples.
Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor digitalto-analog converter (DAC) and an interstage residual multiplying
DAC (MDAC). The MDAC magnifies the difference between
the reconstructed DAC output and the flash input for the next
stage in the pipeline. One bit of redundancy is used in each stage
to facilitate digital correction of flash errors. The last stage
consists of a flash ADC.
The AD9652 uses internal digital processing to continually track
internal errors that occur at each of the pipeline stages and corrects
for them to ensure continuous performance over various operating
conditions. This requires additional start-up time due to the
resetting and collection of correction data.
The input stage of each channel contains a differential sampling
circuit that can be ac-coupled or dc-coupled in differential or
single-ended modes. The output staging block aligns the data,
corrects errors, and passes the data to the output buffers. The
output buffers are powered from a separate supply, allowing
digital output noise to be separated from the analog core. During
power-down, the output buffers enter a high impedance state.
ANALOG INPUT CONSIDERATIONS
The analog inputs to the AD9652 are high performance
differential buffers that are designed for optimum performance
while processing a differential input signal. The input buffer
provides a consistent input impedance to ease interface of the
analog input.
The differential analog input impedance is approximately 54 kΩ
in parallel with a 5.8 pF capacitor. A passive network of discrete
components can create a low-pass filter at the ADC input; the
precise values are dependent on the application.
In intermediate frequency (IF) undersampling applications, reduce
the shunt capacitors. In combination with the driving source
impedance, the shunt capacitors limit the input bandwidth. Refer
to the Analog Dialogue article, “Transformer-Coupled Front-End
for Wideband A/D Converters,” for more information on this
subject.
The AD9652 uses internal optimized settings for the various
input signal frequencies. Register 0x22A configures the ADC
for the desired frequency band.
Table 9. Register 0x22A Settings
Register 0x22A Setting
0 (Default)
1
2
Input Frequency Range
0 to 155 MHz (1st Nyquist)
155 to 310 MHz (2nd Nyquist)
310 MHz and above (3rd Nyquist)
For best dynamic performance, the source impedances driving
each of the differential inputs, match VIN±x, and differentially
balance the inputs.
Input Common Mode
The analog inputs of the AD9652 are not internally dc biased. In
ac-coupled applications, the user must provide this bias externally.
Setting the device so that the common-mode voltage equals
2.0 V is recommended for optimum performance. An on-board
common-mode voltage reference is included in the design and
is available from the VCM pin. Using the VCM output to set the
input common mode is recommended. The VCM pin must be
decoupled to ground with a 0.1 µF capacitor, as described in the
Applications Information section. Place this decoupling capacitor
close to the pin to minimize the series resistance and inductance
between the device and this capacitor.
Common-Mode Voltage Servo
In applications where there may be a voltage loss between the VCM
output of the AD9652 and the analog inputs, the common-mode
voltage servo can be enabled. When the inputs are ac-coupled and a
resistance of >100 Ω is placed between the VCM output and the
analog inputs, a significant voltage drop can occur; enable the
common-mode voltage servo. Setting Bit 0 in Register 0x0F to a
logic high enables the VCM servo mode.
Rev. C | Page 20 of 36
Data Sheet
AD9652
In this mode, the AD9652 monitors the common-mode input
level at the analog inputs and adjusts the VCM output level to
keep the common-mode input voltage at an optimal level. If both
channels are operational, Channel A is monitored. However, if
Channel A is in power-down or standby mode, then Channel B
input is monitored.
Dither
The AD9652 has an optional internal dither circuitry that can
improve SFDR, particularly for small signals. Dithering is the act
of injecting a known but random amount of white noise into the
input of the AD9652. Dithering has the effect of improving the
local linearity within the ADC transfer function. The AD9652
allows dither to be added to either ADC input independently.
The full scale of the dither DAC is small enough that enabling
dither does not limit the external input signal amplitude.
As shown in Figure 52, the dither that is added to the input of
the ADC through the dither DAC is precisely subtracted out
digitally to minimize SNR degradation. When dithering is enabled,
the dither DAC is driven by a pseudorandom number generator
(PN gen). In the AD9652, the dither DAC is precisely calibrated
to result in only a very small degradation in SNR and SINAD
when dither is enabled.
DOUT
12169-034
DITHER ENABLE
The SFDR improvement comes at the expense of SNR degradation,
but because the dither is internal and can be correlated, the impact
on SNR is typically limited to less than 0.5 dB in the first Nyquist
zone. Enabling internal dither does not impact full-scale dynamic
range. The magnitude of dither is controllable, which allows the
user to select the desired trade-off between SFDR improvement
vs. SNR degradation.
To enable dither, set Bit 4 of Register 0x30. To modify the dither
gain, use Register 0x212[7:4].
Table 10. Dither Gain
Gain Ratio
Maximum dither
255/256 × max
254/256 × max
252/256 × max
248/256 × max
240/256 × max
224/256 × max
192/256 × max
Minimum dither
Static Linearity
Differential Input Configurations
Figure 52. Dither Block Diagram
Register 0x212[7:4] Setting
0b0000 (default)
0b0001
0b0010
0b0011
0b0100
0b0101
0b0110
0b0111
0b1000
For small signal inputs, the front-end sampling circuit typically
contributes very little distortion, and the SFDR is likely to be
limited by tones caused by DNL errors due to random component
mismatches. Therefore, for small signal inputs (typically, those
below −6 dBFS), dithering can significantly improve SFDR by
converting these DNL tones to white noise.
Utilizing dither randomizes local small signal DNL errors that
produce the discontinuities in the INL transfer function and
therefore improve the peak-to-peak INL performance.
DITHER
DAC
PN GEN
Small Signal FFT
Gain (%)
100
99.6
99.2
98.4
96.8
93.75
87.5
75
50
Optimum performance is achieved by driving the AD9652 in a
differential input configuration. For baseband applications, the
ADL5566, AD8138, ADA4937-2, ADA4938-2, and ADA4930-2
differential drivers provide excellent performance and a flexible
interface to the ADC.
The output common-mode voltage of the ADA4930-2 is easily
set with the VCM pin of the AD9652 (see Figure 53), and the
driver can be configured in a Sallen-Key filter topology to
provide band limiting of the input signal.
15pF
200Ω
VIN±x
Rev. C | Page 21 of 36
76.8Ω
33Ω
90Ω
ADA4930-2
0.1µF
5pF
33Ω
120Ω
15Ω
VIN–x
ADC
15Ω
VIN+x
VCM
15pF
200Ω
33Ω
0.1µF
Figure 53. Differential Input Configuration Using the ADA4930-2
12169-035
ADC CORE
In most cases, dithering does not improve SFDR for large signal
inputs close to full scale, for example, with a −1 dBFS input. For
large signal inputs, the SFDR is typically limited by front-end
sampling distortion, which dithering cannot improve. However,
even for such large signal inputs, dithering can be useful for
certain applications because it makes the noise floor whiter. As
is common in pipeline ADCs, the AD9652 contains small DNL
errors caused by random component mismatches that produce
spurs or tones that make the noise floor somewhat randomly
colored device-to-device. Although these tones are typically at
very low levels and do not limit SFDR when the ADC is quantizing
large signal inputs, dithering converts these tones to noise and
produces a whiter noise floor.
Dithering also removes sharp local discontinuities in the INL
transfer function of the ADC and reduces the overall peak-topeak INL.
AD9652
VIN±x
Large Signal Fast Fourier Transform
AD9652
Data Sheet
input frequency ranges. However, these values are dependent on
the input signal; use the bandwidth only as a starting guide.
Note that the values given in Table 11 are for each R1, R2, C1,
C2, and R3 component shown in Figure 54 and Figure 56.
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration. An example is shown in Figure 54. To bias the
analog input, the VCM voltage can be connected to the center
tap of the secondary winding of the transformer.
Table 11. Example RC Network
C2
R2
Frequency
Range
(MHz)
0 to 100
100 to 300
VIN+x
R1
49.9Ω
ADC
C1
R2
R1
0.1µF
R3
VIN–x
33Ω
C1
Differential
(pF)
Open
Open
R2
Series
(Ω)
0
15
C2
Shunt
(pF)
15
2.7
R3
Shunt
(Ω)
49.9
0
VCM
0.1µF
C2
An alternative to using a transformer-coupled input at frequencies
in the second Nyquist zone is to use an amplifier with variable
gain. The AD8375 or AD8376 digital variable gain amplifier
(DVGA) provides good performance for driving the AD9652.
Figure 55 shows an example of the AD8376 driving the AD9652
through a band-pass antialiasing filter.
12169-036
2V p-p
R1
Series
(Ω)
33
15
Figure 54. Differential Transformer-Coupled Configuration
The signal characteristics must be considered when selecting a
transformer. Most RF transformers saturate at frequencies below a
few megahertz. Excessive signal power can also cause core
saturation, which leads to distortion.
180nH 220nH
1000pF
1µH
165Ω
VPOS
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9652. For applications
where SNR is a key parameter, differential double balun coupling is
the recommended input configuration (see Figure 56). In this
configuration, the input is ac-coupled and the VCM voltage is
provided to each input through a 33 Ω resistor. These resistors
compensate for losses in the input baluns to provide a 50 Ω
impedance to the driver.
AD8376
5.1pF
1nF
1µH
15pF
3.9pF
AD9652
VCM
301Ω
165Ω
1nF
54kΩ║2.9pF
68nH
180nH 220nH
1000pF
NOTES
1. ALL INDUCTORS ARE COILCRAFT® 0603CS COMPONENTS WITH THE
EXCEPTION OF THE 1µH CHOKE INDUCTORS (COIL CRAFT 0603LS).
2. FILTER VALUES SHOWN ARE FOR A 20MHz BANDWIDTH FILTER
CENTERED AT 140MHz.
Figure 55. Differential Input Configuration Using the AD8376
In the double balun and transformer configurations, the value
of the input capacitors and resistors is dependent on the input
frequency and source impedance. Based on these parameters,
the value of the input resistors and capacitors may need to be
adjusted, or some components may need to be removed. Table 11
displays recommended values to set the RC network for different
C2
R3
R1
0.1µF
0.1µF
2V p-p
R2
VIN+x
33Ω
S
S
P
0.1µF
33Ω
0.1µF
ADC
C1
R1
R2
R3
VIN–x
33Ω
C2
VCM
0.1µF
12169-038
PA
Figure 56. Differential Double Balun Input Configuration
Table 12. VREF Configuration Options
Selected Mode
External Reference
Internal Fixed Reference
1
2
SENSE Voltage
AVDD
GND
Resulting ADC Reference Voltage (V)
N/A1
VREF2
N/A means not applicable.
VREF is set via Register 0x18. The default VREF is 1.25 V.
Rev. C | Page 22 of 36
Resulting Input Span (Differential V p-p)
2 × external reference
2 × VREF2
12169-037
R3
Data Sheet
AD9652
0
VOLTAGE REFERENCE
A stable and accurate programmable reference is built into the
AD9652, allowing a voltage reference from 1.0 V to 1.25 V to
provide up to a 2.5 V p-p differential full-scale input. By default
the VREF voltage is set 1.25 V, but can be modified using
Register 0x18[2:0], VREF select.
To configure the AD9652 for an internal reference, the SENSE
pin must be tied low. When SENSE is tied low, the ADC uses
VREF directly and provides a differential input voltage of two
times the VREF value.
To achieve optimal noise performance when using the internal
reference, it is recommended that the VREF pin be decoupled
by 1.0 µF and 0.1 µF capacitors close to the pin. Figure 57 shows
the configuration for the internal reference connection resulting
in a input voltage set by VREF, that is, a 2.5 V p-p differential
full-scale input.
VIN+A/VIN+B
VIN–A/VIN–B
ADC
CORE
0.1µF
SENSE
–3
–4
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
LOAD CURRENT (mA)
Figure 58. Reference Voltage Error vs. Load Current
External Reference Operation
The use of an external reference can be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics.
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference that is applied to
the VREF pin. An internal reference buffer loads the external
reference with an equivalent 6 kΩ load. The internal buffer
generates the positive and negative full-scale references for the
ADC core. Therefore, the external reference must be limited to
a maximum of 1.25 V to maintain an input voltage of 2.5 V p-p
differential full-scale input or less.
CLOCK INPUT CONSIDERATIONS
VREF
1.0µF
–2
12169-056
Internal Reference Connection
–1
VREF ERROR (%)
A stable and accurate voltage reference is built into the AD9652.
The full-scale input range can be adjusted by varying the reference
voltage via the SPI. The input span of the ADC linearly tracks
reference voltage changes.
VREF = 1.25V
For optimum performance, clock the AD9652 sample clock
inputs, CLK+ and CLK−, with a differential signal with a high
slew rate. The signal is typically ac-coupled into the CLK+ and
CLK− pins via a transformer or via capacitors. These pins are
biased internally (see Figure 59) and require no external bias. If
the inputs are floated, the CLK− pin is intentionally biased
slightly lower than CLK+ to prevent spurious clocking (this is
not shown in Figure 59).
SELECT
LOGIC
AD9652
12169-039
VSELECT
Figure 57. Internal Reference Configuration
If the internal reference of the AD9652 drives multiple converters
to improve gain matching, the loading of the reference by the
other converters must be considered. Figure 58 shows how the
internal reference voltage is affected by loading.
AVDD_CLK
0.9V
CLK+
CLK–
5pF
12169-041
5pF
Figure 59. Simplified Equivalent Clock Input Circuit
Rev. C | Page 23 of 36
AD9652
Data Sheet
Clock Input Options
A third option is to ac couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 63. The AD9510,
AD9511, AD9512, AD9513, AD9514, AD9515, AD9516-5,
AD9517-1, AD9518-1, AD9520-5, AD9522-1, AD9523, and
AD9524 clock drivers offer excellent jitter performance.
Figure 60 and Figure 61 show two preferable methods for
clocking the AD9652 (at clock rates of up to 1240 MHz). A low
jitter clock source is converted from a single-ended signal to a
differential signal using an RF balun or RF transformer.
CLOCK
INPUT
The RF balun configuration is recommended for clock frequencies
between 125 MHz and 1240 MHz, and the RF transformer is
recommended for clock frequencies from 80 MHz to 200 MHz.
The back-to-back Schottky diodes are used across the transformer
secondary or the balun balanced side to limit clock amplitude
excursions into the AD9652 to approximately 0.8 V p-p differential.
This limit helps prevent large voltage swings of the clock from
feeding through to other portions of the AD9652, while preserving
fast rise and fall times of the clock, which are critical to low
jitter performance.
Mini-Circuits®
ADT1-1WT, 1:1Z
390pF
XFMR
390pF
CLOCK
INPUT
390pF
25Ω
390pF
12169-042
12169-043
Figure 61. Balun-Coupled Differential Clock (Up to 1240 MHz)
The AD9652 contains a clock DCS that retimes the nonsampling
(falling) edge, providing an internal clock signal with a nominal
50% duty cycle. This allows the user to provide a wide range of
clock input duty cycles without affecting the performance of the
AD9652.
If a low jitter clock source is not available, another option is to
ac couple a differential PECL signal to the sample clock input
pins as shown in Figure 62. The AD9510, AD9511, AD9512,
AD9513, AD9514, AD9515, AD9516-5, AD9517-1, AD9518-1,
AD9520-5, AD9522-1, AD9523, AD9524, and ADCLK905/
ADCLK907/ADCLK925 clock drivers offer excellent jitter
performance.
CLOCK
INPUT
AD95xx
0.1µF
50kΩ
50kΩ
ADC
0.1µF
PECL DRIVER
240Ω
CLK+
100Ω
0.1µF
CLK–
240Ω
Figure 62. Differential PECL Sample Clock (Up to 1240 MHz)
12169-044
0.1µF
CLOCK
INPUT
CLK–
50kΩ
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals and, as a result, may be sensitive
to clock duty cycle. Commonly, a ±5% tolerance is required on the
clock duty cycle to maintain dynamic performance characteristics.
CLK–
SCHOTTKY
DIODES:
HSMS2822
25Ω
0.1µF
Clock Duty Cycle
CLK+
1nF
100Ω
Drive the SYNC input using a single-ended CMOS type signal.
If not used, connect the SYNC pin to ground.
ADC
390pF
50kΩ
LVDS DRIVER
The AD9652 clock divider can be synchronized using the external
SYNC input. Bit 1 and Bit 2 of Register 0x100 allow the clock
divider to be resynchronized on every SYNC signal or only on
the first SYNC signal after the register is written. A valid SYNC
causes the clock divider to reset to its initial state. This synchronization feature allows multiple devices to have their clock dividers
aligned to guarantee simultaneous input sampling. With the
divider enabled and the SYNC option used, the ADC clock divider
output phase can be adjusted after synchronization in increments
of input clock cycles using Register 0x16.
Figure 60. Transformer-Coupled Differential Clock (Up to 200 MHz)
CLOCK
INPUT
AD95xx
0.1µF
The AD9652 contains an input clock divider with the ability to
divide the input clock by integer values of 1, 2, 4 or 8. In these
cases, the DCS is enabled by default on power-up. The clock
divide ratio is set in Register 0x0B.
CLK–
SCHOTTKY
DIODES:
HSMS2822
ADC
CLK+
Input Clock Divider
ADC
390pF
0.1µF
Figure 63. Differential LVDS Sample Clock (Up to 625 MHz)
CLK+
100Ω
50Ω
0.1µF
CLOCK
INPUT
Jitter on the rising edge of the input clock is still of paramount
concern and is not reduced by the duty cycle stabilizer. The
DCS control loop does not function for clock rates less than
80 MHz nominally. The loop has a time constant associated
with it that must be considered when the clock rate changes
dynamically. A wait time of 1.5 µs to 5 µs is required after a
dynamic clock frequency increase or decrease before the DCS
loop is relocked to the input clock. During that time period, the
loop is not locked, the DCS loop is bypassed, and internal
device timing is dependent on the duty cycle of the input clock
signal. In some cases, it may be appropriate to disable the duty
Rev. C | Page 24 of 36
12169-045
The AD9652 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal being used, clock source jitter is
of the most concern, as described in the Jitter Considerations
section.
Data Sheet
AD9652
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) can be calculated by
0.9
0.8
0.3
72
70
68
MEASURED
0.8ps
0.2ps
0.1ps
0.05ps
0.05ps
50
500
12169-046
SNRFS (dB)
74
fIN (MHz)
0.5
0.2
180
230
SAMPLE RATE (MSPS)
280
0
12169-047
130
By asserting power-down (either through setting Register 0x08
or by asserting the PDWN pin high), the AD9652 is placed in
power-down mode. In this state, the ADC typically dissipates
less than 1 mW. During power-down, the output drivers are
placed in a high impedance state. Deasserting the PDWN pin
(forcing it low) returns the AD9652 to its normal operating
mode. Note that the level on PDWN is referenced to the digital
output driver supply (DRVDD) and cannot exceed that supply
voltage.
76
5
1.0
0.4
Figure 65. Power and Current vs. Sample Rate
78
60
0.5
0
80
80
62
1.5
0.6
0.1
In the equation, the rms aperture jitter represents the rootmean-square of all jitter sources, which includes the clock
input, the analog input signal, and the ADC aperture jitter
specification. IF undersampling applications are particularly
sensitive to jitter, as shown in Figure 64.
64
2.0
0.7
SNRHF = −10 log[(2π × fIN × tJRMS)2 + 10 ( − SNRLF /10) ]
66
2.5
AVDD3
AVDD_CLK
DRVDD/SPIVDD
AVDD
POWER
POWER (W)
Jitter Considerations
1.0
CURRENT (A)
cycle stabilizer, for example, if a high quality RF clock is
available to drive the AD9652 clock input and does not need
adjustment in duty cycle correction. In most other applications,
enabling the DCS circuit is recommended to maximize ac
performance.
Figure 64. SNRFS vs. Input Frequency and Jitter
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9652.
Drive external clock sources and buffers from a clean ADC
output driver supply to avoid modulating the ADC clock with
noise. Low jitter, crystal controlled oscillators make the best
clock sources. If the clock is generated from another type of
source (by gating, dividing, or another method), retime it by the
original clock at the last step.
Refer to the AN-501 Application Note, Aperture Uncertainty
and ADC System Performance, and the AN-756 Application
Note, Sampled Systems and the Effects of Clock Phase Noise and
Jitter, for more information about jitter performance as it relates
to ADCs.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 65, the power dissipated by the AD9652 is
proportional to its sample rate. The data in Figure 65 was taken
using the same operating conditions as those used for the
Typical Performance Characteristics section.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times.
When using the SPI port interface, the user can place the ADC
in power-down mode or standby mode. Standby mode allows
the user to keep the internal reference circuitry powered when
faster wake-up times are required. See the AN-877 Application
Note, Interfacing to High Speed ADCs via SPI, for additional
details.
INTERNAL BACKGROUND CALIBRATION
The AD9652 uses a background calibration to continually correct
errors between internal analog circuits to maintain the high
level of noise performance over varying conditions. The calibration
correction digitally monitors the errors in the various analog
blocks, calculates the error, and applies corrections. The background correction is calculated every 3 × 233 samples; therefore,
when running at 310 MSPS, the update rate is about 83 seconds.
Each calibration cycle is independent from previous calibrations to
improve tracking. There are no requirements on the input signal
for the background calibration.
The calibration occurs independently for each ADC path. The
background calibration continually operates but does not
update if the input signal is significantly out of range (beyond
the OTR) because this can cause errors in the calibration
calculation.
Rev. C | Page 25 of 36
AD9652
Data Sheet
The calibration engine monitors any errors and resets the
calibration cycle if the input signal exceeds the input range for
1000 samples within a single calibration cycle.
At startup, when the AD9652 is first powered and a valid clock
is applied, a fast start-up background calibration is performed
and converges 64 times faster than the normal calibration cycle.
At 310 MSPS, the fast start-up calibration updates after 1.3 seconds.
The fast start-up calibration allows the AD9652 to be used
sooner than waiting for a full calibration cycle and typically
degrades SNR performance by less than 0.5 dB. This degradation
lasts until a full calibration cycle completes.
In cases where configuration of the AD9652 changes and a
recalibration is needed, a fast start-up calibration can be
initiated by an SPI register write or by asserting and
deasserting the PDWN pin.
To initiate using the SPI register, use Register 0x08[1:0]. To start
a new fast calibration, put either or both ADC channels in
standby and then return them to normal operation mode by
writing 0x2 and then 0x0 to Register 0x08[1:0]. After returning
to normal operation mode, the fast calibration is initiated one
time followed by the normal, full calibration cycle. In addition
to standby, this is also the case for power-down. Writing a 0x1
followed by a 0x0 initiates a fast calibration. Alternatively, a fast
start-up calibration can be initiated by writing 0x0C and then
0x08 to Register 0x4FB.
The PDWN pin can be configured to put the device in powerdown or standby mode based on the setting in Register 0x08[1:0].
Transitioning from either power-down or standby into normal
mode causes a fast calibration to be initiated. Configuration
changes that require a new calibration include, but are not
limited to, changes of setting for VREF, dither enable/disable,
clock input changes, and DCS state changes.
There are various advanced configuration options associated
with the background calibration for applications that require
special treatment. The options include an optional recovery
mode for standby and a pausing background calibration.
If standby is used in an application, by default, the AD9652
keeps the current corrections, but initiates a new fast calibration
when returning to normal operation mode. For standby, if
conditions have not significantly changed, the AD9652 can be
configured to retain the last correction coefficients by writing
0x00 to Register 0x4FA before entering the standby mode. This
returns the device to the same operation as when it entered
standby, retaining previous calibration values in standby mode
and continuing the normal calibration cycle when returned to
normal operation mode.
Although this is not recommended, in some instances such as
when all the environmental, clocking, and input signals are very
stable, the calibration can be paused. Pausing the background
calibration causes a slight degradation in performance, but can
be accomplished by writing 0x1 to Register 0x4FB, Bit 0. To reenable the background calibration, write 0x0 to Register 0x4FB,
Bit 0. Note: Register 0x4FB has reserved bits that must be
preserved when accessing that and similar registers.
DIGITAL OUTPUTS
The AD9652 output drivers are for standard ANSI LVDS, but
optionally the drive current can be reduced using Register 0x15.
The reduced drive current for the LVDS outputs potentially
reduce the digitally induced noise.
As detailed in the AN-877 Application Note, Interfacing to High
Speed ADCs via SPI, the data format can be selected for offset
binary, twos complement, or gray code when using the SPI
control.
The AD9652 has a flexible three-state ability for the digital
output pins. The three-state mode is enabled when the device is
set for power-down mode.
Timing
The AD9652 provides latched data with a pipeline delay of
26 input sample clock cycles. Data outputs are available one
propagation delay (tPD) after the rising edge of the clock signal.
Minimize the length of the output data lines and the corresponding
loads to reduce transients within the AD9652. These transients
can degrade converter dynamic performance.
The lowest typical conversion rate of the AD9652 is 80 MSPS.
At clock rates below 80 MSPS, dynamic performance may
degrade.
Data Clock Output
The AD9652 also provides a data clock output (DCO) intended
for capturing the data in an external register. Figure 2 shows a
timing diagram of the AD9652 output modes. The DCO relative to
the data output can be adjusted using Register 0x17. There are 32
delay settings with approximately 81 ps per step. Data is output
in a DDR format and is aligned to the rising and falling edges of
the clock derived from DCO±.
ADC OVERRANGE
The ADC overrange (OR) indicator is asserted when an
overrange is detected on the input of the ADC. The overrange
condition is determined at the output of the ADC pipeline and,
therefore, is subject to a latency of 26 ADC clocks. An
overrange at the input is indicated by this bit, 26 clock cycles
after it occurs.
Rev. C | Page 26 of 36
Data Sheet
AD9652
Table 13. Output Data Format
Differential Input Voltage (V):
(VIN+x) – (VIN–x)
Input Span = 2.5 V p-p (V)
+1.25
Offset Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Twos Complement Mode (Default)
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
Rev. C | Page 27 of 36
OR± Pin Logic Level
1
0
0
0
1
AD9652
Data Sheet
FAST THRESHOLD DETECTION (FDA/FDB)
The selected threshold register is compared with the signal
magnitude at the output of the ADC. The fast upper threshold
detection has a latency of seven clock cycles. The approximate
upper threshold is a 4-bit value defined by
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped. The
standard overflow indicator on the OR± pins provide delayed
information, which is synchronized with the output data. The
delayed indicator is of limited value in preventing clipping in this
case. Therefore, it is helpful to have a programmable threshold
below full scale that allows time to reduce external gain before the
clip occurs. In addition, because input signals can have significant
slew rates, latency of this function is of concern.
Upper Threshold (% Full Scale) =
((Register 0x47 value)/8) × 100%
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, Register 0x49 and Register 0x4A. The fast detect lower
threshold register is a 15-bit register that is compared with the
signal magnitude at the output of the ADC. This comparison is
subject to the ADC pipeline latency but is accurate in terms of
converter resolution. The lower threshold is defined by
Using the SPI port, the user can provide a threshold above
which the fast detect (FD) output is active. Bit 0 of Register 0x45
enables the FD feature. Register 0x47 to Register 0x4C allow the
user to set the threshold levels and timing. As long as the signal
is below the selected threshold, the FD output remains low. In
this mode, the magnitude of the data is considered in the calculation of the condition, but the sign of the data (either positive
or negative) is not considered. The threshold detection responds
identically to positive and negative signals outside the desired
range (magnitude).
Lower Threshold (% Full Scale) =
((Register 0x49/Register 0x4A value)/32767) × 100%
For example, to set an upper threshold of 50% full scale, write
0x04 to Register 0x47, and to set a lower threshold of 40% full
scale, write 0x3333 to Register 0x49 and Register 0x4A.
The fast detect indicators, FDA for Channel A and FDB for
Channel B, are asserted when the input magnitude exceeds the
value programmed in the fast detect upper threshold register,
Register 0x47.
The dwell time can be programmed from 1 sample clock cycle
to 65,535 sample clock cycles by placing the desired value in the
fast detect dwell time registers, Register 0x4B and Register 0x4C
(see Figure 66).
UPPER THRESHOLD
DWELL TIME
LOWER THRESHOLD
DWELL TIME
FDA OR FDB
Figure 66. Threshold Settings for FDA and FDB Signals
Rev. C | Page 28 of 36
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE
LOWER THRESHOLD
12169-048
MIDSCALE
TIMER RESET BY
RISE ABOVE
LOWER
THRESHOLD
Data Sheet
AD9652
SERIAL PORT INTERFACE
The AD9652 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
The SPI gives the user added flexibility and customization,
depending on the application. Addresses are accessed via the
serial port and can be written to or read from via the port.
Memory is organized into bytes that can be further divided into
fields. These fields are documented in the Memory Map
section. For detailed operational information, see the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
CONFIGURATION USING THE SPI
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a readback
operation, performing a readback causes the serial data input/
output (SDIO/DCS) pin to change direction from an input to an
output at the appropriate point in the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see the AN-877 Application Note.
Three pins define the SPI of this ADC: the SCLK pin, the SDIO
pin, and the CSB pin (see Table 14). The SCLK (serial clock) pin
synchronizes the read and write data presented from/to the ADC.
The SDIO (serial data input/output) pin is a dual-purpose pin
that allows data to be sent and read from the internal ADC
memory map registers. The CSB (chip select bar) pin is an
active low control that enables or disables the read and write cycles.
HARDWARE INTERFACE
Table 14. Serial Port Interface Pins
The SPI interface is flexible enough to be controlled by either
field-programmable grid arrays (FPGAs) or microcontrollers.
One method for SPI configuration is described in detail in the
AN-812 Application Note, Microcontroller-Based Serial Port
Interface (SPI) Boot Circuit.
Pin
SCLK
SDIO
CSB
Function
Serial clock. The serial shift clock input, which synchronizes
serial interface reads and writes.
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active low control that gates the read
and write cycles. Must be pulled to logic high during
power up.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Table 5 and
Figure 4.
Other modes involving the CSB pin are available. The CSB pin
can be held low indefinitely, which permanently enables the
device; this is called streaming. The CSB pin can stall high
between bytes to allow for additional external timing. When
CSB is tied high, SPI functions are placed in a high impedance
mode.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase, and its length is determined
by the W0 and the W1 bits.
All data is composed of 8-bit words. The first bit of each
individual byte of serial data indicates whether a read or write
command is issued. This allows the serial data input/output
(SDIO) pin to change direction from an input to an output.
The pins described in Table 14 comprise the physical interface
between the user programming device and the serial port of the
AD9652. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI port must not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is used
for other devices, it may be necessary to provide buffers between
this bus and the AD9652 to prevent these signals from transitioning at the converter inputs during critical sampling periods.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO pin and the SCLK pin serve as standalone CMOScompatible control pins. When the device is powered up, it is
assumed that the user intends to use the pins as static control
lines for the DCS and output data format feature control. In this
mode, connect CSB to AVDD, which disables the serial port
interface.
Table 15. Mode Selection
Pin
SDIO
SCLK
Rev. C | Page 29 of 36
External Voltage
AVDD (default)
AGND
AVDD
AGND (default)
Configuration
DCS enabled
DCS disabled
Twos complement enabled
Offset binary enabled
AD9652
Data Sheet
SPI ACCESSIBLE FEATURES
Table 16 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the AN-877 Application Note.
Table 16. Features Accessible Using the SPI
Feature Name
Power Modes
Clock
Offset
Test I/O
Output Mode
Output Phase
Output Delay
VREF
Description
Allows the user to set either power-down mode or standby mode
Allows the user to access the DCS via the SPI
Allows the user to digitally adjust the converter offset
Allows the user to set test modes to have known data on output bits
Allows the user to set up outputs
Allows the user to set the output clock polarity
Allows the user to vary the delay of the clock derived from DCO±
Allows the user to set the reference voltage
Rev. C | Page 30 of 36
Data Sheet
AD9652
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Logic Levels
Each row in the memory map register table has eight bit
locations. The memory map is roughly divided into three
sections: the chip configuration registers (Address 0x00 to
Address 0x02); the channel index and transfer registers
(Address 0x05 and Address 0xFF); and the ADC functions
registers, including setup, control, and test (Address 0x08 to
Address 0x4FB).
An explanation of logic level terminology follows:
The memory map register table (see Table 17) documents the
default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the
default hexadecimal value given. For example, Address 0x09,
the global clock register, has a hexadecimal default value of
0x01. This means that the LSB or Bit 0 = 1, and the remaining
bits are 0s. This setting is the default output format value, which
is twos complement. For more information on the functions
controlled by Register 0x00 to Register 0x17, see the AN-877
Application Note. This application note also details the
functions controlled by all remaining registers.
The 0x08, 0x0D, 0x10, 0x14, 0x30, and 0x45 to 0x4C registers
are shadowed. Writes to these addresses do not affect device
operation until a transfer command is issued by writing 0x01 to
Address 0xFF, which sets the transfer bit. This allows these registers
to be updated internally and simultaneously when the transfer bit
is set. The internal update occurs when the transfer bit is set,
and then the bit autoclears.
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
Transfer Register Map
Open and Reserved Locations
All address and bit locations that are not included in Table 17
are not currently supported for this device. Unused bits of a
valid address location must be written with 0s, unless otherwise
noted. Writing to these locations is required only when part of
an address location is open (for example, Address 0x18). If the
entire address location is open/unused/undocumented (for
example, Address 0x13), this address location must not be written.
Default Values
After the AD9652 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 17.
Channel Specific Registers
Some channel setup functions, such as the signal monitor
thresholds, can be programmed to a different value for each
channel. In these cases, channel address locations are internally
duplicated for each channel. These registers and bits are designated
in Table 17 as local. These local registers and bits can be accessed
by setting the appropriate Channel A or Channel B bits in
Register 0x05. If both bits are set, the subsequent write affects
the registers of both channels. In a read cycle, only Channel A
or Channel B are set to read one of the two registers. If both bits
are set during an SPI read cycle, the device returns the value for
Channel A. Registers and bits designated as global in Table 17
affect the entire device and the channel features for which
independent settings are not allowed. The settings in Register 0x05
do not affect the global registers and bits.
Rev. C | Page 31 of 36
AD9652
Data Sheet
MEMORY MAP REGISTER TABLE
All address and bit locations that are not included in Table 17 are not currently supported for this device.
Table 17. Memory Map Registers
Addr
Register
Bit 7
(Hex)
Name
(MSB)
Chip Configuration Registers
0x00
SPI port
0
configuration
(global) 1
0x01
0x02
Chip ID
(global)
Chip grade
(global)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
LSB first
Soft reset
1
1
Soft reset
LSB first
0
0x09
Reserved,
set to 1
0x18
The nibbles
are mirrored
so that LSB
first mode
or MSB first
mode
registers
correctly,
regardless
of shift
mode
Read only
0xC1
Speed grade ID,
0x00: default
0x00
Speed
grade ID
differentiates
devices;
read only
Channel A
(default)
0x03
Transfer
0x00
Bits are
set to
determine
which
device on
the chip
receives
the next
write
command;
applies to
local
registers
only
Synchronously
transfers
data from
the master
shift register
to the slave
Channel B
(default)
Transfer
(global)
ADC Functions
0x08
Power
modes
(local)
Default
Notes/
Comments
8-Bit Chip ID[7:0], (AD9652 = 0xC1) (default)
Channel Index and Transfer Registers
0x05
Channel
index
(global)
0xFF
Default
Value
(Hex)
Internal power-down
mode (local)
00 = normal operation
01 = full power-down
10 = standby
11 = reserved
External
powerdown pin
function
(local)
0=
powerdown
1=
standby
Global clock
(global)
Enable
DCS
(default)
Rev. C | Page 32 of 36
0x80
0x01
Controls
powerdown
options
Data Sheet
Addr
(Hex)
0x0B
Register
Name
Clock divide
(global)
0x0D
Test mode
(local)
0x0F
Commonmode servo
(global)
0x10
Offset adjust
(local)
Output
mode (local)
0x14
0x15
Output
LVDS
control
(global)
0x16
Clock phase
adjust
(global)
0x17
DCO±
output delay
(global)
0x18
Input span
select
(global)
0x30
Dither (local)
AD9652
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Reset PN23
long gen
PN23:
1 + x17 +
x22
Reset
PN9
short gen
PN9:
1 + x3 + x8
Bit 3
Bit 0
Bit 2
Bit 1
(LSB)
Clock divide ratio
000 = divide by 1
001 = divide by 2
010 = reserved, do not use
011 = divide by 4
100 = divide by 8
Output test mode
0000 = off (default)
0001 = midscale short
0010 = positive FS
0011 = negative FS
0100 = alternating checkerboard
0101 = PN23 long sequence
0110 = PN9 short sequence
0111 = one/zero word toggle
Enable
commonmode
servo
Offset adjust in LSBs from +127 (0111 1111) to −128 (1000 0000)
(twos complement format)
Reserved,
set to 1
Output format
00 = offset binary
(default)
01 = twos complement
10 = gray code
11 = reserved
LVDS output drive current adjust
000 = 3.72 mA (ANSI-LVDS,
default)
001 = 3.50 mA
010 = 3.30 mA
011 = 2.96 mA
100 = 2.82 mA
101 = 2.57 mA
110 = 2.27 mA
111 = 2.00 mA (reduced swing
LVDS)
Input clock divider phase adjust
000 = no delay
001 = 1 input clock cycle
010 = 2 input clock cycle
011 = 3 input clock cycle
100 = 4 input clock cycle
101 = 5 input clock cycle
110 = 6 input clock cycle
111 = 7 input clock cycle
DCO± clock delay
(Delay = (2500 ps × register value/31))
00000 = 0 ps
00001 = 81 ps
00010 = 161 ps
…
11110 = 2419 ps
11111 = 2500 ps
VREF select
000 = 1.25 V (2.5 V p-p input), default
001 = 1.125 V (2.25 V p-p input)
010 = 1.20 V (2.4 V p-p input)
011 = 1.25 V (2.5 V p-p input)
100 = do not use
101 = 1.0 V (2.0 V p-p input)
Reserved,
set to 1
Dither
enable
Rev. C | Page 33 of 36
Default
Value
(Hex)
0x00
Default
Notes/
Comments
0x00
When this
register is
set, the test
data is
placed on
the output
pins (D0±
to D15±) in
place of
normal data
0x00
0x00
0x00
0x00
0x00
0x00
0xC0
0x00
Configures
the outputs
and the
format of
the data
AD9652
Addr
(Hex)
0x45
Register
Name
Fast detect
(FD) control
(local)
0x47
FD upper
threshold
(local)
0x49
FD lower
threshold
(local)
FD lower
threshold
(local)
FD dwell
time (local)
FD dwell
time (local)
SYNC
control
(global)
0x4A
0x4B
0x4C
0x100
0x212
Dither gain
(global)
0x22A
Input
frequency
settings
(global)
Calibration
powerdown
configuration
(global)
0x4FA
0x4FB
1
Calibration
power-down
configuration (global)
Data Sheet
Bit 7
(MSB)
Bit 6
Bit 5
Bit 0
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Enable
fast
detect
output
Fast Detect Upper Threshold[3:0]
Valid programming range = 0x1 to 0x8
Threshold = midscale ± (register value) × (1/8) ×
(full scale)
Fast Detect Lower Threshold[7:0]
Fast Detect Lower Threshold[14:8]
Default
Value
(Hex)
0x00
0x08
0x00
0x02
Fast Detect Dwell Time[7:0]
0x00
Fast Detect Dwell Time[15:8]
0x08
Reserved,
set to 0
0b0000: 100% dither applied
0b0001: 99.6% dither applied
0b0010: 99.2% dither applied
0b0011: 98.4% dither applied
0b0100: 96.8% dither applied
0b0101: 93.75% dither applied
0b0110: 87.5% dither applied
0b0111: 75% dither applied
0b1000: 50% dither applied
Clock
divider
next SYNC
only
Reserved,
set to 0
Reserved,
set to 0
Reserved,
set to 0
Reserved,
set to 0
Reserved,
set to 0
Reserved,
set to 0
Reserved,
set to 0
Reserved,
set to 0
Reserved,
set to 0
Reserved,
set to 0
Reserved,
set to 0
Reserved,
set to 1
Reset
background
calibration,
set high
then low
Set the channel index register at Address 0x05 to 0x03 (default) when writing to Address 0x00.
Rev. C | Page 34 of 36
Clock
divider
SYNC
enable
Reserved,
set to 0
Master
SYNC
buffer
enable
Reserved,
set to 0
0: fIN in 1st Nyquist
1: fIN in 2nd Nyquist
2: fIN in 3rd Nyquist or
higher
Power down/standby
initial calibration
action:
0b00: use previous
calibration correction
0b11: initiate a fast
calibration
Reserved, Pause
set to 0
background
calibration
0x00
0x08
0x00
0x03
0x08
Default
Notes/
Comments
Data Sheet
AD9652
APPLICATIONS INFORMATION
DESIGN GUIDELINES
VCM
Before starting system level design and layout of the AD9652, it
is recommended that the designer become familiar with these
guidelines, which describes the special circuit connections and
layout requirements needed for certain pins.
The VCM pin must be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 54. For optimal channel-to-channel
isolation, a 33 Ω resistor must be included between the AD9652
VCM pin and the Channel A analog input network connection,
as well as between the AD9652 VCM pin and the Channel B
analog input network connection.
Power and Ground Recommendations
When connecting power to the AD9652, it is recommended that
three separate power supplies be used. AVDD3 requires a 3.3 V
supply, AVDD_CLK and AVDD require a 1.8 V supply, and
DRVDD requires a 1.8 V supply. SPIVDD is typically connected
to the same supply as DRVDD, but can be connected to a separate
supply between 1.8 V and 3.3 V to ease the interface to the logic
device that connects to the SPI pins (CLK, SDIO, and CSB).
The AVDD3 supply must be supplied from a clean 3.3 V power
source. Decoupling must be a combination of PCB plane
capacitance and decoupling capacitors to cover both high and low
frequency noise sources. Typical capacitors of 0.1 μF and 1 μF
near the AD9652 AVDD3 pins are advised.
The AVDD and AVDD_CLK supply connection must be
powered up simultaneously to achieve proper on-chip biasing;
therefore, it is recommended to connect the two supply voltages
to a single source. Similar to the AVDD3 supply, decoupling must
be a combination of PCB plane capacitance and decoupling
capacitors to cover both high and low frequency noise sources.
Typical capacitors of 0.1 μF and 1 μF near the AD9652 AVDD
and AVDD_CLK pins is advised.
RBIAS
The AD9652 requires that a 10 kΩ resistor be placed between
the RBIAS pin and ground. This resistor sets the master current
reference of the ADC core and must have at least a 1% tolerance.
Reference Decoupling
Decouple the VREF pin externally to ground with a low ESR,
1.0 μF capacitor in parallel with a low ESR, 0.1 μF ceramic
capacitor.
SPI Port
The SPI port must not be active during periods when the full
dynamic performance of the converter is required. Because the
SCLK, CSB, and SDIO signals are typically asynchronous to the
ADC clock, noise from these signals can degrade converter
performance. If the on-board SPI bus is used for other devices,
it may be necessary to provide buffers between this bus and the
AD9652 to keep these signals from transitioning at the converter
input pins during critical sampling periods.
The DRVDD and SPIVDD supply connection must also have
decoupling but these can be placed slightly further away from
the AD9652. DRVDD and SPIVDD can be tied together for
applications that can use a 1.8 V SPI interface logic. Optionally,
SPIVDD can be driven with a supply of up to 3.3 V to support
higher voltage logic interfaces.
Multiple large area PCB ground planes are recommended and
provide many benefits. Low impedance power and ground
planes are needed to maintain performance. Stacking power and
ground planes in the PCB provides high frequency decoupling.
Ground planes and thermal vias help dissipate heat generated
by the device. With proper decoupling and smart partitioning
of the PCB analog, digital, and clock sections, optimum
performance is easily achieved.
Rev. C | Page 35 of 36
AD9652
Data Sheet
OUTLINE DIMENSIONS
A
B
C
D
E
F
G
H
J
K
L
M
8.80
BSC SQ
0.80
BSC
TOP VIEW
1.40
1.34
1.19
DETAIL A
A1 BALL
CORNER
12 11 10 9 8 7 6 5 4 3 2 1
0.60 REF
BOTTOM VIEW
0.33 NOM
0.28 MIN
SEATING
PLANE
DETAIL A
1.11
1.01
0.91
*0.50
0.45
0.40
BALL DIAMETER
COPLANARITY
0.12
*COMPLIANT WITH JEDEC STANDARDS MO-275-EEAA-1
WITH THE EXCEPTION TO BALL DIAMETER.
11-18-2011-A
A1 BALL
CORNER
10.10
10.00 SQ
9.90
Figure 67. 144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-144-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9652BBCZ-310
AD9652BBCZRL7-310
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
144-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Z = RoHS Compliant Part.
©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12169-0-1/18(C)
Rev. C | Page 36 of 36
Package Option
BC-144-6
BC-144-6
工商网监
湘ICP备2023018690号
