Precision Analog Microcontroller, Tunable
Optical Control Microcontroller
ADuCM310
Data Sheet
FEATURES
External 16 MHz crystal option
External clock source
Memory
2× 128 kB Flash/EE memories, 32 kB SRAM
In-circuit download, SW-DP-based debugging
Software triggered in-circuit reprogrammability
On-chip peripherals
UART, 2× I2C and 2× SPI serial input/output
28-pin general-purpose input/output (GPIO) port
3 general-purpose timers
Wake-up (W/U) timer
Watchdog timer (WDT)
32-element programmable logic array (PLA)
Vectored interrupt controller
Interrupt on edge or level external pin inputs
9× external interrupts
Power
Multiple supplies
5 V for VDAC6 and VDAC7
3.3 V for digital and analog inputs/outputs
1.8 V to 2.7 V for IDACs
−5 V supply for IDAC3 and VDAC2/VDAC3
Package and temperature range
6 mm × 6 mm, 112-ball CSP_BGA package
Fully specified for −40°C to +85°C ambient operation
Tools
QuickStart™ development system
Full third party support
Analog input/output
22-channel, 14-bit, 800 kSPS analog-to-digital
converter (ADC)
10 external channels
1 on-chip die temperature monitor
6 current output digital-to-analog converter (IDAC)
monitor channels
3 power monitor channels
2 buffered reference output channels
Fully differential and single-ended modes
0 V to 2.5 V analog input range
6 low noise, 12-/14-bit IDAC outputs
1× 250 mA, 1× 200 mA, 2× 100 mA, and 2× 20 mA
Semiconductor optical amplifier (SOA) IDAC pull-down
to −3.0 V for fast current sink
Eight 12-bit voltage output DACs (VDACs)
Channel 0 and Channel 1: 0 V to 3 V, 75 Ω load
Channel 2 and Channel 3: −5 V to 0 V, 500 Ω load
Channel 4 and Channel 5: 0 V to 3 V, 300 Ω load
Channel 6: 0 V to 5 V, 500 Ω load
Channel 7: 0 V to 5 V, 100 Ω load
2.5 V, on-chip voltage reference
2 buffered 2.5 V outputs
Microcontroller
ARM Cortex-M3 processor, 32-bit RISC architecture
Serial wire port supports code download and debugging
Clocking options
Trimmed on-chip oscillator (±3%)
80 MHz phase-locked loop (PLL)
APPLICATIONS
Optical modules—tunable laser modules
FUNCTIONAL BLOCK DIAGRAM
AIN0
BUF
32.786kHz
16MHz OSC
80MHz PLL
POR
AIN9
INTERNAL CHANNELS,
IDACs, TEMPERATURE,
SUPPLIES
2.5V BAND
GAP VREF
VREF_1.2
BUF_VREF2.5A
MEMORY
256k FLASH
32k SRAM
BUF_VREF2.5B
VDAC0
ARM
CORTEX-M3
PROCESSOR
VDAC
VDAC7
VDAC
IDAC0
IDAC
IDAC5
IDAC
ON-CHIP
1.8V LDO
GPIO PORTS
UART PORT
2 × SPI PORT
2 × I2C PORT
EXT IRQs
DMA
NVIC
3 × GP TIMER
WD TIMER
W/U TIMER
PWM
PLA
32 × ELEMENTS
SERIAL
WIRE
RESET
IOVDDx
PVDD_IDACx
AVDDx
DGNDx
PGND
GENERALPURPOSE
I/O PORTS
ADuCM310
SWDIO
SWCLK
13040-001
MUX
14-BIT
SAR
ADC
Figure 1.
Rev. C
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ADuCM310
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Thermal Resistance .................................................................... 17
Applications ....................................................................................... 1
ESD Caution................................................................................ 17
Functional Block Diagram .............................................................. 1
Pin Configuration and Function Descriptions........................... 18
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 22
General Description ......................................................................... 3
Recommended Circuit and Component Values ........................ 25
Specifications..................................................................................... 4
Outline Dimensions ....................................................................... 27
Timing Specifications ................................................................ 12
Ordering Guide .......................................................................... 27
Absolute Maximum Ratings.......................................................... 17
REVISION HISTORY
2/2019—Rev. B to Rev. C
Changes to IDAC0 and IDAC1 Parameter, Table 1 ..................... 7
Added Allowed Power-Up Time for DVDD Supply Parameter,
Table 1 .............................................................................................. 10
Changes to Ordering Guide .......................................................... 27
7/2017—Rev. A to Rev. B
Change to Features ........................................................................... 1
Change to General Description ...................................................... 3
Changes to Specifications Section and Table 1 ............................. 4
Added Endnote 1, Table 1; Renumbered Sequentially .............. 12
11/2015—Rev. 0 to Rev. A
Change to Features Section ..............................................................1
Changes to Specifications Section and Table 1 ..............................4
Changes to Table 6 and Figure 5 ................................................... 15
Changes to Table 7 and Figure 6 ................................................... 16
Changes to Figure 7 ........................................................................ 18
5/2015—Revision 0: Initial Version
Rev. C | Page 2 of 27
Data Sheet
ADuCM310
GENERAL DESCRIPTION
The ADuCM310 is a multidie stack, on-chip system designed
for diagnostic control of tunable laser optical module applications.
The ADuCM310 features a 16-bit (14-bit accurate) multichannel
successive approximation register (SAR) ADC, an ARM
Cortex™-M3 processor, eight voltage DACs (VDACs), six
current output DACs, and Flash/EE memory packaged in a
6 mm × 6 mm, 112-ball CSP_BGA package.
The bottom die in the stack supports the bulk of the low voltage
analog circuitry and is the largest of the three die. It contains
the ADC, VDACs, main IDAC circuits, as well as other analog
support circuits, such as the low drift precision 2.5 V voltage
reference source.
The middle die in the stack supports the bulk of the digital
circuitry, including the ARM Cortex-M3 processor, the flash
and SRAM blocks, and all of the digital communication
peripherals. In addition, this die provides the clock sources for
the whole chip. A 16 MHz internal oscillator is the source of the
internal PLL that outputs an 80 MHz system clock.
The top die, which is the smallest die, was developed on a high
voltage process, and this die supports the −5 V and +5 V
VDAC outputs. It also implements the SOA IDAC current sink
circuit that allows the external SOA diode to pull to a −3.0 V
level to implement the fast shutdown of the laser output.
Regarding the individual blocks, the ADC is capable of
operating at conversion rates up to 800 kSPS. There are
10 external inputs to the ADC, which can be single ended or
differential. Several internal channels are included, such as the
supply monitor channels, an on-chip temperature sensor, and
internal voltage reference monitors.
The VDACs are 12-bit string DACs with output buffers capable
of sourcing between 10 mA and 50 mA, and these DACs are all
capable of driving 10 nF capacitive loads.
The low drift current DACs have 14-bit resolution and varied
full-scale output ranges from 0 mA to 20 mA to 0 mA to
250 mA on the SOA IDAC (IDAC3). The SOA IDAC also
comes with a 0 mA to −80 mA current sink capability.
A precision 2.5 V on-chip reference source is available. The
internal ADC, IDACs, and VDAC circuits use this on-chip
reference source to ensure low drift performance for all of these
peripherals
The ADuCM310 also provides 2× buffered reference outputs
capable of sourcing up to 1.2 mA. These outputs can be used
externally to the chip.
The ADuCM310 integrates an 80 MHz ARM Cortex-M3
processor. It is a 32-bit reduced instruction set computer (RISC)
machine, offering up to 100 DMIPS peak performance. The ARM
Cortex-M3 processor also has a flexible 14-channel direct
memory access (DMA) controller supporting serial peripheral
interface (SPI), UART, and I2C communication peripherals.
The ADuCM310 has 256 kB of nonvolatile Flash/EE memory
and 32 kB of SRAM integrated on-chip.
A 16 MHz on-chip oscillator generates the 80 MHz system
clock. This clock internally divides to allow the processor to
operate at lower frequency, thus saving power. A low power
internal 32 kHz oscillator is available and can clock the timers.
The ADuCM310 includes three general-purpose timers, a
wake-up timer (which can be used as a general-purpose timer),
and a system watchdog timer.
A range of communication peripherals can be configured as
required in a specific application. These peripherals include
UART, 2 × I2C, 2 × SPI, GPIO ports, and pulse-width
modulation (PWM).
On-chip factory firmware supports in-circuit serial download via
the UART, while nonintrusive emulation and program download
are supported via the serial wire debug port (SW-DP) interface.
These features are supported on the EVAL-ADuCM310QSPZ
development system.
The ADuCM310 operates from 2.9 V to 3.6 V and is specified
over a temperature range of −40°C to +85°C.
Note that, throughout this data sheet, multifunction pins, such
as P1.0/SIN/ECLKIN/PLAI[4], are referred to either by the
entire pin name or by a single function of the pin, for example,
P1.0, when only that function is relevant.
For additional information on the ADuCM310, see the
ADuCM310 reference manual, How to Set Up and Use the
ADuCM310.
Rev. C | Page 3 of 27
ADuCM310
Data Sheet
SPECIFICATIONS
AVDD = IOVDD = DVDD = 2.9 V to 3.6 V (the input supply voltages). The difference between AVDD, IOVDD, and DVDD must be ≤0.3 V.
AVNEG (the supply voltage) = −5.5 V to −4.65 V. VDACVDD (the VDAC supply voltage) = 3.07 V to 5.35 V (for VDAC6 and VDAC7),
and VDACVDD must be ≥ AVDD. PVDD (the IDAC supply voltage) for the IDACs = 1.8 V to 2.7 V. AVDD ≥ PVDD + 0.4V. VREF = 2.5 V
internal reference, fCORE = 80 MHz, TA = −40°C to +85°C, unless otherwise noted.
For power sequencing, connect the AGND, DGND, PGND, and IOGND pins to ground before applying power to the AVNEG or VDACVDD pins.
For register and bit information, see the ADuCM310 reference manual, How to Set Up and Use the ADuCM310.
Table 1.
Parameter
ADC CHANNEL SPECIFICATIONS
ADC Power-Up Time
DC Accuracy
Resolution
Integral Nonlinearity
Input Buffer
Disabled
Min
Internal Channels
Gain Error Drift2
Test Conditions/Comments
All measurements in single-ended
mode, unless otherwise stated
fSAMPLE ≥500 kSPS
Bits
−0.99
±2
±1.51
±2.5
±2
±1.51
±0.7
+1.51
LSB
LSB
LSB
LSB
LSB
LSB
−0.99
±0.7
+2.0
LSB
±3
±5
LSB
2.5 V internal reference
2.5 V internal reference
External reference
External reference
2.5 V external reference;
no missing codes
2.5 V external reference;
no missing codes
ADC input voltage = 1.25 V dc
ADC update rate up to 800 kSPS
−0.8
±0.2
+0.8
mV
−0.61
±0.2
+0.61
mV
Offset Error Drift2
Buffer On or Buffer Off
Full-Scale Error
Buffer On or Buffer Off
Unit
μs
14
DC Code Distribution
ENDPOINT ERRORS
Offset Error (All Channels Except
the Internal Channels)
Buffer On or Buffer Off
Max
5
Enabled
Disabled
Differential Nonlinearity
Typ
−0.75
−0.71
±3.2
μV/°C
±2.51
μV/°C
±0.2
±0.2
±0.2
+0.75
+0.61
+1
mV
mV
% of full scale
±0.2
±0.61
% of full scale
0.75
2
% of full scale
0.75
1.51
% of full scale
2
μV/°C
Rev. C | Page 4 of 27
Buffer on, chop mode on and
automatic zero or buffer off
Buffer on, chop mode on and
automatic zero or buffer off
Buffer on, chop mode on and
automatic zero or buffer off
Buffer on, chop mode on and
automatic zero or buffer off
ADC update rate up to 800 kSPS
Excluding internal channels
Excluding internal channels
Input buffer on; AVDD/2, IOVDD/2,
PVDD voltage on PVDD_IDAC2 pin
Input buffer on; AVDD/2, IOVDD/2,
PVDD voltage on PVDD_IDAC2 pin
Input buffer on; IDAC0 to IDAC5;
measured with 1.5 V on the IDAC0
to IDAC5 pins
Input buffer on; IDAC0 to IDAC5;
measured with 1.5 V on the IDAC0
to IDAC5 pins
Full-scale error drift minus offset
error drift; all modes; internal
reference
Data Sheet
Parameter
DYNAMIC PERFORMANCE2
ADuCM310
Min
Signal-to-Noise Ratio (SNR)
Input Buffer
Disabled
Enabled
Total Harmonic Distortion (THD)
Input Buffer
Disabled
Enabled
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
ANALOG INPUT
Absolute Input Voltage Range
Unbuffered Mode
Buffered Mode
Input Voltage Ranges
Differential Mode
Common-Mode Voltage Range
Single-Ended Mode
Input Current3
Buffered Mode
AIN0, AIN1, AIN2, and AIN3
Unbuffered Mode
Unit
Test Conditions/Comments
fIN = 665.283 Hz sine wave; fSAMPLE =
100 kSPS; internally unbuffered
channels; the filter on the analog
inputs is a 15 Ω resistor and a 2 nF
capacitor
80
dB
78
74
dB
dB
Includes distortion and noise
components
Chop mode on
Automatic zero
−86
−86
−88
−95
dB
dB
dB
dB
Chop mode on and automatic zero
Buffer on and off
Measured on adjacent channels; fIN =
25 kHz sine wave; buffer on and off
AVDD
2.5
V
V
Voltage level on AINx pin
Voltage level on AINx pin
−VREF
+VREF
V
Voltage difference between AIN+
(positive input) and AIN− (negative
input)
0.9
AGND
1.6
VREF
V
V
+132
+60
+902
nA
nA
nA
pA/°C
−102
−40
−602
±5
±15
±25
±20
±101
pA/°C
±34
pA/°C
±201
pA/°C
−502
−2152
−3502
−11002
±20
±50
−90
+750
−1.62
±1401
±530
20
+1
Input Current Drift
Input Capacitance
Input Leakage Current
Max
AGND
AGND + 0.15
Input Current Drift
AIN4 to AIN9
Typ
+502
+1102
+902
+17002
nA
nA
nA
nA
+3.52
pA/°C
pA/°C
pF
nA
Rev. C | Page 5 of 27
Voltage difference between AIN+
and AIN−
VIN = 0.15 V to 2.5 V
ADC sampling rate ≤ 100 kSPS
ADC sampling rate ≤ 500 kSPS
ADC sampling rate ≤ 800 kSPS
Input buffer on, ADC sampling rate ≤
500 kSPS
Input buffer on, ADC sampling rate ≤
500 kSPS
Input buffer on, ADC sampling rate ≤
800 kSPS
Input buffer on, ADC sampling rate ≤
800 kSPS
AIN4 to AIN9 ≤ 100 kSPS
ADC sampling rate ≤ 500 kSPS
ADC sampling rate ≤ 800 kSPS
VIN = 0 V to 2.5 V, all channels, all
sampling rates
VIN = 1 V
VIN = 1 V
During ADC acquisition, buffer on
ADC off, buffer off or buffer on,
AINx connected 2.5 V
ADuCM310
Parameter
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Accuracy4
Reference Temperature Coefficient2, 5
Power Supply Rejection Ratio
Output Impedance
Internal VREF Power-On Time2
EXTERNAL REFERENCE INPUT2
Input Voltage Range2
Data Sheet
Min
Typ
Max
2.505
1.8
Switching Time
External to Internal Reference
Internal to External Reference
BUFFERED VREF OUTPUTS
(BUF_VREF2.5x PINS)
Output Voltage
Accuracy
Reference Temperature Coefficient2
50
V
mV
ppm/°C
ppm/°C
dB
Ω
ms
2.5
V
±5
301
44
15
15
70
3
38
2.5
1
Test Conditions/Comments
0.47 μF from VREF_1.2 to AGND
TA = 25°C
For ADC_CAPP, TA = 25°C
Turned on by default
ADC maximum reference voltage =
2.5 V
ms
ms
2.5
±5
301
15
15
2.5
3
Load Regulation
Output Impedance
Load Current
Power Supply Rejection Ratio
IDAC CHANNEL SPECIFICATIONS6, 7
Voltage Compliance Range2
Unit
50
1.2
70
V
mV
ppm/°C
ppm/°C
mV/mA
Ω
mA
dB
TA = 25°C, load = 0.4 mA
100 nF capacitor required on both
outputs
TA = 25°C
Output voltage compliance;
minimum compliance if IDACx set to
full scale, see Figure 15 to Figure 20
IDAC0, IDAC1, and IDAC2
0.4
IDAC4 and IDAC5
0.4
IDAC3
0.5
PVDD −
200 mV
PVDD –
275 mV
PVDD –
200 mV
PVDD −
450 mV
V
V
V
−3.0
V
At −3.5 V, maximum sink current is
80 mA; pin voltage clamped to
−3.5 V, tolerance of clamping
voltage is ±200 mV
0.38
mA
IDAC Reference Current Shutdown
Threshold
0.76
mA
Temperature Coefficient2, 5
Over Heat Shutdown
Resolution
IDAC0, IDAC1, IDAC4,and IDAC5
7
135
Using internal reference, 0.1%,
≤5 ppm, 3.16 kΩ external resistor
If the external resistor (REXT) value
drops below 1.580 kΩ, IDAC output
currents disable
Using internal reference;
Junction temperature
−3.7
Reference Current Generator
Reference Current
25
ppm/°C
°C
14
Bits
IDAC2
14
Bits
IDAC3
14
Bits
IDAC3
8
Bits
Rev. C | Page 6 of 27
11-bit MSBs and 5-bit LSBs are
guaranteed monotonic
11-bit MSBs and 5-bit LSBs are
guaranteed monotonic
0 V to 2 V compliant range, 11-bit
MSBs and 5-bit LSBs are guaranteed
monotonic
−4.5 V to 0 V compliant range
Data Sheet
Parameter
Full-Scale Output
IDAC0 and IDAC1
IDAC4 and IDAC5
IDAC2
IDAC3
Integral Nonlinearity
ADuCM310
Min
Typ
Max
100
20
200
250
−90
−801
−3
−2.51
Unit
mA
mA
mA
mA
±1.5
±1.5
+4
+4
LSB
LSB
Noise Current
IDAC0 and IDAC1
IDAC4 and IDAC5
IDAC2
IDAC3
Full-Scale Error
IDAC0 and IDAC1
IDAC4 and IDAC 5
IDAC2
IDAC3
1.5
0.3
4
5
−2.31
−3.0
−0.71
−1
−1.751
−1.77
−21
−2.4
μA
μA
μA
μA
±0.25
±0.25
±0.25
±0.25
±0.25
±0.25
±0.25
±0.25
+11
+1.3
±0.7
+0.7
±0.65
±1.41
+1.6
IDAC2 and IDAC3
IDAC2 and IDAC3
IDAC0 and IDAC1
IDAC0 and IDAC1
Full-Scale Error Drift vs. Time8
IDAC0
Including internal reference drift
and 5 ppm external resistor
−401
−58
−1451
−205
−100
−12
−12
+55
+40
+551
+90
+40
450
IDAC2
500
IDAC3
2250
IDAC4 and IDAC5
40
Pull-Down Current
IDAC4 and IDAC5
Pull-Down Current
+301
+58
+1451
+205
+100
−1201
−180
−135
−251
−31
−30
−115
−24
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
ppm/°C
Full temperature range
Reduced 25°C to 85°C range
Full temperature range
Reduced 25°C to 85°C range
Long-term stability
μA/
1000 hours
μA/
1000 hours
μA/
1000 hours
μA/
1000 hours
μA/
1000 hours
200
IDAC1
Zero-Scale Error
IDAC0 and IDAC1
Current source
Current sink
Current sink
11-bit
11-bit
RMS noise; maximum bandwidth
setting, IDACxCON[5:2] = 0000b
Measured driving 10 Ω
Measured driving 100 Ω
Measured driving 5 Ω
Measured driving 5 Ω
%
%
%
%
%
%
%
%
Full-Scale Error Drift vs. Temperature
IDAC4 and IDAC5
Test Conditions/Comments
+751
+115
−100
+15
+15
−22
Rev. C | Page 7 of 27
μA
μA
μA
μA
μA
μA
Pull-down current off
Reduced −10°C to +85°C range
ADuCM310
Parameter
IDAC2 and IDAC3
Pull-Down Current for IDAC2
Zero-Scale Error Drift2
IDAC0 and IDAC1
IDAC4 and IDAC5
Data Sheet
Min
−3501
−460
−300
Typ
−8501
−1400
−120
−120
±300
±300
±50
±50
±1
IDAC2 and IDAC3
Settling Time
IDAC0, IDAC1, IDAC2, and IDAC3
−288
Max
+2801
+300
−160
Unit
μA
μA
μA
+12001
+1400
+2051
+230
nA/°C
nA/°C
nA/°C
nA/°C
μA/°C
1
ms
IDAC4 and IDAC5
IDAC0, IDAC1, IDAC2, and IDAC3
2
250
ms
μs
IDAC4 and IDAC5
IDAC0, IDAC1, IDAC2, and IDAC3
1.2
50
ms
μs
IDAC4 and IDAC5
IDAC3 Switching Time2
1.1
1
ms
μs
Transconductance
IDAC0 and IDAC1
IDAC2
IDAC3
IDAC4 and IDAC5
IDAC Shutdown Temperature
VDAC CHANNEL SPECIFICATIONS6, 9, 10
DC Accuracy
Resolution
Relative Accuracy
VDAC0, VDAC1, and VDAC2
VDAC4 and VDAC5
VDAC3, VDAC6, and VDAC7
Differential Nonlinearity
Offset Error
Calculated
Actual
VDAC0, VDAC1, VDAC4, and
VDAC5
VDAC6 and VDAC7
VDAC2 and VDAC3
Full-Scale Error
VDAC0, VDAC1, and VDAC72
7.99/100
12.6/100
18.6/100
1.16/100
125
mA/mV
mA/mV
mA/mV
mA/mV
°C
12
−6.3
−7.3
−7
−0.99
To 0.1%, IDACxCON[5:2] = 0101b,
±1 mA change in output current
To 1%, IDACxCON[5:2] = 0101b,
±1 mA change in output current
To 1%, IDACxCON[5:2] = 0000b,
±1 mA change in output current
Time to switch from current source
to current sink
Analog input signal coupled on to
CDAMP_IDACx pin via 1 nF capacitor;
frequency range = 100 kHz to
1000 kHz; voltage is the peak to
peak voltage on the CDAMP_IDACx
pin of the associated IDAC; current
is peak-to-peak current change
Die temperature; enabled via
IDACxCON[6]
Bits
±1
±2
±2
±0.6
+10
+11
+8.5
+1
±5
−30
Test Conditions/Comments
LSB
LSB
LSB
LSB
mV
4
7
mV
15
−20
22
±0.71
mV
mV
% of full scale
±0.9
% of full scale
±0.71
±0.9
%
%
Rev. C | Page 8 of 27
Guaranteed monotonic
2.5 V internal reference
Measured at Code 0
For VDAC2, VDAC3, VDAC4, VDAC5,
and VDAC6
For VDAC2, VDAC3, VDAC4, VDAC5,
and VDAC6
With 500 Ω load
With 500 Ω load
Data Sheet
Parameter
VDAC0 and VDAC1
ADuCM310
Min
VDAC7
Gain Mismatch Error
Offset Error Drift
Calculated
VDAC0, VDAC1, VDAC4, and
VDAC5
VDAC2, VDAC3, VDAC6, and
VDAC7
Actual
VDAC0, VDAC1, VDAC4, and
VDAC5
VDAC2, VDAC3, VDAC6, and
VDAC7
Gain Error Drift
VDAC0, VDAC1, VDAC4, and
VDAC5
VDAC2, VDAC3, VDAC6, and
VDAC7
Output Impedance
VDAC0, VDAC1, VDAC4,
VDAC5, VDAC6, and VDAC7
VDAC2 and VDAC3
Short-Circuit Current
VDAC0 and VDAC1
VDAC2 and VDAC3
VDAC4 and VDAC5
VDAC6 and VDAC7
VDAC Outputs
Output Impedance
VDAC0, VDAC1, and VDAC4
to VDAC7
VDAC2 and VDAC3
Output Range
VDAC0 and VDAC1
VDAC2 and VDAC3
VDAC4 and VDAC5
VDAC6
VDAC7
Typ
±0.5
Max
Unit
%
±0.5
%
0.1
0.2
0.1
0.35
%
%
%
%
±5
μV/°C
±25
μV/°C
±13
μV/°C
±75
μV/°C
5
ppm/°C
10
ppm/°C
1
Ω
1.5
Ω
Test Conditions/Comments
With 75 Ω load, over full
temperature range
With 100 Ω load, over full
temperature range
VDAC0 relative to VDAC1
VDAC2 relative to VDAC3
VDAC4 relative to VDAC5
VDAC6 relative to VDAC7; both
driving a 500 Ω load
Measured at Code 0
Excluding internal reference drift
Measured with VDAC shorted to
ground and to associated power
supply
±200
±170
±200
±200
mA
mA
mA
mA
Capacitive load up to 0.01 μF
0 + Actual
Offset1
AVNEG +
250 mV
0 + Actual
Offset1
0 + Actual
Offset1
0 + Actual
Offset1
1.8
Ω
1.2
Ω
AVDD –
600 mV
−0.15
V
AVDD –
300 mV
VDACVDD −
250 mV
VDACVDD −
700 mV
V
Rev. C | Page 9 of 27
V
V
V
Buffer on
RL = 75 Ω, 40 mA maximum, VOUT
maximum = 3 V
RL = 500 Ω, 10 mA maximum, VOUT
maximum = −5 V, gain = −2.25 V
RL = 300 Ω, 10 mA maximum, VOUT
maximum = 3 V
RL = 500 Ω, 10 mA maximum, VOUT
maximum = 5 V
RL = 100 Ω, 50 mA maximum, VOUT
maximum = 5 V
ADuCM310
Parameter
DAC AC CHARACTERISTICS
Slew Rate
VDAC0, VDAC1, VDAC4, and
VDAC5
VDAC2, VDAC3, and VDAC6
Voltage Output Settling Time
Data Sheet
Min
Digital-to-Analog Glitch Energy
AC PSRR 100 Hz
VDAC0, VDAC1, VDAC4, and
VDAC5
VDAC2 and VDAC3
VDAC6 and VDAC7
AC PSRR 1 kHz
VDAC0, VDAC1, VDAC4, and
VDAC5
VDAC2 and VDAC3
VDAC6 and VDAC7
POWER-ON RESET (POR)
POR Trip Level
POR Hysteresis
Allowed Power-Up Time for DVDD
Supply
EXTERNAL RESET
External Reset Minimum Pulse
Width2
2.80
2.74
Typ
Max
3
V/μs
1.1
10
0.05
20
V/μs
μs
ms
nV/sec
72
dB
67
64
dB
dB
56
dB
53
50
dB
dB
2.85
2.79
65
0.2
FLASH/EE MEMORY
Endurance
Data Retention
INTERNAL HIGH POWER OSCILLATOR
Accuracy
INTERNAL LOW POWER OSCILLATOR
Accuracy
LOGIC INPUTS
Input Low Voltage (VINL)
Input High Voltage (VINH)
Short-Circuit Current2
LOGIC OUTPUTS
Output High Voltage (VOH)11
Output Low Voltage (VOL)11
Short-Circuit Current2
2.9
2.83
100
1.5
1.25
1.37
50
ns
1.494
V
10,000
20
Cycles
Years
MHz
16
−2.251
−3.0
−121
−22
V
V
mV
ms
μs
Reset Pin Glitch Immunity2
TEMPERATURE SENSOR
Accuracy2
Unit
+2.251
+3
32.768
±8
±8
+12
+12
0.2 × IOVDD
12
0.4
12
V
V
mA
IOVDD − 0.4
Rev. C | Page 10 of 27
Load =100 pF
Load = 0.01 μF
1 LSB change at major carry
(DACxDAT register change from
0x07FF0000 to 0x08000000)
Refers to voltage at DVDD pin
Power-on level
Power-down level
Minimum pulse width required on
external RESET pin to trigger a reset
sequence
Maximum low pulse width on RESET
pin that does not generate a reset
Indicates die temperature; ADC
measured voltage for temperature
sensor channel without calibration, TA
= 25°C
TJ = 85°C
Used as input to PLL to generate
80 MHz clock
%
%
kHz
%
V
V
mA
0.7 × IOVDD
Test Conditions/Comments
ISOURCE = 2 mA
ISINK = 2 mA
Data Sheet
Parameter
INPUT LEAKAGE CURRENT
Logic 1
Internal Pull-Up Disabled
Logic 0
Internal Pull-Up Disabled
Pull-Up
CRYSTAL INPUTS XCLKI AND XCLKO
(16 MHz)
Logic Inputs, XCLKI Only
Input Low Voltage (VINL)
Input High Voltage (VINH)
XCLKI Input Capacitance
XCLKO Output Capacitance
MICROCONTROLLER UNIT CLOCK RATE
Using PLL Output2
PROCESSOR START-UP TIME
At Power-On2
ADuCM310
Min
−22
−22
30
3
+22
+22
72
Test Conditions/Comments
μA
nA
μA
nA
kΩ
VINH = 3.6 V
VINH = 0 V
If not disabled, disabled at reset;
pull-up can be described as an
80 μA (typical) current source
V
V
pF
pF
0.05
38
80
MHz
50
ms
1.44
ms
3 to 5
fCLK
Includes kernel power-on
execution time
Includes kernel power-on
execution time
Measured between AVDDx and
AGND
Measured between IOVDDx and
AGND
3.3
3.6
V
2.9
3.3
3.6
V
6.5
7.2
mA
ADC, VDACs, IDACs off
29
2.7
32
5.1
mA
mA
CLKCON1[2:0] = [000b]
All GPIO pull-ups enabled
3.1
3.6
mA
ADC Input Buffer2
IDAC2
DAC2
4.1
26.5
2.7
4.8
30
3.1
mA
mA
mA
ADC continuously converting at
100 kSPS
Both buffers enabled
VDAC2 and VDAC32
−1.7
mA
VDAC6 and VDAC72
1
mA
Analog Power Supply Currents
AVDD Current
Digital Power Supply Current
Current in Normal Mode
DVDD
IOVDD
Additional Power Supply Currents
ADC2
2
80
+6
80
+6
40
Unit
2.9
IOVDD
1
Max
1.1
1.7
8
8
After Reset Event
After Processor Power Down
Mode 1, Mode 2, or Mode 3
POWER REQUIREMENTS
Power Supply Voltage Range
AVDD
Typ
Total for all VDACs driving
maximum allowed load with
DACxDAT = 0
IDD when VDAC2 and VDAC3 are
driving maximum allowed load
with DACxDAT set to 0
IDD sourced from the VDACVDD
supply when VDAC6 and VDAC7
are driving the maximum allowed
load with DACxDAT set to 0
Reduced temperature range of − 10°C to + 85°C.
These numbers are not production tested but are guaranteed by design or characterization data at production release.
The input current is the total input current including the input pad and mux leakage plus the charge current for the full input circuit. The input current relates to the
ADC sampling frequency.
Rev. C | Page 11 of 27
ADuCM310
Data Sheet
4
The internal reference calibration and trimming are performed when the processor operates in normal mode with CD = 0, when ADC is enabled and converting, when
IDACs are all on, and when VDACs are on. VREF accuracy can vary under other operating conditions.
5
Measured using the following box method:
VREF Maximum at Any Temperature VREF Minimum at Any Temperature
2.5 Temperature Maximum Temperature Minimum
16
6
VDAC linearity specifications are calculated with following ranges:
VDAC0 and VDAC1 = +150 mV to +2.699 V
VDAC2 and VDAC3: −150 mV to −4.22 V
VDAC4 and VDAC5: +150 mV to +2.98 V
VDAC6: +150 mV to +4.747 V
VDAC7: +150 mV to +4.297 V
7
Analog Devices, Inc., production IDAC full-scale trimming conditions include PVDD_IDACx pin voltage = 0.7 V, all IDACs on.
8
The long-term stability specifications is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
9
For all VDAC specifications for VDAC0, VDAC1, VDAC4, and VDAC5, DACxCON[10:9] = 11.
10
VDACx minimum and maximum limits apply to the internal reference only (DACxCON[1:0] = 00b). AVDDx supply valid only with typical specifications.
11
The average current from the GPIO pins must not exceed 3 mA per pin. See Figure 22.
TIMING SPECIFICATIONS
I2C Timing
Table 2. I2C Timing in Standard Mode (100 kHz)
Parameter
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
tVD;DAT
tVD;ACK
Description
SCLx low pulse width
SCLx high pulse width
Start condition hold time
Data setup time
Data hold time (SDAx held internally for 300 ns after falling edge of SCLx)
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCLx and SDAx
Fall time for both SCLx and SDAx
Data valid time
Data valid acknowledge time
Min
4.7
4.0
4.0
250
0
4.7
4.0
4.7
Slave
Typ
Max
3.45
15
1
300
3.45
3.45
Unit
μs
ns
μs
ns
μs
μs
μs
μs
μs
ns
μs
μs
Table 3. I2C Timing in Fast Mode (400 kHz)
Parameter
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
tVD;DAT
tVD;ACK
Description
SCLx low pulse width
SCLx high pulse width
Start condition hold time
Data setup time
Data hold time (SDAx held internally for 300 ns after falling edge of SCLx)
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCLx and SDAx
Fall time for both SCLx and SDAx
Data valid time
Data valid acknowledge time
Rev. C | Page 12 of 27
Min
1.3
0.6
0.3
100
0
0.6
0. 3
1.3
20
Slave
Typ
15
Max
300
300
0.9
0.9
Unit
μs
ns
μs
ns
μs
μs
μs
μs
ns
ns
μs
μs
Data Sheet
ADuCM310
tBUF
tR
MSB
LSB
tDSU
tVD;DAT
tSHD
1
SCLx (I)
tH
2
TO 7
tDHD
tRSU
tVD;ACK
8
tR
9
tL
S
MSB
tF
tDSU
tDHD
tPSU
P
ACK
1
S(R)
STOP
START
CONDITION CONDITION
REPEATED
START
tF
13040-002
SDAx (I/O)
Figure 2. I2C Compatible Interface Timing
SPI Timing
Table 4. SPI Master Mode Timing (Phase Mode = 1)
Parameter
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
2
Min
0
Typ
(SPIxDIV1 + 1) × tHCLK2/2
(SPIxDIV1 + 1) × tHCLK2/2
3
½ SCLKx
SCLKx
SCLKx
25
25
20
Max
For SPI0, x is 0, and for SPI1, x is 1.
tHCLK is the divided system clock, UCLK/CLKCON1[2:0].
SCLKx
(POLARITY = 0)
tSH
tSL
tSR
SCLKx
(POLARITY = 1)
tDAV
tDF
MOSIx
MISOx
MSB
MSB IN
tSF
tDR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
tDSU
LSB
LSB IN
13040-003
1
Description
SCLKx low pulse width
SCLKx high pulse width
Data output valid after SCLKx edge
Data input setup time before SCLKx edge
Data input hold time after SCLKx edge
Data output fall time
Data output rise time
SCLKx rise time
SCLKx fall time
tDHD
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
Rev. C | Page 13 of 27
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADuCM310
Data Sheet
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter
tSL
tSH
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
2
Min
0
Typ
(SPIxDIV1 + 1) × tHCLK2/2
(SPIxDIV1 + 1) × tHCLK2/2
3
½ SCLKx
SCLKx
SCLKx
25
25
20
20
Max
For SPI0, x is 0, and for SPI1, x is 1.
tHCLK is the divided system clock, UCLK/CLKCON1[2:0].
SCLKx
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLKx
(POLARITY = 1)
tDAV
tDOSU
MOSIx
MISOx
tDF
MSB
MSB IN
tDR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
LSB IN
tDSU
13040-004
1
Description
SCLKx low pulse width
SCLKx high pulse width
Data output valid after SCLKx edge
Data output setup before SCLKx edge
Data input setup time before SCLKx edge
Data input hold time after SCLKx edge
Data output fall time
Data output rise time
SCLKx rise time
SCLKx fall time
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Rev. C | Page 14 of 27
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
ADuCM310
Table 6. SPI Slave Mode Timing (Phase Mode = 1)
Parameter
tCS0/tCS1
Description
CS0/CS1 to SCLKx edge
Min
10
tCSM
CS0/CS1 high time between active periods
SCLKx
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tSFS
2
Max
SCLKx low pulse width
SCLKx high pulse width
Data output valid after SCLKx edge
Data input setup time before SCLKx edge
Data input hold time after SCLKx edge
Data output fall time
Data output rise time
SCLKx rise time
SCLKx fall time
CS0/CS1 high after SCLKx edge
2
(SPIxDIV + 1) × tHCLK
(SPIxDIV1 + 1) × tHCLK2
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
25
25
1
1
20
For SPI0, x is 0, and for SPI1, x is 1.
tHCLK is the divided system clock, UCLK/CLKCON1[2:0].
tCSM
CS0/CS1
tSFS
tCS0/tCS1
SCLKx
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLKx
(POLARITY = 1)
tDAV
MISOx
tDF
MSB
MOSIx
MSB IN
tDR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
tDSU
tDHD
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
Rev. C | Page 15 of 27
Unit
ns
ns
1
LSB
LSB IN
13040-005
1
Typ
ADuCM310
Data Sheet
Table 7. SPI Slave Mode Timing (Phase Mode = 0)
Parameter
tCS0/tCS1
Description
CS0/CS1 to SCLKx edge
Min
10
tCSM
CS0/CS1 high time between active periods
SCLKx
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
2
Max
SCLKx low pulse width
SCLKx high pulse width
Data output valid after SCLKx edge
Data input setup time before SCLKx edge
Data input hold time after SCLKx edge
Data output fall time
Data output rise time
SCLKx rise time
SCLKx fall time
Data output valid after CS0/CS1 edge
CS0/CS1 high after SCLKx edge
2
(SPIxDIV + 1) × tHCLK
(SPIxDIV1 + 1) × tHCLK2
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
25
25
1
1
20
10
For SPI0, x is 0, and for SPI1, x is 1
tHCLK is the divided system clock, UCLK/CLKCON1[2:0].
tCSM
CS0/CS1
tCS0 /tCS1
tSFS
SCLKx
(POLARITY = 0)
tSH
tSL
tSF
tSR
SCLKx
(POLARITY = 1)
tDAV
tDOCS
tDF
MISOx
MOSIx
MSB
MSB IN
tDSU
tDR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
LSB IN
tDHD
Figure 6. SPI Slave Mode Timing (Phase Mode = 0)
Rev. C | Page 16 of 27
Unit
ns
ns
1
13040-006
1
Typ
Data Sheet
ADuCM310
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 8.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
AVDD to AGNDx
AVNEG to AGNDx
VDACVDD to AGNDx
IOVDDx to DGNDx
Digital Input Voltage to DGNDx
Digital Output Voltage to DGNDx
Analog Inputs to AGNDx
Total Positive GPIO Pins Current
Total Negative GPIO Pins Current
IDAC3 Pull-Down Voltage
IDAC3 Pull-Down Current
Operating Temperature Range
Storage Temperature Range
Junction Temperature
ESD Rating, All Pins
Human Body Model (HBM)
Field-Induced Charged Device
Model (FICDM)
Rating
−0.3 V to +3.96 V
−5.5 V to +0.3 V
−0.3 V to +5.5 V
−0.3 V to +3.96 V
−0.3 V to IOVDDx + 0.3 V
−0.3 V to IOVDDx + 0.3 V
−0.3 V to AVDD + 0.3 V
0 mA to 30 mA
−30 mA to 0 mA
AVNEG − 0.3 V
−100 mA
−40°C to +85°C
−65°C to +150°C
150°C
Table 9. Thermal Resistance
Package Type
112-Ball CSP_BGA
ESD CAUTION
1 kV
1.25 kV
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. C | Page 17 of 27
θJA
44.5
θJC
11
Unit
°C/W
ADuCM310
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
A
RESERVED
IDAC0
PVDD_
IDAC0
IDAC2
PVDD_
IDAC2
IDAC3
PGND
PVDD_
IDAC3
PVDD_
IDAC1
IDAC1
RESERVED
A
B
IDAC4
CDAMP_
IDAC0
CDAMP_
IDAC2
IDAC2
PVDD_
IDAC2
IDAC3
PGND
PVDD_
IDAC3
CDAMP_
IDAC3
CDAMP_
IDAC1
IDAC5
B
C
PVDD_
IDAC4
CDAMP_
IDAC4
P2.3/BM
P1.0/
SIN/
ECLKIN/
PLAI[4]
P1.2/
PWM0/
PLAI[6]
P1.3/
PWM1/
PLAI[7]
P1.4/
PWM2/
SCLK1/
PLAO[10]
P1.5/
PWM3/
MISO1/
PLAO[11]
P1.6/
PWM4/
MOSI1/
PLAO[12]
CDAMP_
IDAC5
PVDD_
IDAC5
C
D
RESERVED
RESET
P3.2/
PLAI[14]
P2.0/IRQ2/
PWMTRIP/
PLACLK2/
PLAI[8]
P1.1/SOUT/
PLACLK1/
PLAI[5]
RESERVED
P2.4/IRQ5/
ADCCONV/
PWM6/
PLAO[18]
P2.5/IRQ6/
PWM7/
PLAO[19]
P1.7/IRQ1/
PWM5/CS1/
PLAO[13]
DGND2
IREF
D
E
IOVDD1
P0.1/
MISO0/
PLAI[1]
P0.0/
SCLK0/
PLAI[0]
P2.2/IRQ4/
MRST/
CLKOUT/
PLAI[10]
P2.1/IRQ3/
PWMSYNC/
PLAI[9]
SWDIO
SWCLK
IOVDD2
E
F
IOGND1
P0.3/
IRQ0/CS0/
PLAI[3]
P0.2/
MOSI0/
PLAI[2]
RESERVED
RESERVED
VDACV DD
AVDD_REG1
IOGND2
F
G
P0.7/
SDA1/
PLAO[5]
P0.6/
SCL1/
PLAO[4]
P0.5/
SDA0/
PLAO[3]
P.04/
SCL0/
PLAO[2]
AIN4
AGND2
AVDD_REG2
VREF_1.2
G
H
P2.6/
IRQ7/
PLAO[20]
P2.7/
IRQ8/
PLAO[21]
P3.0/
PLAI[12]
AGND5
VDAC5
RESERVED
AIN1
AIN5
VDAC6
VDAC7
AVDD4
H
J
P3.4/
PLAO[26]
XTALO
P3.1/
PLAI[13]
VDAC4
DVDD
AIN0
AIN2
AIN6
VDAC2
BUF_
VREF2.5A
AGND4
J
K
IOVDD3
XTALI
DVDD_REG1
VDAC1
AGND1
AVNEG
AIN3
AIN7
VDAC3
ADC_CAPN
BUF_
VREF2.5B
K
L
IOGND3
DGND1
DVDD_REG2
VDAC0
AVDD3
AGND3
AGND6
AIN8
AIN9
ADC_CAPN
ADC_CAPP
L
1
2
3
4
5
6
7
8
9
10
11
IDAC RELATED
ADuCM310
TOP VIEW
(Not to Scale)
DIGITAL PINS
ANALOG PINS
RESERVED
13040-007
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 7. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
D2
E3
Mnemonic
RESET
P0.0/SCLK0/PLAI[0]
Type1
I
I/O
E2
P0.1/MISO0/PLAI[1]
I/O
F3
P0.2/MOSI0/PLAI[2]
I/O
F2
P0.3/IRQ0/CS0/PLAI[3]
I/O
G4
P0.4/SCL0/PLAO[2]
I/O
Description
Reset Input (Active Low). An internal pull-up is included on this pin.
General-Purpose Input and Output Port 0.0/SPI0 Clock/Input to PLA
Element 0. This pin defaults as an input with the internal pull-up resistor
disabled.
General-Purpose Input and Output Port 0.1/SPI0 Data Master Input-Slave
Output/Input to PLA Element 1. This pin defaults as an input with the
internal pull-up disabled.
General-Purpose Input and Output Port 0.2/SPI0 Data Master OutputSlave Input/Input of PLA Element 2. This pin defaults as an input with the
internal pull-up disabled.
General-Purpose Input and Output Port 0.3/External Interrupt Request 0/
SPI0 Chip Select Input/Input of PLA Element 3. This pin defaults as an
input with the internal pull-up disabled. If SPI0 is used, configure this pin
as CS0.
General-Purpose Input and Output Port 0.4/I2C Interface Clock for
I2C0/Output of PLA Element 2. This pin defaults as an input with the
internal pull-up disabled.
Rev. C | Page 18 of 27
Data Sheet
ADuCM310
Pin No.
G3
Mnemonic
P0.5/SDA0/PLAO[3]
Type1
I/O
G2
P0.6/SCL1/PLAO[4]
I/O
G1
P0.7/SDA1/PLAO[5]
I/O
C4
P1.0/SIN/ECLKIN/PLAI[4]
I/O
D5
P1.1/SOUT/PLACLK1/PLAI[5]
I/O
C5
P1.2/PWM0/PLAI[6]
I/O
C6
P1.3/PWM1/PLAI[7]
I/O
C7
P1.4/PWM2/SCLK1/PLAO[10]
I/O
C8
P1.5/PWM3/MISO1/PLAO[11]
I/O
C9
P1.6/PWM4/MOSI1/PLAO[12]
I/O
D9
P1.7/IRQ1/PWM5/CS1/PLAO[13]
I/O
D4
P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8]
I/O
E8
P2.1/IRQ3/PWMSYNC/PLAI[9]
I/O
E4
P2.2/IRQ4/MRST/CLKOUT/PLAI[10]
I/O
C3
P2.3/BM
I/O
D7
P2.4/IRQ5/ADCCONV/PWM6/PLAO[18]
I/O
D8
P2.5/IRQ6/PWM7/PLAO[19]
I/O
H1
P2.6/IRQ7/PLAO[20]
I/O
H2
P2.7/IRQ8/PLAO[21]
I/O
H3
P3.0/PLAI[12]
I/O
Description
General-Purpose Input and Output Port 0.5/I2C Interface Data for
I2C0/Output of PLA Element 3. This pin defaults as an input with internal
pull-up disabled.
General-Purpose Input and Output Port 0.6/I2C Interface Clock for
I2C1/Output of PLA Element 4. This pin defaults as an input with internal
pull-up disabled.
General-Purpose Input and Output Port 0.7/I2C Interface Data for
I2C1/Output of PLA Element 5. This pin defaults as an input with internal
pull-up disabled.
General-Purpose Input and Output Port 1.0/UART Input Pin/External
Input Clock/Input to PLA Element 4. The ECLKIN pin is used for the UART
downloader. This pin defaults as an input with internal pull-up disabled.
General-Purpose Input and Output Port 1.1/UART Output Pin/PLA Input
Clock/Input to PLA Element 5. The PLACLK1 pin is used for the UART
downloader. This pin defaults as an input with internal pull-up disabled.
General-Purpose Input and Output Port 1.2/PWM0 Output/Input to PLA
Element 6. This pin defaults as an input with internal pull-up disabled.
General-Purpose Input and Output Port 1.3/PWM1 Output/Input to PLA
Element 7. This pin defaults as an input with internal pull-up disabled.
General-Purpose Input and Output Port 1.4/PWM2 Output/SPI1
Clock/Output of PLA Element 10. This pin defaults as an input with
internal pull-up disabled.
General-Purpose Input and Output Port 1.5/PWM3 Output/SPI1 Data
Master Input-Slave Output/Output of PLA Element 11. This pin defaults as
an input with internal pull-up disabled.
General-Purpose Input and Output Port 1.6/PWM4 Output/SPI1 Data
Master Output-Slave Input/Output of PLA Element 12. This pin defaults as
an input with internal pull-up disabled.
General-Purpose Input and Output Port 1.7/External Interrupt Request 1/
PWM5 Output/SPI1 Chip Select Input/Output of PLA Element 13. This pin
defaults as an input with internal pull-up disabled. If SPI1 is used,
configure this pin as CS1.
General-Purpose Input and Output Port 2.0/External Interrupt Request 2/
PWM Trip Input Source/PLA Input Clock/Input to PLA Element 8. This pin
defaults as an input with the internal pull-up disabled.
General-Purpose Input and Output Port 2.1/External Interrupt Request 3/
PWM Sync Input/Input to PLA Element 9. This pin defaults as an input
with the internal pull-up disabled.
General-Purpose Input and Output Port 2.2/External Interrupt Request 4/
Reset Out Pin/Clock Output/Input to PLA Element 10. This pin defaults as
an input with the internal pull-up disabled.
General-Purpose Input and Output Port 2.3/BM pin. If this pin is low, then
the device enters UART download after the next rest sequence. This pin
defaults as an input with the internal pull-up disabled.
General-Purpose Input and Output Port 2.4/External Interrupt Request 5/
External Input to Start ADC Conversions/PWM6 Output/Output of
PLA Element 18. This pin defaults as an input with the internal pull-up
disabled.
General-Purpose Input and Output Port 2.5/External Interrupt Request 6/
PWM7 Output/Output of PLA Element 19. This pin defaults as an input
with the internal pull-up disabled.
General-Purpose Input and Output Port 2.6/External Interrupt Request 7/
Output of PLA Element 20. This pin defaults as an input with the internal
pull-up disabled.
General-Purpose Input and Output Port 2.7/External Interrupt Request 8/
Output of PLA Element 21. This pin defaults as an input with the internal
pull-up disabled.
General-Purpose Input and Output Port 3.0/Input to PLA Element 12. This
pin defaults as an input with the internal pull-up disabled.
Rev. C | Page 19 of 27
ADuCM310
Data Sheet
Pin No.
J3
Mnemonic
P3.1/PLAI[13]
Type1
I/O
D3
P3.2/PLAI[14]
I/O
J1
P3.4/PLAO[26]
I/O
E10
E9
G11
SWCLK
SWDIO
VREF_1.2
I
I/O
AO
D11
IREF
AI
J6
H7
J7
K7
G8
AIN0
AIN1
AIN2
AIN3
AIN4
AI
AI
AI
AI
AI
H8
J8
K8
L8
L9
L4
K4
J9
K9
J4
H5
H9
H10
A2
A3
B2
A10
A9
B10
B11
C11
C10
B1
C1
C2
A4, B4
A5, B5
B3
A6, B6
A8, B8
B9
A7, B7
K5, G9,
L6, J11,
H4, L7
AIN5
AIN6
AIN7
AIN8
AIN9
VDAC0
VDAC1
VDAC2
VDAC3
VDAC4
VDAC5
VDAC6
VDAC7
IDAC0
PVDD_IDAC0
CDAMP_IDAC0
IDAC1
PVDD_IDAC1
CDAMP_IDAC1
IDAC5
PVDD_IDAC5
CDAMP_IDAC5
IDAC4
PVDD_IDAC4
CDAMP_IDAC4
IDAC2
PVDD_IDAC2
CDAMP_IDAC2
IDAC3
PVDD_IDAC3
CDAMP_IDAC3
PGND
AGND1, AGND2, AGND3, AGND4,
AGND5, AGND6
AI
AI
AI
AI
AI
AO
AO
AO
AO
AO
AO
AO
AO
AO
S
AI
AO
S
AI
AO
S
AI
AO
S
AI
AO
S
AI
AO
S
AI
S
S
Description
General-Purpose Input and Output Port 3.1/Input to PLA Element 13. This
pin defaults as an input with the internal pull-up disabled.
General-Purpose Input and Output Port 3.2/Input to PLA Element 14. This
pin defaults as an input with the internal pull-up disabled.
General-Purpose Input and Output Port 3.4/Output of PLA Element 26. This
pin defaults as an input with the internal pull-up disabled.
Serial Wire Debug Clock Input Pin.
Serial Wire Debug Data Input/Output Input Pin.
1.2 V Reference Output. This pin cannot be used to source current
externally. Connect this pin to AGND via a 470 nF capacitor.
This pin generates the reference current for the IDACs. Connect this pin to
analog ground via a 5 ppm, 3.16 kΩ external resistor (REXT).
Single-Ended or Differential Analog Input 0.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 2.
Single-Ended or Differential Analog Input 3.
Single-Ended or Differential Analog Input 4. This is also the input for the
digital comparator.
Single-Ended or Differential Analog Input 5.
Single-Ended or Differential Analog Input 6.
Single-Ended or Differential Analog Input 7.
Single-Ended or Differential Analog Input 8.
Single-Ended or Differential Analog Input 9.
12-Bit VDAC Output 0, 0 V to 3 V Range.
12-Bit VDAC Output 1, 0 V to 3 V Range.
12-Bit VDAC Output 2, −5 V to 0 V Range.
12-Bit VDAC Output 3, −5 V to 0 V Range.
12-Bit VDAC Output 4, 0 V to 3 V Range.
12-Bit VDAC Output 5, 0 V to 3 V Range.
12-Bit VDAC Output 6, 0 V to 5 V Range.
12-Bit VDAC Output 7, 0 V to 5 V Range.
IDAC0 (100 mA).
Power for IDAC0.
Damping Capacitor Pin for IDAC0. Connect this pin to the PVDD supply.
IDAC1 (100 mA).
Power for IDAC1.
Damping capacitor pin for IDAC1. Connect this pin to the PVDD supply.
IDAC5 (20 mA).
Power for IDAC5.
Damping capacitor pin for IDAC5. Connect this pin to the PVDD supply.
IDAC4 (20 mA).
Power for IDAC4.
Damping capacitor pin for IDAC4. Connect this pin to the PVDD supply.
IDAC2 (200 mA).
Power for IDAC2.
Damping Capacitor for IDAC2. Connect this pin to the PVDD supply.
IDAC3 (250 mA).
Power for IDAC3.
Damping Capacitor Pin for IDAC3. Connect this pin to the PVDD supply.
Power Supply Ground of the IDACs.
Analog Ground Pins.
Rev. C | Page 20 of 27
Data Sheet
ADuCM310
Pin No.
J5
Mnemonic
DVDD
Type1
S
F9
L5, H11
K3
VDACVDD
AVDD3, AVDD4
DVDD_REG1
S
S
S
L3
DVDD_REG2
S
F10
AVDD_REG1
S
G10
AVDD_REG2
S
K6
E1
L2, D10
E11, K1
F1, F11,
L1
J2
AVNEG
IOVDD1
DGND1, DGND2
IOVDD2, IOVDD3
IOGND1, IOGND2, IOGND3
S
S
S
S
S
XTALO
DO
K2
XTALI
DI
J10
BUF_VREF2.5A
AO
K11
BUF_VREF2.5B
AO
K10, L10
ADC_CAPN
S
L11
ADC_CAPP
S
A1, A11,
D1, F4,
F8, D6,
H6
RESERVED
1
Description
Digital Supply Pin. This pin is the supply for the 16 MHz oscillator, PLL,
POR, and digital core, including the flash that requires a regulated 1.8 V
supply and a 3 V supply.
5 V Analog Supply Pin.
Analog Supply Pin (3.3 V).
Output of 2.5 V on Chip Low Dropout (LDO) Regulator. Connect a 470 nF
capacitor to this pin and DGND. This regulator supplies the inter-die digital
interface.
Output of 1.8 V on chip LDO regulator. Connect a 470 nF capacitor to this
pin and DGND. This regulator supplies flash and the Cortex-M3 processor.
Output of 2.5 V on chip LDO regulator. Connect a 470 nF capacitor to this
pin and DGND. This regulator supplies the ADC.
Output of 2.5 V on chip LDO regulator. Connect a 470 nF capacitor to this
pin and DGND. This regulator supplies the IDACs.
−5 V Supply Pin.
3.3 V GPIO Supply Pin.
Digital Ground Pins.
3.3 V GPIO Supply Pins.
GPIO Ground Pins.
Output from the Crystal Oscillator Inverter. If an external crystal is not
used, leave this pin unconnected.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits. If an external crystal is not used, connect this pin to
the DGND system ground.
Buffered 2.5 V Bias, Maximum Load = 1.2 mA. Connect this pin to AGND
via a 100 nF capacitor.
Buffered 2.5 V Bias, Maximum Load = 1.2 mA. Connect this pin to AGND
via a 100 nF capacitor.
Decoupling Capacitor Connection for ADC Reference Buffer. Connect this
pin to AGND.
Decoupling Capacitor Connection for ADC Reference Buffer. Connect this
pin to a 4.7 μF capacitor and connect the other side of the capacitor to
the AGND and the ADC_CAPN pins.
Reserved. Do not connect to this pin.
I is input, I/O is input/output, AO is analog output, AI is analog input, S is supply, DO is digital output, and DI is digital input.
Rev. C | Page 21 of 27
ADuCM310
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
600
450
400
HEADROOM VOLTAGE (mV)
HEADROOM VOLTAGE (mV)
500
400
300
HEADROOM 125°C
200
HEADROOM 25°C
100
350
300
250
200
HEADROOM 125°C
150
100
HEADROOM 25°C
100
200
300
400
500
600
700
800
900
1000
LOAD RESISTANCE (Ω)
600
500
HEADROOM VOLTAGE (mV)
600
500
400
300
HEADROOM 125°C
200
0
100
200
300 400 500 600 700
LOAD RESISTANCE (Ω)
800
900
1000
200
300
400
500
600
700
800
900
1000
400
300
HEADROOM 125°C
200
100
HEADROOM 25°C
0
13040-009
0
100
LOAD RESISTANCE (Ω)
700
100
Figure 9. Typical Headroom Voltage vs. Load Resistance for VDAC7,
VDACVDD = 5 V; Headroom = VDACVDD − VDAC Output Voltage
HEADROOM 25°C
0
200
400
600
800
1000
1200
LOAD RESISTANCE (Ω)
Figure 12. Typical Headroom Voltage vs. Load Resistance for VDAC4,
AVDD = 3 V; Headroom = AVDD − VDAC Output Voltage
1000
0.8
900
0.6
800
0.4
600
500
HEADROOM 25°C
400
300
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
0
–0.2
–0.4
200
–0.6
100
0
100
200
300
400
500
600
700
LOAD RESISTANCE (Ω)
800
900
1000
–0.8
13040-010
0
0.2
Figure 10. Typical Headroom Voltage vs. Load Resistance for VDAC2,
AVNEG = −5 V; Headroom = AVNEG − VDAC Output Voltage
0
0.5
1.0
1.5
VIN (V)
2.0
2.5
3.0
13040-013
HEADROOM 125°C
700
INPUT CURRENT (µA)
HEADROOM VOLTAGE (mV)
0
Figure 11. Typical Headroom Voltage vs. Load Resistance for VDAC0,
AVDD = 3 V; Headroom = AVDD − VDAC Output Voltage
Figure 8. Typical Headroom Voltage vs. Load Resistance for VDAC7,
VDACVDD = 3 V; Headroom = VDACVDD − VDAC Output Voltage
HEADROOM VOLTAGE (mV)
0
13040-012
0
13040-008
0
13040-011
50
Figure 13. Input Current vs. VIN, VDD = 3.3 V, TA = 25°C, Unbuffered Mode, 100 kSPS
Rev. C | Page 22 of 27
Data Sheet
ADuCM310
250
15
+115°C
10
200
+85°C
HEADROOM (mV)
0
–5
AIN0
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
AIN9
–15
–20
–25
–30
–35
0
0.5
1.0
1.5
2.0
2.5
3.0
VIN (V)
+25°C
150
–40°C
100
50
0
75
100
125
150
175
200
225
IDAC OUTPUT CURRENT (mA)
13040-017
–10
13040-014
INPUT CURRENT (µA)
5
Figure 17. Typical IDAC2 PVDD_IDAC2 Pin Voltage Headroom vs.
Output Current for Different Temperatures; PVDD = 1.8 V
Figure 14. Input Current vs. VIN, VDD = 3.3 V, TA = 25°C, Buffered Mode, 100 kSPS
250
600
+115°C
500
+115°C
+85°C
+85°C
150
HEADROOM (mV)
+25°C
–40°C
100
50
+25°C
300
–40°C
200
50.0
62.5
75.0
87.5
100.0
112.5
IDAC OUTPUT CURRENT (mA)
0
100
125
150
175
200
225
Figure 15. Typical IDAC0 PVDD_IDAC0 Pin Voltage Headroom vs.
Output Current for Different Temperatures; PVDD = 1.8 V
275
Figure 18. Typical IDAC3 PVDD_IDAC3 Pin Voltage Headroom vs.
Output Current for Different Temperatures; PVDD = 1.8 V
250
160
+115°C
+115°C
140
200
HEADROOM (mV)
150
+85°C
120
+85°C
+25°C
–40°C
100
100
+25°C
80
–40°C
60
40
50
20
0
37.5
50.0
62.5
75.0
87.5
100.0
112.5
IDAC OUTPUT CURRENT (mA)
13040-016
HEADROOM (mV)
250
IDAC OUTPUT CURRENT (mA)
13040-018
100
13040-015
0
37.5
400
Figure 16. Typical IDAC1 PVDD_IDAC1 Pin Voltage Headroom vs.
Output Current for Different Temperatures; PVDD = 1.8 V
0
5
10
15
25
25
IDAC OUTPUT CURRENT (mA)
Figure 19. Typical IDAC4 PVDD_IDAC4 Pin Voltage Headroom vs.
Output Current for Different Temperatures; PVDD = 1.8 V
Rev. C | Page 23 of 27
13040-019
HEADROOM (mV)
200
ADuCM310
Data Sheet
160
3.0
140
2.5
100
OUTPUT VOLTAGE (V)
+115°C
80
+85°C
+25°C
60
40
2.0
VOH MIN
1.5
1.0
VOH MAX
–40°C
0.5
20
7
9
11
13
15
17
19
0
13040-020
5
21
IDAC OUTPUT CURRENT (mA)
0
2
4
6
8
10
12
14
16
LOAD CURRENT (mA)
13040-022
HEADROOM (mV)
120
0
VOL MAX
VOL MIN
Figure 22. Typical Output Voltage vs. Load Current
Figure 20. Typical IDAC5 PVDD_IDAC5 Pin Voltage Headroom vs.
Output Current for Different Temperatures, PVDD = 1.8 V
90
80
77.2
77.6
78.2
3.60
80
70
61.9
AFTER 50ms DVDD MUST
STAY ABOVE 2.85V INCLUDING
NOISE EXCURSIONS
DVDD (V)
50
46.2
40
20
2.90
2.85
30
50ms min
20
DVDD MUST BE ABOVE 2.9V
FOR AT LEAST 50ms TO
COMPLETE POR
0
1.30
1.45
1.50
1.60
1.80
2.00
2.50
EXT VREF (V)
Figure 21. ADC SNR vs. External Reference Voltage (EXT VREF)
TIME (Not to Scale)
Figure 23. DVDD Power-On Requirements
Rev. C | Page 24 of 27
13040-024
10
13040-021
SNR (dB)
60
Data Sheet
ADuCM310
RECOMMENDED CIRCUIT AND COMPONENT VALUES
Figure 24 shows a typical connection diagram for the
ADuCM310.
There are four digital supply balls: IOVDD1, IOVDD2,
IOVDD3, and DVDD. Decouple these balls with a 0.1 μF
capacitor placed as close as possible to each of the four balls and a
10 μF capacitor at the supply source. Similarly, the analog supply
pins, AVDD3 and AVDD4, each require a 0.1 μF capacitor
placed as close as possible to each ball with a 10 μF capacitor at
the supply source.
The IDACs source their output currents from the PVDD supply
balls, PVDD_IDACx. Connect a 100 nF capacitor close to each
PVDD supply ball. Place at least one 10 μF capacitor at the
source of the PVDD supply (PVDD_IDACx balls).
The IDAC output filters depend on a 10 nF capacitor placed
between the CDAMP_IDACx ball and the PVDD_IDACx ball.
The ADC reference requires a 4.7 μF capacitor between the
ADC_CAPN and ADC_CAPP balls. Directly connect
ADC_CAPN to the analog ground (AGND).
The ADuCM310 contains four internal regulators. These regulators
require external decoupling capacitors. The DVDD_REG1 and
DVDD_REG2 balls each requires a 0.47 μF capacitor to the
digital ground (DGND). The AVDD_REG1 and AVDD_REG2
balls each requires a decoupling capacitor to the AGND.
To generate an accurate and low drift reference current, connect the
IREF ball to the analog ground via a low parts per million
(ppm) 3.16 kΩ resistor.
Connect the VREF_1.2 ball to AGND via a 0.47 μF capacitor.
See Figure 24 for more details.
Rev. C | Page 25 of 27
ADuCM310
Data Sheet
IOVDD
0.1µF
0.1µF
DVDD
0.47µF 0.47µF
0.1µF
0.1µF
DGND
J5
K3
L3
L2
D10
DVDD
DVDD_ REG1
DVDD_REG2
DGND1
DGND2
10KΩ
D2 RESET
100nF
100nF
100nF
K2
XTALI
J2
XTALO
F1
F11
L1
IOGND3
K1
IOGND2
E11
IOGND1
E1
IOVDD1
IOVDD3
DVDD
PVDD
IOVDD2
DGND
ADuCM310
10KΩ
P2.3/BM C3
A8 PVDD_IDAC3
P1.0/SIN/ECLKIN/PLAI[4]C4
B8 PVDD_IDAC3
SWCLK E10
C1 PVDD_IDAC4
C11 PVDD_IDAC5
100nF
AGND
DVDD
B5 PVDD_IDAC2
100nF
–0.1µF
AVNEG K6
A5 PVDD_IDAC2
100nF
AGND
–5V
A3 PVDD_IDAC0
100nF
0.1µF
VDACVDD F9
A9 PVDD_IDAC1
100nF
+5V
P1.1/SOUT/PLACLK1/PLAI[5]D5
B2 CDAMP_IDAC0
SWDIO E9
B10 CDAMP_IDAC1
10nF
PGND A7
B3 CDAMP_IDAC2
10nF
B9 CDAMP_IDAC3
L11 L10 K10 G10
AGND4
D11
AGND3
ADC_CAPP
G11
AGND1
IREF
H11
AGND2
VREF_1.2
10nF
ADC_CAPN
AVDD4
10nF
ADC_CAPN
AVDD3
L5
C10 CDAMP_IDAC5
AVDD_REG1
PGND B7
C2 CDAMP_IDAC4
10nF
AVDD_REG2
10nF
F10
K5 G9
L6
J11
AVDD
0.47µF 0.47µF
0.47µF 3.16kΩ 4.7µF
0.1µF
0.1µF
INTERFACE BOARD CONNECTOR
AGND
RESET
RESET
GND
DGND
SWDIO
Tx
SWCLK
Rx
NO CONNECT
DVDD
DVDD
1.6Ω
10µF
DGND DGND1
VIN
IOVDD
ADP7102ARDZ-3.3-R7
10µF
AGND1
AVDD
1.6Ω
VIN VOUT
0.1µF
0.1µF
0.1µF
SENSE
0.1µF
10kΩ
EN
PG
10µF
0.1µF
10µF
DGND
GND
AGND AGND
ADP1741ACPZ
+2.5V
V IN
VIN VOUT
30k Ω
10µF
EN
ADJ
10k Ω
EP
GND
PGND
0.1µF
10µF
SS
–5V
ADP3605
PVDD
0.1µF
AGND
10µF
PGND
+
–
VSENSE
CP+
10µF
GND
AGND
Figure 24. Typical Connection Diagram
Rev. C | Page 26 of 27
0.1µF
0.1µF
–
+
0.1µF
–
+
31.6kΩ
CP–
SD
PGND
V OUT
13040-023
+5V
Data Sheet
ADuCM310
OUTLINE DIMENSIONS
A1 BALL
CORNER
6.10
6.00 SQ
5.90
A1 BALL
CORNER
11 10 9 8 7 6 5 4 3 2 1
A
B
C
D
E
F
G
H
J
K
L
5.00
REF SQ
0.50
BSC
1.200
1.083
1.000
BOTTOM VIEW
0.50
REF
0.26
REF
DETAIL A
DETAIL A
0.223 NOM
0.173 MIN
SEATING
PLANE
0.35
0.30
0.25
BALL DIAMETER
0.93
0.86
0.79
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-195-AC
WITH THE EXCEPTION TO BALL COUNT
04-02-2013-A
TOP VIEW
Figure 25. 112-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-112-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADuCM310BBCZ
ADuCM310BBCZ-RL
EVAL-ADuCM310QSPZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
112-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
112-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board with QuickStart Development System
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2015–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13040-0-2/19(C)
Rev. C | Page 27 of 27
Package Option
BC-112-4
BC-112-4
工商网监
湘ICP备2023018690号
