Precision Analog Microcontroller, 16-Bit Analog
Input/Output with MDIO Interface, Arm Cortex-M33
ADuCM410
Data Sheet
FEATURES
Analog input/output
Multichannel, 16-bit, 2 MSPS ADC
Up to 16 external channels
On-chip die temperature monitor
4 power monitor channels
4 PGA/TIA channels supporting voltage and current
measurements
Fully differential and single-ended modes
0 V to VREF analog input range
12-bit voltage output DACs
8× 0 V to 2.5 V, 1 kΩ load
4× 0 V to 2.5 V, 2.5 kΩ load
On-chip low drift voltage reference, 1.25 V or 2.5 V
Buffered 1.25 V or 2.5 V output
4 voltage comparators
Microcontroller
32-bit Arm Cortex-M33 core, 32-bit RISC architecture, FPU
Serial wire port supports code download and debug
Clocking options
16 MHz on-chip oscillator
160 MHz PLL output with programmable divider
External clock source
Memory
2× 512 kB independent Flash/EE memories
10,000 cycles Flash/EE endurance
10-year Flash/EE retention
128 kB SRAM with ECC
Software triggered, in circuit reprogrammability via MDIO or I2C
On-chip peripherals
2× UART, 3× SPI, 3× I2C serial input/output
Multilevel voltage (3.3 V, 1.8 V, 1.2 V) GPIOs
MDIO slave up to 10 MHz
5× general-purpose timers
Wake-up timer (WUTs)
Watchdog timers (WDTs)
32-element PLA
16-bit PWM
10 external Interrupts
Power
Multiple supplies: 3.3 V for voltage DACs and ADCs, and
3.3 V, 1.8 V, or 1.2 V for digital inputs/outputs
Flexible operating modes for low power applications
Packages and temperature range
5 mm × 5 mm, 81-ball CSP_BGA and 3.46 mm × 3.46 mm
64-ball WLCSP
BGA package uses ULA molding compounds
Rev. 0
Fully specified for −40°C to +105°C operation
Tools
Low cost quick start development system
Full third-party support
APPLICATIONS
Optical networking 100 Gbps/200 Gbps/400 Gbps and
higher frequency modules
Industrial control, automation, and instrumentation systems
GENERAL DESCRIPTION
The ADuCM410 is a fully integrated, single package device that
includes high performance analog peripherals together with
digital peripherals (controlled by a 160 MHz Arm® Cortex™M33 processor) and integrated flash for code and data.
The analog-to-digital converter (ADC) on the ADuCM410
provides 16-bit, 2 MSPS data acquisition using up to 16 input
pins that can be programmed for single-ended or differential
operation with a programmable gain amplifier (PGA) or
transimpedance amplifier (TIA) for voltage and current
measurements. Additionally, the die temperature and supply
voltages can be measured.
The ADC input voltage is 0 V to VREF. A sequencer is provided
that allows a user to select a set of ADC channels to be measured in
sequence without software involvement during the sequence.
The sequence can optionally repeat automatically at a user
selectable rate.
Up to 12 channels of 12-bit voltage digital-to-analog converters
(VDACs) are provided with output buffers supported.
The ADuCM410 can be configured so that the digital and analog
outputs retain their output voltages through a watchdog or
software reset sequence. Therefore, a product can remain
functional even while the ADuCM410 is resetting itself.
The ADuCM410 has a low power ARM Cortex-M33 processor
and a 32-bit reduced instruction set computer (RISC) machine
that offers up to 240 MIPS peak performance with a floatingpoint unit (FPU). Also integrated are 2× 512 kB Flash/EE
memory and 128 kB static random access memory (SRAM)—
both with single-error correction (SEC) and double error
detection (DED) error checking and correction (ECC). The
flash comprises two separate 512 kB blocks supporting
execution from one flash block and simultaneous writing
and/or erasing of the other flash block.
Continued on Page 3
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Technical Support
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ADuCM410
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ........................................... 17
Applications ....................................................................................... 1
Pin Configurations and Function Descriptions ......................... 18
General Description ......................................................................... 1
Theory of Operation ...................................................................... 29
Revision History ............................................................................... 2
RMS Noise Resolution of ADC .................................................... 30
Functional Block Diagram .............................................................. 4
Applications Information .............................................................. 31
Specifications..................................................................................... 5
Power Supplies ............................................................................ 31
Timing Specifications ................................................................ 11
Power-Up Requirements ........................................................... 31
Absolute Maximum Ratings.......................................................... 16
Recommended Circuit and Component Values .................... 32
Thermal Resistance .................................................................... 16
Outline Dimensions ....................................................................... 34
Electrostatic Discharge (ESD) Ratings .................................... 16
Ordering Guide .......................................................................... 35
ESD Caution ................................................................................ 16
REVISION HISTORY
9/2020—Revision 0: Initial Version
Rev. 0 | Page 2 of 35
Data Sheet
ADuCM410
The ADuCM410 operates from an on-chip oscillator and has a
phase-locked loop (PLL) of 160 MHz. This clock can optionally
be divided down to reduce current consumption. Additional
low power modes can be set via the ADuCM410 software.
The device includes a management data input/output (MDIO)
interface capable of operating up to 10 MHz. User programming is
eased by incorporating physical address (PHYADR) and device
address (DEVAD) hardware comparators. The nonerasable
kernel code combined with flags in user flash allow user code to
reliably switch between the two hardware independent flash
blocks.
The ADuCM410 integrates a range of on-chip peripherals that
can be configured under software control, as required in the
application. These peripherals include 2× universal asynchronous
receiver transmitter (UART), 3× I2C, and 3× serial peripheral
interface (SPI) serial input/output communication controllers,
general-purpose inputs/outputs (GPIOs), 32-element
programmable logic arrays (PLAs), five general-purpose timers,
a wake-up timer (WUT), and a system watchdog timer (WDT).
A 16-bit pulse-width modulation (PWM) with eight output
channels is also provided.
The GPIO pins (Px.x) power up in high impedance input mode.
In output mode, the software chooses between open-drain
mode and push/pull mode. The pull-up and pull-down resistors
can be disabled and enabled in the software. The GPIO pins can
be configured with different voltage levels according to the
IOVDDx pin, such as 3.3 V, 1.8 V, and 1.2 V. In GPIO output
mode, the inputs can remain enabled to monitor the GPIO pins.
The GPIO pins can also be programmed to handle digital or
analog peripheral signals, in which case, the pin characteristics
are matched to the specific requirement.
A large support ecosystem is available for the Arm Cortex-M33
processor to ease product development of the ADuCM410.
Access is via the Arm serial wire debug port. On-chip factory
firmware supports in-circuit serial download via MDIO or I2C.
These features are incorporated into a low cost, quick start
development system supporting this precision analog
microcontroller.
Note that throughout this data sheet, multifunction pins, such
as VDAC7/P4.2, are referred to either by the entire pin name or
by a single function of the pin, for example, P4.2, when only
that function is relevant.
Rev. 0 | Page 3 of 35
ADuCM410
Data Sheet
VDAC10 1 VDAC111
PGA0OUT
12-BIT
VDAC
PGA0
0.2V/
0.5V
12-BIT
VDAC
AIN2/PADC0P
VDAC1
12-BIT
VDAC
AIN0
AIN1
VDAC0 1
12-BIT
VDAC
FUNCTIONAL BLOCK DIAGRAM
PGA1
AIN4/PADC01N 1
AIN3/PADC1P
AIN5/PADC2P
PGA2
0.2V/
0.5V
ADuCM410
PGA2OUT
PGA3
AIN7/PADC23N 1
AIN8/COM0P
INPUT MUX
AIN6/PADC3P
PGA0
COMP
AIN9/COM0N/PGA2OUT
VDAC8
AIN10/COM1P
AIN11/COM1N/PGA0OUT
AIN12/COM2P
PGA1
AIN0
COMP
VDAC9
AIN15
PGA2
AVDD/2
IOVDD/2
AGND
COMP
AIN13/COM2N
PGA3
COMP
AIN15/COM3N 1
BUF
BUF
BUF0_VREF 1
BUF1_VREF 1
GP TIMER
WATCHDOG
TIMER
WAKE-UP TIMER
2 × 512kB FLASH/EE
WITH ECC/MPU
2 × 64kB SRAM
WITH ECC/MPU
CACHE
CONTROLLER
DMA
TEMPERATURE
SENSOR
VDAC10
AIN14/COM3P 1
BUF
16-BIT
SAR ADC
AT 2MSPS
16MHz
OSC
PLL
32kHz
OSC
HP
REF8
ALP
REF9
POR
DLP
2.5V
1.1V
ALDO10 REF11 DLDO12
VDAC11
AVDD_REG
DVDD_REG
WIC7
NVIC6
GPIO
GPIOs2
PLA
PLAOx
PLAIx
MDIO
MDIO4
SPI
SPIs5
I2C
SDAx,
SCLx
Arm Cortex-M33
WITH DSP
UP TO 160MHz
UART
SWD
PWM
SOUTx,
SINx
SERIAL WIRE
EMULATION3
IS A PARTIAL FUNCTION OF A MULTIFUNCTION PIN. FOR EXAMPLE, VDAC0 AND AIN4/PADC01N ARE SEPARATE FUNCTIONS
ON THE SAME PIN, AIN4/PADC01N/VDAC0.
2 GPIOs REFER TO Px.x.
3 SERIAL WIRE EMULATION REFERS TO SWDIO, SWCLK, AND SWO.
4 MDIO REFERS TO PRTADDRx, MDIO, AND MCK.
5 SPIs REFER TO SLKx, CSx, MOSIx, SRDYx, AND MISOx.
6 NVIC IS NESTED VECTORED INTERRUPT CONTROLLER.
7 WAKE-UP INTERRUPT CONTROLLER.
8 HP REF IS HIGH POWER REFERENCE.
9ALP REF IS ANALOG LOW POWER REFERENCE.
10ALDO IS ANALOG LOW DROPOUT REGULATOR.
11DLP REF IS DIGITAL LOW POWER REFERENCE.
12DLDO IS DIGITAL LOW DROPOUT REGULATOR.
Figure 1.
Rev. 0 | Page 4 of 35
20321-001
1THIS
Data Sheet
ADuCM410
SPECIFICATIONS
AVDD = IOVDD0 = 2.85 V to 3.6 V, IOVDD1 = 1.2 V or 1.8 V, DVDD = 1.8 V to 3.6 V, VREF = 2.5 V for the internal reference, the core
frequency (fCORE) = 160 MHz, and TA = −40°C to +105°C, unless otherwise noted. HCLK is the high speed system clock.
Table 1.
Parameter
ADC CHANNEL SPECIFICATIONS
ADC Power-Up Time
Data Rate (fADC)
Resolution
Integral Nonlinearity
Differential Nonlinearity
DC Code Distribution1
ENDPOINT ERRORS
Offset Error
Offset Error Drift
Offset Error Drift Matching
Min
Typ
Max
5
Unit
16
−4
±1
+3
μs
MSPS
Bits
LSB
−9.5
±1
+6
LSB
−9.5
±5
±4
±5
±5
±8
+8
LSB
LSB
LSB
LSB
LSB
−8
−8
−11.5
−15
−0.9
±3
±3
±6
±8
±0.9
+12
+8
+11.5
+15
+1.5
LSB
LSB
LSB
LSB
LSB
2
±9
LSB
±5
LSB
±5
LSB
±5
LSB
−425
−770
±150
±200
+330
+830
µV
µV
−250
−415
−610
−1460
±150
±250
±200
±250
±4
±1
+225
+365
+555
+1375
µV
µV
µV
µV
µV/°C
µV/°C
Rev. 0 | Page 5 of 35
Test Conditions/Comments
2.5 V internal reference
Voltage input to AINx, PGA off,
differential mode
Voltage input to AINx, PGA off, singleended mode
PGA voltage input to ADC, G = 2
G=4
G=6
G=8
G = 10
TIA input channels
TIA resistance (RTIA) = 250 Ω
RTIA = 750 Ω, 2 kΩ
RTIA = 5 kΩ
RTIA = 10 kΩ, 20 kΩ,100 kΩ
Differential and single-ended
Minimum and maximum range from
mean ADC codes for 1000 samples
ADC input = 2 V, single-ended mode,
fADC = 2 MSPS, PGA off
ADC input = 1 V, differential mode, fADC =
50 kSPS, PGA gain = 2, oversampling ratio
(OSR) = 8
ADC input = 200 mV, differential mode,
fADC = 50 kSPS, PGA gain = 10, OSR = 8
TIA mode, gain resistor = 100 kΩ, fADC =
25 kSPS, OSR = 4, input current = 10 µA
Voltage inputs only
PGA off
PGA channels; voltage input to ADC; G =
2, 4, 6, 8, 10; TIA input channels; all gain
settings; current converted to a voltage;
not production calibrated; user calibration
can remove this error
Gain resistor = 250 Ω, 750 Ω
Gain resistor = 2 kΩ
Gain resistor = 5 kΩ
Gain resistor = 10 kΩ, 20 kΩ,100 kΩ
PGA off
Matching compared to AIN0; for voltage
input channels, PGA off only
ADuCM410
Parameter
Full-Scale Error
Data Sheet
Min
−900
−0.33
Typ
±250
±0.2
Max
+370
+0.3
Unit
µV
% of FS2
−0.5
±0.2
+0.4
% of FS2
−5
+5
+12
% of FS2
−1
±0.5
±5
±0.5
+1
% of FS2
ppm/°C
ppm/°C
+0.2
+0.3
Gain Error Drift
Gain Error Drift Matching
PGA Mismatch Error
−0.3
PGA Mismatch Error Drift
DYNAMIC PERFORMANCE
4
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel to Channel Crosstalk
ANALOG INPUT (VOLTAGE CHANNELS)
Input Voltage Ranges
Differential Mode
Single-Ended Mode
Leakage Current
%
dB
89
−100
−88
−96
dB
dB
dB
dB
PGA gain = 2, 4, 6, 8, 10; VCM is commonmode voltage
2.5
±5
V
nA
±30
nA
Gain = 1 and PGA = off
Input voltage to AINx = 0.15 V to 2.5 V
(except AIN4 and AIN7)
AIN4 and AIN7 only
Input buffer enabled
At 100 kHz sample rate from 0.15 V to
2.5 V, AINx = 0.15 V to 2.5 V (except AIN4
and AIN7)
AIN4 and AIN7 only
PGA off, 2 MSPS ADC sample rate
During ADC acquisition
±10
+60
nA
−60
−230
±50
±50
30
+135
+530
nA
nA
pF
−5
250
500
Measured on adjacent channels
V
−60
ANALOG INPUT (TIA CURRENT
CHANNELS)
Source and Sink Current Range
TIA Bias Voltage Range
Input frequency (fIN) = 500 Hz sine wave,
sampling frequency (fSAMPLE) = 1 MSPS
internally
Includes distortion and noise
components, voltage input, PGA off,
single-ended mode
Voltage input, PGA off, differential mode
VCM + VREF/(2
× gain)
Input Current
1
10
250
Matching compared to AIN0; for voltage
input channels, PGA off only
Error between adjacent gain settings of
PGA
ppm/°C
84
VCM −
VREF/(2 ×
gain)
0
Input Capacitance
ANALOG INPUT (PGA VOLTAGE
CHANNELS)
PGA Gain Options
Settling Time
Compliant Range
Test Conditions/Comments
PGA off, voltage input to AINx
PGA voltage input to ADC; G = 2, 4 (not
factory calibrated); user calibration can
remove this error
G = 6, 8, 10 (not factory calibrated); user
calibration can remove this error
TIA input channels, all gain settings,
current converted to a voltage
Internal channels only
10
Lower of
2500 or
AVDD − 800
+5
Lower of
2500 or
AVDD – 800
1800
Rev. 0 | Page 6 of 35
G = 1, 2, 4, 6, 8, or 10
μs
mV
mA
mV
mV
RTIA = 250 Ω
Data Sheet
Parameter
Output Voltage Range
ADuCM410
Min
250
Typ
500
Max
Lower of
2500 or
AVDD − 800
1800
Unit
mV
Test Conditions/Comments
Except RTIA = 250 Ω
mV
RTIA = 250 Ω
No external extra capacitors to AGND or
to supply on AINx when used as TIA
inputs
120
30
+12
120
+0.9
pF
pF
%
ppm/°C
%
±5
30
20
V
mV
ppm/°C
ppm/°C
Allowed External Load Capacitance1
TIA Gain Resistors
250 Ω, 750 Ω
2 kΩ, 5 kΩ, 10 kΩ, 20 kΩ, 100 kΩ
Gain Accuracy
Gain Drift over Temperature
Gain Mismatch Error
−5
−0.8
+5
60
±0.3
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Accuracy
Reference Temperature Coefficient
2.5
10
10
Power Supply Rejection Ratio (PSRR)
DC
AC
70
60
dB
dB
Output Impedance
2
Ω
2.5
V
5
kΩ
1.25 or
2.5
V
EXTERNAL REFERENCE INPUT
Input Voltage Range
Input Impedance
BUFFERED REFERENCE VOLTAGE
OUTPUTS (BUFx_VREF)
Output Voltage
Accuracy
Reference Temperature Coefficient
10
10
2.5
2.5
Load Regulation
Output Impedance
Load Current
PSRR
VOLTAGE DAC (VDAC) CHANNEL
SPECIFICATIONS
DC Accuracy
Resolution
Relative Accuracy3
Differential Nonlinearity3
Calculated Offset Error
Actual Offset Error
±6
30
20
4
70
mV
ppm/°C
ppm/°C
mV/mA
Ω
mA
dB
TIA gain resistor and ADC gain error
Error introduced when moving up or
down one RTIA value
4.7 μF decoupling capacitor between
ADCREFP and ADCREFN
TA = 25°C
TA = −40°C to +25°C range
TA = 25°C to 105°C range
AVDD change effects, 2.85 V to 3.6 V
Tested with AVDD noise of 1 kHz, 10 kHz,
100 kHz, and 1 MHz
Do not use as external reference source,
TA = 25°C
Only supports 2.5 V external reference
input
External reference source must be
capable of sourcing 500 µA minimum
1 μF capacitor required on both outputs
TA = 25°C, load = 4 mA
TA = −40°C to +25°C range
TA = 25°C to 105°C range
VDAC Channel 0 to Channel 7: buffer on;
load resistance (RL) = 1 kΩ, load
capacitance (CL) = 100 pF; DACCONx, Bit 9
= 0 (normal drive, unless otherwise
stated); VDAC Channel 8 to Channel 11:
buffer on, RL = 2.5 kΩ, CL = 100 pF
12
−2
−0.9
−13.5
−10
−10
±1.5
±0.5
±5
+2
+2
+3
+0.9
+15.5
+10
+10
Rev. 0 | Page 7 of 35
Bits
LSB
LSB
mV
mV
mV
Guaranteed monotonic
2.5 V internal reference
Measured at Code 0
VDAC Channel 0 to Channel 7: DACCONx,
Bit 9 = 1; RL = 250 Ω; CL = 100 pF
ADuCM410
Parameter
Gain Error
Data Sheet
Min
−0.7
−0.7
Offset Error Drift
Gain Error Drift
Short-Circuit Current
DAC OUTPUTS
Output Range1
Typ
±0.2
±0.2
Max
+0.5
+0.5
±10
15
±32
±15
0
0
2.5
Lower of 2.5
or AVDD − 0.7
Unit
% of FS2
% of FS2
VDAC Channel 0 to Channel 7
VDAC Channel 8 to Channel 11
V
V
VDAC Channel 0 to Channel 7
VDAC Channel 8 to Channel 11
1
Ω
2.5
10
±20
V/µs
µs
nV-sec
COMPARATOR INPUT
Offset Voltage
±15
mV
−30
31
101
+43
501
740
Voltage Range
Capacitance
Hysteresis
Hysteresis Voltage Accuracy
Response Time
POWER-ON RESET (POR)
POR Trip Level (DVDD)
Timeout from POR
FLASH MEMORY
Endurance
Data Retention
INTERNAL HIGH POWER OSCILLATOR
Accuracy
nA
nA
nA
940
nA
0.5
AVDD − 1.2
V
AGND
0
AVDD
2.0
V
10
840
7
50
10
210
35
5
15
5
1.6
1.62
1.66
32
1.77
1.7
VDAC Channel 0 to Channel 7: DACCONx,
Bit 9 = 1; RL = 250 Ω; CL = 100 pF
μV/°C
ppm/°C
mA
mA
Output Impedance
DAC AC CHARACTERISTICS
Slew Rate
Voltage Output Settling Time
Digital to Analog Glitch Energy
Bias Current
Test Conditions/Comments
pF
mV
% of target
hysteresis
% of target
hysteresis
µs
V
V
ms
1 LSB change at major carry (where
maximum number of bits simultaneously
changes in DACDATx register)
The offset voltage is dependent on the
comparator being enabled with its input
pins connected to external biasing
circuits; if the comparator is left powered
down or if the inputs to the comparator
are left floating, over time the offset error
may increase
Noninverting (positive), input
Inverting (negative), input, hysteresis
disabled
Inverting (negative), input, hysteresis =
10 mV
Inverting (negative), input, hysteresis =
210 mV
Negative input range (reference node of
the comparator)
Positive input range to comparator
Differential input range; positive input −
negative input voltage
16 configurable options4
10 mV to 35 mV settings
50 mV to 210 mV settings
Refers to voltage at DVDD pin
Power-on level, see Figure 18
Power-down level (brownout)
2× 512 kB, 128 kB SRAM
10,000
10
16
±3
Rev. 0 | Page 8 of 35
Cycles
Years
MHz
%
Junction temperature (TJ) = 125°C
Data Sheet
Parameter
TEMPERATURE SENSOR
Voltage Output at 25°C
Voltage Temperature Coefficient
Accuracy
INTERNAL LOW POWER OSCILLATOR
Accuracy
3.3 V GPIO
Logic Inputs
Input Low Voltage (VINL)
Input High Voltage (VINH)
Pull-Up Current
Pull-Down Current
Internal Pull-Up/Pull-Down
Disabled
Logic Outputs
Output High Voltage (VOH)
Output Low Voltage (VOL)
Input Capacitor
Short-Circuit Current
1.8 V GPIO
Logic Inputs
VINL
VINH
Pull-Up Current
Pull-Down Current
Internal Pull-Up/Pull-Down
Disabled
Logic Outputs
VOH
VOL
Input Capacitor
Short-Circuit Current
1.2 V GPIO
Logic Inputs
VINL
VINH
Pull-Up Current
Pull-Down Current
Internal Pull-Up/Pull-Down
Disabled
Logic Outputs
VOH
VOL
Input Capacitor
Short-Circuit Current
MDIO
Logic Inputs
VINL
VINH
Logic Output
VOH
VOL
ADuCM410
Min
Typ
−3
0.13625
0.4568
±2
32
±7
−10
Max
Unit
+4.4
V
mV/°C
°C
kHz
%
+10
Test Conditions/Comments
Indicates die temperature
IOVDD0 = 3.3 V
0.99
2
120
125
−32
160
163
+1
IOVDD × 0.3
210
210
+65
V
V
µA
µA
nA
0.4
V
V
Source current (ISOURCE) = 12 mA
Sink current (ISINK) = 12 mA; for I2C SCL0,
SCL2, SDA0, and SDA2, ISINK = 20 mA; for
I2C SCL1 and SDA1, ISINK = 12 mA
2.4
10
13
VIN = 0 V
VIN = 3.3 V
IOVDD0 power source
pF
mA
IOVDD1 = 1.8 V
0.54
1.26
155
170
−500
194
217
+25
240
270
+2000
1.4
0.3
10
17
V
V
µA
µA
nA
V
V
pF
mA
Input voltage (VIN) = 0 V
VIN = 1.8 V
IOVDD1 power source
ISOURCE = 12 mA
ISINK = 12 mA
IOVDD1 = 1.2 V
0.36
0.84
55
55
−450
76
82
+20
100
110
+1510
1.0
0.18
10
7
0.36
0.84
1.0
0.2
Rev. 0 | Page 9 of 35
V
V
µA
µA
nA
V
V
pF
mA
VIN = 0 V
VIN = 1.2 V
IOVDD1 power source
ISOURCE = 6 mA
ISINK = 6 mA
V
V
V
V
ISOURCE = 4 mA
ISINK = 4 mA
ADuCM410
Parameter
Input Capacitor
Short-Circuit Current
MICROCONTROLLER UNIT (MCU)
CLOCK RATE
Using PLL Output
EXTERNAL RESET
Minimum Pulse Duration
PROCESSOR START-UP TIME
At Power-On
After Reset Event
After Processor Power-Down
Core Sleep (Mode 1)5
System Sleep (Mode 2), Hibernate
(Mode 3)5
POWER REQUIREMENTS
Power Supply Voltage Range
AVDD to AGND
DVDD to DGND
IOVDD0 to IOGND
IOVDD1 to IOGND
Analog Power Supply Currents
AVDD Current
Digital Power Supply Current
Current in Normal Mode
IOVDD0
IOVDD1
DVDD Current
Active Mode
Core Sleep (Mode 1)5
System Sleep (Mode 2)5
Hibernate (Mode 3)5
Additional Power Supply Currents
ADC
PGA
DAC
Total Supply Current
Data Sheet
Min
Typ
Max
10
Unit
pF
mA
163
MHz
7
160
10
2.85
1.8
2.85
1.08
Test Conditions/Comments
µs
Pin voltage must stay low for this period
32
1
ms
ms
Includes kernel power-on execution time
Includes kernel power-on execution time
30
85
HCLK cycles
µs
Fixed number of HCLK periods
HCLK = 160 MHz from PLL
3
µs
HCLK = 16 MHz from internal oscillator
3.3
1.8 or
3.3
3.3
1.2 or
1.8
3.6
3.6
V
V
3.6
1.98
V
V
900
1050
µA
If unused, can be tied to DVDD_REG or to
DGND
Analog peripherals in idle mode
On power-up, GPIOs unloaded
175
20
12
200
60
30
µA
µA
mA
Executing typical code (current from all
supplies)
HCLK = 160 MHz from PLL
HCLK = 16 MHz from internal oscillator
HCLK = 160 MHz from PLL
HCLK = 16 MHz from internal oscillator
16
4.8
11
4.3
2.46
19
mA
mA
mA
mA
mA
2.44
17
mA
Full clock, PLL = 160 MHz
2.8
0.375
3.4
0.465
mA
mA
330
350
µA
Continuously converting at 2 MSPS
Per powered up PGA, excluding load
current
Per powered up DAC, excluding load
current
Active mode with PLL clock of 160 MHz
and ADC enabled.
18.8
mA
These numbers are not production tested but are guaranteed by design and/or characterization data at production release.
FS is full scale.
3
VDAC linearity specifications generated using reduced DAC code range of 82 to 4095. For VDAC Channel 8 to Channel 11, end code of 4095 only used when AVDD –
0.7 V > 2.5 V.
4
These options include 10 mV, 25 mV, 35 mV, 50 mV, 60 mV, 75 mV, 100 mV, 110 mV, 125 mV, 135 mV, 150 mV, 160 mV, 175 mV, 185 mV, 200 mV, and 210 mV.
5
In core sleep mode, the system gates the clock to the Cortex-M33 core after the Cortex-M33 enters sleep mode. In system sleep mode, the system gates the system
bus clock and the peripheral bus clock after the Cortex-M33 enters sleep mode. See the ADuCM410 hardware reference manual for more information about the
various power modes.
1
2
Rev. 0 | Page 10 of 35
Data Sheet
ADuCM410
TIMING SPECIFICATIONS
I2C Timing
Table 2. I2C Timing in Standard Mode (100 kHz)—Slave/Master
Parameter
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
tVD; DAT
tVD; ACK
CB
Description
SCLx low pulse width
SCLx high pulse width
Start condition hold time
Data setup time
Data hold time (SDAx held internally after falling edge of SCLx, duration set via
TCTL register, THDATIN bits)
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCLx and SDAx
Fall time for both SCLx and SDAx
Data valid time
Data valid acknowledge time
Capacitive load for each bus line (not shown in Figure 2)
Min
4.7
4.0
4.0
250
0
Typ
Max
3.45
Unit
µs
µs
µs
ns
µs
1
300
3.45
3.45
400
µs
µs
µs
µs
ns
µs
µs
pF
4.7
4.0
4.7
15
Table 3. I2C Timing in Fast Mode (400 kHz)—Slave/Master
Parameter
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
tVD; DAT
tVD; ACK
CB
Description
SCLx low pulse width
SCLx high pulse width
Start condition hold time
Data setup time
Data hold time (SDAx held internally after falling edge of SCLx, duration set via TCTL register,
THDATIN bits)
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCLx and SDAx
Fall time for both SCLx and SDAx
Data valid time
Data valid acknowledge time
Capacitive load for each bus line (not shown in Figure 2)
Min
1.3
0.6
0.6
100
0
Typ
0.6
0.6
1.3
20
15
Max
300
300
0.9
0.9
400
Unit
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
µs
µs
pF
I2C GPIOs (P0.7 to P0.4 and P1.3 to P1.2) drive strength set to 20 mA.
Table 4. I2C Timing in Fast Mode Plus (1 MHz)—Slave/Master
Parameter
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
tVD; DAT
tVD; ACK
CB
Description
SCLx low pulse width
SCLx high pulse width
Start condition hold time.
Data setup time
Data hold time (SDAx held internally after falling edge of SCLx, duration set via
TCTL register, THDATIN bits)
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCLx and SDAx
Fall time for both SCLx and SDAx
Data valid time
Data valid acknowledge time
Capacitive load for each bus line (not shown in Figure 2)
Rev. 0 | Page 11 of 35
Min
0.5
0.26
0.26
50
0
Typ
Max
0.26
0.26
0.5
120
120
0.45
0.45
550
Unit
µs
µs
µs
ns
µs
µs
µs
µs
ns
ns
µs
µs
pF
ADuCM410
Data Sheet
I2C GPIOs (P0.7 to P0.4 and P1.3 to P1.2) drive strength set to 20 mA.
Table 5. I2C Timing in High Speed Mode (3.4 MHz)—Slave Only
tRSU
tPSU
tBUF
tR
tF
CB
Description
SCLx low pulse width
SCLx high pulse width
Start condition hold time.
Data setup time
Data hold time (SDAx held internally after falling edge of SCLx, duration set via
TCTL register, THDATIN bits)
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCLx and SDAx
Up to CB = 100 pF
Up to CB = 400 pF
Fall time for both SCLx and SDAx
Up to CB = 400 pF
Capacitive load for each bus line (not shown in Figure 2)
Min
160
60
160
10
0
Max
Unit
ns
ns
ns
ns
ns
160
160
200
ns
ns
ns
10
40
80
40
80
400
10
tBUF
ns
ns
ns
ns
pF
tR
SDAx (I/O)
MSB
tDSU
LSB
tVD; DAT
1
S
tF
tRSU
tR
tVD; ACK
8
2–7
MSB
tDHD
tH
tSHD
SCLx (I)
ACK
tDSU
tDHD
tPSU
P
Typ
9
1
tL
S(R)
STOP
START
CONDITION CONDITION
REPEATED
START
tF
20321-002
Parameter
tL
tH
tSHD
tDSU
tDHD
Figure 2. I2C-Compatible Interface Timing
SPI Timing Specifications: Slave Mode
SPI GPIOs (P0.3 to P0.0, P1.7 to P1.4, and P2.7 to P2.4) drive strength set to 12 mA, IOVDD1 ≥ 1.2 V, and 40 MHz SPI clock.
See Figure 3 and Figure 4.
Table 6. SPI Slave Mode Timing
Parameter
TIMING REQUIREMENTS
CSx to SCLKx Edge
Minimum valid CSx inactive period
SCLKx Low Pulse Width
SCLKx High Pulse Width
Data Input Setup Time Before SCLKx Edge
Data Input Hold Time After SCLKx Edge
SWITCHING CHARACTERISTICS
Data Output Valid After SCLKx Edge
Data Output Valid After CSx Edge
CSx High After SCLKx Edge
Symbol
Min
tCS
25
tCSM
25
tSL
tSH
tDSU
tDHD
tDAV
tDOCS
tSFS
Rev. 0 | Page 12 of 35
Typ
Max
Unit
ns
ns
10
10
ns
ns
ns
ns
10
15
8.75
ns
ns
ns
5
5
Data Sheet
ADuCM410
tCSM
CSx
tCS
tSFS
SCLKx
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLKx
(POLARITY = 1)
tDAV
tDOCS
tDF
tDR
MSB
MISOx
20321-003
MOSIx
Figure 3. SPI Slave Mode Timing (Serial Clock Phase Mode, CTL Register, Bit 2, CPHA = 0)
tCSM
CSx
tCSx
tSFS
SCLKx
(POLARITY = 0)
tSH
tSL
SCLKx
(POLARITY = 1)
tDAV
tDOCS
tDF
MOSIx
MSB
MSB IN
tDSU
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
LSB IN
20321-004
MISOx
tDR
tDHD
Figure 4. SPI Slave Mode Timing (CPHA = 1)
Rev. 0 | Page 13 of 35
ADuCM410
Data Sheet
SPI Timing: Master Mode
SCLKx = 40 MHz, SPI SPI GPIOs (P0.3 to P0.0, P1.7 to P1.4, and P2.7 to P2.4) pin drive strength set to 12 mA. IOVDD1 ≥ 1.2 V. DIV is
the SPI clock divider in the SPI baud rate selection register (see the ADuCM410 hardware reference manual for more information). tHCLK
is the time period of HCLK set up by the user.
Table 7. SPI Master Mode Timing (Phase Mode = 0 and 1)
Description
SCLKx low pulse width
SCLKx high pulse width
Data output valid after SCLKx edge
Data input setup time before SCLKx edge
Data input hold time after SCLKx edge
Data output fall time
Data output rise time
SCLKx rise time
SCLKx fall time
SCLKx
(POLARITY = 0)
tSH
Min
Typ
(DIV + 1) × tHCLK/2
(DIV + 1) × tHCLK/2
5
5
5
5
tSL
tDAV
tSR
tDF
MSB
MISOx
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
0
5
5
SCLKx
(POLARITY = 1)
MOSIx
Max
tSF
tDR
BIT 6 TO BIT 1
MSB IN
LSB
BIT 6 TO BIT 1
LSB IN
20321-005
tDSU
tDHD
Figure 5. SPI Master Mode Timing (CPHA = 1)
SCLKx
(POLARITY = 0)
tSH
tSL
tSF
tSR
SCLKx
(POLARITY = 1)
tDAV
tDF
MOSIx
MISOx
MSB
MSB IN
tDR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
LSB IN
tDSU
20321-007
Parameter
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDHD
Figure 6. SPI Master Mode Timing (CPHA = 0)
Rev. 0 | Page 14 of 35
Data Sheet
ADuCM410
Table 8. MDIO vs. MDC Timing
Parameter1
Maximum MCK Clock Speed
tSETUP
tHOLD
tDELAY
Min
Typ
Max
10
4
5
10
7
10
26
100
In Figure 7, CFP is C formfactor pluggable. VIH is the voltage input high level, and VIL is voltage input low level.
MCK
VIH
VIL
CFP
INPUT
MDIO
VIH
VIL
CFP
INPUT
MDIO
VOH
VOL
CFP
OUTPUT
tSETUP
tHOLD
Figure 7. MDIO Timing
Rev. 0 | Page 15 of 35
tDELAY
20321-008
1
Description
Push/pull mode
Open-drain mode, pull-up resistance (RPULLUP) = 312 Ω
MDIO setup before MCK edge (push/pull mode)
Open-drain mode, RPULLUP = 312 Ω
MDIO valid after MCK edge (push/pull mode)
Open-drain mode, RPULLUP = 312 Ω
Data output after MCK edge (push/pull mode)
Open-drain mode, RPULLUP = 312 Ω
Unit
MHz
MHz
ns
ns
ns
ns
ns
ADuCM410
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 9.
Parameter
AVDD to AGND
IOVDD0 to IOGND
IOVDD1 to IOGND
DVDD to DGND
AVDD to IOVDD0
Analog Input Voltage to AGND
(AVDD Range = 2.85 V to 3.6 V)
Digital Input Voltage to IOGND
Digital Input Voltage to IOGND (P1.0
to P1.7 and P0.0 to P0.3 Only)1
AGND to DGND
IOGND to DGND
Total Positive GPIO Pins Current
Total Negative GPIO Pins Current
Temperature Ranges
Storage
Operating
Reflow Profiles
SnPb Assemblies (10 sec to 30 sec)
Pb-Free Assemblies (20 sec to
40 sec)
Junction Temperature
1
Rating
−0.3 V to +3.63 V
−0.3 V to +3.63 V
−0.3 V to +1.98 V
−0.3 V to +3.63 V
IOVDD0 ± 0.3 V
−0.3 V to AVDD + 0.3 V,
must be ≤3.63 V
−0.3 V to IOVDD0 + 0.3 V,
must be ≤3.63 V
−0.3 V to IOVDD1 + 0.3 V,
must be ≤1.98 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
0 mA to 40 mA
−40 mA to 0 mA
−65°C to +150°C
−40°C to +105°C
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 10. Thermal Resistance
Package Type
BC-81-4
CB-64-2
1
θJA1
35
34
θJC
0.12
0.16
Unit
°C/W
°C/W
JEDEC 2S2P.
ELECTROSTATIC DISCHARGE (ESD) RATINGS
The following ESD information is provided for handling of ESD
sensitive devices in an ESD protected area only.
Human body model (HBM) per ANSI/ESDA/JEDEC JS-001.
Field induced charged device model (FICDM) per
ANSI/ESDA/JEDEC JS-002.
240°C
260°C
ESD Ratings for ADuCM410
Table 11. ADuCM410, 81-Ball CSP_BA and 64-Ball WLCSP
150°C
When IOVDD1 is the selected power rail.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD Model
HBM
FICDM
ESD CAUTION
Rev. 0 | Page 16 of 35
Withstand Threshold (kV)
3
0.5
Class
2
C2A
Data Sheet
ADuCM410
TYPICAL PERFORMANCE CHARACTERISTICS
2.510
16
DEVICE 1
DEVICE 2
DEVICE 3
2.508
14
12
INPUT CURRENT (nA)
2.502
2.500
2.498
2.496
10
8
6
4
2.494
2
2.492
0
2.490
0.1
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.0
LOAD CURRENT (mA)
–2
0.30
0.60
DEVICE 5, AIN8
DEVICE 5, AIN9
DEVICE 5, AIN10
DEVICE 5, AIN11
DEVICE 5, AIN12
DEVICE 5, AIN13
DEVICE 5, AIN14
DEVICE 5, AIN15
0.90
DEVICE 6, AIN0
DEVICE 6, AIN1
DEVICE 6, AIN2
DEVICE 6, AIN3
DEVICE 6, AIN4
1.20
1.35
1.65
VOLTAGE (V)
DEVICE 6, AIN5
DEVICE 6, AIN6
DEVICE 6, AIN7
DEVICE 6, AIN8
1.95
2.25
2.50
Figure 11. ADC Input Current vs. Voltage on AINx, fSAMPLE = 100 kSPS
Figure 8. BUF0_VREF Load Regulation, 2.5 V Output Setting
3
1.258
DEVICE 1
DEVICE 2
DEVICE 3
1.256
2
1.254
1.252
ERROR (°C)
OUTPUT VOLTAGE (V)
DEVICE 5, AIN0
DEVICE 5, AIN1
DEVICE 5, AIN2
DEVICE 5, AIN3
DEVICE 5, AIN4
DEVICE 5, AIN5
DEVICE 5, AIN6
DEVICE 5, AIN7
20321-020
2.504
20321-017
OUTPUT VOLTAGE (V)
2.506
1.250
1.248
1
0
1.246
1.244
–1
0.1
0.5
0.9
1.3
1.7
2.1
2.5
2.9
3.3
3.7
4.0
LOAD CURRENT (mA)
–2
–40 –30 –20 –10
20321-018
1.240
0
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
Figure 12. Temperature Sensor Accuracy, No Calibration, 240 Devices
Figure 9. BUF0_VREF Load Regulation, 1.25 V Output Setting
350
2.504
2.503
300
REFERENCE VOLTAGE (V)
200
150
0
0.30
0.60
DEVICE 5, AIN8
DEVICE 5, AIN9
DEVICE 5, AIN10
DEVICE 5, AIN11
DEVICE 5, AIN12
DEVICE 5, AIN13
DEVICE 5, AIN14
DEVICE 5, AIN15
0.90
DEVICE 6, AIN0
DEVICE 6, AIN1
DEVICE 6, AIN2
DEVICE 6, AIN3
DEVICE 6, AIN4
1.20
1.35
1.65
VOLTAGE (V)
2.501
2.500
2.499
2.498
2.497
2.496
DEVICE 6, AIN5
DEVICE 6, AIN6
DEVICE 6, AIN7
DEVICE 6, AIN8
1.95
2.25
2.495
2.50
2.494
–40 –30 –20 –10 0
Figure 10. Input Current vs. Voltage on AINx, fSAMPLE = 2 MSPS
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (°C)
20321-022
50
DEVICE 5, AIN0
DEVICE 5, AIN1
DEVICE 5, AIN2
DEVICE 5, AIN3
DEVICE 5, AIN4
DEVICE 5, AIN5
DEVICE 5, AIN6
DEVICE 5, AIN7
20321-019
INPUT CURRENT (nA)
2.502
250
100
20321-021
1.242
Figure 13. Reference Voltage Drift vs. Temperature, 250 Devices
Rev. 0 | Page 17 of 35
ADuCM410
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
2
3
4
5
6
7
8
9
A
VDAC1
VDAC3/
P4.0/
PLAI11
VDAC7/
P4.2
RESET
P2.3/
BM/
PLAI10
P2.5/
MISO2/
PLAO19
P2.6/IRQ5/
SCLK2/
PLAO20
IOVDD0
IOGND
B
VREF
AIN15/
COM3N/
BUF1_VREF
VDAC6/
P4.1/
PLAO28
SWDIO
SWCLK
P2.4/
MOSI2/
PLAO18
P2.7/IRQ6/
CS2/
PLAO21
P0.4/SCL0/
SIN0/
PLAO2
P0.5/SDA0/
SOUT0/
PLAO3
C
AIN0
AIN3/
PADC1P
AIN10/
COM1P
VDAC5/
P4.4
P2.2/
POR/
CLKOUT/
SWO
P2.0/
ADCCONV/
COMPDIN2/
PLAI8
P2.1/DM/
IRQ2/
ECLKIN/
COMPDIN3/
PLAI9
P0.7/IRQ4/
SDA2/
COMPDIN1/
PLAO5
P0.6/IRQ3/
SCL2/
COMPDIN0/
PLAO4
D
AIN1
AIN2/
PADC0P
AIN11/
COM1N/
PGA0OUT
VDAC8/
P5.0
VDAC11/
P5.3
P5.6
P4.7/
IRQ7/
PLACLK2
IOGND
IOVDD1
E
ADCREFN
AIN5/
PADC2P
AIN12/
COM2P
VDAC9/
P5.1
DNC
P5.5
P1.2/
SCL1/
PWM0/
PLAI6
P1.1/SOUT1/
COMOUT3/
PLAI5
P1.0/SIN1/
COMOUT2/
PLAI4
F
ADCREFP
AIN6/
PADC3P
AIN9/
COM0N/
PGA2OUT
VDAC10/
P5.2
P5.4
P4.5/PWM7
P1.3/
SDA1/
PWM1/
PLAI7
P0.1/MISO0/
COMOUT1/
PLAI1
P0.0/SCLK0/
COMOUT0/
PLAI0
G
AIN4/
PADC01N/
VDAC0
AIN14/
COM3P/
BUF0_VREF
AIN8/
COM0P
P3.2/
PRTADDR2/
PWMTRIP/
PLAI14
P3.3/
PRTADDR3/
SIN0/
PLAI15
P4.3/PWM6
P1.4/
SCLK1/
PWM2/
PLAO10
P0.3/IRQ0/
CS0/
PLACLK0/
PLAI3
P0.2/MOSI0/
PLACLK1/
PLAI2
H
AIN7/
PADC23N/
VDAC2
AIN13/
COM2N
AGND
P3.1/
PRTADDR1/
PWMSYNC/
PLAI13
P3.4/
IRQ9/
PRTADDR4/
SOUT0/
PLAO26
P3.7/
PLAO29
P1.5/
MISO1/
PWM3/
PLAO11
DGND
DVDD
J
VDAC4
AVDD_REG
AVDD
P3.0/
IRQ8/
PRTADDR0/
SRDY0/
PLAI12
P3.5/
MCK/
SRDY1/
PLAO27
P3.6/
MDIO/
SRDY2/
PLAO30
P1.6/
MOSI1/
PWM4/
PLAO12
P1.7/IRQ1/
CS1/
PWM5/
PLAO13
DVDD_REG
20321-009
1
DNC = DO NOT CONNECT. KEEP THIS PIN FLOATING.
Figure 14. 81-Ball CSP_BGA Pin Configuration
Table 12. 81-Ball CSP_BGA Pin Configuration Descriptions
Ball No.
A1
A2
Mnemonic
VDAC1
VDAC3/P4.0/PLAI11
Type1
AO
AO/I/O
A3
VDAC7/P4.2
AO/I/O
A4
A5
RESET
P2.3/BM/PLAI10
I
I/O
Description
Voltage DAC 1 Output.
Voltage DAC 3 Output (VDAC3).
Digital Input/Output Port 4.0 (P4.0).
Input to PLA Element 11 (PLAI11).
Voltage DAC 7 Output (VDAC7).
Digital Input/Output Port 4.2 (P4.2).
Reset Input (Active Low). An internal pull-up resistor is included with this pin.
Digital Input/Output Port 2.3 (P2.3). An internal pull-up resistor is enabled
at power-up on P2.3.
Boot Mode (BM). This pin determines the start-up sequence after every
reset.
Input to PLA Element 10 (PLAI10).
Rev. 0 | Page 18 of 35
Data Sheet
ADuCM410
Ball No.
A6
Mnemonic
P2.5/MISO2/PLAO19
Type1
I/O
A7
P2.6/IRQ5/SCLK2/ PLAO20
I/O
A8
A9
B1
B2
IOVDD0
IOGND
VREF
AIN15/COM3N/BUF1_VREF
S
S
AO/AI
AI/AO
B3
VDAC6/P4.1/PLAO28
AO/I/O
B4
B5
B6
SWDIO
SWCLK
P2.4/MOSI2/PLAO18
I/O
I
I/O
B7
P2.7/IRQ6/CS2/PLAO21
I/O
B8
P0.4/SCL0/SIN0/PLAO2
I/O
B9
P0.5/SDA0/SOUT0/PLAO3
I/O
C1
C2
AIN0
AIN3/PADC1P
AI
AI
C3
AIN10/COM1P
AI
C4
VDAC5/P4.4
AO
C5
P2.2/POR/CLKOUT/SWO
I/O
C6
P2.0/ADCCONV/COMPDIN2/PLAI8
I/O
Description
Digital Input/Output Port 2.5 (P2.5).
SPI Channel 2 (SPI2) Master Input, Slave Output (MISO2).
Output of PLA Element 19 (PLAO19).
Digital Input/Output Port 2.6 (P2.6).
External Interrupt 5 (IRQ5).
SPI2 Clock (SCLK2).
Output of PLA Element 20 (PLAO20).
3.3 V GPIO Supply.
Ground for Digital Inputs/Outputs.
0.92 V Reference with a 100 nF Capacitor.
Analog Input 15 (AIN15).
Comparator 3 Emitter Voltage (VE) Negative (COM3N).
Buffered Reference Voltage Source (BUF1_VREF).
Voltage DAC 6 Output (VDAC6).
Digital Input/Output Port 4.1 (P4.1).
Output of PLA Element 2 (PLAO28).
Serial Wire Bidirectional Data.
Serial Wire Debug Clock.
Digital Input/Output Port 2.4 (P2.4).
SPI2 Master Output, Slave Input (MOSI2).
Output of PLA Element 18 (PLAO18).
Digital Input/Output Port 2.7 (P2.7).
External Interrupt 6 (IRQ6).
SPI2 Chip Select (CS2). Active low.
Output of PLA Element 21 (PLAO21).
Digital Input/Output Port 0.4 (P0.4).
I2C Channel 0 (I2C0) Serial Clock (SCL0).
UART Channel 0 (UART0) Input (SIN0).
Output of PLA Element 2 (PLAO2).
Digital Input/Output Port 0.5 (P0.5).
I2C0 Serial Data (SDA0).
UART0 Output (SOUT0).
Output of PLA Element 3 (PLAO3).
Analog Input 0.
Analog Input 3 (AIN3).
PGA Channel 1 Positive (PADC1P).
Analog Input 10 (AIN10).
Comparator 1 Positive input (COM1P).
Voltage DAC 5 Output (VDAC5).
Digital Input/Output Port 4.4 (P4.4).
Digital Input/Output Port 2.2 (P2.2).
Reset Output (POR). This pin function is an output and it is the default.
Clock Output (CLKOUT).
Serial Wire Debug Output (SWO).
Digital Input/Output Port 2.0 (P2.0).
External Input to Start ADC Conversions (ADCCONV).
Comparator 2 Digital Input for Three-State (COMPDIN2).
Input to PLA Element 8 (PLAI8).
Rev. 0 | Page 19 of 35
ADuCM410
Data Sheet
Ball No.
C7
Mnemonic
P2.1/DM/IRQ2/ECLKIN/COMPDIN3/PLAI9
Type1
I/O
C8
P0.7/IRQ4/SDA2/COMPDIN1/PLAO5
I/O
C9
P0.6/IRQ3/SCL2/COMPDIN0/PLAO4
I/O
D1
D2
AIN1
AIN2/PADC0P
AI
AI
D3
AIN11/COM1N/PGA0OUT
AO/AI
D4
VDAC8/P5.0
AO/I/O
D5
VDAC11/P5.3
AO/I/O
D6
D7
P5.6
P4.7/IRQ7/PLACLK2
I/O
I/O
D8
D9
IOGND
IOVDD1
S
S
E1
ADCREFN
AO/AI
E2
AIN5/PADC2P
AI
E3
AIN12/COM2P
AI
E4
VDAC9/P5.1
AO/I/O
E5
E6
E7
DNC
P5.5
P1.2/SCL1/PWM0/PLAI6
I/O
I/O
Description
Digital Input/Output Port 2.1 (P2.1).
Download Mode Selection (DM).
External Interrupt 2 (IRQ2).
External Input Clock (ECLKIN).
Comparator 3 Digital Input for Three-State (COMPDIN3).
Input to PLA Element 9 (PLAI9).
Digital Input/Output Port 0.7 (P0.7).
External Interrupt 4 (IRQ4).
I2C Channel 2 (I2C2) Serial Data (SDA2).
Comparator 1 Digital Input for Three-State (COMPDIN1).
Output of PLA Element 5 (PLAO5).
Digital Input/Output Port 0.6 (P0.6).
External Interrupt 3 (IRQ3).
I2C2 Serial Clock (SCL2).
Comparator 0 Digital Input for Three-State (COMPDIN0).
Output of PLA Element 4 (PLAO4).
Analog Input 1.
Analog Input 2 (AIN2).
PGA Channel 0 Positive (PADC0P).
Analog Input 11 (AIN11).
Comparator 1 VE Negative (COM1N).
PGA Channel 0 Output (PGA0OUT).
Voltage DAC 8 Output (VDAC8).
Digital Input/Output Port 5.0 (P5.0).
Voltage DAC 11 Output (VDAC11).
Digital Input/Output Port 5.1 (P5.3).
Digital Input/Output Port 5.6.
Digital Input/Output Port 4.7 (P4.7).
External Interrupt 7 (IRQ7).
PLA Input Clock 2 (PLACLK2).
Ground for Digital Inputs/Outputs.
1.2 V/1.8 V GPIO Supply. If unused, IOVDD1 can be tied to DVDD_REG or
to DGND.
Decoupling Capacitor Connection for ADC Reference Buffer. Connect this
pin to AGND.
Analog Input 5 (AIN5).
PGA Channel 2 Positive (PADC2P).
Analog Input 12 (AIN12).
Comparator 2 VE Positive (COM2P).
Voltage DAC 9 Output (VDAC9).
Digital Input/Output Port 5.1 (P5.1).
Do Not Connect. Keep this pin floating.
Digital Input/Output Port 5.5.
Digital Input/Output Port 1.2 (P1.2).
I2C Channel 1 (I2C1) Serial Clock (SCL1).
PWM Output 0 (PWM0).
Input to PLA Element 6 (PLAI6).
Ball E7 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Rev. 0 | Page 20 of 35
Data Sheet
ADuCM410
Ball No.
E8
Mnemonic
P1.1/SOUT1/COMOUT3/PLAI5
Type1
I/O
E9
P1.0/SIN1/COMOUT2/PLAI4
I/O
F1
ADCREFP
AO/AI
F2
AIN6/PADC3P
AI
F3
AIN9/COM0N/PGA2OUT
AO/AI
F4
VDAC10/P5.2
AO/I/O
F5
F6
P5.4
P4.5/PWM7
I/O
I/O
F7
P1.3/SDA1/PWM1/PLAI7
I/O
F8
P0.1/MISO0/COMOUT1/PLAI1
I/O
F9
P0.0/SCLK0/COMOUT0/PLAI0
I/O
G1
AIN4/PADC01N/VDAC0
AI
G2
AIN14/COM3P/BUF0_VREF
AI/AO
G3
AIN8/COM0P
AI
Description
Digital Input/Output Port 1.1 (P1.1).
UART1 Output (SOUT1).
Comparator 3 Output (COMOUT3).
Input to PLA Element 5 (PLAI5).
Ball E8 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 1.0 (P1.0).
UART1 Input (SIN1).
Comparator 2 Output (COMOUT2).
Input to PLA Element 4 (PLAI4).
Ball E9 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Decoupling Capacitor Connection for ADC Reference Buffer with 4.7 µF
Decoupling Capacitor.
Analog Input 6 (AIN6).
PGA Channel 3 Positive (PADC3P).
Analog Input 9 (AIN9).
Comparator 0 VE Negative (COM0N).
PGA Channel 2 Output (PGA2OUT).
Voltage DAC 10 Output (VDAC10).
Digital Input/Output Port 5.2 (P5.2).
Digital Input/Output Port 5.4.
Digital Input/Output Port 4.5 (P4.5).
PWM Output 7 (PWM7).
Digital Input/Output Port 1.3 (P1.3).
I2C1 Serial Data (SDA1).
PWM Output 1 (PWM1).
Input to PLA Element 7 (PLAI7).
Ball F7 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 0.1 (P0.1).
SPI Channel 0 (SPI0) Master Input, Slave Output (MISO0).
Comparator 1 Output (COMOUT1).
Input to PLA Element 1 (PLAI1).
Ball F8 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 0.0 (P0.0).
SPI0 Clock (SCLK0).
Comparator 0 Output (COMOUT0).
Input to PLA Element 0 (PLAI0).
Ball F9 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Analog Input 4 (AIN4).
PGA Channel 0/PGA Channel 1 Negative (PADC01N).
Voltage DAC 0 Output (VDAC0).
Analog Input 14 (AIN14).
Comparator 3 VE Positive (COM3P).
Buffered Reference Voltage Source (BUF0_VREF).
Analog Input 8 (AIN8).
Comparator 0 VE Positive (COM0P).
Rev. 0 | Page 21 of 35
ADuCM410
Data Sheet
Ball No.
G4
Mnemonic
P3.2/PRTADDR2/PWMTRIP/PLAI14
Type1
I/O
G5
P3.3/PRTADDR3/SIN0/PLAI15
I/O
G6
P4.3/PWM6
I/O
G7
P1.4/SCLK1/PWM2/PLAO10
I/O
G8
P0.3/IRQ0/CS0/PLACLK0/PLAI3
I/O
G9
P0.2/MOSI0/PLACLK1/PLAI2
I/O
H1
AIN7/PADC23N/VDAC2
AI
H2
AIN13/COM2N
AI
H3
H4
AGND
P3.1/PRTADDR1/PWMSYNC/PLAI13
S
I/O
H5
P3.4/IRQ9/PRTADDR4/SOUT0/PLAO26
I/O
H6
P3.7/PLAO29
I/O
H7
P1.5/MISO1/PWM3/PLAO11
I/O
H8
H9
DGND
DVDD
S
S
Description
Digital Input/Output Port 3.2 (P3.2).
MDIO Port Address Bit 2 (PRTADDR2).
PWM Trip (PWMTRIP).
Input to PLA Element 14 (PLAI14).
Digital Input/Output Port 3.3 (P3.3).
MDIO Port Address Bit 3 (PRTADDR3).
UART0 Input (SIN0).
Input of PLA Element 15 (PLAI15).
Digital Input/Output Port 4.3 (P4.3).
PWM Output 6 (PWM6).
Digital Input/Output Port 1.4 (P1.4).
SPI Channel 1 (SPI1) Clock (SCLK1).
PWM Output 2 (PWM2).
Output of PLA Element 10 (PLAO10).
Ball G7 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 0.3 (P0.3).
External Interrupt 0 (IRQ0).
SPI0 Chip Select (CS0). Active low.
PLA Clock 0 (PLACLK0).
Input to PLA Element 3 (PLAI3).
Ball G8 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 0.2 (P0.2).
SPI0 Master Output, Slave Input (MOSI0).
PLA Clock 1 (PLACLK1).
Input to PLA Element 2 (PLAI2).
Ball G9 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Analog Input 7 (AIN7).
PGA Channel 2/PGA Channel 3 Negative (PADC23N).
Voltage DAC 2 Output (VDAC2).
Analog Input 13 (AIN13).
Comparator 2 VE Negative (COM2N).
Analog Ground.
Digital Input/Output Port 3.1 (P3.1).
MDIO Port Address Bit 1 (PRTADDR1).
PWM Synchronization (PWMSYNC).
Input to PLA Element 13 (PLAI13).
Digital Input/Output Port 3.4 (P3.4).
External Interrupt 9 (IRQ9).
MDIO Port Address Bit 4 (PRTADDR4).
UART0 Output (SOUT0).
Output of PLA Element 26 (PLAO26).
Digital Input/Output Port 3.7 (P3.7).
Output of PLA Element 29 (PLAO29).
Digital Input/Output Port 1.5 (P1.5).
SPI1 Master Input, Slave Output (MISO1).
PWM Output 3 (PWM3).
Output of PLA Element 11 (PLAO11).
Ball H7 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Ground.
1.8 V/3.3 V Digital Power Supply.
Rev. 0 | Page 22 of 35
Data Sheet
ADuCM410
Ball No.
J1
J2
Mnemonic
VDAC4
AVDD_REG
Type1
AO
AO
J3
J4
AVDD
P3.0/IRQ8/PRTADDR0/SRDY0/PLAI12
S
I/O
J5
P3.5/MCK/SRDY1/PLAO27
I/O
J6
P3.6/MDIO/SRDY2/PLAO30
I/O
J7
P1.6/MOSI1/PWM4/PLAO12
I/O
J8
P1.7/IRQ1/CS1/PWM5/PLAO13
I/O
J9
DVDD_REG
AO
1
Description
Voltage DAC 4 Output.
2.5 V Analog Regulator Supply with 0.47 µF Decoupling Capacitor. Do not
use AVDD_REG to power external circuits.
3.3 V Analog Power Supply.
Digital Input/Output Port 3.0 (P3.0).
External Interrupt 8 (IRQ8).
MDIO Port Address Bit 0 (PRTADDR0).
SPI0 Ready (SRDY0).
Input to PLA Element 12 (PLAI12).
Digital Input/Output Port 3.5 (P3.5).
MDIO Slave Clock (MCK).
SPI1 Ready (SRDY1).
Output of PLA Element 27 (PLAO27).
Digital Input/Output Port 3.6 (P3.6).
MDIO Slave Data (MDIO).
SPI2 Ready (SRDY2).
Output of PLA Element 30 (PLAO30).
Digital Input/Output Port 1.6 (P1.6).
SPI1 Master Output, Slave Input (MOSI1).
PWM Output 4 (PWM4).
Output of PLA Element 12 (PLAO12).
Ball J7 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 1.7 (P1.7).
External Interrupt 1 (IRQ1).
SPI1 Chip Select (CS1). Active low.
PWM Output 5 (PWM5).
Output of PLA Element 13 (PLAO13).
Ball J8 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
1.1 V Digital Regulator Supply with 0.47 µF Decoupling Capacitor. Do not
use DVDD_REG to power external circuits.
AO is analog output, I/O is input/output, I is digital input, S is supply, and AI is analog input.
Rev. 0 | Page 23 of 35
Data Sheet
1
2
3
4
5
6
7
8
SWDIO
VDAC7
VDAC6
VDAC5
VDAC3
A
IOGND
P2.0/
ADCCONV/
COMPDIN2/
PLAI8
P2.1/DM/
IRQ2/
ECLKIN/
COMPDIN3/
PLAI9
B
P0.3/IRQ0/
CS0/
PLACLK0/
PLAI3
P0.2/MOSI0/
PLACLK1/
PLAI2
P2.3/
BM
PLAI10
SWCLK
RESET
VDAC1
VREF
AVDD
C
IOVDD1
P0.1/MISO0/
COMOUT1/
PLAI1
P0.0/SCLK0/
COMOUT0/
PLAI0
P1.0/SIN1/
COMOUT2/
PLAI4
P2.2/
POR/
CLKOUT/
SWO
AIN14/
COM3P/
BUF0_VREF
AIN2/
PADC0P
AIN4/
PADC01N/
VDAC0
D
DVDD_REG
DGND
P1.2/
SCL1/
PWM0/
PLAI6
P1.3/
SDA1/
PWM1/
PLAI7
P1.1/
SOUT1/
COMOUT3/
PLAI5
AIN3/
PADC1P
AIN0
AIN10/
COM1P
E
IOVDD0
IOGND
P1.4/
SCLK1/
PWM2/
PLAO10
P1.7/
IRQ1/CS1/
PWM5/
PLAO13
VDAC8/
P5.0
AIN12/
COM2P
AGND
AVDD_REG
F
P1.5/
MISO1/
PWM3/
PLAO11
P1.6/
MOSI1/
PWM4/
PLAO12
P0.7/IRQ4/
SDA2/
COMPDIN1/
PLAO5
P3.2/
PRTADDR2/
PWMTRIP/
PLAI14
VDAC9/
P5.1
AIN8/
COM0P
ADCREFN
ADCREFP
G
P0.4/SCL0/
SIN0/
PLAO2
P0.5/SDA0/
SOUT0/
PLAO3
P0.6/IRQ3/
SCL2/
COMPDIN0/
PLAO4
P3.1/
PRTADDR1/
PWMSYNC/
PLAI13
VDAC11/
P5.3
AIN7/
PADC23N/
VDAC2
AIN1
AIN9/
COM0N
H
IOGND
DVDD
P3.6/
MDIO
P3.5/
MCK/
SRDY1/
PLAO27
P3.0/
PRTADDR0/
SRDY0/
PLAI12
VDAC10/
P5.2
VDAC4
AIN13/
COM2N
20321-010
ADuCM410
Figure 15. 64-Ball WLCSP Pin Configuration
Table 13. 64-Ball WLCSP Pin Function Descriptions
Pin No.
A1
A2
Mnemonic
IOGND
P2.0/ADCCONV/COMPDIN2/PLAI8
Type1
S
I/O
A3
P2.1/DM/IRQ2/ECLKIN/COMPDIN3/PLAI9
I/O
A4
A5
A6
A7
A8
SWDIO
VDAC7
VDAC6
VDAC5
VDAC3
I/O
AO
AO
AO
AO
Description
Ground for Digital Inputs/Outputs.
Digital Input/Output Port 2.0 (P2.0).
External Input to Start ADC Conversions (ADCCONV).
Comparator 2 Digital Input for Three-State (COMPDIN2).
Input to PLA Element 8 (PLAI8).
Ball A2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital I/O Port 2.1 (P2.1).
Download Mode Selection (DM).
External Interrupt 2 (IRQ2).
External Input Clock (ECLKIN).
Comparator 3 Digital Input for Three-State (COMPDIN3).
Input to PLA Element 9 (PLAI9).
Ball A3 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Serial Wire Bidirectional Data.
Voltage DAC 7 Output.
Voltage DAC 6 Output.
Voltage DAC 5 Output.
Voltage DAC 3 Output.
Rev. 0 | Page 24 of 35
Data Sheet
ADuCM410
Pin No.
B1
Mnemonic
P0.3/IRQ0/CS0/PLACLK0/PLAI3
Type1
I/O
B2
P0.2/MOSI0/PLACLK1/PLAI2
I/O
B3
P2.3/BM/PLAI10
I/O
B4
B5
B6
B7
B8
C1
SWCLK
RESET
VDAC1
VREF
AVDD
IOVDD1
I
I
AO
AO/AI
S
S
C2
P0.1/MISO0/COMOUT1/PLAI1
I/O
C3
P0.0/SCLK0/COMOUT0/PLAI0
I/O
C4
P1.0/SIN1/COMOUT2/PLAI4
I/O
C5
P2.2/POR/CLKOUT/SWO
I/O
C6
AIN14/COM3P/BUF0_VREF
AI/AO
C7
AIN2/PADC0P
AI
Description
Digital Input/Output Port 0.3 (P0.3).
External Interrupt 0 (IRQ0).
SPI0 Chip Select (CS0).
PLA Clock 0 (PLACLK0).
Input to PLA Element 3 (PLAI3).
Ball B1 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 0.2 (P0.2).
SPI0 Master Out, Slave In (MOSI0).
PLA Clock 1 (PLACLK1).
Input to PLA Element 2 (PLAI2).
Ball B2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 2.3 (P2.3). An internal pull-up resistor is enabled
at power-up on P2.3.
Boot Mode (BM). This pin determines the start-up sequence after every
reset.
Input to PLA Element 10 (PLAI10).
Serial Wire Debug Clock.
Reset Input (Active Low). An internal pull-up resistor is included with this pin.
Voltage DAC 1 Output.
0.92 V Reference with a 100 nF Capacitor.
3.3 V Analog Power Supply.
1.2 V/1.8 V GPIO Supply. If unused, IOVDD1 can be tied to DVDD_REG or
to DGND.
Digital Input/Output Port 0.1 (P0.1).
SPI 0 Master Input, Slave Output (MISO0).
Comparator 1 Output (COMOUT1)
Input to PLA Element 1 (PLAI1).
Ball C2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 0.0 (P0.0).
SPI 0 Clock (SCLK0).
Comparator 0 Output (COMOUT0).
Input to PLA Element 0 (PLAI0).
Ball C3 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 1.0 (P1.0).
UART Input 1 (SIN1).
Comparator 2 Output (COMOUT2).
Input to PLA Element 4 (PLAI4).
Ball C4 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 2.2 (P2.2).
Reset Output (POR). This pin function is an output, and it is the default.
Clock Output (CLKOUT).
Serial Wire Debug (SWD) Output (SWO).
Analog Input 14 (AIN14).
Comparator 3 Emitter Voltage (VE) Positive (COM3P).
Buffered Reference Voltage source (BUF0_VREF).
Analog Input 2 (AIN2).
PGA Channel 0 Positive (PADC0P).
Rev. 0 | Page 25 of 35
ADuCM410
Data Sheet
Pin No.
C8
Mnemonic
AIN4/PADC01N/VDAC0
Type1
AI
D1
DVDD_REG
AO
D2
D3
DGND
P1.2/SCL1/PWM0/PLAI6
S
I/O
D4
P1.3/SDA1/PWM1/PLAI7
I/O
D5
P1.1/SOUT1/COMOUT3/PLAI5
I/O
D6
AIN3/PADC1P
AI
D7
D8
AIN0
AIN10/COM1P
AI
AI
E1
E2
E3
IOVDD0
IOGND
P1.4/SCLK1/PWM2/PLAO10
S
S
I/O
E4
P1.7/IRQ1/CS1/PWM5/PLAO13
I/O
E5
VDAC8/P5.0
AO/I/O
E6
AIN12/COM2P
AI
E7
E8
AGND
AVDD_REG
S
AO
Description
Analog Input 4 (AIN4).
PGA Channel 0/PGA Channel 1 Negative (PADC01N).
Voltage DAC 0 Output (VDAC0).
1.1 V Digital Regulator Supply with 0.47 µF Decoupling Capacitor. Do not
use DVDD_REG to power external circuits.
Digital Ground.
Digital Input/Output Port 1.2 (P1.2).
I2C1 Serial Clock (SCL1).
PWM Output 0 (PWM0).
Input to PLA Element 6 (PLAI6).
Ball D3 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 1.3 (P1.3).
I2C1 Serial Data (SDA1).
PWM Output 1 (PWM1).
Input to PLA Element 7 (PLAI7).
Ball D4 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 1.1 (P1.1).
UART Channel 1 (UART1) Output (SOUT1).
Comparator 3 Output (COMOUT3)
Input to PLA Element 5 (PLAI5).
Ball D5 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Analog Input 3 (AIN3).
PGA Channel 1 Positive (PADC1P).
Analog Input 0.
Analog Input 10 (AIN10).
Comparator 1 VE Positive (COM1P).
3.3 V GPIO Supply.
Ground for Digital Inputs/Outputs.
Digital Input/Output Port 1.4 (P1.4).
SPI1 Clock (SCLK1).
PWM Output 2 (PWM2).
Output of PLA Element 10 (PLAO10).
Ball E3 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 1.7 (P1.7).
External Interrupt 1 (IRQ1).
SPI1 Chip Select (CS1).
PWM Output 5 (PWM5).
Output of PLA Element 13 (PLAO13).
Ball E4 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Voltage DAC 8 Output (VDAC8).
Digital Input/Output Port 5.0 (P5.0).
Analog Input 12 (AIN12).
Comparator 2 VE Positive (COM2P).
Analog Ground.
2.5 V Analog Regulator Supply with 0.47 µF Decoupling Capacitor. Do not
use AVDD_REG to power external circuits.
Rev. 0 | Page 26 of 35
Data Sheet
ADuCM410
Pin No.
F1
Mnemonic
P1.5/MISO1/PWM3/PLAO11
Type1
I/O
F2
P1.6/MOSI1/PWM4/PLAO12
I/O
F3
P0.7/IRQ4/SDA2/COMPDIN1/PLAO5
I/O
F4
P3.2/PRTADDR2/PWMTRIP/PLAI14
I/O
F5
VDAC9/P5.1
AO/I/O
F6
AIN8/COM0P
AI
F7
F8
ADCREFN
ADCREFP
AO/AI
AO/AI
G1
P0.4/SCL0/SIN0/PLAO2
I/O
G2
P0.5/SDA0/SOUT0/PLAO3
I/O
G3
P0.6/IRQ3/SCL2/COMPDIN0/PLAO4
I/O
G4
P3.1/PRTADDR1/PWMSYNC/PLAI13
I/O
G5
VDAC11/P5.3
AO/I/O
G6
AIN7/PADC23N/VDAC2
AI
G7
G8
AIN1
AIN9/COM0N
AI
AI
H1
IOGND
S
Description
Digital Input/Output Port 1.5 (P1.5).
SPI1 Master Input, Slave Output (MISO1).
PWM Output 3 (PWM3).
Output of PLA Element 11 (PLAO11).
Ball F1 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 1.6 (P1.6).
SPI1 Master Out, Slave Input (MOSI1).
PWM Output 4 (PWM4).
Output of PLA Element 12 (PLAO12).
Ball F2 is a multilevel voltage input/output with 3.3 V, 1.8 V, or 1.2 V
support. Note that 3.3 V is the default.
Digital Input/Output Port 0.7 (P0.7).
External Interrupt 4 (IRQ4).
I2C2 Serial Data (SDA2).
Comparator 1 Digital Input for Three-State (COMPDIN1).
Output of PLA Element 5 (PLAO5).
Digital Input/Output Port 3.2 (P3.2).
MDIO Port Address Bit 2 (PRTADDR2).
PWM Trip (PWMTRIP).
Input to PLA Element 14 (PLAI14).
Voltage DAC 9 Output (VDAC9).
Digital Input/Output Port 5.1 (P5.1).
Analog Input 8 (AIN8).
Comparator 0 VE Positive (COM0P).
Decoupling Capacitor Connection for ADC. Connect ADCREFN to AGND.
Decoupling Capacitor Connection for ADC Reference Buffer with 4.7 µF
Decoupling Capacitor.
Digital Input/Output Port 0.4 (P0.4).
I2C0 Serial Clock (SCL0).
UART0 Input (SIN0).
Output of PLA Element 2 (PLAO2).
Digital Input/Output Port 0.5 (P0.5).
I2C0 Serial Data (SDA0).
UART0 Output (SOUT0).
Output of PLA Element 3 (PLAO3).
Digital Input/Output Port 0.6 (P0.6).
External Interrupt 3 (IRQ3).
I2C2 Serial Clock (SCL2).
Comparator 0 Digital Input for Three-State (COMPDIN0).
Output of PLA Element 4 (PLAO4).
Digital Input/Output Port 3.1 (P3.1).
MDIO Port Address Bit 1 (PRTADDR1).
PWM Synchronization (PWMSYNC).
Input to PLA Element 13 (PLAI13).
Voltage DAC 11 Output (VDAC11).
Digital Input/Output Port 5.1 (P5.3).
Analog Input 7 (AIN7).
PGA Channel 2/PGA Channel 3 Negative (PADC23N).
Voltage DAC 2 Output (VDAC2).
Analog Input 1.
Analog Input 9 (AIN9).
Comparator 0 VE Negative (COM0N).
Ground for Digital Inputs/Outputs.
Rev. 0 | Page 27 of 35
ADuCM410
Data Sheet
Pin No.
H2
H3
Mnemonic
DVDD
P3.6/MDIO
Type1
S
I/O
H4
P3.5/MCK/SRDY1/PLAO27
I/O
H5
P3.0/PRTADDR0/SRDY0/PLAI12
I/O
H6
VDAC10/P5.2
AO/I/O
H7
H8
VDAC4
AIN13/COM2N
AO
AI
1
Description
1.8 V/3.3 V Digital Power Supply.
Digital Input/Output Port 3.6 (P3.6).
MDIO Slave Data (MDIO).
Digital Input/Output Port 3.5 (P3.5).
MDIO Slave Clock (MCK).
SPI1 Ready (SRDY1).
Output of PLA Element 27 (PLAO27).
Digital Input/Output Port 3.0 (P3.0).
MDIO Port Address Bit 0 (PRTADDR0).
SPI 0 Ready (SRDY0).
Input to PLA Element 12 (PLAI12).
Voltage DAC 10 Output (VDAC10).
Digital Input/Output Port 5.2 (P5.2).
Voltage DAC 4 Output.
Analog Input 13 (AIN13).
Comparator 2 VE Negative (COM2N).
S is supply, I/O is input/output, AO is analog output, I is digital input, and AI is analog input.
Rev. 0 | Page 28 of 35
Data Sheet
ADuCM410
THEORY OF OPERATION
The ADuCM410 is an on-chip system. The ADuCM410 is
mixed-signal microcontroller based on the Arm Cortex-M33
processor.
See the ADuCM410 hardware reference manual for full details
on the operation of the ADuCM410, including, but not limited
to, all register details and information about the various features
and operation of the power management unit, the Arm CortexM33 processor, the ADC circuit, the flash controller, and the
SPI, I2C, and UART interfaces.
Rev. 0 | Page 29 of 35
ADuCM410
Data Sheet
RMS NOISE RESOLUTION OF ADC
The rms noise specifications for the ADC with different ADC
digital filter settings are described in Table 14.
settings. Peak-to-peak effective bit results are shown in
parentheses. RMS bits are calculated as follows:
The internal 2.5 V reference was used for all measurements.
Input Range
log
RMS Noise
For gain = 1, single-ended measurements with VIN = 2 V was used.
For PGA gains ≥ 2, a differential input voltage was applied,
ensuring the PGA output to the ADC was always 2 V. For
example, for gain = 4, VIN = 500 mV.
Peak-to-peak bits are calculated as follows:
Input Range
log 2
6.6 × RMS Noise
Table 15 shows the rms and peak-to-peak effective number of
bits based on the noise results in Table 14 for various PGA gain
Table 14. ADC RMS Noise
Update Rate
(Hz)
2,000,000
50,000
20,000
5000
5000
Oversampling Ratio
(OSR)
1
8
32
16
8
Gain = 1
81.3
32.44
20.15
Not applicable
Not applicable
RMS Noise (μV), PGA Output Voltage = 2 V for All Settings
Gain = 2
Gain = 4
Gain = 6
Gain = 8
Gain = 10
Not applicable Not applicable Not applicable Not applicable Not applicable
30.8
17.4
11.9
7.5
5.2
Not applicable Not applicable Not applicable Not applicable Not applicable
13.4
10.0
11.5
9.96
10.78
15.8
11.47
12.7
10.6
11.4
Table 15. ADC Effective Bits, Based on RMS Noise (Peak-to-Peak Effective Bits in Parenthesis)
Update Rate (Hz)
2,000,000
50,000
20,000
5000
5000
Sinc3 OSR
1
8
32
16
8
Gain = 1
14.9 (12.18 p-p)
16 (13.5 p-p)
16 (14.19 p-p)
Not applicable
Not applicable
Gain = 2
Not applicable
15.3 (12.6 p-p)
Not applicable
16 (13.78 p-p)
16 (13.54 p-p)
Gain = 4
Not applicable
15.1 (12.4 p-p)
Not applicable
15.9 (13.2 p-p)
15.73 (13 p-p)
Rev. 0 | Page 30 of 35
Gain = 6
Not applicable
15.1 (12.37 p-p)
Not applicable
15.15 (12.4 p-p)
15 (12.27 p-p)
Gain = 8
Not applicable
15.3 (12.6 p-p)
Not applicable
14.9 (12.2 p-p)
14.85 (12.1 p-p)
Gain = 10
Not applicable
15.5 (12.8 p-p)
Not applicable
14.5 (11.8 p-p)
14.4 (11.7 p-p)
Data Sheet
ADuCM410
APPLICATIONS INFORMATION
POWER SUPPLIES
The ADuCM410 operational power supply voltage range is
2.85 V to 3.6 V for AVDD and IOVDD0.
IOVDD1 can be 1.2 V, 1.8 V, or the same as IOVDD0. The
DVDD range is 1.8 V to 3.6 V.
Separate analog (AVDD) and digital power supply pins
(IOVDD1 and DVDD) allow AVDD to be kept relatively free
of noisy digital signals often present in the system DVDD line.
In this mode, the ADuCM410 can also operate with split
supplies. That is, the device can use different voltage levels for
each supply (see Table 1). A typical split supply configuration is
shown in Figure 16.
DIGITAL SUPPLY
ADuCM410
AVDD
DVDD
0.1µF
10µF
REF
3.6
0.1µF
IOVDD1
DGND
AGND
IS A COMMON GROUND BETWEEN AGND AND DGND.
Figure 16. External Multiple Supply Connections
As an alternative to providing two separate power supplies, the
user can reduce noise on AVDD by placing a small series
resistor and/or ferrite bead between AVDD and DVDD, and
then decouple AVDD separately to ground. An example of this
configuration is shown in Figure 17. With this configuration,
other analog circuitry (such as op amps and voltage reference)
can be powered from the AVDD supply line as well.
BEAD
10µF
AVDD
DVDD
0.1µF
1.8V
10µF
0.1µF
DVDD MUST BE ABOVE
1.8V FOR AT LEAST 50ms
TO COMPLETE POR
TIME (Not to Scale)
Figure 18. DVDD Power-Up Requirements
25ms
DVDD
10µF
AVDD
2.85V
0.1µF
IOVDD0
0.1µF
LDO
50ms MIN
1.6
1.6V
ADuCM410
0.1µF
1.8
1.7
AVDD/DVDD (V)
3.3V
AFTER 50ms DVDD MUST
STAY ABOVE 1.7V INCLUDING
NOISE EXCURSIONS
GNDREF1
IOVDD1
AGND
1.6V
AFTER DVDD RISES
ABOVE 1.6V
(POR THRESHOLD),
AVDD MUST REACH
2.85V (min.) WITHIN 25ms.
OTHERWISE, RESET ADC
AND VDACs IN SOFTWARE 1.
1GND
REF IS A COMMON GROUND BETWEEN AGND AND DGND.
20321-012
DGND
Figure 17. External Single-Supply Connections
TIME
1DETAILS
IN HARDWARE REFERENCE MANUAL.
Figure 19. AVDD Power-Up Requirements
Rev. 0 | Page 31 of 35
20321-014
1GND
0.1µF
IOVDD0
GNDREF1
0.1µF
1.8V
10µF
DVDD (V)
0.1µF
POWER-UP REQUIREMENTS
20321-013
10µF
The analog and digital ground pins on the ADuCM410 must be
referenced to the same system ground reference point.
Figure 18 and Figure 19 show the power-up requirements for
DVDD and AVDD. Figure 20 shows the power-up requirement
for IOVDD0 if no external pull-up is applied to the
P2.3/BM/PLAI10 pin.
ANALOG SUPPLY
20321-011
3.3V
In both Figure 16 and Figure 17, a large value (10 μF) reservoir
capacitor is connected to DVDD, and a separate 10 μF
capacitor is connected to AVDD. In addition, local small value
(0.1 μF) capacitors are located at each AVDD, IOVDD0,
IOVDD1, and DVDD pin of the chip. Include all
recommended capacitors shown, and ensure that the smaller
capacitors are close to each supply pin with trace lengths as
short as possible. Connect the ground terminal of each of these
capacitors directly to the underlying ground plane.
ADuCM410
Data Sheet
25ms
There are three digital supply balls, IOVDD0, IOVDD1, and
DVDD. Decouple these balls with a 0.1 μF capacitor placed as
near as possible to each of the three balls and their associated
ground balls (DGND and AGND, respectively). In addition,
place a 10 μF capacitor near these balls. For DVDD, to improve
noise reduction, place a ferrite bead in series with a 10 μF
capacitor to DGND.
DVDD
IOVDD0
1.6V
Similarly, the analog supply pin (AVDD) requires a 0.1 μF
capacitor placed as near as possible to each ball and its associated
AGND ball. Also place a 10 μF capacitor near these balls.
TIME
20321-015
AVDD/DVDD (V)
2.85V
Figure 20. IOVDD0 Power-Up Requirement, No External Pull-Up
RECOMMENDED CIRCUIT AND COMPONENT
VALUES
Figure 21 shows a typical connection diagram for the ADuCM410.
Adequately decouple the supplies and regulators with
capacitors connected between the AVDD_REG, DVDD_REG,
and IOVDDx balls and their associated ground balls (AGND
and DGND). Table 12 and Table 13 indicate which ground
balls are paired with which supply balls.
The ADC reference requires a 4.7 μF capacitor be placed
between ADCREFP and ADCREFN and located as near as
possible to each ball. ADCREFN must be connected directly to
AGND. The ADuCM410 contains two internal regulators.
These regulators require external decoupling capacitors. The
DVDD_REG and AVDD_REG balls each require a 0.47 μF
capacitor to DGND and AGND, respectively. Take care in the
layout to ensure that currents flowing from the ground end of
each decoupling capacitor to its associated ground ball share as
little track as possible with other ground currents on the PCB.
Rev. 0 | Page 32 of 35
Data Sheet
ADuCM410
DGND
IOGND
IOGND
DVDD_REG
IOVDD1
IOVDD0
DVDD
0.47µF
IOVDD0
10kΩ
RESET
IOVDD0
10kΩ
ADuCM410
P2.3/BM/PLAI10
P1.0/SIN1/COMOUT2/PLAI4
SWCLK
RESET
0.47µF
AGND
ADCREFN
SWDIO
0.1µF
RESET
GND
SWDIO
Tx
SWCLK
Rx
NC
IOVDD0
AVDD
LT3022EMSE
VIN
IN
0.1µF
OUT
IOVDD1
10kΩ
10µF
PGND
0.1µF
0.1µF
AVDD
AGND ADJ/SENSE
0.1µF
ADP7104ARDZ-3.3
VIN
VIN
0.1µF
10µF
10µF
AVDD
VOUT
10kΩ
EN/UVLO
GND
10µF
10µF
PG
0.1µF
10µF
0.1µF
10µF
20321-016
INTERFACE BOARD CONNECTOR
4.7µF
VREF
ADCREFP
AVDD_REG
P1.1/SOUT1/COMOUT3/PLAI5
SENSE/ADJ
Figure 21. Recommended Circuit and Component Values (ADuCM410, LT3022EMSE, and ADP7104ARDZ-3.3)
Rev. 0 | Page 33 of 35
ADuCM410
Data Sheet
OUTLINE DIMENSIONS
A1 BALL
CORNER
5.10
5.00 SQ
4.90
9
8
7
6
5
3
4
2
A1 BALL
CORNER
1
A
B
C
4.00 REF
SQ
0.50
BSC
D
E
F
G
H
J
0.91
0.85
0.79
BOTTOM VIEW
0.50
REF
DETAIL A
SIDE VIEW
0.35
0.30
0.25
BALL DIAMETER
SEATING
PLANE
PKG-006068
0.69
0.64
0.59
DETAIL A
0.26
0.21
0.16
COPLANARITY
0.08
10-31-2018-A
TOP VIEW
COMPLIANT TO JEDEC STANDARDS MO-195-AB
Figure 22. 81-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-81-6)
Dimensions shown in millimeters
3.50
3.46 SQ
3.42
8
7
6
5
4
3
2
1
A
BALL A1
IDENTIFIER
B
C
2.80
REF
D
E
F
G
0.40
BSC
TOP VIEW
(BALL SIDE DOWN)
SEATING
PLANE
END VIEW
0.330
0.300
0.270
(BALL SIDE UP)
2.80 REF
COPLANARITY
0.05
0.300
0.260
0.220
0.230
0.200
0.170
Figure 23. 64-Ball Wafer Level Chip Scale Package [WLCSP]
(CB-64-2)
Dimensions shown in millimeters
Rev. 0 | Page 34 of 35
08-13-2019-B
0.560
0.500
0.440
H
BOTTOM VIEW
Data Sheet
ADuCM410
ORDERING GUIDE
Model1, 2
ADuCM410BBCZ
ADuCM410BBCZ-RL7
ADuCM410BCBZ-RL7
EVAL-ADUCM410QSPZ
EVAL-ADUCM410QSP1Z
1
2
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Package Description
81-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
81-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
64-Ball Wafer Level Chip Scale Package [WLCSP]
BGA Evaluation Board and Quick Start Development System
WLCSP Evaluation Board and Quick Start Development System
Z = RoHS Compliant Part.
CSP_BGA package uses ultralow alpha (ULA) molding compounds.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D20321-9/20(0)
Rev. 0 | Page 35 of 35
Package Option
BC-81-6
BC-81-6
CB-64-2
工商网监
湘ICP备2023018690号
