AD9684BBPZRL7-500

14-Bit, 500 MSPS LVDS, Dual Analog-to-Digital Converter AD9684 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, MC-GSM, LTE General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Radar Digital oscilloscopes High speed data acquisition systems DOCSIS CMTS upstream receiver paths HFC digital reverse path receivers Rev. 0 AVDD1 (1.25V) AVDD2 (2.5V) AVDD3 (3.3V) DRVDD (1.25V) DVDD (1.25V) SPIVDD (1.8V TO 3.4V) BUFFER VIN+A SIGNAL MONITOR FD_B DIGITAL DOWNCONVERTER BUFFER VIN+B VIN–B ADC CORE D0± D1± D2± D3± D4± D5± D6± D7± D8± D9± D10± D11± D12± D13± DCO± STATUS± 14 CONTROL REGISTERS FAST DETECT V_1P0 SIGNAL MONITOR CLOCK GENERATION CLK+ CLK– 16 LVDS/SYNC CONTROL FD_A LVDS OUTPUT STAGING DIGITAL DOWNCONVERTER LVDS OUTPUTS 14 ADC CORE VIN–A FAST DETECT SYNC+ SYNC– SPI CONTROL ÷2 ÷4 AD9684 PDWN/ STBY ÷8 AGND DRGND DGND SDIO SCLK CSB 13015-001 Parallel LVDS (DDR) outputs 1.1 W total power per channel at 500 MSPS (default settings) SFDR = 85 dBFS at 170 MHz fIN (500 MSPS) SNR = 68.6 dBFS at 170 MHz fIN (500 MSPS) ENOB = 10.9 bits at 170 MHz fIN DNL = ±0.5 LSB INL = ±2.5 LSB Noise density = −153 dBFS/Hz at 500 MSPS 1.25 V, 2.50 V, and 3.3 V supply operation No missing codes Internal analog-to-digital converter (ADC) voltage reference Flexible input range and termination impedance 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal) 400 Ω, 200 Ω, 100 Ω, and 50 Ω differential SYNC± input allows multichip synchronization DDR LVDS (ANSI-644 levels) outputs 2 GHz usable analog input full power bandwidth >96 dB channel isolation/crosstalk Amplitude detect bits for efficient AGC implementation Two integrated wideband digital processors per channel 12-bit numerically controlled oscillator (NCO) 3 cascaded half-band filters Differential clock inputs Serial port control Integer clock divide by 2, 4, or 8 Small signal dither Figure 1. GENERAL DESCRIPTION The AD9684 is a dual, 14-bit, 500 MSPS ADC. The device has an on-chip buffer and a sample-and-hold circuit designed for low power, small size, and ease of use. This product is designed for sampling wide bandwidth analog signals. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package. The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth buffered inputs, supporting a variety of user selectable input ranges. An integrated voltage reference eases design considerations. Each ADC data output is internally connected to an optional decimate by 2 block. The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and three half-band decimation filters supporting a divide by factor of two, four, and eight. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9684 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 DDC I/Q Output Selection ....................................................... 31 Applications ....................................................................................... 1 DDC General Description ........................................................ 31 Functional Block Diagram .............................................................. 1 Frequency Translation ................................................................... 37 General Description ......................................................................... 1 General Description ................................................................... 37 Revision History ............................................................................... 2 DDC NCO Plus Mixer Loss and SFDR ................................... 38 Product Highlights ........................................................................... 3 Numerically Controlled Oscillator .......................................... 38 Specifications..................................................................................... 4 FIR Filters ........................................................................................ 40 DC Specifications ......................................................................... 4 General Description ................................................................... 40 AC Specifications.......................................................................... 5 Half-Band Filters ........................................................................ 41 Digital Specifications ................................................................... 6 DDC Gain Stage ......................................................................... 42 Switching Specifications .............................................................. 7 DDC Complex to Real Conversion Block............................... 42 Timing Specifications .................................................................. 8 DDC Example Configurations ................................................. 43 Absolute Maximum Ratings .......................................................... 16 Digital Outputs ............................................................................... 47 Thermal Characteristics ............................................................ 16 Digital Outputs ........................................................................... 47 ESD Caution ................................................................................ 16 ADC Overrange .......................................................................... 47 Pin Configuration and Function Descriptions ........................... 17 Multichip Synchronization............................................................ 48 Typical Performance Characteristics ........................................... 19 SYNC± Setup and Hold Window Monitor ............................. 49 Equivalent Circuits ......................................................................... 22 Test Modes ....................................................................................... 51 Theory of Operation ...................................................................... 24 ADC Test Modes ........................................................................ 51 ADC Architecture ...................................................................... 24 Serial Port Interface (SPI) .............................................................. 52 Analog Input Considerations.................................................... 24 Configuration Using the SPI ..................................................... 52 Voltage Reference ....................................................................... 26 Hardware Interface ..................................................................... 52 Clock Input Considerations ...................................................... 27 SPI Accessible Features .............................................................. 52 Power-Down/Standby Mode..................................................... 28 Memory Map .................................................................................. 53 Temperature Diode .................................................................... 28 Reading the Memory Map Register Table............................... 53 ADC Overrange and Fast Detect .................................................. 29 Memory Map Register Table ..................................................... 54 ADC Overrange .......................................................................... 29 Applications Information .............................................................. 63 Fast Threshold Detection (FD_A and FD_B) ........................ 29 Power Supply Recommendations............................................. 63 Signal Monitor ................................................................................ 30 Outline Dimensions ....................................................................... 64 Digital Downconverters (DDCs).................................................. 31 Ordering Guide .......................................................................... 64 DDC I/Q Input Selection .......................................................... 31 REVISION HISTORY 5/15—Revision 0: Initial Version Rev. 0 | Page 2 of 64 Data Sheet AD9684 The AD9684 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly reduce the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9684 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal that the ADC digitized. The dual ADC output data is routed directly to the one external, 14-bit LVDS output port, supporting double data rate (DDR) formatting. An external data clock and status bit are offered for data capture flexibility. The LVDS outputs have several configurations, depending on the acceptable rate of the receiving logic device and the sampling rate of the ADC. Multiple device synchronization is supported through the SYNC± input pins. The AD9684 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.4 V capable 3-wire serial port interface (SPI). The AD9684 is available in a Pb-free, 196-ball ball grid array (BGA) and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. 6. 7. Rev. 0 | Page 3 of 64 Wide full power bandwidth supports intermediate frequency (IF) sampling of signals up to 2 GHz. Buffered inputs with programmable input termination ease filter design and implementation. Four integrated wideband decimation filters and NCO blocks supporting multiband receivers. Flexible SPI controls various product features and functions to meet specific system requirements. Programmable fast overrange detection and signal monitoring. SYNC± input allows synchronization of multiple devices. 12 mm × 12 mm, 196-ball BGA_ED. AD9684 Data Sheet SPECIFICATIONS DC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (500 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage Range (Programmable) Common-Mode Voltage (VCM) Differential Input Capacitance 1 Analog Input Full Power Bandwidth POWER SUPPLY AVDD1 AVDD2 AVDD3 DVDD DRVDD SPIVDD IAVDD1 IAVDD2 IAVDD3 IDVDD IDRVDD ISPIVDD POWER CONSUMPTION Total Power Dissipation 2 Power-Down Dissipation Standby 1 2 Temperature Full Full Full Full Full Full Full Full Min 14 −0.3 −6.5 −0.6 −4.5 Typ Max Unit Bits Guaranteed 0 0 0 0 ±0.5 ±2.5 +0.3 +0.3 +6.5 +5.0 +0.7 +5.0 % FSR % FSR % FSR % FSR LSB LSB 25°C 25°C Full ±3 −39 1.0 ppm/°C ppm/°C V 25°C 2.63 LSB rms Full 25°C 25°C 25°C 1.46 2.06 2.05 1.5 2 2.06 V p-p V pF GHz Full Full Full Full Full Full Full Full Full Full Full Full 1.22 2.44 3.2 1.22 1.22 1.22 1.25 2.50 3.3 1.25 1.25 1.8 448 396 103 108 106 2 1.28 2.56 3.4 1.28 1.28 3.4 503 455 124 127 119 6 V V V V V V mA mA mA mA mA mA Full Full Full Differential capacitance is measured between the VIN+x and VIN−x pins (x = A or B). Parallel interleaved LVDS mode. The power dissipation on DRVDD changes with the output data mode used. Rev. 0 | Page 4 of 64 2.2 710 1.0 W mW W Data Sheet AD9684 AC SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (500 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted. Table 2. Parameter 1 ANALOG INPUT FULL SCALE NOISE DENSITY 2 SIGNAL-TO-NOISE RATIO (SNR) 3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz SIGNAL-TO-NOISE RATIO AND DISTORTION RATIO (SINAD)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR)3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz WORST HARMONIC, SECOND OR THIRD3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz Temperature Full Full 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C Rev. 0 | Page 5 of 64 Min 67.5 67 10.8 76 Typ 2.06 −153 Max Unit V p-p dBFS/Hz 69.2 68.6 68.4 68.0 64.4 63.8 60.5 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 68.7 68.5 67.6 67.2 63.8 62.5 58.3 dBFS dBFS dBFS dBFS dBFS dBFS dBFS 11.1 10.9 10.8 10.8 10.3 10.1 9.5 Bits Bits Bits Bits Bits Bits Bits 83 85 82 86 81 76 69 dBFS dBFS dBFS dBFS dBFS dBFS dBFS −83 −85 −82 −86 −81 −76 −69 −76 dBFS dBFS dBFS dBFS dBFS dBFS dBFS AD9684 Data Sheet Parameter 1 WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC3 fIN = 10 MHz fIN = 170 MHz fIN = 340 MHz fIN = 450 MHz fIN = 765 MHz fIN = 985 MHz fIN = 1950 MHz TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7 dBFS fIN1 = 185 MHz, fIN2 = 188 MHz fIN1 = 338 MHz, fIN2 = 341 MHz CROSSTALK 4 FULL POWER BANDWIDTH Temperature Min Typ 25°C Full 25°C 25°C 25°C 25°C 25°C −93 −92 −90 −92 −89 −89 −85 25°C 25°C 25°C 25°C −88 −87 96 2 Max −76 Unit dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dB GHz See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Noise density is measured at a low analog input frequency (30 MHz). See Table 9 for the recommended settings for full-scale voltage and buffer current control. 4 Crosstalk is measured at 170 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel. 1 2 3 DIGITAL SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate (500 MSPS), 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted. Table 3. Parameter CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance SYNC INPUTS (SYNC+, SYNC−) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance (Differential) LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance LOGIC OUTPUT (SDIO) Logic Compliance Logic 1 Voltage (IOH = 800 µA) Logic 0 Voltage (IOL = 50 µA) LOGIC OUTPUTS (FD_A, FD_B) Logic Compliance Logic 1 Voltage Logic 0 Voltage Input Resistance Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Min 600 Rev. 0 | Page 6 of 64 LVDS/LVPECL 1200 0.85 35 Max Unit 1800 mV p-p V kΩ pF 2.5 400 0.6 LVDS/LVPECL 1200 0.85 35 1800 2.0 2.5 0 Full Full Full Full Full Full Full Typ 0.8 0 mV p-p V kΩ pF CMOS 0.8 × SPIVDD 0.2 × SPIVDD 30 V V kΩ CMOS 0.8 × SPIVDD 0.2 × SPIVDD V V CMOS SPIVDD 0 30 V V kΩ Data Sheet Parameter DIGITAL OUTPUTS (Dx±, 1 DCO±, STATUS±) Logic Compliance Differential Output Voltage Output Common-Mode Voltage (VCM) AC-Coupled Short-Circuit Current (IDSHORT) Differential Return Loss (RLDIFF) 2 Common-Mode Return Loss (RLCM) 2 Differential Termination Impedance 1 2 AD9684 Temperature Min Full Full 25°C 25°C 25°C 25°C Full Typ Max Unit 230 430 mV p-p 0 −100 8 6 80 1.8 +100 V mA dB dB Ω LVDS 100 120 Where x = 0 to 13. Differential and common-mode return loss is measured from 100 MHz to 0.75 MHz × baud rate. SWITCHING SPECIFICATIONS AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate, 1.7 V p-p full-scale differential input, 1.0 V internal reference, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted. Table 4. Parameter CLOCK Clock Rate (at CLK+/CLK− Pins) Maximum Sample Rate 1 Minimum Sample Rate 2 Clock Pulse Width High Low LVDS DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) 3 DCO± Propagation Delay (tDCO)3 DCO± to Data Skew Rising Edge Data (tSKEWR)3 Falling Edge Data (tSKEWF)3 STATUS± Propagation Delay (tSTATUS) 4 DCO± to STATUS± Skew (tFRAME)4 Data Propagation Delay (tPD)3 DCO± Propagation Delay (tDCO)3 LATENCY 5 Pipeline Latency Fast Detect Latency HB1 Filter Latency3 HB1 + HB2 Filter Latency3 HB1 + HB2 + HB3 Filter Latency3 HB1 + HB2 + HB3 + HB4 Filter Latency3 Fast Detect Latency Wake-Up Time 6 Standby Power-Down Temperature Min Full Full Full 0.25 500 250 Full Full 1000 1000 Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C Rev. 0 | Page 7 of 64 Typ Max Unit 4 GHz MSPS MSPS ps ps 2.225 2.2 −150 850 −150 −25 1.025 2.2 −25 2.225 2.2 ns ns +100 1100 +100 35 28 50 101 217 433 28 1 4 ps ps ns ps ns ns Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles Clock cycles ms ms AD9684 Data Sheet Parameter APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tj) Out of Range Recovery Time Temperature Min Typ Full Full Full Max Unit 530 55 1 ps fs rms Clock Cycles The maximum sample rate is the clock rate after the divider. The minimum sample rate operates at 300 MSPS. This specification is valid for parallel interleaved, channel multiplexed, and byte mode output modes. 4 This specification is valid for byte mode output mode only. 5 No DDCs used. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode or standby mode. 1 2 3 TIMING SPECIFICATIONS Table 5. Parameter CLK± to SYNC± TIMING REQUIREMENTS tSU_SR tH_SR SPI TIMING REQUIREMENTS tDS tDH tCLK tS tH tHIGH tLOW tEN_SDIO Description See Figure 2 Device clock to SYNC± setup time Device clock to SYNC± hold time See Figure 3 Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the SCLK Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK must be in a logic high state Minimum period that SCLK must be in a logic low state Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 3) Time required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 3) tDIS_SDIO Min Typ Max 117 −96 Unit ps ps 2 2 40 2 2 10 10 10 ns ns ns ns ns ns ns ns 10 ns Timing Diagrams CLK– CLK+ tSU_SR tH_SR 13015-002 SYNC– SYNC+ Figure 2. SYNC± Setup and Hold Timing tHIGH tDS tS tCLK tDH tH tLOW CSB SCLK DON’T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 D5 Figure 3. Serial Port Interface Timing Diagram Rev. 0 | Page 8 of 64 D4 D3 D2 D1 D0 DON’T CARE 13015-003 SDIO DON’T CARE DON’T CARE Data Sheet AD9684 APERTURE DELAY N + 35 N VIN±x N + 39 N + 36 N + 40 N–1 N+x N + 37 N+y N + 38 N + 41 SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET SYNC+ SYNC– CLK+ CLK– tCLK FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE CONSTANT LATENCY = X CLK CYCLES tDCO tPD DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 90° PHASE ADJUST 1 DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 270° PHASE ADJUST 2 tSKEWF tSKEWR CONVERTER 0 CONVERTER 0 CONVERTER 0 CONVERTER 0 CONVERTER 0 SAMPLE SAMPLE SAMPLE SAMPLE SAMPLE [N] [N + 1] [N + 2] [N + 3] [N + 4] STATUS+ (OVERRANGE/STATUS BIT) STATUS STATUS STATUS STATUS STATUS STATUS STATUS D13± D13 D13 D13 D13 D13 D13 D13 D0± D0 D0 D0 D0 D0 D0 D0 190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. 2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. Figure 4. Parallel Interleaved Mode—One Converter, ≤14-Bit Data Rev. 0 | Page 9 of 64 13015-004 STATUS– AD9684 Data Sheet APERTURE DELAY N + 36 N VIN±x N + 38 N+x N + 37 SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET SYNC+ SYNC– CLK+ CLK– CONSTANT LATENCY = X CLK CYCLES tDCO tCLK tPD DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST tSKEWR STATUS BIT SELECTED BY REGISTER 0x559, BITS[2:0] IN THE REGISTER MAP STATUS+ (OVERRANGE/STATUS BIT) tSKEWF CONVERTER 0 SAMPLE [N] CONVERTER 1 SAMPLE [N] CONVERTER 0 SAMPLE [N + 1] CONVERTER 1 SAMPLE [N + 1] CONVERTER 0 SAMPLE [N + 2] STATUS STATUS STATUS STATUS STATUS STATUS STATUS STATUS D13± D13 D13 D13 D13 D13 D13 D13 D13 D0± D0 D0 D0 D0 D0 D0 D0 D0 Figure 5. Parallel Interleaved Mode—Two Converters, ≤14-Bit Data, Output Sample Rate < 625 MSPS Rev. 0 | Page 10 of 64 13015-005 STATUS– Data Sheet AD9684 APERTURE DELAY N + 36 N VIN±x N + 38 N+x N + 37 SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET SYNC+ SYNC– CLK+ CLK– CONSTANT LATENCY = X CLK CYCLES tDCO tPD tCLK DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST tSKEWR STATUS BIT SELECTED BY REGISTER 0x559, BITS[2:0] IN THE REGISTER MAP STATUS+ (OVERRANGE/STAUS BIT) STATUS– STATUS STATUS S[N – y] (ODD BITS) S[N – x] (EVEN BITS) STATUS tSKEWF CONVERTERS SAMPLE [N] CONVERTERS SAMPLE [N] CONVERTERS SAMPLE [N + 1] CONVERTERS SAMPLE [N + 1] CONVERTERS SAMPLE [N + 2] STATUS STATUS STATUS STATUS STATUS S[N] (ODD BITS) S[N + 1] (EVEN BITS) S[N + 1] (ODD BITS) S[N + 2] (EVEN BITS) S[N] S[N – 1] (ODD BITS) (EVEN BITS) CHANNEL A D0±/D1± Figure 6. Channel Multiplexed (Even/Odd) Mode—One Converter, ≤14-Bit Data Rev. 0 | Page 11 of 64 13015-006 CHANNEL A D12±/D13± AD9684 Data Sheet APERTURE DELAY N + 36 N VIN±x N + 38 N+x N + 37 SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET SYNC+ SYNC– CLK+ CLK– tCLK CONSTANT LATENCY = X CLK CYCLES tDCO tPD DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST tSKEWR STATUS BIT SELECTED BY REGISTER 0x559, BITS[2:0] IN THE REGISTER MAP STATUS+ (OVERRANGE/STATUS BIT) STATUS– STATUS tSKEWF CONVERTERS SAMPLE [N] CONVERTERS SAMPLE [N] CONVERTERS SAMPLE [N + 1] CONVERTERS SAMPLE [N + 1] CONVERTERS SAMPLE [N + 2] STATUS STATUS STATUS STATUS STATUS STATUS STATUS S[N – y] (ODD BITS) S[N – x] (EVEN BITS) S[N] S[N – 1] (ODD BITS) (EVEN BITS) S[N] (ODD BITS) S[N + 1] (EVEN BITS) S[N + 1] (ODD BITS) S[N + 2] (EVEN BITS) S[N – y] (ODD BITS) S[N – x] (EVEN BITS) S[N] S[N – 1] (ODD BITS) (EVEN BITS) S[N] (ODD BITS) S[N + 1] (EVEN BITS) S[N + 1] (ODD BITS) S[N + 2] (EVEN BITS) CHANNEL A D12±/D13± CHANNEL B D12±/D13± CHANNEL B D0±/D1± Figure 7. Channel Multiplexed (Even/Odd) Mode—Two Converters, ≤14-Bit Data, Output Sample Rate < 625 MSPS Rev. 0 | Page 12 of 64 13015-007 CHANNEL A D0±/D1± Data Sheet AD9684 APERTURE DELAY N+z N VIN±x N–1 N + 39 N + 36 N + 40 N + 42 N+x N + 37 N + 38 N+y N + 41 SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET SYNC+ SYNC– CLK+ CLK– tCLK FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE CONSTANT LATENCY = X CLK CYCLES tDCO tPD tSTATUS DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 90° PHASE ADJUST 1 DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 270° PHASE ADJUST 2 tFRAME STATUS– (FRAME CLOCK OUTPUT)3 FRAME 0 STAUS+ STATUS+ (OVERRANGE STATUS BIT) FRAME 1 tSKEWF tSKEWR I0[N] EVEN I0[N] ODD Q 0[N] EVEN Q 0[N] ODD I0[N + 1] EVEN I0[N + 1] Q 0[N + 1] Q 0[N + 1] ODD EVEN ODD PAR 4 PAR STATUS PAR STATUS PAR STATUS PAR STATUS PAR D7± D15 D15 D14 D15 D14 D15 D14 D15 D14 D15 D0± D1 D1 D0 D1 D0 D1 D0 D1 D0 D1 STATUS– 1) ENABLED (ALWAYS ON). 2) DISABLED (ALWAYS OFF). 3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDO-RANDOM BIT). 4STATUS BIT SELECTED BY REGISTER 0x559, BITS[2:0] IN THE REGISTER MAP. Figure 8. LVDS Byte Mode—Two Virtual Converters, One DDC, I/Q Data Decimate by 4 Rev. 0 | Page 13 of 64 13015-008 190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. 2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. 3FRAME CLOCK OUTPUT SUPPORTS 3 MODES OF OPERATION: Rev. 0 | Page 14 of 64 D1 D0± N+y N+z N + 36 N + 37 N + 38 N + 39 N + 40 N + 41 N + 42 tPD tSTATUS Figure 9. LVDS Byte Mode—Four Virtual Converters, Two DDCs, ≤16-Bit Data, I/Q Data Decimate by 8 D0 D14 STATUS D1 D15 PAR D0 D14 STATUS Q0[N] EVEN tSKEWF I0[N] ODD D1 D15 PAR Q0[N] ODD D0 D14 STATUS I1[N + 1] EVEN FRAME 0 FRAME 0 D1 D15 PAR I1[N] ODD D0 D14 STATUS Q1[N] EVEN FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE I0[N] EVEN 1) ENABLED (ALWAYS ON). 2) DISABLED (ALWAYS OFF). 3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDO-RANDOM BIT). 4STATUS BIT SELECTED BY REGISTER 0x559, BITS[2:0] IN THE REGISTER MAP. D1 D15 PAR tSKEWR tFRAME CONSTANT LATENCY = X CLK CYCLES tDCO D1 D15 PAR Q1[N] ODD D0 D14 STATUS I0[N+1] EVEN D1 D15 PAR I0[N+1] ODD D0 D14 STATUS Q0[N+1] EVEN D1 D15 PAR Q0[N+1] ODD D0 D14 STATUS I1[N + 1] EVEN D1 D15 PAR I1[N+1] ODD FRAME 1 FRAME 1 SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET N+x APERTURE DELAY 190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. 2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. 3FRAME CLOCK OUTPUT SUPPORTS 3 MODES OF OPERATION: D15 PAR4 tCLK N–1 D7± STATUS– STATUS+ (OVERRANGE STATUS BIT) STATUS+ STATUS– (FRAME CLOCK OUTPUT)3 DCO± (DATA CLOCK OUTPUT) 270° PHASE ADJUST 2 DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 90° PHASE ADJUST 1 DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST CLK– CLK+ SYNC– SYNC+ VIN±x N D0 D14 STATUS Q1[N+1] EVEN D1 D15 PAR Q1[N+1] ODD AD9684 Data Sheet 13015-010 Rev. 0 | Page 15 of 64 D1 D0± N+2 N+3 N+4 N+5 N+6 N+7 N+8 N + 10 D1 D15 D14 D0 PAR STATUS CONSTANT LATENCY = X CLK CYCLES D0 D14 STATUS I0[N] EVEN D1 D15 PAR I0[N] ODD D0 D14 STATUS Q0[N] EVEN D1 D15 PAR D0 D14 STATUS Q0[N] I1[N] ODD EVEN D1 D15 PAR I1[N] ODD FIXED DELAY FROM SYNC EVENT TO DCO KNOWN PHASE D0 D14 STATUS Q1[N] EVEN CLOCK OUTPUT SUPPORTS 3 MODES OF OPERATION: 1) ENABLED (ALWAYS ON). 2) DISABLED (ALWAYS OFF). 3) GAPPED PERIODIC (CONDITIONALLY ENABLED BASED ON PSEUDO-RANDOM BIT). 4STATUS BIT SELECTED BY REGISTER 0x559, BITS[2:0] IN THE REGISTER MAP. 3FRAME N+9 D1 D15 PAR D0 D14 STATUS Q1[N] I2[N] ODD EVEN FRAME 0 D1 D15 PAR I2[N] ODD D0 D14 STATUS Q2[N] EVEN D1 D15 PAR D0 D14 STATUS Q2[N] I3[N] ODD EVEN D1 D15 PAR I0[N] ODD D0 D14 STATUS Q3[N] EVEN D1 D15 PAR D0 D14 STATUS D1 D15 PAR D0 D14 STATUS D1 D15 PAR D0 D14 STATUS D1 D15 PAR D0 D14 STATUS D1 D15 PAR D0 D14 STATUS D1 D15 PAR D0 D14 STATUS D1 D15 PAR D0 D14 STATUS D1 D15 PAR D0 D14 STATUS D1 D15 PAR Q3[N] I0[N+1] I0[N+1] Q0[N+1]Q0[N+1] I1[N+1] I1[N+1] Q1[N+1]Q1[N+1] I2[N+1] I2[N+1] Q2[N+1]Q2[N+1] I3[N+1] I3[N+1] Q3[N+1]Q3[N+1] ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD EVEN ODD FRAME 1 SYNCHRONOUS LOW TO HIGH TRANSITIONS OF THE SYNC SIGNAL CAPTURED ON THE RISING EDGE OF THE CLK SIGNAL CAUSES THE DCO INTERNAL DIVIDER TO BE RESET N+1 APERTURE DELAY 190° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. 2270° PHASE ADJUST IS GENERATED USING THE FALLING EDGE OF CLK±. D15 PAR4 D7± STATUS+ (STATUS BIT) STATUS– STATUS+ (FRAME CLOCK OUTPUT)3 DCO± (DATA CLOCK OUTPUT) 270° PHASE ADJUST2 DCO± (DATA CLOCK OUTPUT) 180° PHASE ADJUST DCO± (DATA CLOCK OUTPUT) 90° PHASE ADJUST1 DCO± (DATA CLOCK OUTPUT) 0° PHASE ADJUST CLK+ (ENCODE CLOCK) SYNC+ (SYSTEM REFERENCE) VIN±x N 13015-011 N–1 Data Sheet AD9684 Figure 10. LVDS Byte Mode—Eight Virtual Converters, Four DDCs, ≤16-Bit Data, I/Q Data Decimate by 16 AD9684 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS Table 6. Parameter Electrical AVDD1 to AGND AVDD2 to AGND AVDD3 to AGND DVDD to DGND DRVDD to DRGND SPIVDD to AGND AGND to DRGND VIN±x to AGND SCLK, SDIO, CSB to AGND VIN±x Maximum Swing PDWN/STBY to AGND Environmental Operating Temperature Range (TCASE) Maximum Junction Temperature Storage Temperature Range (Ambient) Rating Typical θJA, θJB, and θJC are specified vs. the number of printed circuit board (PCB) layers in different airflow velocities (in m/sec). Airflow increases heat dissipation effectively reducing θJA and θJB. The use of appropriate thermal management techniques is recommended to ensure that the maximum junction temperature does not exceed the limits shown in Table 7. 1.32 V 2.75 V 3.63 V 1.32 V 1.32 V 3.63 V −0.3 V to +0.3 V 3.2 V −0.3 V to SPIVDD + 0.3 V 4.3 V p-p −0.3 V to SPIVDD + 0.3 V PCB Type JEDEC 2s2p Board −40°C to +85°C 10-Layer PCB 125°C −65°C to +150°C Table 7. Simulated Thermal Data Airflow Velocity (m/sec) 0.0 1.0 2.5 0.0 1.0 2.5 θJB 6.31, 3 5.91, 3 5.71, 3 4.6 4.6 4.6 θJC_TOP 4.71, 5 N/A4 N/A4 4.7 N/A4 N/A4 θJC_BOT 1.21, 5 N/A4 N/A4 1.2 N/A4 N/A4 Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per JEDEC JESD51-8 (still air). 4 N/A means not applicable. 5 Per MIL-STD 883, Method 1012.1. 1 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. θJA 17.81, 2 15.61, 2 15.01, 2 13.8 12.7 12.0 ESD CAUTION Rev. 0 | Page 16 of 64 Unit °C/W °C/W °C/W °C/W °C/W °C/W Data Sheet AD9684 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A AGND AGND AGND AVDD2 AVDD1 AGND CLK+ CLK– AGND AVDD1 AVDD2 AGND AGND AGND A B AVDD3 AGND AGND AVDD2 AVDD1 AGND AGND AGND AGND AVDD1 AVDD2 AGND AGND AVDD3 B C AVDD3 AGND AGND AVDD2 AVDD1 AGND SYNC+ SYNC– AGND AVDD1 AVDD2 AGND AGND AVDD3 C D AGND AGND AGND AVDD2 AVDD1 AGND AVDD1 AGND AGND AVDD1 AVDD2 AGND AGND AGND D E VIN–B AGND AGND AVDD2 AVDD1 AGND AGND AGND AGND AVDD1 AVDD2 AGND AGND VIN–A E F VIN+B AGND AGND AVDD2 AGND AGND AGND AGND AGND AGND AVDD2 AGND AGND VIN+A F G AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AVDD2 AGND AGND AGND G H AGND AGND AGND CSB AGND AGND AGND AGND AGND V_1P0 AGND AGND AGND AGND H J FD_B AGND AGND SCLK SPIVDD AGND AGND AGND AGND AVDD2 SPIVDD AGND PDWN/STBY FD_A J K DGND DGND AGND SDIO AGND AGND AGND AGND AGND AGND AGND AGND DCO– DCO+ K L DVDD DVDD DGND DGND AGND AGND AGND AGND AGND AGND AGND AGND STATUS– STATUS+ L M D1+ D1– DVDD DVDD DRVDD DRVDD DRVDD DRGND DRGND DRGND DRGND DRGND D13– D13+ M N D2– D3– D4– D5– D6– D0– DRVDD DRGND D7– D8– D9– D10– D11– D12– N P D2+ D3+ D4+ D5+ D6+ D0+ DRVDD DRGND D7+ D8+ D9+ D10+ D11+ D12+ P 1 2 3 4 5 7 8 9 10 11 12 13 14 6 13015-012 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 11. Pin Configuration (Top View) Table 8. Pin Function Descriptions Pin No. Power Supplies A5, A10, B5, B10, C5, C10, D5, D7, D10, E5, E10 A4, A11, B4, B11, C4, C11, D4, D11, E4, E11, F4, F11, G11, J10 B1, B14, C1, C14 L1, L2, M3, M4 M5, M6, M7, N7, P7 J5, J11 K1, K2, L3, L4 M8 to M12, N8, P8 A1, A2, A3, A6, A9, A12, A13, A14, B2, B3, B6, B7, B8, B9, B12, B13, C2, C3, C6, C9, C12, C13, D1, D2, D3, D6, D8, D9, D12, D13, D14, E2, E3, E6 to E9, E12, E13, F2, F3, F5 to F10, F12, F13, G1 to G10, G12, G13, G14, H1, H2, H3, H5 to H9, H11 to H14, J2, J3, J6 to J9, J12, K3, K5 to K12, L5 to L12 Analog E14, F14 E1, F1 H10 A7, A8 Mnemonic Type Description AVDD1 Supply Analog Power Supply (1.25 V Nominal). AVDD2 Supply Analog Power Supply (2.50 V Nominal). AVDD3 DVDD DRVDD SPIVDD DGND DRGND AGND Supply Supply Supply Supply Ground Ground Ground Analog Power Supply (3.3 V Nominal) Digital Power Supply (1.25 V Nominal). Digital Driver Power Supply (1.25 V Nominal). Digital Power Supply for SPI (1.8 V to 3.4 V). Ground Reference for DVDD. Ground Reference for DRVDD. Ground Reference for AVDD. VIN−A, VIN+A VIN−B, VIN+B V_1P0 Input Input Input/DNC CLK+, CLK− Input ADC A Analog Input Complement/True. ADC B Analog Input Complement/True. 1.0 V Reference Voltage Input/Do Not Connect. This pin is configurable through the SPI as a no connect or as an input. Do not connect this pin if using the internal reference. This pin requires a 1.0 V reference voltage input if using an external voltage reference source. Clock Input True/Complement. Rev. 0 | Page 17 of 64 AD9684 Pin No. CMOS Outputs J14, J1 Digital Inputs C7, C8 Data Outputs N6, P6 M1, M2 N1, P1 N2, P2 N3, P3 N4, P4 N5, P5 N9, P9 N10, P10 N11, P11 N12, P12 N13, P13 N14, P14 M13, M14 L13, L14 K13, K14 SPI Controls K4 J4 H4 J13 Data Sheet Mnemonic Type Description FD_A, FD_B Output Fast Detect Outputs for Channel A and Channel B. SYNC+, SYNC− Input Active High LVDS SYNC Input—True/Complement. D0−, D0+ D1+, D1− D2−, D2+ D3−, D3+ D4−, D4+ D5−, D5+ D6−, D6+ D7−, D7+ D8−, D8+ D9−, D9+ D10−, D10+ D11−, D11+ D12−, D12+ D13−, D13+ STATUS−, STATUS+ DCO−, DCO+ Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output LVDS Lane 0 Output Data—Complement/True. LVDS Lane 1 Output Data—True/Complement. LVDS Lane 2 Output Data—Complement/True. LVDS Lane 3 Output Data—Complement/True. LVDS Lane 4 Output Data—Complement/True. LVDS Lane 5 Output Data—Complement/True. LVDS Lane 6 Output Data—Complement/True. LVDS Lane 7 Output Data—Complement/True. LVDS Lane 8 Output Data—Complement/True. LVDS Lane 9 Output Data—Complement/True. LVDS Lane 10 Output Data—Complement/True. LVDS Lane 11 Output Data—Complement/True. LVDS Lane 12 Output Data—Complement/True. LVDS Lane 13 Output Data—Complement/True. LVDS Status Output Data—Complement/True. LVDS Digital Clock Output Data—Complement/True. SDIO SCLK CSB PDWN/STBY Input/output Input Input Input SPI Serial Data Input/Output. SPI Serial Clock. SPI Chip Select (Active Low). Power-Down Input (Active High). The operation of this pin depends on the SPI mode and can be configured as powerdown or standby. Rev. 0 | Page 18 of 64 Data Sheet AD9684 TYPICAL PERFORMANCE CHARACTERISTICS AVDD1 = 1.2 V, AVDD2= 2.5 V, AVDD3 = 3.3 V, DVDD = 1.2 V, DRVDD = 1.2 V, SPIVDD = 1.8 V, sampling rate = 500 MHz, 1.6 V p-p full-scale differential input, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, 256k FFT sample, unless otherwise noted. 0 0 AIN = −1dBFS SNR = 68.9dBFS ENOB = 10.9 BITS SFDR = 83dBFS BUFFER CONTROL 1 = 2.0× –20 –40 –40 AMPLITUDE (dBFS) –60 –80 –100 –120 –60 –80 –100 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) –140 13015-014 –140 0 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) Figure 12. Single Tone FFT with fIN = 10.3 MHz Figure 15. Single Tone FFT with fIN = 450.3 MHz 0 0 AIN = −1dBFS SNR = 68.7dBFS ENOB = 10.9 BITS SFDR = 84dBFS BUFFER CONTROL 1 = 2.0× –20 AIN = −1dBFS SNR = 63.9dBFS ENOB = 10.3 BITS SFDR = 81dBFS BUFFER CONTROL 1 = 5.0× –20 –40 –40 AMPLITUDE (dBFS) AMPLITUDE (dBFS) 25 13015-017 –120 –60 –80 –100 –120 –60 –80 –100 –120 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) –140 13015-015 –140 0 25 50 75 100 125 150 175 200 225 250 225 250 FREQUENCY (MHz) Figure 13. Single Tone FFT with fIN = 170.3 MHz 13015-018 AMPLITUDE (dBFS) AIN = −1dBFS SNR = 67.3dBFS ENOB = 10.8 BITS SFDR = 86dBFS BUFFER CONTROL 1 = 4.5× –20 Figure 16. Single Tone FFT with fIN = 765.3 MHz 0 AIN = −1dBFS SNR = 62.8dBFS ENOB = 10.1 BITS SFDR = 76dBFS BUFFER CONTROL 1 = 5.0× 0 AIN = −1dBFS SNR = 67.8dBFS ENOB = 10.8 BITS SFDR = 82dBFS BUFFER CONTROL 1 = 4.5× –40 AMPLITUDE (dBFS) –20 –20 –60 –80 –60 –80 –100 –100 –120 –140 –140 0 25 50 75 100 125 150 175 200 225 FREQUENCY (MHz) 250 Figure 14. Single Tone FFT with fIN = 340.3 MHz Rev. 0 | Page 19 of 64 0 25 50 75 100 125 150 175 200 FREQUENCY (MHz) Figure 17. Single-Tone FFT with fIN = 985.3 MHz 13015-019 –120 13015-016 AMPLITUDE (dBFS) –40 AD9684 Data Sheet 95 0 AIN = −1dBFS SNR = 61.7dBFS ENOB = 9.9 BITS SFDR = 70dBFS BUFFER CONTROL 1 = 8.0× –20 90 SFDR 85 SNR/SFDR (dBFS) –40 AMPLITUDE (dBFS) 2.0× 2.0× 3.0× 3.0× 4.0× 4.0× –60 –80 80 75 –100 70 –120 65 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) 60 13015-020 –140 Figure 18. Single Tone FFT with fIN = 1205.3 MHz 0 AIN = −1dBFS SNR = 60.1dBFS ENOB = 9.7 BITS SFDR = 71dBFS BUFFER CONTROL 1 = 8.0× AIN1 AND AIN2 = –7dBFS SFDR = 88dBFS IMD2 = 95dBFS IMD3 = 88dBFS BUFFER CONTROL 1 = 2.0× –20 AMPLITUDE (dBFS) –60 –80 –100 –120 –40 –60 –80 0 25 50 75 100 125 150 175 200 225 250 FREQUENCY (MHz) –120 0 100 150 200 250 FREQUENCY (MHz) Figure 19. Single Tone FFT with fIN = 1630.3 MHz Figure 22. Two-Tone FFT with fIN1 = 184 MHz and fIN2 = 187 MHz 0 0 AIN = −1dBFS SNR = 59.0dBFS ENOB = 9.5 BITS SFDR = 69dBFS BUFFER CONTROL 1 = 8.0× –20 50 13015-025 –140 13015-021 –100 AIN1 AND AIN2 = –7dBFS SFDR = 87dBFS IMD2 = 94dBFS IMD3 = 87dBFS BUFFER CONTROL 1 = 2.0× –20 AMPLITUDE (dBFS) –40 –60 –80 –100 –120 –40 –60 –80 –140 0 25 50 75 100 125 150 175 200 225 FREQUENCY (MHz) 250 13015-022 –100 Figure 20. Single Tone FFT with fIN = 985.3 MHz –120 0 50 100 150 200 FREQUENCY (MHz) Figure 23. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz Rev. 0 | Page 20 of 64 250 13015-026 AMPLITUDE (dBFS) –40 AMPLITUDE (dBFS) 500 Figure 21. SNR/SFDR vs. Analog Input Frequency (fIN); fIN < 500 MHz; Buffer Control 1 Setting = 2.0×, 3.0×, and 4.0× 0 –20 400 100 200 300 ANALOG INPUT FREQUENCY (MHz) 0 13015-023 SNR Data Sheet AD9684 90 0 SFDR –20 85 SNR/SFDR (dBFS) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) 80 75 –100 70 IMD3 (dBFS) –120 –140 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 INPUT AMPLITUDE (dBFS) 65 –40 Figure 24. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 184 MHz and fIN2 = 187 MHz –25 –10 0 25 15 TEMPERATURE (°C) 40 70 55 85 13015-030 SNR 13015-027 SFDR/IMD3 (dBc AND dBFS) SFDR (dBc) Figure 27. SNR/SFDR vs. Temperature, fIN = 170.3 MHz 0 2.30 2.25 –20 2.20 POWER DISSIPATION (W) SFDR/IMD3 (dBc AND dBFS) SFDR (dBc) –40 IMD3 (dBc) –60 –80 SFDR (dBFS) –100 2.15 2.10 2.05 2.00 1.95 1.90 IMD3 (dBFS) Figure 25. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 338 MHz and fIN2 = 341 MHz 100 SFDR (dBc) 80 SFDR (dBFS) 40 SNR (dBc) 20 0 –20 INPUT AMPLITUDE (dBFS) 0 13015-029 –6 –12 –18 –24 –30 –36 –42 –48 –60 –54 –66 –72 –78 –84 –40 –90 SNR/SFDR (dBc AND dBFS) SNR (dBc) 60 Figure 26. SNR/SFDR vs. Input Amplitude, fIN = 170.3 MHz Rev. 0 | Page 21 of 64 500 480 460 440 420 400 380 360 340 320 1.80 SAMPLE RATE (MSPS) Figure 28. Power Dissipation vs. Sample Rate (fS) (Default SPI) 13015-031 INPUT AMPLITUDE (dBFS) 13015-028 1.85 –140 –90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6 300 –120 AD9684 Data Sheet EQUIVALENT CIRCUITS AVDD3 AVDD3 AVDD3 3pF 1.5pF 200Ω 67Ω 200Ω 28Ω VIN+x 200Ω 67Ω 28Ω 200Ω 400Ω 10pF VCM BUFFER SPIVDD ESD PROTECTED AVDD3 AVDD3 SPIVDD 1kΩ SCLK VIN–x ESD PROTECTED 13015-036 3pF 1.5pF 13015-032 30kΩ AIN CONTROL (SPI) Figure 29. Analog Inputs Figure 33. SCLK Inputs AVDD1 SPIVDD 25Ω CLK+ ESD PROTECTED 30kΩ 1kΩ CSB AVDD1 20kΩ VCM = 0.85V 13015-033 20kΩ 13015-037 ESD PROTECTED 25Ω Figure 30. Clock Inputs Figure 34. CSB Input AVDD1 SYNC+ SPIVDD 1kΩ ESD PROTECTED SDO 20kΩ AVDD1 SDI 30kΩ VCM = 0.85V ESD PROTECTED 20kΩ 13015-034 1kΩ Figure 31. SYNC± Inputs Figure 35. SDIO SPIVDD SWING CONTROL (SPI) ESD PROTECTED DRVDD DATA+ OUTPUT DRIVER DATA– DRGND ESD PROTECTED DRVDD Dx± DRGND FD FD_A/FD_B Dx± TEMPERATURE DIODE (FD_A ONLY) FD_x PIN CONTROL (SPI) 13015-035 SYNC– 1kΩ SDIO 13015-038 LEVEL TRANSLATOR SPIVDD Figure 32. LVDS Digital Outputs, STATUS±, DCO± Figure 36. FD_A/FD_B Outputs Rev. 0 | Page 22 of 64 13015-039 CLK– Data Sheet AD9684 AVDD2 SPIVDD ESD PROTECTED 1kΩ PDWN/STBY CONTROL (SPI) V_1P0 ESD PROTECTED 13015-040 PDWN/ STBY ESD PROTECTED 30kΩ V_1P0 PIN CONTROL (SPI) Figure 38. V_1P0 Input/Output Figure 37. PDWN/STBY Input Rev. 0 | Page 23 of 64 13015-041 ESD PROTECTED AD9684 Data Sheet THEORY OF OPERATION The AD9684 has several functions that simplify the AGC function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly reduce the system gain to avoid an overrange condition at the ADC input. The LVDS outputs can be configured depending on the decimation ratio. Multiple device synchronization is supported through the SYNC± input pins. ADC ARCHITECTURE The architecture of the AD9684 consists of an input buffered pipelined ADC. The input buffer provides a termination impedance to the analog input signal. This termination impedance can be changed using the SPI to meet the termination needs of the driver/ amplifier. The default termination value is set to 400 Ω. The input buffer is optimized for high linearity, low noise, and low power. The input buffer provides a linear high input impedance (for ease of drive) and reduces kickback from the ADC. The buffer is optimized for high linearity, low noise, and low power. The quantized outputs from each stage are combined into a final 14-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample, whereas the remaining stages operate with the preceding samples. Sampling occurs on the rising edge of the clock. ANALOG INPUT CONSIDERATIONS The analog input to the AD9684 is a differential buffer. The internal common-mode voltage of the buffer is 2.05 V. The clock signal alternately switches the input circuit between sample mode and hold mode. When the input circuit is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor, in series with each input, helps reduce the peak transient current injected from the output stage of the driving source. In addition, low Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and, thus, achieve the maximum bandwidth of the ADC. Such use of low Q inductors or ferrite beads is required when driving the converter front end at high IF For best dynamic performance, the source impedances driving VIN+x and VIN−x must be matched such that common-mode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates a differential reference that defines the span of the ADC core. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9684, the available span is 2.06 V p-p differential. Differential Input Configurations There are several ways to drive the AD9684, either actively or passively. However, optimum performance is achieved by driving the analog input differentially. For applications in which SNR and SFDR are key parameters, differential transformer coupling is the recommended input configuration because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9684. For low to midrange frequencies, a double balun or double transformer network is recommended for optimum performance of the AD9684 (see Figure 39). For higher frequencies in the second and third Nyquist zones, it is better to remove some of the front-end passive components to ensure wideband operation (see Figure 40). ETC1-11-13/ MABA007159 1:1Z 10Ω 10Ω 0.1µF 25Ω 4pF 0.1µF 25Ω 10Ω 2pF ADC 10Ω 0.1µF 13015-042 The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs that support a variety of user selectable input ranges. An integrated voltage reference eases design considerations. frequencies. Place either a differential capacitor or two singleended capacitors on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input, which limits unwanted broadband noise. For more information, see the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005). In general, the precise values depend on the application. 4pF Figure 39. Differential Transformer-Coupled Configuration for First and Second Nyquist Frequencies 25Ω MARKI BAL-0006 OR BAL-0006SMG 25Ω 25Ω 0.1µF 0.1µF 25Ω 0.1µF ADC 13015-043 The AD9684 has two analog input channels and 14 LVDS output lane pairs. The ADC is designed to sample wide bandwidth analog signals of up to 2 GHz. The AD9684 is optimized for wide input bandwidth, a high sampling rate, excellent linearity, and low power in a small package. Figure 40. Differential Transformer-Coupled Configuration for Second and Third Nyquist Frequencies Rev. 0 | Page 24 of 64 Data Sheet AD9684 Input Common Mode 95 Analog Input Controls and SFDR Optimization 4.5× 85 3.0× 75 SFDR (dBFS) The analog inputs of the AD9684 are internally biased to the common mode as shown in Figure 41. The common-mode buffer has a limited range in that the performance suffers greatly if the common-mode voltage drops by more than 100 mV. Therefore, in dc-coupled applications, set the common-mode voltage to 2.05 V ± 100 mV to ensure proper ADC operation. 2.0× 65 1.5× 55 The AD9684 offers flexible controls for the analog inputs, such as input termination and buffer current. All of the available controls are shown in Figure 41. 1.0× 35 50 AVDD3 150 100 200 250 300 350 400 450 500 INPUT FREQUENCY (MHz) 13015-046 45 Figure 43. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF), 10 MHz < fIN < 500 MHz VIN+x 3pF 200Ω 67Ω 200Ω 28Ω 90 AVDD3 VCM BUFFER SFDR (dBFS) 200Ω 67Ω 28Ω 200Ω 400Ω 10pF 4.5× 5.0× 6.0× 7.0× 8.0× 85 AVDD3 VIN–x 80 75 3pF 70 65 500 Figure 41. Analog Input Controls (Should the AIN Using Register 0x018, the buffer currents on each channel can be scaled to optimize the SFDR over various input frequencies and bandwidths of interest. As the input buffer currents are set, the amount of current required by the AVDD3 supply changes. For a complete list of buffer current settings, see Table 29. 550 600 650 700 750 800 850 900 950 1000 INPUT FREQUENCY (MHz) 13015-047 13015-044 AIN CONTROL (SPI) REGISTERS (REG 0x008, REG 0x015, REG 0x016, REG 0x018, REG 0x025) Figure 44. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF), 500 MHz < fIN < 1000 MHz 80 75 250 70 210 IAVDD3 (mA) 190 170 60 55 150 130 50 110 4.5× 5.0× 6.0× 7.0× 8.0× 8.0× 45 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 90 INPUT FREQUENCY (MHz) 2.5× 3.5× 4.5× 5.5× 6.5× 7.5× 8.5× BUFFER CURRENT SETTING Figure 42. AVDD3 Power (IAVDD3) vs. Buffer Current Control Setting in Register 0x018 13015-045 70 50 1.5× 65 13015-048 SFDR (dBFS) 230 Figure 45. Buffer Current Sweeps (SFDR vs. Input Frequency and IBUFF), 1 GHz < fIN < 2 GHz, Front-End Network Shown in Figure 40 Figure 43, Figure 44, and Figure 45 show how the SFDR can be optimized using the buffer current setting in Register 0x018 for different Nyquist zones. At frequencies greater than 1 GHz, it is better to run the ADC at input amplitudes less than −1 dBFS (−3 dBFS, for example). This greatly improves the linearity of the converted signal without sacrificing SNR performance. Rev. 0 | Page 25 of 64 AD9684 Data Sheet The use of an external reference may be necessary, in some applications, to enhance the gain accuracy of the ADC or improve thermal drift characteristics. Figure 47 shows the typical drift characteristics of the internal 1.0 V reference. Table 9 shows the recommended buffer current and full-scale voltage settings for the different analog input frequency ranges. Absolute Maximum Input Swing The absolute maximum input swing allowed at the inputs of the AD9684 is 4.3 V p-p differential. Signals operating near or at this level can cause permanent damage to the ADC. 1.0010 1.0009 1.0008 VOLTAGE REFERENCE V_1P0 VOLTAGE (V) 1.0007 A stable and accurate 1.0 V voltage reference is built into the AD9684. This internal 1.0 V reference sets the full-scale input range of the ADC. For more information on adjusting the input swing, see Table 29. Figure 46 shows the block diagram of the internal 1.0 V reference controls. 1.0006 1.0005 1.0004 1.0003 1.0002 1.0000 VIN–A/ VIN–B 0.9999 0.9998 –50 INTERNAL V_1P0 GENERATOR 0 ADC CORE FULL-SCALE VOLTAGE ADJUST 25 90 TEMPERATURE (°C) Figure 47. Typical V_1P0 Drift The external reference must be a stable 1.0 V reference. The ADR130 is a good option for providing the 1.0 V reference. Figure 48 shows how the ADR130 can be used to provide the external 1.0 V reference to the AD9684. The grayed out areas show unused blocks within the AD9684 while using the ADR130 to provide the external reference. INPUT FULL-SCALE RANGE ADJUST SPI REGISTER (REGISTER 0x025) V_1P0 13015-049 V_1P0 PIN CONTROL SPI REGISTER (REGISTER 0x024) Figure 46. Internal Reference Configuration and Controls Register 0x024 enables the user either to use this internal 1.0 V reference, or to provide an external 1.0 V reference. When using an external voltage reference, provide a 1.0 V reference. The full-scale adjustment is made using the SPI, irrespective of the reference voltage. For more information on adjusting the fullscale level of the AD9684, see the Memory Map Register Table section. Table 9. SFDR Optimization for Input Frequencies Frequency DC to 250 MHz 250 MHz to 500 MHz 500 MHz to 1 GHz 1 GHz to 2 GHz Buffer Control 1 (Register 0x018) 0x20 (2.0×) 0x70 (4.5×) Input Full-Scale Range (Register 0x025) 0x0C (2.06 V p-p) 0x0C (2.06 V p-p) Input Full-Scale Control (Register 0x030) 0x04 0x04 Input Termination (Register 0x016) 1 0x0C/0x1C/0x6C 0x0C/0x1C/0x6C 0x80 (5.0×) 0x08 (1.46 V p-p) 0x18 0x0C/0x1C/0x6C 0xF0 (8.5×) 0x08 (1.46 V p-p) 0x18 0x0C/0x1C/0x6C The input termination can be changed to accommodate the application with little or no impact to ac performance. INTERNAL V_1P0 GENERATOR ADR130 INPUT 1 NC 2 GND SET 5 3 VIN 0.1µF FULL-SCALE VOLTAGE ADJUST NC 6 VOUT 4 V_1P0 0.1µF FULL-SCALE CONTROL Figure 48. External Reference Using the ADR130 Rev. 0 | Page 26 of 64 13015-054 1 13015-050 1.0001 VIN+A/ VIN+B Data Sheet AD9684 CLOCK INPUT CONSIDERATIONS Input Clock Divider For optimum performance, drive the AD9684 sample clock inputs (CLK+ and CLK−) with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or clock drivers. These pins are biased internally and require no additional biasing. The AD9684 contains an input clock divider with the ability to divide the Nyquist input clock by 1, 2, 4, and 8. The divider ratios can be selected using Register 0x10B. This is shown in Figure 52. Figure 49 shows a preferred method for clocking the AD9684. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. 0.1µF CLK+ 100Ω CLK+ ADC CLK– 0.1µF CLK– ÷2 ÷4 Figure 49. Transformer Coupled Differential Clock ÷8 Another option is to ac couple a differential CML or LVDS signal to the sample clock input pins, as shown in Figure 50 and Figure 51. 3.3V 71Ω 33Ω 0.1µF ADC Z0 = 50Ω 0.1µF 13015-052 CLK+ CLK– Input Clock Divider ½ Period Delay Adjustment Figure 50. Differential CML Sample Clock CLK+ LVDS DRIVER CLK+ 100Ω CLK– CLOCK INPUT 50Ω1 50Ω1 Clock Fine Delay Adjustment ADC CLK– 0.1µF 150Ω RESISTORS ARE OPTIONAL. 13015-053 0.1µF The input clock divider inside the AD9684 provides phase delay in increments of ½ the input clock cycle. Program Register 0x10C to enable this delay independently for each channel. 0.1µF 0.1µF CLOCK INPUT Figure 52. Clock Divider Circuit The AD9684 clock divider can be synchronized using the external SYNC± input. A valid SYNC± input causes the clock divider to reset to a programmable state. This feature is enabled by setting Bit 7 of Register 0x10D. This synchronization feature allows multiple devices to have their clock dividers aligned to guarantee simultaneous input sampling. 10pF 33Ω Z0 = 50Ω REG 0x10B 13015-055 1:1Z 50Ω 13015-051 CLOCK INPUT The maximum frequency at the CLK± inputs is 4 GHz. This is the limit of the divider. In applications where the clock input is a multiple of the sample clock, the appropriate divider ratio must be programmed into the clock divider before applying the clock signal. This ensures that the current transients during device startup are controlled. Figure 51. Differential LVDS Sample Clock Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. In applications where the clock duty cycle cannot be guaranteed to be 50%, a higher multiple frequency clock can be supplied to the device. The AD9684 can be clocked at 2 GHz with the internal clock divider set to 2. The output of the divider offers a 50% duty cycle, high slew rate (fast edge) clock signal to the internal ADC. See the Memory Map section for more details on using this feature. To adjust the AD9684 sampling edge instant, write to Register 0x117 and Register 0x118. Setting Bit 0 of Register 0x117 enables the fine delay feature, and Register 0x118, Bits[7:0] set the value of the delay. This value can be programmed individually for each channel. The clock delay can be adjusted from −151.7 ps to +150 ps in ~1.7 ps increments. The clock delay adjust takes effect immediately when it is enabled via SPI writes. Enabling the clock fine delay adjustment in Register 0x117 causes a datapath reset. Clock Jitter Considerations High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by SNR = 20 × log 10 (2 × π × fA × tJ) In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter specifications. IF undersampling applications are particularly sensitive to jitter (see Figure 53). Rev. 0 | Page 27 of 64 AD9684 POWER-DOWN/STANDBY MODE RMS CLOCK JITTER REQUIREMENT 120 The AD9684 has a PDWN/STBY pin that configures the device in power-down or standby mode. The default operation is the power-down function. The PDWN/STBY pin is a logic high pin. The power-down option can also be set via Register 0x03F and Register 0x040. SNR (dB) 110 100 16 BITS 90 14 BITS 80 12 BITS TEMPERATURE DIODE 70 10 BITS 60 40 30 1 100 10 ANALOG INPUT FREQUENCY (MHz) 1000 13015-056 0.125ps 0.25ps 0.5ps 1.0ps 2.0ps 8 BITS 50 Figure 53. Ideal SNR vs. Analog Input Frequency and Jitter Treat the clock input as an analog signal when aperture jitter may affect the dynamic range of the AD9684. Separate the power supplies for the clock drivers from the ADC output driver supplies to avoid modulating the clock signal with digital noise. If the clock is generated from another type of source (by gating, dividing, or other methods), retime the clock by the original clock at the last step. For more in-depth information about jitter performance as it relates to ADCs, see the AN-501 Application Note and the AN-756 Application Note. Figure 54 shows the estimated SNR of the AD9684 across the input frequency for different clock induced jitter values. Estimate the SNR using the following equation:  − SNR JITTER    − SNR ADC     SNR (dBFS) = 10log10 10  + 10 10       The AD9684 contains a diode-based temperature sensor for measuring the temperature of the die. This diode can output a voltage and serve as a coarse temperature sensor to monitor the internal die temperature. The temperature diode voltage can be output to the FD_A pin using the SPI. Use Register 0x028, Bit 0 to enable or disable the diode. Register 0x028 is a local register. Channel A must be selected in the device index register (Register 0x008) to enable the temperature diode readout. Configure the FD_A pin to output the diode voltage by programming Register 0x040, Bits[2:0]. See Table 29 for more information. The voltage response of the temperature diode (with SPIVDD = 1.8 V) is shown in Figure 55. 0.90 0.85 DIODE VOLTAGE (V) 130 Data Sheet 0.80 0.75 0.70 75 0.65 0.60 –55 –45 –35 –25 –15 –5 SNR (dBFS) 65 5 15 25 35 45 55 65 75 85 95 105 115 125 TEMPERATURE (°C) 25fs 50fs 75fs 100fs 125fs 150fs 175fs 200fs 60 55 Figure 55. Diode Voltage vs. Temperature 45 1M 10M 100M INPUT FREQUENCY (Hz) 1G 10G 13015-057 50 Figure 54. Estimated SNR Degradation for the AD9684 vs. Input Frequency and Clock Jitter Rev. 0 | Page 28 of 64 13015-058 70 Data Sheet AD9684 ADC OVERRANGE AND FAST DETECT The operation of the upper threshold and lower threshold registers, along with the dwell time registers, is shown in Figure 56. In receiver applications, it is desirable to have a mechanism to reliably determine when the converter is about to be clipped. The standard overrange pin outputs information on the state of the analog input. It is also helpful to have a programmable threshold below full scale that allows time to reduce the gain before the clip actually occurs. In addition, because input signals can have significant slew rates, the latency of this function is of major concern. Highly pipelined converters can have significant latency. The AD9684 contains fast detect circuitry for individual channels to monitor the threshold and assert the FD_A and FD_B pins. The FD_x indicator is asserted if the input magnitude exceeds the value programmed in the fast detect upper threshold registers, in Register 0x247 and Register 0x248. The selected threshold register is compared with the signal magnitude at the output of the ADC. The fast upper threshold detection has a latency of 28 clock cycles (maximum). The approximate upper threshold magnitude is defined by Upper Threshold Magnitude (dBFS) = 20log(Threshold Magnitude/213) ADC OVERRANGE The ADC overrange indicator is asserted when an overrange is detected on the input of the ADC. The overrange indicator can be output on the STATUS± pins (when CSB > 0). The latency of this overrange indicator matches the sample latency. The FD indicators are not cleared until the signal drops below the lower threshold for the programmed dwell time. The lower threshold is programmed in the fast detect lower threshold registers, in Register 0x249 and Register 0x24A. The fast detect lower threshold register is a 13-bit register that is compared with the signal magnitude at the output of the ADC. This comparison is subject to the ADC pipeline latency, but is accurate in terms of converter resolution. The lower threshold magnitude is defined by The AD9684 also records any overrange condition in any of the four virtual converters. The overrange status of each virtual converter is registered as a sticky bit in Register 0x563. The contents of Register 0x563 can be cleared using Register 0x562, by toggling the bits corresponding to the virtual converter to set and reset the position. Lower Threshold Magnitude (dBFS) = 20log(Threshold Magnitude/213) FAST THRESHOLD DETECTION (FD_A AND FD_B) For example, to set an upper threshold of −6 dBFS, write 0xFFF to Register 0x247 and Register 0x248. To set a lower threshold of −10 dBFS, write 0xA1D to Register 0x249 and Register 0x24A. The fast detect (FD) bit (enabled via the control bits in Register 0x559) is immediately set whenever the absolute value of the input signal exceeds the programmable upper threshold level. The FD bit is cleared only when the absolute value of the input signal drops below the lower threshold level for greater than the programmable dwell time. This feature provides hysteresis and prevents the FD bit from excessively toggling. The dwell time can be programmed from 1 to 65,535 sample clock cycles by placing the desired value in the fast detect dwell time registers, in Register 0x24B and Register 0x24C. See the Memory Map section (Register 0x040, and Register 0x245 to Register 0x24C in Table 29) for more details. UPPER THRESHOLD DWELL TIME TIMER RESET BY RISE ABOVE LOWER THRESHOLD DWELL TIME FD_A OR FD_B Figure 56. Threshold Settings for FD_A and FD_B Signals Rev. 0 | Page 29 of 64 TIMER COMPLETES BEFORE SIGNAL RISES ABOVE LOWER THRESHOLD 13015-059 MIDSCALE LOWER THRESHOLD AD9684 Data Sheet SIGNAL MONITOR The signal monitor block provides additional information about the signal being digitized by the ADC. The signal monitor computes the peak magnitude of the digitized signal. This information can be used to drive an AGC loop to optimize the range of the ADC in the presence of real-world signals. The results of the signal monitor block can be obtained by reading back the internal values from the SPI port. A global, 24-bit programmable period controls the duration of the measurement. Figure 57 shows the simplified block diagram of the signal monitor block. The peak detector captures the largest signal within the observation period. The detector only observes the magnitude of the signal. The resolution of the peak detector is a 13-bit value and the observation period is 24 bits and represents converter output samples. Derive the peak magnitude using the following equation: Peak Magnitude (dBFS) = 20log(Peak Detector Value/213) The magnitude of the input port signal is monitored over a programmable time period, which is determined by the signal SIGNAL MONITOR PERIOD REGISTER (SMPR) REG 0x271, REG 0x272, REG 0x273 After enabling this mode, the value in the SMPR is loaded into a monitor period timer that decrements at the decimated clock rate. The magnitude of the input signal is compared with the value in the internal magnitude storage register (not accessible to the user), and the greater of the two is updated as the current peak level. The initial value of the magnitude storage register is set to the current ADC input signal magnitude. This comparison continues until the monitor period timer reaches a count of 1. When the monitor period timer reaches a count of 1, the 13-bit peak level value is transferred to the signal monitor holding register, which can be read through the memory map. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. In addition, the magnitude of the first input sample is updated in the magnitude storage register. DOWN COUNTER IS COUNT = 1? LOAD CLEAR FROM INPUT MAGNITUDE STORAGE REGISTER LOAD LOAD SIGNAL MONITOR HOLDING REGISTER COMPARE A>B Figure 57. Signal Monitor Block Rev. 0 | Page 30 of 64 TO STATUS± PINS AND MEMORY MAP 13015-060 FROM MEMORY MAP monitor period register (SMPR). To enable the peak detector function, set Bit 1 of Register 0x270 in the signal monitor control register. The 24-bit SMPR must be programmed before activating this mode. Data Sheet AD9684 DIGITAL DOWNCONVERTERS (DDCs) The AD9684 includes four digital downconverters that provide filtering and reduce the output data rate. This digital processing section includes an NCO, a half-band decimating filter, a finite impulse response (FIR) filter, a gain stage, and a complex to real conversion stage. Each of these processing blocks has a control line that allows the block to be independently enabled and disabled to provide the desired processing function. The DDCs can be configured to output either real data or complex output data. DDC I/Q INPUT SELECTION The AD9684 has two ADC channels and four DDC channels. Each DDC channel has two input ports that can be paired to support both real and complex inputs through the I/Q crossbar mux. For real signals, both DDC input ports must select the same ADC channel (that is, DDC Input Port I = ADC Channel A and DDC Input Port Q = ADC Channel A). For complex signals, each DDC input port must select different ADC channels (that is, DDC Input Port I = ADC Channel A and DDC Input Port Q = ADC Channel B). The inputs to each DDC are controlled by the DDC input selection registers (Register 0x311, Register 0x331, Register 0x351, and Register 0x371). See Table 29 for information on how to configure the DDCs. DDC I/Q OUTPUT SELECTION Each DDC channel has two output ports that can be paired to support both real or complex outputs. For real output signals, only the DDC Output Port I is used (the DDC Output Port Q is invalid). For complex I/Q output signals, both DDC Output Port I and DDC Output Port Q are used. The I/Q outputs to each DDC channel are controlled by the DDC complex to real enable bit in the DDC control registers (Bit 3 in Register 0x310, Register 0x330, Register 0x350, and Register 0x370). The Chip I only bit in the chip application mode register (Register 0x200, Bit 5) controls the chip output muxing of all the DDC channels. When all DDC channels use real outputs, set this bit high to ignore all DDC Q output ports. When any of the DDC channels are set to use complex I/Q outputs, the user must clear this bit to use both DDC Output Port I and DDC Output Port Q. DDC GENERAL DESCRIPTION The four DDC blocks extract a portion of the full digital spectrum captured by the ADCs. They are intended for IF sampling or oversampled baseband radios requiring wide bandwidth input signals. Each DDC block contains the following signal processing stages: • • • • Frequency translation stage (optional) Filtering stage Gain stage (optional) Complex to real conversion stage (optional) Frequency Translation Stage (Optional) This stage consists of a 12-bit complex NCO and quadrature mixers that can be used for frequency translation of both real or complex input signals. This stage shifts a portion of the available digital spectrum down to baseband. Filtering Stage After shifting down to baseband, this stage decimates the frequency spectrum using a chain of up to four half-band, lowpass filters for rate conversion. The decimation process lowers the output data rate, which, in turn, reduces the output interface rate. Gain Stage (Optional) Due to losses associated with mixing a real input signal down to baseband, this stage compensates by adding an additional 0 dB or 6 dB of gain. Complex to Real Conversion Stage (Optional) When real outputs are necessary, this stage converts the complex outputs back to real outputs by performing an fS/4 mixing operation in addition to a filter to remove the complex component of the signal. Figure 58 shows the detailed block diagram of the DDCs implemented in the AD9684. Rev. 0 | Page 31 of 64 AD9684 Data Sheet GAIN = 0dB OR 6dB COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) COMPLEX TO REAL CONVERSION (OPTIONAL) HB1 FIR DCM = 2 GAIN = 0dB OR 6dB ADC SAMPLING AT fS GAIN = 0dB OR 6dB REAL/I GAIN = 0dB OR 6dB REAL/Q Q HB2 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB3 FIR DCM = BYPASS OR 2 I HB4 FIR DCM = BYPASS OR 2 DDC 0 REAL/I REAL/I CONVERTER 0 Q CONVERTER 1 SYNC± Q CONVERTER 3 REAL/Q Q ADC SAMPLING AT fS HB1 FIR DCM = 2 I HB2 FIR DCM = BYPASS OR 2 REAL/I HB3 FIR DCM = BYPASS OR 2 DDC 2 REAL/I CONVERTER 4 OUTPUT INTERFACE HB1 FIR DCM = 2 REAL/I CONVERTER 2 SYNC± NCO + MIXER (OPTIONAL) REAL/I HB2 FIR DCM = BYPASS OR 2 REAL/Q Q HB3 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB4 FIR DCM = BYPASS OR 2 I/Q CROSSBAR MUX I HB4 FIR DCM = BYPASS OR 2 DDC 1 REAL/I Q CONVERTER 5 SYNC± SYNC± SYNCHRONIZATION CONTROL CIRCUITS HB1 FIR DCM = 2 REAL/I CONVERTER 6 Q CONVERTER 7 13015-061 REAL/Q Q HB2 FIR DCM = BYPASS OR 2 NCO + MIXER (OPTIONAL) HB3 FIR DCM = BYPASS OR 2 I HB4 FIR DCM = BYPASS OR 2 DDC 3 REAL/I SYNC± Figure 58. DDC Detailed Block Diagram Figure 59 shows an example usage of one of the four DDC blocks with a real input signal and four half-band filters (HB4 + HB3 + HB2 + HB1). It shows both complex (decimate by 16) and real (decimate by 8) output options. When DDCs have different decimation ratios, the chip decimation ratio (Register 0x201) must be set to the lowest decimation ratio for all the DDC blocks. In this scenario, samples of higher decimation ratio DDCs are repeated to match the chip decimation ratio sample rate. Whenever the NCO frequency is set or changed, the DDC soft reset must be issued. If the DDC soft reset is not issued, the output may potentially show amplitude variations. Table 10 through Table 15 show the DDC samples when the chip decimation ratio is set to 1, 2, 4, 8, or 16, respectively. When DDCs have different decimation ratios, the chip decimation ratio must be set to the lowest decimation ratio of all the DDC channels. In this scenario, samples of higher decimation ratio DDCs are repeated to match the chip decimation ratio sample rate. Rev. 0 | Page 32 of 64 Data Sheet AD9684 ADC ADC SAMPLING AT fS REAL REAL INPUT—SAMPLED AT fS BANDWIDTH OF INTEREST IMAGE –fS/2 –fS/3 BANDWIDTH OF INTEREST fS/32 –fS/32 DC –fS/16 fS/16 –fS/8 –fS/4 REAL FREQUENCY TRANSLATION STAGE (OPTIONAL) DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) fS/3 fS/4 fS/8 fS/2 I NCO TUNES CENTER OF BANDWIDTH OF INTEREST TO BASEBAND cos(wt) REAL 12-BIT NCO 90° 0° –sin(wt) Q DIGITAL FILTER RESPONSE –fS/2 –fS/3 fS/32 –fS/32 DC –fS/16 fS/16 –fS/8 –fS/4 BANDWIDTH OF INTEREST IMAGE (–6dB LOSS DUE TO NCO + MIXER) BANDWIDTH OF INTEREST (–6dB LOSS DUE TO NCO + MIXER) fS/4 fS/8 fS/2 fS/3 FILTERING STAGE I HALFBAND FILTER Q HALFBAND FILTER 2 HALFBAND FILTER 2 HALFBAND FILTER 2 HALFBAND FILTER 2 HALFBAND FILTER 2 HALFBAND FILTER I HB1 FIR HB2 FIR HB3 FIR HB4 FIR HB1 FIR HB2 FIR HB3 FIR HB4 FIR 4 DIGITAL HALF-BAND FILTERS (HB4 + HB3 + HB2 + HB1) 2 HALFBAND FILTER Q 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS COMPLEX (I/Q) OUTPUTS GAIN STAGE (OPTIONAL) DIGITAL FILTER RESPONSE I GAIN STAGE (OPTIONAL) Q 0dB OR 6dB GAIN COMPLEX TO REAL CONVERSION STAGE (OPTIONAL) fS/4 MIXING + COMPLEX FILTER TO REMOVE Q –fS/32 fS/32 DC –fS/16 fS/16 –fS/8 I REAL (I) OUTPUTS +6dB +6dB fS/8 2 +6dB 2 +6dB I Q –fS/32 fS/32 DC –fS/16 fS/16 DOWNSAMPLE BY 2 I DECIMATE BY 8 Q DECIMATE BY 16 0dB OR 6dB GAIN Q COMPLEX REAL/I TO REAL –fS/8 –fS/32 fS/32 DC –fS/16 fS/16 fS/8 Figure 59. DDC Theory of Operation Example (Real Input, Decimate by 16) Rev. 0 | Page 33 of 64 13015-062 6dB GAIN TO COMPENSATE FOR NCO + MIXER LOSS AD9684 Data Sheet Table 10. DDC Samples When the Chip Decimation Ratio = 1 HB1 FIR (DCM 1 = 1) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 N + 18 N + 19 N + 20 N + 21 N + 22 N + 23 N + 24 N + 25 N + 26 N + 27 N + 28 N + 29 N + 30 N + 31 1 Real (I) Output (Complex to Real Enabled) HB2 FIR + HB3 FIR + HB2 HB4 FIR + HB3 FIR HB1 FIR FIR + HB1 FIR + HB2 FIR + HB1 (DCM1 = 2) (DCM1 = 4) FIR (DCM1 = 8) N N N N+1 N+1 N+1 N N N N+1 N+1 N+1 N+2 N N N+3 N+1 N+1 N+2 N N N+3 N+1 N+1 N+4 N+2 N N+5 N+3 N+1 N+4 N+2 N N+5 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 N+8 N+4 N+2 N+9 N+5 N+3 N+8 N+4 N+2 N+9 N+5 N+3 N + 10 N+4 N+2 N + 11 N+5 N+3 N + 10 N+4 N+2 N + 11 N+5 N+3 N + 12 N+6 N+2 N + 13 N+7 N+3 N + 12 N+6 N+2 N + 13 N+7 N+3 N + 14 N+6 N+2 N + 15 N+7 N+3 N + 14 N+6 N+2 N + 15 N+7 N+3 Complex (I/Q) Outputs (Complex to Real Disabled) HB2 FIR + HB3 FIR + HB2 HB4 FIR + HB3 FIR + HB1 FIR HB1 FIR FIR + HB1 FIR HB2 FIR + HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16) N N N N N+1 N+1 N+1 N+1 N N N N N+1 N+1 N+1 N+1 N+2 N N N N+3 N+1 N+1 N+1 N+2 N N N N+3 N+1 N+1 N+1 N+4 N+2 N N N+5 N+3 N+1 N+1 N+4 N+2 N N N+5 N+3 N+1 N+1 N+6 N+2 N N N+7 N+3 N+1 N+1 N+6 N+2 N N N+7 N+3 N+1 N+1 N+8 N+4 N+2 N N+9 N+5 N+3 N+1 N+8 N+4 N+2 N N+9 N+5 N+3 N+1 N + 10 N+4 N+2 N N + 11 N+5 N+3 N+1 N + 10 N+4 N+2 N N + 11 N+5 N+3 N+1 N + 12 N+6 N+2 N N + 13 N+7 N+3 N+1 N + 12 N+6 N+2 N N + 13 N+7 N+3 N+1 N + 14 N+6 N+2 N N + 15 N+7 N+3 N+1 N + 14 N+6 N+2 N N + 15 N+7 N+3 N+1 DCM means decimation. Table 11. DDC Samples When the Chip Decimation Ratio = 2 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR (DCM1 = 4) (DCM1 = 8) (DCM 1 = 2) N N N N+1 N+1 N+1 N+2 N N N+3 N+1 N+1 N+4 N+2 N N+5 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 N+8 N+4 N+2 N+9 N+5 N+3 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16) N N N N N+1 N+1 N+1 N+1 N+2 N N N N+3 N+1 N+1 N+1 N+4 N+2 N N N+5 N+3 N+1 N+1 N+6 N+2 N N N+7 N+3 N+1 N+1 N+8 N+4 N+2 N N+9 N+5 N+3 N+1 Rev. 0 | Page 34 of 64 Data Sheet Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR (DCM1 = 4) (DCM 1 = 2) (DCM1 = 8) N + 10 N+4 N+2 N + 11 N+5 N+3 N + 12 N+6 N+2 N + 13 N+7 N+3 N + 14 N+6 N+2 N + 15 N+7 N+3 1 AD9684 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB3 FIR + HB2 FIR + HB2 FIR + HB2 FIR + HB1 FIR HB1 FIR HB1 FIR HB1 FIR (DCM1 = 2) (DCM1 = 4) (DCM1 = 8) (DCM1 = 16) N + 10 N+4 N+2 N N + 11 N+5 N+3 N+1 N + 12 N+6 N+2 N N + 13 N+7 N+3 N+1 N + 14 N+6 N+2 N N + 15 N+7 N+3 N+1 DCM means decimation. Table 12. DDC Samples When the Chip Decimation Ratio = 4 Real (I) Output (Complex to Real Enabled) HB3 FIR + HB2 FIR + HB1 HB4 FIR + HB3 FIR + HB2 FIR FIR (DCM 1 = 4) + HB1 FIR (DCM1 = 8) N N N+1 N+1 N+2 N N+3 N+1 N+4 N+2 N+5 N+3 N+6 N+2 N+7 N+3 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB2 FIR + HB1 FIR HB3 FIR + HB2 FIR + HB4 FIR + HB3 FIR + HB2 FIR (DCM1 = 4) HB1 FIR (DCM1 = 8) + HB1 FIR (DCM1 = 16) N N N N+1 N+1 N+1 N+2 N N N+3 N+1 N+1 N+4 N+2 N N+5 N+3 N+1 N+6 N+2 N N+7 N+3 N+1 DCM means decimation. Table 13. DDC Samples When the Chip Decimation Ratio = 8 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 8) N N+1 N+2 N+3 N+4 N+5 N+6 N+7 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 HB3 FIR + HB2 FIR + HB1 FIR(DCM1 = 8) FIR (DCM1 = 16) N N N+1 N+1 N+2 N N+3 N+1 N+4 N+2 N+5 N+3 N+6 N+2 N+7 N+3 DCM means decimation. Table 14. DDC Samples When the Chip Decimation Ratio = 16 Real (I) Output (Complex to Real Enabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 16) Not applicable Not applicable Not applicable Not applicable 1 Complex (I/Q) Outputs (Complex to Real Disabled) HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16) N N+1 N+2 N+3 DCM means decimation. Rev. 0 | Page 35 of 64 AD9684 Data Sheet For example, if the chip decimation ratio is set to decimate by 4, DDC 0 is set to use HB2 + HB1 filters (complex outputs, decimate by 4) and DDC 1 is set to use HB4 + HB3 + HB2 + HB1 filters (real outputs, decimate by 8). DDC 1 repeats its output data two times for every one DDC 0 output. The resulting output samples are shown in Table 15. Table 15. Chip Decimation Ratio = 4, DDC 0 Decimation = 4 (Complex), and DDC 1 Decimation = 8 (Real) DDC Input Samples N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 Output Port I I0 (N) DDC 0 Output Port Q Q0 (N) Output Port I I1 (N) DDC 1 Output Port Q Not applicable I0 (N + 1) Q0 (N + 1) I1 (N + 1) Not applicable I0 (N + 2) Q0 (N + 2) I1 (N) Not applicable I0 (N + 3) Q0 (N + 3) I1 (N + 1) Not applicable Rev. 0 | Page 36 of 64 Data Sheet AD9684 FREQUENCY TRANSLATION GENERAL DESCRIPTION Variable IF Mode Frequency translation is accomplished using a 12-bit complex NCO with a digital quadrature mixer. The frequency translation translates either a real or complex input signal from an IF to a baseband complex digital output (carrier frequency = 0 Hz). The NCO and the mixers are enabled. The NCO output frequency can be used to digitally tune the IF frequency. 0 Hz IF (ZIF) Mode The mixers are bypassed and the NCO is disabled. The frequency translation stage of each DDC can be controlled individually and supports four different IF modes using Bits[5:4] of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). These IF modes are The mixers and the NCO are enabled in a special downmixing by fS/4 mode to save power. Test Mode Variable IF mode 0 Hz IF, or zero IF (ZIF), mode fS/4 Hz IF mode Test mode The input samples are forced to 0.999 × full scale to positive full scale. The NCO is enabled. This test mode allows the NCOs to drive the decimation filters directly. Figure 60 and Figure 61 show examples of the frequency translation stage for both real and complex inputs. NCO FREQUENCY TUNING WORD (FTW) SELECTION 12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 I ADC + DIGITAL MIXER + NCO REAL INPUT—SAMPLED AT fS REAL ADC SAMPLING AT fS cos(wt) REAL 12-BIT NCO 90° 0° COMPLEX –sin(wt) Q BANDWIDTH OF INTEREST BANDWIDTH OF INTEREST IMAGE –fS/2 –fS/3 –fS/4 –fS/8 –fS/32 fS/32 DC fS/16 –fS/16 fS/8 fS/4 fS/3 fS/2 –6dB LOSS DUE TO NCO + MIXER 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) POSITIVE FTW VALUES –fS/32 DC fS/32 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = –1365 (0xAAB) –fS/32 NEGATIVE FTW VALUES DC fS/32 Figure 60. DDC NCO Frequency Tuning Word Selection—Real Inputs Rev. 0 | Page 37 of 64 13015-063 • • • • fS/4 Hz IF Mode AD9684 Data Sheet NCO FREQUENCY TUNING WORD (FTW) SELECTION 12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096 I + I I I Q Q 90° PHASE 12-BIT NCO 90° 0° Q Q ADC SAMPLING AT fS Q Q I I – –sin(wt) QUADRATURE ANALOG MIXER + 2 ADCs + QUADRATURE DIGITAL REAL MIXER + NCO COMPLEX INPUT—SAMPLED AT fS QUADRATURE MIXER ADC SAMPLING AT fS I + COMPLEX Q + BANDWIDTH OF INTEREST IMAGE DUE TO ANALOG I/Q MISMATCH –fS/3 –fS/4 –fS/32 fS/32 –fS/16 fS/16 DC –fS/8 fS/8 fS/4 fS/3 fS/2 12-BIT NCO FTW = ROUND ((fS/3)/fS × 4096) = +1365 (0x555) POSITIVE FTW VALUES –fS/32 fS/32 13015-064 –fS/2 DC Figure 61. DDC NCO Frequency Tuning Word Selection—Complex Inputs DDC NCO PLUS MIXER LOSS AND SFDR Setting Up the NCO FTW and POW When mixing a real input signal down to baseband, 6 dB of loss is introduced in the signal due to filtering of the negative image. The NCO introduces an additional 0.05 dB of loss. The total loss of a real input signal mixed down to baseband is 6.05 dB. For this reason, it is recommended to compensate for this loss by enabling the 6 dB of gain in the gain stage of the DDC to recenter the dynamic range of the signal within the full scale of the output bits. The NCO frequency value is given by the 12-bit, twos complement number entered in the NCO FTW. Frequencies between ±fS/2 (+fS/2 excluded) are represented using the following frequency words: When mixing a complex input signal down to baseband, the maximum value that each I/Q sample can reach is 1.414 × full scale after it passes through the complex mixer. To avoid an overrange of the I/Q samples and to keep the data bit-widths aligned with real mixing, introduce 3.06 dB of loss (0.707 × fullscale) in the mixer for complex signals. The NCO introduces an additional 0.05 dB of loss. The total loss of a complex input signal mixed down to baseband is −3.11 dB. The worst case spurious signal from the NCO is greater than 102 dBc SFDR for all output frequencies. NUMERICALLY CONTROLLED OSCILLATOR The AD9684 has a 12-bit NCO for each DDC that enables the frequency translation process. The NCO allows the input spectrum to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. The NCO can be set up by providing a frequency tuning word (FTW) and a phase offset word (POW). • • • 0x800 represents a frequency of −fS/2. 0x000 represents dc (frequency is 0 Hz). 0x7FF represents a frequency of +fS/2 − fS/212. Calculate the NCO frequency tuning word using the following equation:  mod ( f C , f S )   NCO_ FTW = round 212  fS   where: NCO_FTW is a 12-bit, twos complement number representing the NCO FTW. fC is the desired carrier frequency in Hz. fS is the AD9684 sampling frequency (clock rate) in Hz. mod( ) is a remainder function. For example, mod(110,100) = 10, and for negative numbers, mod(−32, +10) = −2. round( ) is a rounding function. For example, round(3.6) = 4, and for negative numbers, round(−3.4) = −3. Note that this equation applies to the aliasing of signals in the digital domain (that is, aliasing introduced when digitizing analog signals). Rev. 0 | Page 38 of 64 Data Sheet AD9684 For example, if the ADC sampling frequency (fS) is 1250 MSPS and the carrier frequency (fC) is 416.667 MHz, Use the following two methods to synchronize multiple PAWs within the chip:  mod( 416.667,1250 )  NCO _ FTW = round  212  = 1365 MHz 1250   • This, in turn, converts to 0x555 in the 12-bit, twos complement representation for NCO_FTW. Calculate the actual carrier frequency based on the following equation: f C _ ACTUAL = NCO _ FTW × f S = 416.56 MHz 212 • A 12-bit POW is available for each NCO to create a known phase relationship between multiple AD9684 chips or individual DDC channels inside one AD9684 chip. The following procedure must be followed to update the FTW and/or POW registers to ensure proper operation of the NCO: 1. 2. 3. Write to the FTW registers for all the DDCs. Write to the POW registers for all the DDCs. Synchronize the NCOs either through the DDC soft reset bit, accessible through the SPI, or through the assertion of the SYNC± pins. Note that the NCOs must be synchronized either through the SPI or through the SYNC± pins after all writes to the FTW or POW registers are complete. This synchronization is necessary to ensure the proper operation of the NCO. NCO Synchronization Each NCO contains a separate phase accumulator word (PAW) that determines the instantaneous phase of the NCO. The initial reset value of each PAW is determined by the POW, described in the Setting Up the NCO FTW and POW section. The phase increment value of each PAW is determined by the FTW. Using the SPI. Use the DDC NCO soft reset bit in the DDC synchronization control register (Register 0x300, Bit 4) to reset all the PAWs in the chip. This is accomplished by toggling the DDC NCO soft reset bit. Note that this method synchronizes DDC channels within the same AD9684 chip only. Using the SYNC± pins. When the SYNC± pins are enabled in the SYNC± control registers (Register 0x120 and Register 0x121), and the DDC synchronization is enabled in Bits[1:0] in the DDC synchronization control register (Register 0x300), any subsequent SYNC± event resets all the PAWs in the chip. Note that this method synchronizes DDC channels within the same AD9684 chip or DDC channels within separate AD9684 chips. Mixer The NCO is accompanied by a mixer, which operates similarly to an analog quadrature mixer. It performs the downconversion of input signals (real or complex) by using the NCO frequency as a local oscillator. For real input signals, this mixer performs a real mixer operation with two multipliers. For complex input signals, the mixer performs a complex mixer operation with four multipliers and two adders. The mixer adjusts its operation based on the input signal (real or complex) provided to each individual channel. The selection of real or complex inputs can be controlled individually for each DDC block using Bit 7 of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). Rev. 0 | Page 39 of 64 AD9684 Data Sheet FIR FILTERS GENERAL DESCRIPTION Table 16 shows the different bandwidth options by including different half-band filters. In all cases, the DDC filtering stage of the AD9684 provides less than −0.001 dB of pass-band ripple and greater than 100 dB of stop band alias rejection. There are four sets of decimate by 2, low-pass, half-band, FIR filters (labeled HB1 FIR, HB2 FIR, HB3 FIR, and HB4 FIR in Figure 58) following the frequency translation stage. After the carrier of interest is tuned down to dc (carrier frequency = 0 Hz), these filters efficiently lower the sample rate while providing sufficient alias rejection from unwanted adjacent carriers around the bandwidth of interest. Table 17 shows the amount of stop band alias rejection for multiple pass-band ripple/cutoff points. The decimation ratio of the filtering stage of each DDC can be controlled individually through Bits[1:0] of the DDC control registers (Register 0x310, Register 0x330, Register 0x350, and Register 0x370). HB1 FIR is always enabled and cannot be bypassed. The HB2, HB3, and HB4 FIR filters are optional and can be bypassed for higher output sample rates. Table 16. DDC Filter Characteristics ADC Sample Rate (MSPS) 1000 1 DDC Decimation Ratio 2 (HB1) 4 (HB1 + HB2) 8 (HB1 + HB2 + HB3) 16 (HB1 + HB2 + HB3 + HB4) Real Output Sample Rate (MSPS) 1000 500 250 125 Complex (I/Q) Output Sample Rate (MSPS) 500 (I) + 500 (Q) 250 (I) + 250 (Q) 125 (I) + 125 (Q) 62.5 (I) + 62.5 (Q) Alias Protected Bandwidth (MHz) 385.0 192.5 96.3 48.1 Ideal SNR Improvement 1 (dB) 1 4 7 10 Pass-Band Ripple (dB) 100 The ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)). Table 17. DDC Filter Alias Rejection Alias Rejection (dB) >100 90 85 63.3 25 19.3 10.7 1 Pass-Band Ripple/Cutoff Point (dB)