14-Bit, 500 MSPS, JESD204B,
Quad Analog-to-Digital Converter
AD9694
Data Sheet
FEATURES
Amplitude detect bits for efficient AGC implementation
4 integrated wideband digital processors
48-bit NCO, up to 4 cascaded half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
On-chip temperature diode
Flexible JESD204B lane configurations
JESD204B (Subclass 1) coded serial digital outputs
Lane rates up to 15 Gbps
1.66 W total power at 500 MSPS
415 mW per ADC channel
SFDR = 82 dBFS at 305 MHz (1.80 V p-p input range)S
SNR = 66.8 dBFS at 305 MHz (1.80 V p-p input range)
Noise density = −151.5 dBFS/Hz (1.80 V p-p input range)
0.975 V, 1.8 V, and 2.5 V dc supply operation
No missing codes
Internal ADC voltage reference
Analog input buffer
On-chip dithering to improve small signal linearity
Flexible differential input range
1.44 V p-p to 2.16 V p-p (1.80 V p-p nominal)
1.4 GHz analog input full power bandwidth
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, W-CDMA, GSM, LTE, LTE-A
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence (SIGINT)
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD1_SR
(0.975V)
(0.975V)
VIN+A
BUFFER
ADC
CORE
VIN–A
AVDD2
(1.8V)
AVDD3
(2.5V)
DVDD
(0.975V)
FD_B
FAST
DETECT
ADC
CORE
VIN–B
SPIVDD
(1.8V)
JESD204B
HIGH SPEED
SERIALIZER
SIGNAL
MONITOR
BUFFER
VIN+B
DRVDD2
(1.8V)
DIGITAL DOWN
CONVERTER
(DDC)
14
VCM_AB
FD_A
DRVDD1
(0.975V)
2
SERDOUTAB0±
Tx
OUTPUTS
SERDOUTAB1±
DIGITAL DOWN
CONVERTER
(DDC)
14
SIGNAL
MONITOR
AND FAST
DETECT
CLK–
SYSREF±
JESD204B
SUBCLASS 1
CONTROL
CLOCK
GENERATION
CLK+
SYNCINB±AB
SYNCINB±CD
÷2
÷4
VIN+C
÷8
BUFFER
ADC
CORE
VIN–C
VCM_CD/VREF
FD_C
FAST
DETECT
DIGITAL DOWNCONVERTER
(DDC)
14
JESD204B
HIGH SPEED
SERIALIZER
SIGNAL
MONITOR
2
Tx
OUTPUTS
SERDOUTCD0±
SERDOUTCD1±
FD_D
VIN+D
VIN–D
BUFFER
ADC
CORE
DIGITAL DOWNCONVERTER
(DDC)
14
SPI CONTROL
PDWN/STBY
AGND_SR AGND DRGND
SDIO SCLK CSB
14808-001
AD9694
Figure 1.
Rev. B
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Technical Support
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AD9694
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Half-Band Filters ........................................................................ 43
Applications ....................................................................................... 1
DDC Gain Stage ......................................................................... 44
Functional Block Diagram .............................................................. 1
DDC Complex to Real Conversion ......................................... 44
Revision History ............................................................................... 3
DDC Example Configurations ................................................. 45
General Description ......................................................................... 4
Digital Outputs ............................................................................... 50
Product Highlights ........................................................................... 4
Introduction to the JESD204B Interface ................................. 50
Specifications..................................................................................... 5
Setting Up the AD9694 Digital Interface ................................ 50
DC Specifications ......................................................................... 5
Functional Overview ................................................................. 52
AC Specifications.......................................................................... 6
JESD204B Link Establishment ................................................. 52
Digital Specifications ................................................................... 9
Physical Layer (Driver) Outputs .............................................. 53
Switching Specifications ............................................................ 10
JESD204B Tx Converter Mapping ........................................... 54
Timing Specifications ................................................................ 11
Configuring the JESD204B Link .............................................. 56
Absolute Maximum Ratings.......................................................... 12
Latency ............................................................................................. 60
Thermal Resistance .................................................................... 12
End to End Total Latency .......................................................... 60
ESD Caution ................................................................................ 12
Example Latency Calculations.................................................. 60
Pin Configuration and Function Descriptions ........................... 13
LMFC referenced Latency ......................................................... 60
Typical Performance Characteristics ........................................... 15
Deterministic Latency.................................................................... 61
Equivalent Circuits ......................................................................... 22
Subclass 0 Operation.................................................................. 61
Theory of Operation ...................................................................... 24
Subclass 1 Operation.................................................................. 61
ADC Architecture ...................................................................... 24
Multichip Synchronization............................................................ 63
Analog Input Considerations.................................................... 24
Normal Mode.............................................................................. 63
Voltage Reference ....................................................................... 25
Timestamp Mode ....................................................................... 63
DC Offset Calibration ................................................................ 26
SYSREF± Input ........................................................................... 65
Clock Input Considerations ...................................................... 26
SYSREF± Setup/Hold Window Monitor ................................. 66
ADC Overrange and Fast Detect.................................................. 29
Test Modes ....................................................................................... 68
ADC Overrange .......................................................................... 29
ADC Test Modes ........................................................................ 68
Fast Threshold Detection (FD_A, FD_B, FD_C, and
FD_D) .......................................................................................... 29
JESD204B Block Test Modes .................................................... 69
Serial Port Interface ........................................................................ 71
Signal Monitor ................................................................................ 30
Configuration Using the SPI ..................................................... 71
SPORT Over JESD204B ............................................................. 30
Hardware Interface..................................................................... 71
Digital Downconverter (DDC) ..................................................... 33
SPI Accessible Features .............................................................. 71
DDC I/Q Input Selection .......................................................... 33
Memory Map .................................................................................. 72
DDC I/Q Output Selection ....................................................... 33
Reading the Memory Map Register Table............................... 72
DDC General Description ........................................................ 33
Memory Map Register Table—Details .................................... 73
Frequency Translation ................................................................... 39
Applications Information .............................................................. 95
Overview...................................................................................... 39
Power Supply Recommendations............................................. 95
DDC NCO and Mixer Loss and SFDR .................................... 40
Exposed Pad Thermal Heat Slug Recommendations ............ 95
Numerically Controlled Oscillator........................................... 40
AVDD1_SR (Pin 64) and AGND_SR (Pin 63 and Pin 67) ... 95
FIR Filters ........................................................................................ 42
Outline Dimensions ....................................................................... 96
Overview...................................................................................... 42
Ordering Guide .......................................................................... 96
Rev. B | Page 2 of 96
Data Sheet
AD9694
REVISION HISTORY
2/2018—Rev. A to Rev. B
Changed Document Title from Dual 14-Bit, 1.25 GSPS, 1.2 V/
2.5 V Analog-to-Digital Converter to 14-Bit, 500 MSPS,
JESD204B Analog-to-Digital Converter ......................... Universal
Change to Table 10 ..........................................................................14
Moved Temperature Diode Section ..............................................28
12/2017—Rev. 0 to Rev. A
Changed 1.8 V p-p to 1.80 V p-p ................................ Throughout
Changes to Figure 1........................................................................... 1
Changes to Endnote 3, Table 2 ........................................................ 7
Changes to Logic Outputs (FD_A, FD_B, FD_C, FD_D)
Parameter and DIGITAL OUTPUTS (SERDOUTABx±/
SERDOUTCDx±, x = 0 OR 1) Parameter, Table 5 ....................... 9
Changes to Output Parameter and Wake-Up Time Parameter,
Table 6 ...............................................................................................10
Changes to Table 9 ..........................................................................12
Changes to Table 10 ........................................................................13
Changes to Figure 18, Figure 19, Figure 20, and Figure 23 .......17
Changes to Figure 47 and Figure 48 .............................................22
Changes to Analog Input Considerations Section and
Differential Input Configurations Section ...................................24
Changes to Table 11 ........................................................................25
Changes to Voltage Reference Section, DC Offset Calibration
Section, and Figure 62 ....................................................................26
Changes to Clock Duty Cycle Considerations Section and
Figure 65 ...........................................................................................27
Added Input Clock Detect Section ...............................................27
Changes to Temperature Diode Section.......................................28
Changed General Description Section to Overview Section ....39
Changes to Overview Section........................................................ 42
Change to Phase-Locked Loop (PLL) Section ............................ 54
Change to Table 26 .......................................................................... 56
Changes to Table 27 ........................................................................ 57
Changes to Example 2: ADC with DDC Option (Two ADCs
Plus Two DDCs in Each Pair Section and Figure 92 .................. 58
Added Example Latency Calculations Section, Example
Configuration 1 Section, Example Configuration 2 Section,
Table 29, and Table 30; Renumbered Sequentially ..................... 60
Added Deterministic Latency Section, Subclass 0 Operation
Section, Subclass 1 Operation Section, Deterministic Latency
Requirements Section, Setting Deterministic Latency Registers
Section, and Figure 94; Renumbered Sequentially ..................... 61
Added Figure 95 and Figure 96 ..................................................... 62
Added Multichip Synchronization Section, Normal Mode
Section, Timestamp Mode Section, Figure 97............................. 63
Added Figure 98 .............................................................................. 64
Added SYSREF± Input Section, SYSREF± Control Features
Section, Figure 99, Figure 100, Figure 101, and Figure 102 ...... 65
Changes to SYSREF± Setup/Hold Window Monitor Section ... 66
Changes to ADC Test Modes Section .......................................... 68
Deleted Register Table Summary Section and Table 38;
Renumbered Sequentially ...................................................................... 69
Changes to Reading the Memory Map Register Table Section....... 72
Changes to Table 39 ........................................................................ 73
Changes to Power Supply Recommendations Section and
Figure 106 ......................................................................................... 95
10/2016—Revision 0: Initial Version
Rev. B | Page 3 of 96
AD9694
Data Sheet
GENERAL DESCRIPTION
The AD9694 is a quad, 14-bit, 500 MSPS analog-to-digital
converter (ADC). The device has an on-chip buffer and a
sample-and-hold circuit designed for low power, small size, and
ease of use. This device is designed for sampling wide bandwidth
analog signals of up to 1.4 GHz. The AD9694 is optimized for
wide input bandwidth, high sampling rate, excellent linearity,
and low power in a small package.
The quad ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
Users can configure each pair of intermediate frequency (IF)
receiver outputs onto either one or two lanes of Subclass 1
JESD204B-based high speed serialized outputs, depending on
the decimation ratio and the acceptable lane rate of the receiving
logic device. Multiple device synchronization is supported through
the SYSREF±, SYNCINB±AB, and SYNCINB±CD input pins.
The AD9694 has flexible power-down options that allow significant
power savings when desired. All of these features can be programmed using the 1.8 V capable, 3-wire SPI.
The AD9694 is available in a Pb-free, 72-lead LFCSP and is
specified over the −40°C to +105°C junction temperature range.
This product may be protected by one or more U.S. or
international patents.
The analog inputs and clock signals are differential inputs. Each
pair of ADC data outputs is internally connected to two DDCs
through a crossbar mux. Each DDC consists of up to five cascaded
signal processing stages: a 48-bit frequency translator, NCO,
and up to four half-band decimation filters.
PRODUCT HIGHLIGHTS
In addition to the DDC blocks, the AD9694 has several
functions that simplify the automatic gain control (AGC)
function in the communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input.
4.
5.
1.
2.
3.
6.
7.
Rev. B | Page 4 of 96
Low power consumption per channel.
JESD204B lane rate support up to 15 Gbps.
Wide full power bandwidth supports IF sampling of signals
up to 1.4 GHz.
Buffered inputs ease filter design and implementation.
Four integrated wideband decimation filters and numerically
controlled oscillator (NCO) blocks supporting multiband
receivers.
Programmable fast overrange detection.
On-chip temperature diode for system thermal management.
Data Sheet
AD9694
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, 500 MSPS, clock divider = 4, 1.80 V p-p full-scale differential input, 0.5 V internal reference, AIN = −1.0 dBFS, default
SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature
(TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
INPUT REFERRED NOISE
ANALOG INPUTS
Differential Input Voltage Range (Programmable)
Common-Mode Voltage (VCM)
Differential Input Capacitance 1
Differential Input Resistance
Analog Input Full Power Bandwidth
POWER SUPPLY
AVDD1
AVDD1_SR
AVDD2
AVDD3
DVDD
DRVDD1
DRVDD2
SPIVDD
IAVDD1
IAVDD1_SR
IAVDD2
IAVDD3
IDVDD 2
IDRVDD11
IDRVDD21
ISPIVDD
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers)2
Power-Down Dissipation
Standby 3
1
2
3
Min
14
Typ
Max
Guaranteed
0
0
−5.0
−0.7
−5.1
1.0
±0.4
±1.0
+5.0
3.7
+0.7
+5.1
8
214
0.5
2.6
All lanes running. Power dissipation on DRVDD1 changes with lane rate and number of lanes used.
Full bandwidth mode.
Standby mode is controlled by the SPI.
Rev. B | Page 5 of 96
Unit
Bits
% FSR
% FSR
% FSR
% FSR
LSB
LSB
ppm/°C
ppm/°C
V
LSB rms
1.44
1.80
1.34
1.75
200
1.4
2.16
V p-p
V
pF
Ω
GHz
0.95
0.95
1.71
2.44
0.95
0.95
1.71
1.71
0.975
0.975
1.8
2.5
0.975
0.975
1.8
1.8
319
21
438
87
121
162
23
1
1.00
1.00
1.89
2.56
1.00
1.00
1.89
1.89
482
53
473
103
180
207
29
1.6
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
1.66
325
1.20
2.07
W
mW
W
AD9694
Data Sheet
AC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.80 V p-p full-scale differential input, 0.5 V internal reference,
AIN = −1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full
operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 2. 500 MSPS AC Specifications
Parameter 1
ANALOG INPUT FULL SCALE
NOISE DENSITY 2
SIGNAL-TO-NOISE RATIO (SNR) 3
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
SIGNAL-TO-NOISE-AND-DISTORTION
RATIO (SINAD)
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
AT −3 dBFS
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
WORST HARMONIC, SECOND OR THIRD
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
Analog Input Full Scale =
1.44 V p-p
Min
Typ
Max
1.44
−149.7
65.4
65.3
65.2
65.0
64.8
64.5
Analog Input Full Scale =
1.80 V p-p
Min
Typ
Max
1.80
−151.5
Analog Input Full Scale =
2.16 V p-p
Min
Typ
Max
2.16
−153.0
Unit
V p-p
dBFS/Hz
67.1
67.0
66.8
66.6
66.5
66.0
68.4
68.3
68.0
67.8
67.5
66.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
67.0
66.8
66.6
66.4
66.1
65.5
68.2
67.9
67.6
67.3
66.9
66.2
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
10.8
10.8
10.7
10.7
10.6
10.6
11.0
10.9
10.9
10.8
10.8
10.7
Bits
Bits
Bits
Bits
Bits
Bits
90
85
82
83
75
79
80
77
78
77
72
76
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
94
94
89
87
82
85
94
90
90
86
80
82
86
82
83
84
77
79
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−89
−89
−82
−82
−77
−82
−90
−85
−82
−83
−75
−79
−80
−77
−78
−77
−72
−76
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
65.3
65.2
65.1
65.0
64.7
64.2
10.5
10.5
10.5
10.5
10.4
10.3
89
89
82
82
77
82
64.8
64.5
10.4
75
Rev. B | Page 6 of 96
−75
Data Sheet
Parameter 1
WORST HARMONIC, SECOND OR THIRD AT
−3 dBFS
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
WORST OTHER, EXCLUDING SECOND OR
THIRD HARMONIC
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
TWO-TONE INTERMODULATION
DISTORTION (IMD), AIN1 AND AIN2 =
−7 dBFS
fIN1 = 154 MHz, fIN2 = 157 MHz
fIN1 = 302 MHz, fIN2 = 305 MHz
CROSSTALK 4
FULL POWER BANDWIDTH 5
AD9694
Analog Input Full Scale =
1.44 V p-p
Min
Typ
Max
Analog Input Full Scale =
1.80 V p-p
Min
Typ
Max
−94
−94
−89
−87
−82
−85
−94
−90
−90
−86
−80
−82
−96
−97
−97
−95
−92
−90
−98
−97
−98
−96
−91
−89
−93
−90
82
1.4
−90
−90
82
1.4
Analog Input Full Scale =
2.16 V p-p
Min
Typ
Max
−86
Unit
−86
−82
−83
−84
−77
−79
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−99
−97
−97
−96
−88
−86
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−84
−84
82
1.4
dBFS
dBFS
dB
GHz
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Noise density is measured at a low analog input frequency (30 MHz).
3
See Table 11 for recommended settings for the buffer current setting.
4
Crosstalk is measured at 155 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel.
5
Measured with the circuit shown in Figure 56.
1
2
Table 3. 600 MSPS AC Specifications, Analog Input = 1.80 V p-p
Parameter 1
ANALOG INPUT FULL SCALE
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
Min
Rev. B | Page 7 of 96
Typ
1.80
Max
Unit
V p-p
66.6
67
66.8
66.4
66
65.5
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
66.5
66.8
66.5
66.3
65.4
64.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
86
81
81
84
76
75
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
AD9694
Data Sheet
Parameter 1
WORST HARMONIC, SECOND OR THIRD
fIN = 10 MHz
fIN = 155 MHz
fIN = 305 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
1
Min
Typ
Max
−86
−81
−81
−84
−76
−75
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Table 4. 600 MSPS Power Consumption
Parameter
POWER SUPPLY
AVDD1
AVDD1_SR
AVDD2
AVDD3
DVDD
DRVDD1
DRVDD2
SPIVDD
IAVDD1
IAVDD1_SR
IAVDD2
IAVDD3
IDVDD 1
IDRVDD1 2
IDRVDD22
ISPIVDD
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers)
1
2
Full bandwidth mode.
All lanes running. Power dissipation on DRVDD1 changes with lane rate and number of lanes used.
Rev. B | Page 8 of 96
Min
Typ
Max
Unit
0.95
0.95
1.71
2.44
0.95
0.95
1.71
1.71
0.975
0.975
1.8
2.5
0.975
0.975
1.8
1.8
352
23
443
87
146
183
23
1
1.00
1.00
1.89
2.56
1.00
1.00
1.89
1.89
513
55
478
104
200
235
28
1.6
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
1.75
2.16
W
Data Sheet
AD9694
DIGITAL SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, 500 MSPS, clock divider = 4, 1.80 V p-p full-scale differential input, 0.5 V internal reference, AIN = −1.0 dBFS, default
SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature
(TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 5.
Parameter
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
SYSTEM REFERENCE (SYSREF) INPUTS (SYSREF+, SYSREF−) 1
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Single-Ended per Pin)
LOGIC INPUTS (PDWN/STBY)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
LOGIC INPUTS (SDIO, SCLK, CSB)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
LOGIC OUTPUT (SDIO)
Logic Compliance
Logic 1 Voltage (IOH = 800 µA)
Logic 0 Voltage (IOL = 50 µA)
SYNCIN INPUT (SYNCINB+AB/SYNCINB−AB/
SYNCINB+CD/SYNCINB−CD)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Single Ended per Pin)
LOGIC OUTPUTS (FD_A, FD_B, FD_C, FD_D)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
DIGITAL OUTPUTS (SERDOUTABx±/SERDOUTCDx±, x = 0 OR 1)
Logic Compliance
Differential Output Voltage
Short-Circuit Current (ID SHORT)
Differential Termination Impedance
1
Min
600
400
0.6
18
Typ
Max
Unit
LVDS/LVPECL
800
1600
0.69
32
0.9
mV p-p
V
kΩ
pF
LVDS/LVPECL
800
1800
0.69
2.2
22
0.7
mV p-p
V
kΩ
pF
CMOS
0.65 × SPIVDD
0
0.35 × SPIVDD
V
V
MΩ
0.35 × SPIVDD
V
V
kΩ
10
CMOS
0.65 × SPIVDD
0
56
CMOS
SPIVDD − 0.45 V
0
400
0.6
18
0.45
LVDS/LVPECL/CMOS
800
1800
0.69
2.2
22
0.7
V
V
mV p-p
V
kΩ
pF
CMOS
0.8 × SPIVDD
0
DC-coupled input only.
Rev. B | Page 9 of 96
56
V
V
kΩ
CML
455.8
15
100
mV p-p
mA
Ω
0.5
AD9694
Data Sheet
SWITCHING SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, 500 MSPS, clock divider = 4, 1.80 V p-p full-scale differential input, 0.5 V internal reference, AIN = −1.0 dBFS, default
SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature
(TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
Table 6.
Parameter
CLOCK
Clock Rate (at CLK+/CLK− Pins)
Maximum Sample Rate 1
Minimum Sample Rate 2
Clock Pulse Width High
Clock Pulse Width Low
OUTPUT
Unit Interval (UI)3
Rise Time (tR) (20% to 80% into 100 Ω Load)
Fall Time (tF) (20% to 80% into 100 Ω Load)
PLL Lock Time
Data Rate per Channel (Nonreturn-to-Zero (NRZ))4
LATENCY 5
Pipeline Latency
Fast Detect Latency
WAKE-UP TIME
From Standby
From Power-Down
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tj)
Out of Range Recovery Time
Min
Typ
0.3
600
240
125
125
66.67
1.6875
100
31.25
31.37
5
10
Max
Unit
2.4
GHz
MSPS
MSPS
ps
ps
593
15
ps
ps
ps
ms
Gbps
30
Sample clock cycles
Sample clock cycles
54
3
10
ms
ms
160
44
1
ps
fs rms
Sample clock cycles
The maximum sample rate is the clock rate after the divider.
The minimum sample rate operates at 240 MSPS with L = 2 or L = 1. See SPI Register 0x011A to reduce the threshold of the clock detection circuit.
3
Baud rate = 1/UI. A subset of this range can be supported.
4
Default L = 2 for each link. This number can be changed based on the sample rate and decimation ratio.
5
No DDCs used. L = 2, M = 2, F = 2 for each link.
1
2
Rev. B | Page 10 of 96
Data Sheet
AD9694
TIMING SPECIFICATIONS
Table 7.
Parameter
CLK+ to SYSREF+ TIMING REQUIREMENTS
tSU_SR
tH_SR
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tACCESS
Test Conditions/Comments
See Figure 3
Device clock to SYSREF+ setup time
Device clock to SYSREF+ hold time
See Figure 4
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Maximum time delay between falling edge of SCLK and output
data valid for a read operation
Time required for the SDIO pin to switch from an output to an
input relative to the CSB rising edge (not shown in Figure 4)
tDIS_SDIO
Min
Typ
Max
Unit
−44.8
64.4
ps
ps
6
ns
ns
ns
ns
ns
ns
ns
ns
4
2
40
2
2
10
10
10
10
ns
Timing Diagrams
APERTURE
DELAY
SAMPLE N
N – 53
N+1
N – 54
N – 52
N – 51
N–1
N – 50
14808-002
ANALOG
INPUT
SIGNAL
CLK–
CLK+
Figure 2. Data Output Timing (Full Bandwidth Mode; L = 4, M = 2, F = 1)
CLK–
CLK+
tSU_SR
tH_SR
14808-003
SYSREF–
SYSREF+
Figure 3. SYSREF± Setup and Hold Timing
tHIGH
tDS
tS
tACCESS
tCLK
tDH
tH
tLOW
CSB
SDIO DON’T CARE
DON’T CARE
R/W
A14
A13
A12
A11
A10
A9
A8
A7
D7
Figure 4. Serial Port Interface Timing Diagram
Rev. B | Page 11 of 96
D6
D3
D2
D1
D0
DON’T CARE
14808-004
SCLK DON’T CARE
AD9694
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
Parameter
Electrical
AVDD1 to AGND
AVDD1_SR to AGND
AVDD2 to AGND
AVDD3 to AGND
DVDD to DGND
DRVDD1 to DRGND
DRVDD2 to DRGND
SPIVDD to AGND
VIN±x to AGND
CLK± to AGND
SCLK, SDIO, CSB to DGND
PDWN/STBY to DGND
SYSREF± to AGND_SR
SYNCINB±AB/SYNCINB±CD to
DRGND
Environmental
Operating Junction Temperature
Range
Maximum Junction Temperature
Storage Temperature Range
(Ambient)
Rating
1.05 V
1.05 V
2.00 V
2.70 V
1.05 V
1.05 V
2.00 V
2.00 V
−0.3 V to AVDD3 + 0.3 V
−0.3 V to AVDD1 + 0.3 V
−0.3 V to SPIVDD + 0.3 V
−0.3 V to SPIVDD + 0.3 V
0 V to 2.5 V
0 V to 2.5 V
−40°C to +105°C
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure.
θJC_BOT is the bottom junction to case thermal resistance.
Table 9. Thermal Resistance
PCB Type
JEDEC
2s2p Board
10-Layer Board
Airflow Velocity (m/sec)
0.0
1.0
2.5
0.0
θJA
21.581, 2
17.941, 2
16.581, 2
9.74
θJC_BOT
1.951, 4
N/A3
N/A3
1.00
Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
N/A means not applicable.
4
Per MIL-STD 883, Method 1012.1.
1
2
3
ESD CAUTION
125°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. B | Page 12 of 96
Unit
°C/W
°C/W
°C/W
°C/W
Data Sheet
AD9694
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
AVDD2
AVDD1
AVDD1
AVDD1
AVDD1
AGND_SR
SYSREF–
SYSREF+
AVDD1_SR
AGND_SR
AVDD1
CLK–
CLK+
AVDD1
AVDD1
AVDD1
AVDD1
AVDD2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
AD9694
TOP VIEW
(Not to Scale)
AVDD3
VIN–C
VIN+C
AVDD2
AVDD2
AVDD3
VIN+D
VIN–D
AVDD2
AVDD1
AVDD1
VCM_CD/VREF
DVDD
DGND
SPIVDD
CSB
SCLK
SDIO
NOTES
1. EXPOSED PAD. ANALOG GROUND. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE
PROVIDES THE GROUND REFERENCE FOR AVDDx, SPIVDD, DVDD, DRVDD1, AND DRVDD2.
THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
14808-005
SYNCINB–AB
SYNCINB+AB
DRGND
DRVDD1
SERDOUTAB0–
SERDOUTAB0+
SERDOUTAB1–
SERDOUTAB1+
SERDOUTCD1+
SERDOUTCD1–
SERDOUTCD0+
SERDOUTCD0–
DRVDD1
DRGND
SYNCINB+CD
SYNCINB–CD
FD_D
FD_C
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
AVDD3
VIN–A
VIN+A
AVDD2
AVDD2
AVDD3
VIN+B
VIN–B
AVDD2
AVDD1
AVDD1
VCM_AB
DVDD
DGND
DRVDD2
PDWN/STBY
FD_A
FD_B
Figure 5. Pin Configuration (Top View)
Table 10. Pin Function Descriptions
Pin No.
0
Mnemonic
AGND/EPAD
Type
Ground
1, 6, 49, 54
2, 3
4, 5, 9, 46, 50, 51, 55, 72
7, 8
10, 11, 44, 45, 56, 57, 58, 59,
62, 68, 69, 70, 71
12
AVDD3
VIN−A, VIN+A
AVDD2
VIN+B, VIN−B
AVDD1
Supply
Input
Supply
Input
Supply
VCM_AB
Output
13, 42
14, 41
15
16
DVDD
DGND
DRVDD2
PDWN/STBY
Supply
Ground
Supply
Input
17, 18, 35, 36
FD_A, FD_B, FD_D, FD_C
Output
19
SYNCINB−AB
Input
20
SYNCINB+AB
Input
Description
Exposed Pad. Analog Ground. The exposed thermal pad on
the bottom of the package provides the ground reference for
AVDDx, SPIVDD, DVDD, DRVDD1, and DRVDD2. This exposed
pad must be connected to ground for proper operation.
Analog Power Supply (2.5 V Nominal).
ADC A Analog Input Complement/True.
Analog Power Supply (1.8 V Nominal).
ADC B Analog Input True/Complement.
Analog Power Supply (0.975 V Nominal).
Common-Mode Level Bias Output for Analog Input Channel A
and Channel B.
Digital Power Supply (0.975 V Nominal).
Ground Reference for DVDD and SPIVDD.
Digital Power Supply for JESD204B PLL (1.8 V Nominal).
Power-Down Input/Standby (Active High). The operation of
this pin depends on the SPI mode and can be configured as
power-down or standby. This pin requires external 10 kΩ pulldown resistor.
Fast Detect Outputs for Channel A, Channel B, Channel C, and
Channel D.
Active Low JESD204B LVDS Sync Input Complement for
Channel A and Channel B.
Active Low JESD204B LVDS/CMOS Sync Input True for Channel A
and Channel B.
Rev. B | Page 13 of 96
AD9694
Data Sheet
Pin No.
21, 32
22, 31
Mnemonic
DRGND
DRVDD1
Type
Ground
Supply
23, 24
Output
33
SERDOUTAB0−,
SERDOUTAB0+
SERDOUTAB1−,
SERDOUTAB1+
SERDOUTCD1+,
SERDOUTCD1−
SERDOUTCD0+,
SERDOUTCD0−
SYNCINB+CD
Input
34
SYNCINB−CD
Input
37
38
39
40
43
SDIO
SCLK
CSB
SPIVDD
VCM_CD/VREF
Input/output
Input
Input
Supply
Output/input
47, 48
52, 53
60, 61
63, 67
64
65, 66
VIN−D, VIN+D
VIN+C, VIN−C
CLK+, CLK−
AGND_SR
AVDD1_SR
SYSREF+, SYSREF−
Input
Input
Input
Ground
Supply
Input
25, 26
27, 28
29, 30
EPAD
Output
Output
Output
Description
Ground Reference for DRVDD1 and DRVDD2.
Digital Power Supply for SERDOUTABx±/SERDOUTCDx± Pins
(0.975 V Nominal).
Lane 0 Output Data Complement/True for Channel A and
Channel B.
Lane 1 Output Data Complement/True for Channel A and
Channel B.
Lane 1 Output Data True/Complement for Channel C and
Channel D.
Lane 0 Output Data True/Complement for Channel C and
Channel D.
Active Low JESD204B LVDS/CMOS/LVPECL Sync Input True for
Channel C and Channel D.
Active Low JESD204B LVDS/CMOS/LVPECL Sync Input
Complement for Channel C and Channel D.
SPI Serial Data Input/Output.
SPI Serial Clock.
SPI Chip Select (Active Low).
Digital Power Supply for SPI (1.8 V Nominal).
Common-Mode Level Bias Output for Analog Input Channel C
and Channel D/0.5 V Reference Voltage Input. This pin is
configurable through the SPI as an output or an input. Use
this pin as the common-mode level bias output if using the
internal reference. This pin requires a 0.5 V reference voltage
input if using an external voltage reference source.
ADC D Analog Input Complement/True.
ADC C Analog Input True/Complement.
Clock Input True/Complement.
Ground Reference for SYSREF±.
Analog Power Supply for SYSREF± (0.975 V Nominal).
Active Low JESD204B LVDS System Reference Input
True/Complement. DC-coupled input only.
Exposed Pad. Analog ground. The exposed thermal pad on the
bottom of the package provides the ground reference for
AVDDX, SPIVDD, DVDD, DRVDD1, and DRVDD2. This exposed
pad must be connected to ground for proper operation.
Rev. B | Page 14 of 96
Data Sheet
AD9694
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.80 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V,
SPIVDD = 1.8 V, specified maximum sampling rate, clock divider = 4, 1.80 V p-p full-scale differential input, 0.5 V internal reference,
AIN = −1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full
operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C).
–20
–40
AMPLITUDE (dBFS)
–60
–80
–60
–80
–100
–100
–120
–120
50
100
150
200
250
FREQUENCY (MHz)
–140
14808-100
–140
0
–80
–60
–80
–100
–100
–120
–120
–140
100
150
200
250
FREQUENCY (MHz)
–140
0
–80
–80
–100
–120
–120
–140
150
200
FREQUENCY (MHz)
250
–60
–100
100
200
–40
AMPLITUDE (dBFS)
–60
50
150
AIN = –1dBFS
SNR = 66.0dB
SFDR = 79dBFS
ENOB = 10.6 BITS
–20
250
14808-102
AMPLITUDE (dBFS)
0
–40
0
100
Figure 10. Single-Tone FFT with fIN = 765 MHz
AIN = –1dBFS
SNR = 66.8dB
SFDR = 82dBFS
ENOB = 10.7 BITS
–20
50
FREQUENCY (MHz)
Figure 7. Single-Tone FFT with fIN = 155 MHz
0
250
–40
AMPLITUDE (dBFS)
–60
50
200
AIN = –1dBFS
SNR = 66.5dB
SFDR = 75dBFS
ENOB = 10.6 BITS
–20
14808-101
AMPLITUDE (dBFS)
0
–40
0
150
Figure 9. Single-Tone FFT with fIN = 453 MHz
AIN = –1dBFS
SNR = 67.0dB
SFDR = 85dBFS
ENOB = 10.8 BITS
–20
100
FREQUENCY (MHz)
Figure 6. Single-Tone FFT with fIN = 10.3 MHz
0
50
14808-103
–40
0
AIN = –1dBFS
SNR = 66.6dB
SFDR = 83dBFS
ENOB = 10.7 BITS
14808-104
–20
AMPLITUDE (dBFS)
0
AIN = –1dBFS
SNR = 67.10dB
SFDR = 90dBFS
ENOB = 10.8 BITS
–140
Figure 8. Single-Tone FFT with fIN = 305 MHz
0
50
100
150
200
FREQUENCY (MHz)
Figure 11. Single-Tone FFT with fIN = 985 MHz
Rev. B | Page 15 of 96
250
14808-105
0
AD9694
Data Sheet
94
90
93
92
85
SFDR
91
89
SFDR (dBFS)
SNR/SFDR (dBFS)
90
80
75
70
88
87
86
85
84
SNR
83
65
82
81
60
465
ANALOG INPUT FREQUENCY (MHz)
14808-109
365
265
245
225
205
185
165
145
125
105
85
65
10
650
SAMPLE RATE (MHz)
14808-106
625
600
575
550
525
500
475
450
425
400
375
350
325
300
275
250
225
200
175
80
Figure 15. SFDR vs. Analog Input Frequency (fIN), First and Second Nyquist
Zones; AIN at −3 dBFS
Figure 12. SNR/SFDR vs. Sample Rate (fS), fIN = 155 MHz
67.5
95
90
67.0
SNR (dBFS)
SNR/SFDR (dBFS)
85
80
SFDR (dBFS), –40°C
SFDR (dBFS), +50°C
SFDR (dBFS), +105°C
75
SNRFS, –40°C
SNRFS, +50°C
SNRFS, +105°C
70
66.5
65
14808-110
795
765
735
705
675
645
615
585
555
ANALOG INPUT FREQUENCY (MHz)
Figure 13. SNR/SFDR vs. Analog Input Frequency (fIN)
Figure 16. SNR vs. Analog Input Frequency (fIN), Third Nyquist Zone
AIN at −3 dBFS
67.5
94
67.4
93
67.3
92
67.2
91
67.1
90
67.0
89
66.9
SFDR (dBFS)
66.8
66.7
66.6
66.5
88
87
86
85
735
14808-111
ANALOG INPUT FREQUENCY (MHz)
Figure 14. SNR vs. Analog Input Frequency (fIN), First and Second Nyquist
Zones; AIN at −3 dBFS
705
675
645
465
465
365
14808-108
ANALOG INPUT FREQUENCY (MHz)
265
245
225
205
185
165
145
125
105
85
80
65
81
66.0
10
66.1
615
82
585
83
66.2
555
66.3
525
84
66.4
495
SNR (dBFS)
525
465
14808-107
565
465
365
265
245
225
205
185
165
145
125
105
85
65
10
ANALOG INPUT FREQUENCY (MHz)
495
66.0
60
Figure 17. SFDR vs. Analog Input Frequency (fIN), Third Nyquist Zone; AIN
at −3 dBFS
Rev. B | Page 16 of 96
Data Sheet
AD9694
AIN1 AND AIN2 = –7dBFS
SFDR = 86.4dBFS
SNR/SFDR (dB)
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–160
0
50
100
150
200
250
FREQUENCY (MHz)
14808-112
–140
Figure 18. Two-Tone FFT; fIN1 = 153.5 MHz, fIN2 = 156.5 MHz
AIN1 AND AIN2 = –7dBFS
SFDR = 85.9dFS
SNR/SFDR (dB)
AMPLITUDE (dBFS)
–40
–60
–80
–100
–120
–160
50
100
150
200
250
FREQUENCY (MHz)
14808-113
–140
0
SNRFS
SFDR (dBc)
SNR
–90
–80 –70 –60 –50 –40 –30 –20
ANALOG INPUT FREQUENCY (MHz)
–10
0
Figure 21. SNR/SFDR vs. Analog Input Frequency, fIN = 155 MHz
0
–20
SFDR (dBFS)
Figure 19. Two-Tone FFT; fIN1 = 303.5 MHz, fIN2 = 306.5 MHz
120
110
100
90
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
–100
SFDR (dBFS)
SNRFS
SFDR (dBc)
SNR
–90
–80 –70 –60 –50 –40 –30 –20
ANALOG INPUT FREQUENCY (MHz)
–10
0
14808-116
–20
120
110
100
90
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
–100
14808-115
0
Figure 22. SNR/SFDR vs. Analog Input Frequency, fIN = 305 MHz
0
90
SFDR
85
SFDR (dBc)
SNR/SFRDR (dBFS)
–40
IMD3 (dBc)
–60
–80
SFDR (dBFS)
80
75
70
SNR
–100
65
IMD3 (dBFS)
129
122
111
91
71
51
31
11
–10
JUNCTION TEMPERATURE (°C)
Figure 20. Two-Tone SFDR/IMD3 vs. Analog Input Amplitude (AIN) with
fIN1 = 303.5 MHz and fIN2 = 306.5 MHz
Figure 23. SNR/SFDR vs. Junction Temperature, fIN = 155 MHz
Rev. B | Page 17 of 96
14808-117
ANALOG INPUT AMPLITUDE (dBFS)
60
0
–31
–140
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12
–54
–120
14808-114
SFDR/IMD3 (dBc AND dBFS)
–20
AD9694
Data Sheet
2.0
1.85
1.5
1.80
1.75
POWER DISSIPATION (W)
0.5
0
–0.5
–1.0
1.70
1.65
1.60
1.55
1.50
16384
OUTPUT CODE
250
300
350
14808-118
15360
14336
13312
12288
11264
9216
10240
8192
7168
6144
5120
1024
4096
1.40
3072
–2.0
2048
1.45
0
–1.5
400
450
500
SAMPLE RATE (MSPS)
550
600
650
14808-122
INL (LSB)
1.0
Figure 27. Power Dissipation vs. Sample Rate (fS)
Figure 24. INL, fIN = 10.3 MHz
0
1.0
0.8
AIN = –1dBFS
SNRFS = 65.94dB
SFDR = 89.01dBFS
–20
0.6
–40
AMPLITUDE (dBFS)
DNL (LSB)
0.4
0.2
0
–0.2
–0.4
–60
–80
–100
–120
–0.6
OUTPUT CODE
–160
–125
–75
14808-119
16384
15360
14336
13312
12288
11264
10240
9216
8192
7168
5120
6144
4096
3072
2048
0
1024
–1.0
–25
25
FREQUENCY (MHz)
75
125
14808-123
–140
–0.8
Figure 28. DDC Mode (Four DDCs; Decimate by 2; L = 2, M = 4, and F = 4)
with fIN = 305 MHz
Figure 25. DNL, fIN = 10.3 MHz
0
6000
AIN = –1dBFS
SNRFS = 71.80dB
SFDR = 98.27dBFS
–20
5000
AMPLITUDE (dBFS)
4000
3000
2000
–60
–80
–100
–120
1000
Figure 26. Input Referred Noise Histogram
57.5
62.5
37.5
17.5
0
–22.5
–42.5
FREQUENCY (MHz)
14808-124
CODE
–62.5
–160
14808-120
0
–140
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
0
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
NUMBER OF HITS
–40
Figure 29. DDC Mode (Four DDCs; Decimate by 4; L = 1, M = 4, and F = 8)
with fIN = 305 MHz
Rev. B | Page 18 of 96
Data Sheet
AD9694
465
Figure 33. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (First and Second Nyquist Zones)
4.375
9.375
14.375
735
–0.625
FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
Figure 31. DDC Mode (Four DDCs, Decimate by 16, L = 1, M = 4, and F = 8)
with fIN = 305 MHz
Figure 34. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (Third Nyquist Zone)
67.0
66.9
66.8
66.7
66.6
SFDR (dBFS)
SNR (dBFS)
66.5
66.4
66.3
66.2
66.1
66.0
65.9
65.8
65.7
65.6
–80
–78
–76
–74
–72
–70
–68
–66
–64
–62
–60
–58
–56
–54
–52
–50
–48
–46
–44
–42
–40
BUFFER CURRENT
BUFFER CURRENT
BUFFER CURRENT
BUFFER CURRENT
= 320µA
= 360µA
= 400µA
= 440µA
730
760
790
820
850
880
910
940
970
1030
1060
1090
1120
1150
1180
1210
1240
1270
1300
1330
1360
1390
1420
1450
1480
1510
1540
1570
1600
1630
1660
1690
1720
1750
1780
1810
14808-129
0.118
0.132
0.148
0.166
0.185
0.207
0.234
0.262
0.293
0.328
0.370
0.416
0.468
0.526
0.587
0.693
0.778
0.873
0.979
1.091
1.209
1.322
1.482
1.653
1.833
65.5
DIFFERENTIAL VOLTAGE (V)
ANALOG INPUT FREQUENCY (MHz)
Figure 32. SNR vs. Differential Voltage (Clock Amplitude), fIN = 155.3 MHz
14808-131
–5.625
705
–10.625
465
–160
–15.625
14808-126
–140
= 200µA
= 240µA
= 280µA
= 320µA
675
–120
BUFFER CURRENT
BUFFER CURRENT
BUFFER CURRENT
BUFFER CURRENT
645
–100
615
–80
585
–60
SFDR (dBFS)
AMPLITUDE (dBFS)
–40
555
–20
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
–74
–73
–72
–71
–70
–69
–68
–67
–66
–65
525
AIN = –1dBFS
SNRFS = 74.50dB
SFDR = 100.68dBFS
495
0
14808-130
ANALOG INPUT FREQUENCY (MHz)
Figure 30. DDC Mode (Four DDCs; Decimate by 8; L = 1, M = 4, and F = 8)
with fIN = 305 MHz
14808-132
28.75
365
18.75
265
8.75
245
–1.25
FREQUENCY (MHz)
225
–11.25
= 160µA
= 200µA
= 240µA
= 280µA
205
–21.25
10
–160
–31.25
14808-125
–140
185
–120
165
–100
145
–80
125
–60
SFDR (dBFS)
AMPLITUDE (dBFS)
–40
BUFFER CURRENT
BUFFER CURRENT
BUFFER CURRENT
BUFFER CURRENT
85
–20
–95
–94
–93
–92
–91
–90
–89
–88
–87
–86
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
105
AIN = –1dBFS
SNRFS = 71.80dB
SFDR = 98.27dBFS
65
0
Figure 35. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (Fourth Nyquist Zone)
Rev. B | Page 19 of 96
AD9694
Data Sheet
Figure 37. SNR vs. Analog Input Frequency with Different Analog Input
Full Scales (Third Nyquist Zone)
–90
–89
–88
–87
–86
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
–74
–73
–72
–71
–70
14808-136
565
465
365
265
245
225
205
185
INPUT FULL SCALE = 1.44V
ANALOG INPUT FREQUENCY (MHz)
14808-137
795
765
735
705
675
645
615
585
465
INPUT FULL SCALE = 2.16V
555
SFDR (dBFS)
14808-134
735.3
705.3
675.3
645.3
615.3
585.3
555.3
525.3
495.3
INPUT FULL SCALE = 1.44V
ANALOG INPUT FREQUENCY (MHz)
165
ANALOG INPUT FREQUENCY (MHz)
Figure 39. SFDR vs. Analog Input Frequency with Different Analog Input
Full Scales (First and Second Nyquist Zones)
INPUT FULL SCALE = 2.16V
465.3
SNR (dBFS)
Figure 36. SNR vs. Analog Input Frequency with Different Analog Input
Full Scales (First and Second Nyquist Zones)
69.0
68.8
68.6
68.4
68.2
68.0
67.8
67.6
67.4
67.2
67.0
66.8
66.6
66.4
66.2
66.0
65.8
65.6
65.4
65.2
65.0
64.8
64.6
64.4
64.2
64.0
10
465
ANALOG INPUT FREQUENCY (MHz)
14808-133
365
265
245
225
205
185
165
145
125
105
85
65
10
64
145
65
125
INPUT FULL SCALE = 1.44V
INPUT FULL SCALE = 2.16V
525
66
495
67
INPUT FULL SCALE = 1.44V
85
SFDR (dBFS)
SNR (dBFS)
68
–90
–89
–88
–87
–86
–85
–84
–83
–82
–81
–80
–79
–78
–77
–76
–75
–74
–73
–72
–71
–70
105
INPUT FULL SCALE = 2.16V
65
69
Figure 40. SFDR vs. Analog Input Frequency with Different Analog Input
Full Scales (Third Nyquist Zone)
–81
68
INPUT FULL SCALE = 1.44V
–79
67
–77
INPUT FULL SCALE = 2.16V
–75
–73
65
SFDR (dBFS)
SNR (dBFS)
66
INPUT FULL SCALE = 1.44V
64
–71
–69
INPUT FULL SCALE = 2.16V
–67
–65
–63
–61
63
–59
1780
1720
1660
14808-138
ANALOG INPUT FREQUENCY (MHz)
1600
1540
1480
1420
1360
1300
1240
1180
1120
970
1060
910
850
14808-135
730
760
790
820
850
880
910
940
970
1000
1030
1060
1090
1120
1150
1180
1210
1240
1270
1300
1330
1360
1390
1420
1450
1480
1510
1540
1570
1600
1630
1660
1690
1720
1750
1780
1810
ANALOG INPUT FREQUENCY (MHz)
Figure 38. SNR vs. Analog Input Frequency with Different Analog Input
Full Scales (Fourth Nyquist Zone)
790
–55
730
–57
62
Figure 41. SFDR vs. Analog Input Frequency with Different Analog Input
Full Scales (Fourth Nyquist Zone)
Rev. B | Page 20 of 96
Data Sheet
AD9694
2
0
0.16
–2
0.14
–4
POWER (dB)
0.18
0.12
0.10
0.08
–6
–8
–10
–12
0.06
–14
0.04
–16
0.02
–18
Figure 43. Full Power Bandwidth
Rev. B | Page 21 of 96
1595
1800
1545
14808-200
ANALOG INPUT FREQUENCY (MHz)
Figure 42. AVDD3 Power vs. Buffer Current Setting
1495
1445
–20
1495
600
1345
550
1295
500
1245
450
1145
400
1195
350
1075
300
575
250
BUFFER CURRENT SETTING (µA)
825
200
0
150
325
0
100
14808-139
AVDD3 POWER (W)
0.20
AD9694
Data Sheet
EQUIVALENT CIRCUITS
AVDD3
EMPHASIS/SWING
CONTROL (SPI)
AVDD3
DRVDD1
VIN+x
DATA+
SERDOUTABx+/SERDOUTCDx+
x = 0, 1
AVDD3
100Ω
DRGND
OUTPUT
DRIVER
400Ω
VCM
BUFFER
DRVDD1
DATA–
SERDOUTABx–/SERDOUTCDx–
x = 0, 1
10pF
100Ω
AVDD3
DRGND
AVDD3
14808-027
3.5pF
3.5pF
AIN
CONTROL
(SPI)
14808-024
VIN–x
Figure 44. Analog Inputs
Figure 47. Digital Outputs
AVDD1
DRGND
2.5kΩ
16kΩ
SYNCINB+AB/
SYNCINB+CD
AVDD1
DRVDD1
100Ω
10kΩ
1.9pF
25Ω
16kΩ
130kΩ
DRGND
LEVEL
TRANSLATOR
DRGND
VCM = 0.95V
14808-025
CLK–
130kΩ
SYNCINB–AB/
SYNCINB–CD
CMOS
PATH
SYNCINB PIN
CONTROL (SPI)
DRVDD1
10kΩ
100Ω
1.9pF
DRGND
14808-028
CLK+
DRVDD1
25Ω
DRGND
Figure 48. SYNCINB±AB, SYNCINB±CD Inputs
Figure 45. Clock Inputs
AVDD1_SR
100Ω
10kΩ
1.9pF
ESD
PROTECTED
SCLK
130kΩ
56kΩ
LEVEL
TRANSLATOR
130kΩ
100Ω
ESD
PROTECTED
DGND
AVDD1_SR
10kΩ
1.9pF
14808-026
SYSREF–
SPIVDD
Figure 49. SCLK Input
Figure 46. SYSREF± Inputs
Rev. B | Page 22 of 96
DGND
14808-029
SYSREF+
SPIVDD
Data Sheet
AD9694
SPIVDD
SPIVDD
ESD
PROTECTED
ESD
PROTECTED
56kΩ
PDWN/
STBY
ESD
PROTECTED
ESD
PROTECTED
DGND
14808-030
DGND
DGND
DGND
Figure 50. CSB Input
Figure 53. PDWN/STBY Input
SPIVDD
SPIVDD
AVDD2
DGND
ESD
PROTECTED
DGND
DGND
AGND
SPIVDD
SDO
DGND
Figure 51. SDIO Input
Figure 54. VCM_CD/VREF Input/Output
SPIVDD
ESD
PROTECTED
SPIVDD
FD
JESD204B LMFC
56kΩ
JESD204B SYNC
DGND
FD_x PIN CONTROL (SPI)
DGND
14808-032
DGND
VREF PIN
CONTROL (SPI)
14808-031
56kΩ
Figure 52. FD_A/FD_B/FD_C/FD_D Outputs
Rev. B | Page 23 of 96
14808-034
EXTERNAL REFERENCE
VOLTAGE INPUT
VCM_CD/VREF
SDIO
ESD
PROTECTED
TEMPERATURE
DIODE VOLTAGE
SDI
ESD
PROTECTED
FD_A/FD_B/
FD_C/FD_D
PDWN
CONTROL (SPI)
14808-033
CSB
AD9694
Data Sheet
THEORY OF OPERATION
ADC ARCHITECTURE
Differential Input Configurations
The architecture of the AD9694 consists of an input buffered
pipelined ADC. The input buffer is designed to provide a 200 Ω
termination impedance to the analog input signal. The equivalent
circuit diagram of the analog input termination is shown in
Figure 44.
There are several ways to drive the AD9694, either actively or
passively. However, optimum performance is achieved by
driving the analog input differentially.
The input buffer provides a linear high input impedance (for
ease of drive) and reduces kickback from the ADC. The buffer
is optimized for high linearity, low noise, and low power. The
quantized outputs from each stage are combined into a final
14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate with a new input
sample while the remaining stages operate with the preceding
samples at the same time. Sampling occurs on the rising edge of
the clock.
For applications where SNR and SFDR are key parameters,
differential transformer coupling is the recommended input
configuration (see Figure 55 and Figure 56) because the noise
performance of most amplifiers is not adequate to achieve the
true performance of the AD9694.
For low to midrange frequencies, a double balun or double
transformer network (see Figure 55) is recommended for
optimum performance of the AD9694. For higher frequencies
in the third or fourth Nyquist zones, remove some of the frontend passive components to ensure wideband operation (see
Figure 56).
ANALOG INPUT CONSIDERATIONS
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. In the case of the
AD9694, the available span is programmable through the SPI
port from 1.44 V p-p to 2.16 V p-p differential, with 1.80 V p-p
differential being the default.
10Ω
2pF
0Ω
10Ω
50Ω
VIN+x
10Ω
0.1µF
BALUN
2pF
AGND
0.1µF
50Ω
10Ω
10Ω
0Ω
10Ω
VIN–x
2pF
AGND
Figure 55. Differential Transformer Coupled Configuration for First and
Second Nyquist Frequencies
AGND
0.1µF
10Ω
DNI
0Ω
50Ω
10Ω
VIN+x
DNI
0.1µF
BALUN
DNI
AGND
0.1µF
50Ω
10Ω
DNI
0Ω
10Ω
VIN–x
DNI
Dither
The AD9694 has internal on-chip dither circuitry that improves
the ADC linearity and SFDR, particularly at smaller signal
levels. A known but random amount of white noise is injected
into the input of the AD9694. This dither improves the small
signal linearity within the ADC transfer function and is precisely
subtracted out digitally. The dither is turned on by default and
does not reduce the ADC input dynamic range. The data sheet
specifications and limits are obtained with the dither turned on.
The dither can be disabled using SPI writes to Register 0x0922.
Disabling the dither can slightly improve the SNR (by about 0.2 dB)
at the expense of the small signal SFDR.
AGND
Figure 56. Differential Transformer Coupled Configuration for Third and
Fourth Nyquist Zones
Rev. B | Page 24 of 96
14808-039
For best dynamic performance, the source impedances driving
VIN+x and VIN−x must be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference
buffer creates a differential reference that defines the span of the
ADC core.
AGND
0.1µF
14808-038
The analog input to the AD9694 is a differential buffer with an
internal common-mode voltage of 1.34 V. The clock signal
alternately switches the input circuit between sample mode and
hold mode. Either a differential capacitor or two single-ended
capacitors can be placed on the inputs to provide a matching
passive network. This configuration ultimately creates a low-pass
filter at the input, which limits unwanted broadband noise. See
Figure 55 and Figure 56 for details on input network
recommendations.
Data Sheet
AD9694
Input Common Mode
0.20
The analog inputs of the AD9694 are internally biased to the
common mode as shown in Figure 57.
0.18
For dc-coupled applications, the recommended operation procedure
is to export the common-mode voltage to the VCM_CD/VREF
pin using the SPI writes listed in this section. The common-mode
voltage must be set by the exported value to ensure proper ADC
operation. Disconnect the internal common-mode buffer from
the analog input using Register 0x1908.
0.14
AVDD3 POWER (W)
0.16
2.
3.
4.
5.
6.
7.
8.
0.08
0.06
0.02
0
100
150
200
250
300
350
400
450
500
550
600
BUFFER CURRENT SETTING (µA)
14808-139
Set Register 0x1908, Bit 2 to 1 to disconnect the internal
common-mode buffer from the analog input.
Set Register 0x18A6 to 0x00 to turn off the voltage
reference.
Set Register 0x18E6 to 0x00 to turn off the temperature
diode export.
Set Register 0x18E0 to 0x04.
Set Register 0x18E1 to 0x1C.
Set Register 0x18E2 to 0x14.
Set Register 0x18E3, Bit 6 to 0x01 to turn on the VCM export.
Set Register 0x18E3, Bits[5:0] to the buffer current setting
(copy the buffer current setting from Register 0x1A4C and
Register 0x1A4D to improve the accuracy of the commonmode export).
0.10
0.04
When performing SPI writes for dc coupling operation, use the
following register settings in order:
1.
0.12
Figure 58. AVDD3 Power vs. Buffer Current Setting
In certain high frequency applications, the SFDR can be
improved by reducing the full-scale setting.
Table 11 shows the recommended buffer current settings for the
different analog input frequency ranges.
Table 11. SFDR Optimization for Input Frequencies
Nyquist Zone
First, Second, and
Third Nyquist
Fourth Nyquist
Input Buffer Current Control Setting,
Register 0x1A4C and Register 0x1A4D
240 µA (Register 0x1A4C, Bits[5:0] =
Register 0x1A4D, Bits[5:0] = 01100)
400 µA (Register 0x1A4C, Bits[5:0] =
Register 0x1A4D, Bits[5:0] = 10100)
Analog Input Controls and SFDR Optimization
Absolute Maximum Input Swing
The AD9694 offers flexible controls for the analog inputs, such
as buffer current and input full-scale adjustment. All of the
available controls are shown in Figure 57.
The absolute maximum input swing allowed at the inputs of the
AD9694 is 4.3 V p-p differential. Signals operating near or at
this level can cause permanent damage to the ADC.
AVDD3
VOLTAGE REFERENCE
AVDD3
A stable and accurate 0.5 V voltage reference is built into the
AD9694. This internal 0.5 V reference is used to set the fullscale input range of the ADC. The full-scale input range can be
adjusted via Register 0x1910. For more information on adjusting
the input swing, see Table 39. Figure 59 shows the block diagram
of the internal 0.5 V reference controls.
VIN+x
3.5pF
AVDD3
100Ω
400Ω
VCM
BUFFER
10pF
100Ω
VIN+A/
VIN+B
AVDD3
AVDD3
VIN–A/
VIN–B
VIN–x
INTERNAL
VREF
GENERATOR
VREF
Figure 57. Analog Input Controls
Using Register 0x1A4C and Register 0x1A4D, the buffer currents
on each channel can be scaled to optimize the SFDR over various
input frequencies and bandwidths of interest. As the input
buffer currents are set, the amount of current required by the
AVDD3 supply changes. This relationship is shown in Figure 58.
For a complete list of buffer current settings, see Table 39.
Rev. B | Page 25 of 96
ADC
CORE
FULL-SCALE
VOLTAGE
ADJUST
INPUT FULL-SCALE
RANGE ADJUST
SPI REGISTER
(0x1910)
VREF PIN
CONTROL SPI
REGISTER
(0x18A6)
Figure 59. Internal Reference Configuration and Controls
14808-040
AIN
CONTROL
(SPI)
14808-037
3.5pF
AD9694
Data Sheet
INTERNAL
VREF
GENERATOR
FULL-SCALE
VOLTAGE
ADJUST
ADR130
NC
2
GND SET 5
3
VIN
0.1µF
NC 6
VOUT 4
VREF
0.1µF
VREF PIN AND
FULL-SCALE
VOLTAGE
CONTROL
14808-042
INPUT
1
Figure 60. External Reference Using the ADR130
The SPI writes required to use the external voltage reference, in
order, are as follows:
The use of an external reference can be necessary, in some
applications, to enhance the gain accuracy of the ADC or to
improve thermal drift characteristics.
Figure 61 shows a preferred method for clocking the AD9694. The
low jitter clock source is converted from a single-ended signal to
a differential signal using an RF transformer.
0.1µF
CLOCK
INPUT
1:1Z
CLK+
100Ω
50Ω
ADC
CLK–
0.1µF
Figure 61. Transformer Coupled Differential Clock
The external reference must be a stable 0.5 V reference. The
ADR130 is a sufficient option for providing the 0.5 V reference.
Figure 60 shows how the ADR130 provides the external 0.5 V
reference to the AD9694. The dashed lines show unused blocks
within the AD9694 while using the ADR130 to provide the
external reference.
Another option is to ac couple a differential CML or LVDS
signal to the sample clock input pins, as shown in Figure 62 and
Figure 63.
3.3V
71Ω
10pF
33Ω
33Ω
Z0 = 50Ω
DC OFFSET CALIBRATION
0.1µF
CLK+
The AD9694 contains a digital filter to remove the dc offset
from the output of the ADC. For ac-coupled applications, this
filter can be enabled by setting Register 0x0701, Bit 7 to 1 and
setting Register 0x073B, Bit 7 to 0. The filter computes the
average dc signal, and it is digitally subtracted from the ADC
output. As a result, the dc offset is improved to better than
70 dBFS at the output. Because the filter does not distinguish
between the source of dc signals, this feature can be used when
the signal content at dc is not of interest. The filter corrects dc
up to ±512 codes and saturates beyond that.
ADC
CLK–
Z0 = 50Ω
0.1µF
Figure 62. Differential CML Sample Clock
0.1µF
0.1µF
0.1µF
LVDS
DRIVER
100Ω
50Ω1
50Ω1
0.1µF
RESISTORS ARE OPTIONAL.
Figure 63. Differential LVDS Sample Clock
Rev. B | Page 26 of 96
ADC
CLK–
CLK–
CLOCK INPUT
150Ω
CLK+
CLK+
CLOCK INPUT
14808-045
3.
Set Register 0x18E3 to 0x00 to turn off VCM export.
Set Register 0x18E6 to 0x00 to turn off temperature diode
export.
Set Register 0x18A6 to 0x01 to turn on the external voltage
reference.
For optimum performance, drive the AD9694 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled to the CLK+ and CLK− pins via a
transformer or clock drivers. These pins are biased internally
and require no additional biasing.
14808-044
1.
2.
CLOCK INPUT CONSIDERATIONS
14808-043
Register 0x18A6 enables the user to either use this internal 0.5 V
reference, or to provide an external 0.5 V reference. When using
an external voltage reference, provide a 0.5 V reference. The
full-scale adjustment is made using the SPI, irrespective of the
reference voltage. For more information on adjusting the fullscale level of the AD9694, refer to the Memory Map section.
Data Sheet
AD9694
Clock Duty Cycle Considerations
130
Typical high speed ADCs use both clock edges to generate a variety
of internal timing signals. The AD9694 contains an internal clock
divider and a duty cycle stabilizer (DCS). In applications where the
clock duty cycle cannot be guaranteed to be 50%, a higher multiple
frequency clock along with the usage of the clock divider is recommended. When it is not possible to provide a higher frequency
clock, it is recommended to turn on the DCS. The output of the
divider offers a 50% duty cycle, high slew rate (fast edge) clock
signal to the internal ADC. The following SPI writes are
required to turn on DCS (see the Memory Map section for
more details on using this feature):
120
Write 0x81 to 0x011F.
Write 0x09 to 0x011C.
Write 0x09 to 0x011E.
Write 0x0B to 0x011C.
Write 0x0B to 0x011E.
110
IDEAL SNR (dB)
100
80
70
60
50
40
30
10
100
1000
10000
ANALOG INPUT FREQUENCY (MHz)
Figure 65. Ideal SNR vs. Analog Input Frequency over Jitter
Input Clock Divider
The AD9694 contains an input clock divider with the ability to
divide the input clock by 1, 2, 4, or 8. The divider ratios can be
selected using Register 0x0108 (see Figure 64).
In applications where the clock input is a multiple of the sample
clock, care must be taken to program the appropriate divider ratio
into the clock divider before applying the clock signal, which
ensures that the current transients during device startup are
controlled.
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9694. Separate the
power supplies for clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
If the clock is generated from another type of source (by gating,
dividing, or other methods), retime the clock by the original clock
at the last step. Refer to the AN-501 Application Note and the
AN-756 Application Note for more in depth information about
jitter performance as it relates to ADCs.
Figure 65 shows the estimated SNR of the AD9694 across input
frequency for different clock induced jitter values. The SNR can
be estimated by using the following equation:
− SNRJITTER
−SNRADC
SNR(dBFS) = −10log 10 10 + 10 10
CLK+
CLK–
90
14808-047
1.
2.
3.
4.
5.
12.5fS
25fS
50fS
100fS
200fS
400fS
800fS
÷2
÷4
Input Clock Detect
REG 0x0108
14808-046
÷8
Figure 64. Clock Divider Circuit
The AD9694 clock divider can be synchronized using the external
SYSREF± input. A valid SYSREF± causes the clock divider to
reset to a programmable state. This synchronization feature
allows multiple devices to have their clock dividers aligned to
guarantee simultaneous input sampling.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fA) due only to aperture jitter (tJ) can be calculated by
SNR = −20 × log (2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root
mean square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter specifications. IF
undersampling applications are particularly sensitive to jitter
(see Figure 65).
The AD9694 contains input clock detection circuitry to detect
the signal on the input clock pins. If the clock amplitude or the
sample rate is lower than the specified minimum value, the
AD9694 enters power-down mode. When the input clock detect
bit in Register 0x011B is set to 0, the input clock is not detected.
See Register 0x011A and Register 0x011B for more details on
the input clock detect feature.
Power-Down/Standby Mode
The AD9694 has a PDWN/STBY pin that configures the
device in power-down or standby mode. The default operation
is power-down. The PDWN/STBY pin is a logic high pin. When
in power-down mode, the JESD204B link is disrupted. The
power-down option can also be set via Register 0x003F and
Register 0x0040.
In standby mode, the JESD204B link is not disrupted and
transmits zeros for all converter samples. This state can be
changed using Register 0x0571, Bit 7 to select /K/ characters.
Rev. B | Page 27 of 96
AD9694
Data Sheet
5.
Set Register 0x18E6 to 0x02 to turn on the second central
temperature diode of the pair, which is 20× the size of the
first. For the method using two diodes simultaneously to
achieve a more accurate result, see the AN-1432 Application
Note, Practical Thermal Modeling and Measurements in
High Power ICs.
The AD9694 contains a diode-based temperature sensor for
measuring the temperature of the die. This diode can output a
voltage and serve as a coarse temperature sensor to monitor the
internal die temperature.
The SPI writes required to export the temperature diode are as
follows (see Table 39 for more information):
1.
2.
3.
4.
0.80
TEMPERATURE DIODE VOLTAGE (V)
The temperature diode voltage can be output to the VCM_CD/
VREF pin using the SPI. Use Register 0x18E6 to enable or disable
the diode. Register 0x18E6 is a local register. Both cores must be
selected in the pair index register (Register 0x0009 = 0x03) to
enable the temperature diode readout. It is important to note
that other voltages may be exported to the same pin at the same
time, which can result in undefined behavior. Thus, to ensure a
proper readout, switch off all other voltage exporting circuits as
detailed as follows.
Set Register 0x0009 to 0x03 to select both cores.
Set Register 0x18E3 to 0x00 to turn off VCM export.
Set Register 0x18A6 to 0x00 to turn off voltage reference
export.
Set Register 0x18E6 to 0x01 to turn on voltage export of
the central 1× temperature diode. The typical voltage
response of the temperature diode is shown in Figure 66.
Although this voltage represents the die temperature, it is
recommended to take measurements from a pair of diodes
for improved accuracy. The next step explains how to
enable the 20× diode.
Rev. B | Page 28 of 96
0.75
0.70
0.65
0.60
0.55
0.50
–40
–20
0
20
40
60
80
100
JUNCTION TEMPERATURE (°C)
Figure 66. Temperature Diode Voltage vs. Junction Temperature
14808-048
Temperature Diode
Data Sheet
AD9694
ADC OVERRANGE AND FAST DETECT
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located at Register 0x0247 and Register 0x0248. The selected
threshold register is compared with the signal magnitude at the
output of the ADC. The fast upper threshold detection has a
latency of 30 clock cycles (maximum). The approximate upper
threshold magnitude is defined by
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overrange bit in the JESD204B outputs provides
information on the state of the analog input that is of limited
usefulness. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce the gain
before the clip actually occurs. In addition, because input
signals can have significant slew rates, the latency of this
function is of major concern. Highly pipelined converters can
have significant latency. The AD9694 contains fast detect
circuitry for individual channels to monitor the threshold and
to assert the FD_A, FD_B, FD_C, and FD_D pins.
Upper Threshold Magnitude (dBFS) = 20log (Threshold
Magnitude/213)
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Register 0x0249 and Register 0x024A. The
fast detect lower threshold register is a 13-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to the ADC pipeline latency, but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
ADC OVERRANGE
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange indicator can
be embedded within the JESD204B link as a control bit (when
CSB > 0). The latency of this overrange indicator matches the
sample latency.
FAST THRESHOLD DETECTION (FD_A, FD_B, FD_C,
AND FD_D)
Lower Threshold Magnitude (dBFS) = 20log (Threshold
Magnitude/213)
The fast detect (FD) bits in Register 0x0040 are immediately set
whenever the absolute value of the input signal exceeds the
programmable upper threshold level. The FD bits are cleared
only when the absolute value of the input signal drops below the
lower threshold level for greater than the programmable dwell
time. This feature provides hysteresis and prevents the FD bits
from excessively toggling.
For example, to set an upper threshold of −6 dBFS, write 0xFFF
to Register 0x0247 and Register 0x0248. To set a lower threshold of
−10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located at Register 0x024B and Register 0x024C. See
the Memory Map section (Register 0x0040, and Register 0x0245 to
Register 0x024C in Table 39) for more details.
The operation of the upper threshold and lower threshold
registers, along with the dwell time registers, is shown in
Figure 67.
UPPER THRESHOLD
DWELL TIME
TIMER RESET BY
RISE ABOVE
LOWER
THRESHOLD
DWELL TIME
FD_A OR FD_B
Figure 67. Threshold Settings for the FD_A and FD_B Signals
Rev. B | Page 29 of 96
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE
LOWER THRESHOLD
14808-050
MIDSCALE
LOWER THRESHOLD
AD9694
Data Sheet
SIGNAL MONITOR
The signal monitor block provides additional information about
the signal being digitized by the ADC. The signal monitor
computes the peak magnitude of the digitized signal. This
information can be used to drive an AGC loop to optimize the
range of the ADC in the presence of real-world signals.
The results of the signal monitor block can be obtained either
by reading back the internal values from the SPI port or by
embedding the signal monitoring information into the
JESD204B interface as special control bits. A global, 24-bit
programmable period controls the duration of the measurement.
Figure 68 shows the simplified block diagram of the signal
monitor block.
FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
(SMPR)
0x0271, 0x0272, 0x0273
DOWN
COUNTER
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding
register, which can be read through the memory map or output
through the SPORT over the JESD204B interface. The monitor
period timer is reloaded with the value in the SMPR, and the
countdown restarts. In addition, the magnitude of the first
input sample is updated in the magnitude storage register, and
the comparison and update procedure, as explained in the Fast
Threshold Detection (FD_A, FD_B, FD_C, and FD_D) section,
continues.
IS
COUNT = 1?
LOAD
FROM
INPUT
LOAD
LOAD
SIGNAL
MONITOR
HOLDING
REGISTER
SPORT OVER JESD204B
TO SPORT OVER
JESD204B AND
MEMORY MAP
14808-051
CLEAR
MAGNITUDE
STORAGE
REGISTER
COMPARE
A>B
Figure 68. Signal Monitor Block
The peak detector captures the largest signal within the
observation period. The detector only observes the magnitude
of the signal. The resolution of the peak detector is a 13-bit
value, and the observation period is 24 bits and represents
converter output samples. The peak magnitude can be derived
by using the following equation:
Peak Magnitude (dBFS) = 20log(Peak Detector Value/213)
The magnitude of the input port signal is monitored over a
programmable time period, which is determined by the signal
monitor period register (SMPR). The peak detector function is
enabled by setting Bit 1 of Register 0x0270 in the signal monitor
control register. The 24-bit SMPR must be programmed before
activating this mode.
After enabling peak detection mode, the value in the SMPR is
loaded into a monitor period timer, which decrements at the
decimated clock rate. The magnitude of the input signal is
compared with the value in the internal magnitude storage register
(not accessible to the user), and the greater of the two is updated
as the current peak level. The initial value of the magnitude
storage register is set to the current ADC input signal magnitude.
This comparison continues until the monitor period timer reaches
a count of 1.
The signal monitor data can also be serialized and sent over the
JESD204B interface as control bits. These control bits must be
deserialized from the samples to reconstruct the statistical data.
The signal control monitor function is enabled by setting Bit 0 of
Register 0x0279 and Bit 1 of Register 0x027A. Figure 69 shows
two different example configurations for the signal monitor control
bit locations inside the JESD204B samples. A maximum of three
control bits can be inserted into the JESD204B samples; however,
only one control bit is required for the signal monitor. Control
bits are inserted from MSB to LSB. If only one control bit is to be
inserted (CS = 1), only the most significant control bit is used (see
thed Example Configuration 1 and the Example Configuration 2 in
Figure 69). To select the SPORT over JESD204B (signal monitor)
option, program Register 0x0559, Register 0x055A, and
Register 0x058F. See Table 39 for more information on setting
these bits.
Figure 70 shows the 25-bit frame data that encapsulates the
peak detector value. The frame data is transmitted MSB first
with five 5-bit subframes. Each subframe contains a start bit
that can be used by a receiver to validate the deserialized data.
Figure 71 shows the SPORT over JESD204B signal monitor data
with a monitor period timer set to 80 samples.
Rev. B | Page 30 of 96
Data Sheet
AD9694
16-BIT JESD204B SAMPLE SIZE (N' = 16)
EXAMPLE
CONFIGURATION 1
(N' = 16, N = 15, CS = 1)
1-BIT
CONTROL
BIT
(CS = 1)
15-BIT CONVERTER RESOLUTION (N = 15)
15
S[14]
X
14
S[13]
X
13
S[12]
X
12
11
S[11]
X
10
S[10]
X
9
S[9]
X
8
S[8]
X
7
S[7]
X
6
S[6]
X
5
S[5]
X
S[4]
X
4
S[3]
X
3
S[2]
X
2
S[1]
X
1
0
S[0]
X
CTRL
[BIT 2]
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
16-BIT JESD204B SAMPLE SIZE (N' = 16)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S[13]
X
S[12]
X
S[11]
X
S[10]
X
S[9]
X
S[8]
X
S[7]
X
S[6]
X
S[5]
X
S[4]
X
S[3]
X
S[2]
X
S[1]
X
S[0]
X
CTRL
[BIT 2]
X
TAIL
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
Figure 69. Signal Monitor Control Bit Locations
5-BIT SUBFRAMES
5-BIT IDLE
SUBFRAME
(OPTIONAL)
25-BIT
FRAME
IDLE
1
IDLE
1
IDLE
1
IDLE
1
IDLE
1
5-BIT IDENTIFIER START
0
SUBFRAME
ID[3]
0
ID[2]
0
ID[1]
0
ID[0]
1
5-BIT DATA
MSB
SUBFRAME
START
0
P[12]
P[11]
P[10]
P[9]
5-BIT DATA
SUBFRAME
START
0
P[8]
P[7]
P[6]
P[5]
5-BIT DATA
SUBFRAME
START
0
P[4]
P[3]
P[2]
P[1]
5-BIT DATA
LSB
SUBFRAME
START
0
P[0]
0
0
0
P[ ] = PEAK MAGNITUDE VALUE
14808-053
EXAMPLE
CONFIGURATION 2
(N' = 16, N = 14, CS = 1)
Figure 70. SPORT over JESD204B Signal Monitor Frame Data
Rev. B | Page 31 of 96
14808-052
1
CONTROL
BIT
1 TAIL
(CS = 1)
BIT
14-BIT CONVERTER RESOLUTION (N = 14)
AD9694
Data Sheet
SMPR = 80 SAMPLES (0x0271 = 0x50; 0x0272 = 0x00; 0x0273 = 0x00)
80-SAMPLE PERIOD
PAYLOAD 3
25-BIT FRAME (N)
IDENTIFIER
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
80-SAMPLE PERIOD
PAYLOAD 3
25-BIT FRAME (N + 1)
IDENTIFIER
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
80-SAMPLE PERIOD
IDENTIFIER
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
Figure 71. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples
Rev. B | Page 32 of 96
14808-054
PAYLOAD 3
25-BIT FRAME (N + 2)
Data Sheet
AD9694
DIGITAL DOWNCONVERTER (DDC)
The AD9694 includes four digital downconverters (DDCs) that
provide filtering and reduce the output data rate. This digital
processing section includes an NCO, a half-band decimating
filter, a finite impulse response (FIR filter, a gain stage, and a
complex to real conversion stage. Each of these processing blocks
has control lines that allow it to be independently enabled and
disabled to provide the desired processing function. Each pair
of ADC channels has two DDCs (DDC0 and DDC1) for a total
of four DDCs. The digital downconverter can be configured to
output either real data or complex output data.
The DDCs output a 16-bit stream. To enable this operation, the
converter number of bits, N, is set to a default value of 16, even
though the analog core only outputs 14 bits. In full bandwidth
operation, the ADC outputs are the 14-bit word followed by two
zeros, unless the tail bits are enabled.
DDC I/Q INPUT SELECTION
The AD9694 has four ADC channels and four DDC channels.
Each DDC channel has two input ports that can be paired to
support both real and complex inputs through the I/Q crossbar
mux. For real signals, both DDC input ports must select the
same ADC channel (that is, DDC Input Port I = ADC Channel A
and DDC Input Port Q = ADC Channel A). For complex
signals, each DDC input port must select different ADC
channels (that is, DDC Input Port I = ADC Channel A and
DDC Input Port Q = ADC Channel B or DDC Input Port I =
ADC Channel C and DDC Input Port Q = ADC Channel D).
The inputs to each DDC are controlled by the DDC input selection registers (Register 0x0311 and Register 0x0331) in conjunction
with the pair index register (Register 0x0009). See Table 39 for
information on how to configure the DDCs.
DDC I/Q OUTPUT SELECTION
Each DDC channel has two output ports that can be paired to
support both real and complex outputs. For real output signals,
only the DDC Output Port I is used (the DDC Output Port Q is
invalid). For complex I/Q output signals, both DDC Output
Port I and DDC Output Port Q are used.
The I/Q outputs to each DDC channel are controlled by the
DDC x complex to real enable bit, Bit 3, in the DDC control
registers (Register 0x0310 and Register 0x0330) in conjunction
with the pair index register (Register 0x0009).
The Chip Q ignore bit in the chip mode register (Register 0x0200,
Bit 5) controls the chip output muxing of all the DDC channels.
When all DDC channels use real outputs, set this bit high to
ignore all DDC Q output ports. When any of the DDC channels
are set to use complex I/Q outputs, the user must clear this bit
to use both DDC Output Port I and DDC Output Port Q. For
more information, see Figure 80.
DDC GENERAL DESCRIPTION
The four DDC blocks are used to extract a portion of the full
digital spectrum captured by the ADC(s). The DDC blocks are
intended for IF sampling or oversampled baseband radios
requiring wide bandwidth input signals.
Each DDC block contains the following signal processing stages:
•
•
•
•
Frequency translation stage (optional)
Filtering stage
Gain stage (optional)
Complex to real conversion stage (optional)
Frequency Translation Stage (Optional)
This stage consists of a 48-bit complex NCO and quadrature
mixers that can be used for frequency translation of both real
and complex input signals. This stage shifts a portion of the
available digital spectrum down to baseband.
Filtering Stage
After shifting down to baseband, this stage decimates the frequency
spectrum using a chain of up to four half-band low-pass filters
for rate conversion. The decimation process lowers the output
data rate, which in turn reduces the output interface rate.
Gain Stage (Optional)
To compensate for losses associated with mixing a real input
signal down to baseband, this stage adds an additional 0 dB or
6 dB of gain.
Complex to Real Conversion Stage (Optional)
When real outputs are necessary, this stage converts the complex
outputs back to real by performing an fS/4 mixing operation
plus a filter to remove the complex component of the signal.
Figure 72 shows the detailed block diagram of the DDCs
implemented in the AD9694.
Rev. B | Page 33 of 96
AD9694
Data Sheet
REAL/I
CONVERTER 0
Q CONVERTER 1
SYSREF±
GAIN = 0dB
OR 6dB
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
REAL/Q Q
GAIN = 0dB
OR 6dB
NCO
+
MIXER
(OPTIONAL)
ADC
SAMPLING
AT fS
HB1 FIR
DCM = 2
I
HB2 FIR
DCM = BYPASS OR 2
REAL/I
HB3 FIR
DCM = BYPASS OR 2
DDC 1
REAL/I
CONVERTER 2
JESD204B TRANSMIT INTERFACE
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
GAIN = 0dB
OR 6dB
HB1 FIR
DCM = 2
HB2 FIR
DCM = BYPASS OR 2
HB4 FIR
DCM = BYPASS OR 2
REAL/Q Q
HB4 FIR
DCM = BYPASS OR 2
REAL/Q
NCO
+
MIXER
(OPTIONAL)
ADC
SAMPLING
AT fS
I/Q CROSSBAR MUX
REAL/I
I
HB3 FIR
DCM = BYPASS OR 2
DDC 0
REAL/I
L
JESD204B
LANES
AT UP TO
15Gbps
Q CONVERTER 3
SYSREF±
REAL/I
CONVERTER 2
L
JESD204B
LANES
AT UP TO
15Gbps
Q CONVERTER 3
HB1 FIR
DCM = 2
14808-055
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
GAIN = 0dB
OR 6dB
NCO
+
MIXER
(OPTIONAL)
HB1 FIR
DCM = 2
I
HB2 FIR
DCM = BYPASS OR 2
REAL/I
JESD204B TRANSMIT INTERFACE
Q CONVERTER 1
DDC 1
ADC
SAMPLING
AT fS
SYNCHRONIZATION
CONTROL CIRCUITS
REAL/I
CONVERTER 0
SYSREF±
REAL/Q Q
SYSREF
HB2 FIR
DCM = BYPASS OR 2
REAL/Q Q
HB4 FIR
DCM = BYPASS OR 2
NCO
+
MIXER
(OPTIONAL)
HB3 FIR
DCM = BYPASS OR 2
REAL/Q
ADC
SAMPLING
AT fS
I
HB4 FIR
DCM = BYPASS OR 2
REAL/I
I/Q CROSSBAR MUX
REAL/I
HB3 FIR
DCM = BYPASS OR 2
DDC 0
SYSREF±
Figure 72. DDC Detailed Block Diagram
Figure 73 shows an example usage of one of the four DDC blocks
with a real input signal and four half-band filters (HB4 + HB3 +
HB2 + HB1). It shows both complex (decimate by 16) and real
(decimate by 8) output options.
When DDCs have different decimation ratios, the chip decimation
ratio register (Register 0x0201) must be set to the lowest decimation ratio of all the DDC blocks on a per pair basis in conjunction
with the pair index register (Register 0x0009). In this scenario,
samples of higher decimation ratio DDCs are repeated to match
the chip decimation ratio sample rate. Whenever the NCO
frequency is set or changed, the DDC soft reset must be issued.
If the DDC soft reset is not issued, the output may potentially
show amplitude variations.
Table 12 through Table 16 show the DDC samples when the chip
decimation ratio is set to 1, 2, 4, 8, or 16, respectively. When
DDCs have different decimation ratios, the chip decimation
ratio must be set to the lowest decimation ratio of all the DDC
channels. In this scenario, samples of higher decimation ratio
DDCs are repeated to match the chip decimation ratio sample
rate.
Rev. B | Page 34 of 96
Data Sheet
AD9694
ADC
ADC
SAMPLING
AT fS
REAL
REAL INPUT—SAMPLED AT fS
BANDWIDTH OF
INTEREST IMAGE
–fS/2
–fS/3
BANDWIDTH OF
INTEREST
fS/32
–fS/32
DC
–fS/16
fS/16
–fS/8
–fS/4
REAL
fS/2
fS/3
fS/4
fS/8
FREQUENCY TRANSLATION STAGE (OPTIONAL)
I
DIGITAL MIXER + NCO
FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND
((fS/3)/fS × 248) = +9.382513
(0x5555_5555_5555)
NCO TUNES CENTER OF
BANDWIDTH OF INTEREST
TO BASEBAND
cos(ωt)
REAL
48-BIT
NCO
90°
0°
–sin(ωt)
Q
DIGITAL FILTER
RESPONSE
–fS/2
–fS/3
fS/32
–fS/32
DC
–fS/16
fS/16
–fS/8
–fS/4
BANDWIDTH OF
INTEREST IMAGE
(–6dB LOSS DUE TO
NCO + MIXER)
BANDWIDTH OF INTEREST
(–6dB LOSS DUE TO
NCO + MIXER)
fS/2
fS/3
fS/4
fS/8
FILTERING STAGE
I
HALFBAND
FILTER
Q
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
HALFBAND
FILTER
2
I
HB1 FIR
HB2 FIR
HB3 FIR
HB4 FIR
HB1 FIR
HB2 FIR
HB3 FIR
HB4 FIR
4 DIGITAL HALF-BAND FILTERS
(HB4 + HB3 + HB2 + HB1)
HALFBAND
FILTER
2
Q
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
DIGITAL FILTER
RESPONSE
0dB OR 6dB GAIN
I
GAIN STAGE (OPTIONAL)
Q
0dB OR 6dB GAIN
COMPLEX TO REAL
CONVERSION STAGE (OPTIONAL)
fS/32
–fS/32
DC
–fS/16
fS/16
–fS/8
COMPLEX (I/Q) OUTPUTS
DECIMATE BY 16
GAIN STAGE (OPTIONAL)
2
+6dB
2
+6dB
Q
fS/32
–fS/32
DC
–fS/16
fS/16
fS/8
fS/4 MIXING + COMPLEX FILTER TO REMOVE Q
I
DOWNSAMPLE BY 2
I
REAL (I) OUTPUTS
+6dB
I
DECIMATE BY 8
Q
+6dB
Q
COMPLEX REAL/I
TO
REAL
–fS/8
fS/32
–fS/32
DC
–fS/16
fS/16
fS/8
Figure 73. DDC Theory of Operation Example (Real Input, Decimate by 16)
Rev. B | Page 35 of 96
14808-056
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
AD9694
Data Sheet
Table 12. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 1
HB1 FIR
(DCM1 = 1)
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 16
N + 17
N + 18
N + 19
N + 20
N + 21
N + 22
N + 23
N + 24
N + 25
N + 26
N + 27
N + 28
N + 29
N + 30
N + 31
1
Real (I) Output (Complex to Real Enabled)
HB2 FIR +
HB3 FIR + HB2
HB4 FIR + HB3 FIR +
HB1 FIR
FIR + HB1 FIR
HB2 FIR + HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
N
N
N
N
N
N
N+1
N
N
N+1
N
N
N+2
N+1
N
N+2
N+1
N
N+3
N+1
N
N+3
N+1
N
N+4
N+2
N+1
N+4
N+2
N+1
N+5
N+2
N+1
N+5
N+2
N+1
N+6
N+3
N+1
N+6
N+3
N+1
N+7
N+3
N+1
N+7
N+3
N+1
N+8
N+4
N+2
N+8
N+4
N+2
N+9
N+4
N+2
N+9
N+4
N+2
N + 10
N+5
N+2
N + 10
N+5
N+2
N + 11
N+5
N+2
N + 11
N+5
N+2
N + 12
N+6
N+3
N + 12
N+6
N+3
N + 13
N+6
N+3
N + 13
N+6
N+3
N + 14
N+7
N+3
N + 14
N+7
N+3
N + 15
N+7
N+3
N + 15
N+7
N+3
Complex (I/Q) Outputs (Complex to Real Disabled)
HB2 FIR +
HB3 FIR + HB2
HB4 FIR + HB3 FIR +
HB1 FIR
HB1 FIR
FIR + HB1 FIR
HB2 FIR + HB1 FIR
(DCM1 = 2) (DCM1 = 4)
(DCM1 = 8)
(DCM1 = 16)
N
N
N
N
N
N
N
N
N+1
N
N
N
N+1
N
N
N
N+2
N+1
N
N
N+2
N+1
N
N
N+3
N+1
N
N
N+3
N+1
N
N
N+4
N+2
N+1
N
N+4
N+2
N+1
N
N+5
N+2
N+1
N
N+5
N+2
N+1
N
N+6
N+3
N+1
N
N+6
N+3
N+1
N
N+7
N+3
N+1
N
N+7
N+3
N+1
N
N+8
N+4
N+2
N+1
N+8
N+4
N+2
N+1
N+9
N+4
N+2
N+1
N+9
N+4
N+2
N+1
N + 10
N+5
N+2
N+1
N + 10
N+5
N+2
N+1
N + 11
N+5
N+2
N+1
N + 11
N+5
N+2
N+1
N + 12
N+6
N+3
N+1
N + 12
N+6
N+3
N+1
N + 13
N+6
N+3
N+1
N + 13
N+6
N+3
N+1
N + 14
N+7
N+3
N+1
N + 14
N+7
N+3
N+1
N + 15
N+7
N+3
N+1
N + 15
N+7
N+3
N+1
DCM means decimation.
Table 13. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 2
Real (I) Output (Complex to Real Enabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
N
N
N
N+1
N
N
N+2
N+1
N
N+3
N+1
N
N+4
N+2
N+1
N+5
N+2
N+1
N+6
N+3
N+1
N+7
N+3
N+1
N+8
N+4
N+2
N+9
N+4
N+2
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 16)
N
N
N
N
N+1
N
N
N
N+2
N+1
N
N
N+3
N+1
N
N
N+4
N+2
N+1
N
N+5
N+2
N+1
N
N+6
N+3
N+1
N
N+7
N+3
N+1
N
N+8
N+4
N+2
N+1
N+9
N+4
N+2
N+1
Rev. B | Page 36 of 96
Data Sheet
Real (I) Output (Complex to Real Enabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
(DCM 1 = 2)
(DCM1 = 4)
(DCM1 = 8)
N + 10
N+5
N+2
N + 11
N+5
N+2
N + 12
N+6
N+3
N + 13
N+6
N+3
N + 14
N+7
N+3
N + 15
N+7
N+3
1
AD9694
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 16)
N + 10
N+5
N+2
N+1
N + 11
N+5
N+2
N+1
N + 12
N+6
N+3
N+1
N + 13
N+6
N+3
N+1
N + 14
N+7
N+3
N+1
N + 15
N+7
N+3
N+1
DCM means decimation.
Table 14. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 4
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
HB3 FIR + HB2 FIR +
(DCM1 = 8)
HB1 FIR (DCM 1 = 4)
N
N
N+1
N
N+2
N+1
N+3
N+1
N+4
N+2
N+5
N+2
N+6
N+3
N+7
N+3
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
HB3 FIR + HB2 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 4)
HB1 FIR (DCM1 = 8)
(DCM1 = 16)
N
N
N
N+1
N
N
N+2
N+1
N
N+3
N+1
N
N+4
N+2
N+1
N+5
N+2
N+1
N+6
N+3
N+1
N+7
N+3
N+1
DCM means decimation.
Table 15. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 8
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 8)
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR + HB2 FIR +
HB3 FIR + HB2 FIR + HB1 FIR
HB1 FIR (DCM1 = 16)
(DCM1 = 8)
N
N
N+1
N
N+2
N+1
N+3
N+1
N+4
N+2
N+5
N+2
N+6
N+3
N+7
N+3
DCM means decimation.
Table 16. DDC Samples in Each JESD204B Link When Chip Decimation Ratio = 16
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM 1 = 16)
Not applicable
Not applicable
Not applicable
Not applicable
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)
N
N+1
N+2
N+3
DCM means decimation.
Rev. B | Page 37 of 96
AD9694
Data Sheet
For example, if the chip decimation ratio is set to decimate by 4,
DDC 0 is set to use the HB2 + HB1 filters (complex outputs,
decimate by 4) and DDC 1 is set to use the HB4 + HB3 + HB2 +
HB1 filters (real outputs, decimate by 8). DDC 1 repeats its
output data two times for every one DDC 0 output. The resulting
output samples are shown in Table 17.
Table 17. DDC Output Samples in Each JESD204B Link When Chip DCM 1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real)
DDC Input Samples
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
1
Output Port I
I0 (N)
DDC 0
Output Port Q
Q0 (N)
I0 (N + 1)
Q0 (N + 1)
I0 (N + 2)
Q0 (N + 2)
I0 (N + 3)
Q0 (N + 3)
DCM means decimation.
Rev. B | Page 38 of 96
Output Port I
I1 (N)
I1 (N + 1)
DDC 1
Output Port Q
Not applicable
Not applicable
Data Sheet
AD9694
FREQUENCY TRANSLATION
OVERVIEW
Variable IF Mode
Frequency translation is accomplished by using a 48-bit
complex NCO with a digital quadrature mixer. This stage
translates either a real or complex input signal from an IF to a
baseband complex digital output (carrier frequency = 0 Hz).
The NCO and mixers are enabled. NCO output frequency can
be used to digitally tune the IF frequency.
0 Hz IF (ZIF) Mode
The mixers are bypassed, and the NCO is disabled.
The frequency translation stage of each DDC can be controlled
individually and supports four different IF modes using Bits[5:4]
of the DDC control registers (Register 0x0310 and Register 0x0330)
in conjunction with the pair index register (Register 0x0009).
These IF modes are
The mixers and the NCO are enabled in special downmixing by
fS/4 mode to save power.
Test Mode
Input samples are forced to 0.9599 to positive full scale. The
NCO is enabled. This test mode allows the NCOs to directly
drive the decimation filters.
Variable IF mode
0 Hz IF or zero IF (ZIF) mode
fS/4 Hz IF mode
Test mode
Figure 74 and Figure 75 show examples of the frequency
translation stage for both real and complex inputs.
NCO FREQUENCY TUNING WORD (FTW) SELECTION
48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 248
I
ADC + DIGITAL MIXER + NCO
REAL INPUT—SAMPLED AT fS
REAL
cos(ωt)
ADC
SAMPLING
AT fS
REAL
48-BIT
NCO
90°
0°
COMPLEX
–sin(ωt)
Q
BANDWIDTH OF
INTEREST
BANDWIDTH OF
INTEREST IMAGE
–fS/2
–fS/3
–fS/4
–fS/8
fS/32
–fS/32
DC
fS/16
–fS/16
fS/8
fS/4
fS/3
fS/2
–6dB LOSS DUE TO
NCO + MIXER
48-BIT NCO FTW =
ROUND ((fS/3)/fS × 248) =
+9.3825 13 (0x555555555555)
POSITIVE FTW VALUES
–fS/32
DC
fS/32
48-BIT NCO FTW =
ROUND ((–fS/3)/fS × 248) =
–9.3825 13 (0xFFFF000000000000)
NEGATIVE FTW VALUES
–fS/32
DC
fS/32
Figure 74. DDC NCO Frequency Tuning Word Selection—Real Inputs
Rev. B | Page 39 of 96
14808-057
•
•
•
•
fS/4 Hz IF Mode
AD9694
Data Sheet
NCO FREQUENCY TUNING WORD (FTW) SELECTION
48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 248
QUADRATURE ANALOG MIXER +
2 ADCs + QUADRATURE DIGITAL REAL
MIXER + NCO
COMPLEX INPUT—SAMPLED AT fS
QUADRATURE MIXER
ADC
SAMPLING
AT fS
I
+
I
I
Q
Q
90°
PHASE
48-BIT
NCO
90°
0°
Q
Q
ADC
SAMPLING
AT fS
Q
Q
I
I
–
–sin(ωt)
I
I
+
COMPLEX
Q
+
BANDWIDTH OF
INTEREST
IMAGE DUE TO
ANALOG I/Q
MISMATCH
–fS/3
–fS/4
–fS/32
fS/32
fS/16
–fS/16
DC
–fS/8
fS/8
fS/4
fS/3
fS/2
48-BIT NCO FTW =
ROUND (( fS/3)/fS × 248) =
+9.3825 13 (0x555555555555)
POSITIVE FTW VALUES
–fS/32
fS/32
14808-058
–fS/2
DC
Figure 75. DDC NCO Frequency Tuning Word Selection—Complex Inputs
DDC NCO AND MIXER LOSS AND SFDR
Setting Up the NCO FTW and POW
When mixing a real input signal down to baseband, 6 dB of loss
is introduced in the signal due to filtering of the negative image.
An additional 0.05 dB of loss is introduced by the NCO. The total
loss of a real input signal mixed down to baseband is 6.05 dB. For
this reason, it is recommended that the user compensate for this
loss by enabling the 6 dB of gain in the gain stage of the DDC to
recenter the dynamic range of the signal within the full scale of
the output bits.
The NCO frequency value is given by the 32-bit twos
complement number entered in the NCO FTW. Frequencies
between −fS/2 and +fS/2 (fS/2 excluded) are represented using
the following frequency words:
When mixing a complex input signal down to baseband, the
maximum value that each I/Q sample can reach is 1.414 × full
scale after it passes through the complex mixer. To avoid overrange of the I/Q samples and to keep the data bit widths aligned
with real mixing, 3.06 dB of loss is introduced in the mixer for
complex signals. An additional 0.05 dB of loss is introduced by
the NCO. The total loss of a complex input signal mixed down
to baseband is −3.11 dB.
The worst case spurious signal from the NCO is greater than
102 dBc SFDR for all output frequencies.
NUMERICALLY CONTROLLED OSCILLATOR
The AD9694 has a 48-bit NCO for each DDC that enables the
frequency translation process. The NCO allows the input spectrum
to be tuned to dc, where it can be effectively filtered by the subsequent filter blocks to prevent aliasing. The NCO can be set up
by providing a frequency tuning word (FTW) and a phase offset
word (POW).
•
•
•
0x800 represents a frequency of −fS/2.
0x000 represents dc (frequency is 0 Hz).
0x7FF represents a frequency of +fS/2 − fS/212.
The NCO frequency tuning word can be calculated using the
following equation:
mod ( f C , f S )
NCO _ FTW = round 2 48
fS
where:
NCO_FTW is a 48-bit twos complement number representing
the NCO FTW.
fC is the desired carrier frequency in Hz.
fS is the AD9694 sampling frequency (clock rate) in Hz.
round( ) is a rounding function. For example, round(3.6) = 4
and for negative numbers, round(–3.4) = −3.
mod( ) is a remainder function. For example, mod(110,100) =
10 and for negative numbers, mod(–32,10) = −2.
This equation applies to the aliasing of signals in the digital
domain (that is, aliasing introduced when digitizing analog
signals).
Rev. B | Page 40 of 96
Data Sheet
AD9694
For example, if the ADC sampling frequency (fS) is 500 MSPS
and the carrier frequency (fC) is 140.312 MHz, then
mod(140.312,500 )
NCO _ FTW = round 2 48
=
500
7.89886 × 1013 Hz
This, in turn, converts to 0x47D in the 12-bit twos complement
representation for NCO_FTW. The actual carrier frequency,
fC_ACTUAL, is calculated based on the following equation:
f C _ ACTUAL =
NCO _ FTW × f S
= 140.312 MHz
2 48
A 48-bit POW is available for each NCO to create a known phase
relationship between multiple AD9694 chips or individual DDC
channels inside one AD9694 chip.
Use the following procedure to update the FTW and/or POW
registers to ensure proper operation of the NCO:
1.
2.
3.
Write to the FTW registers for all the DDCs.
Write to the POW registers for all the DDCs.
Synchronize the NCOs either through the DDC NCO soft
reset bit (Register 0x0300, Bit 4), which is accessible through
the SPI or through the assertion of the SYSREF± pin.
It is important to note that the NCOs must be synchronized
either through the SPI or through the SYSREF± pin after all
writes to the FTW or POW registers are complete. This step is
necessary to ensure the proper operation of the NCO.
NCO Synchronization
Each NCO contains a separate phase accumulator word (PAW).
The initial reset value of each PAW is set to zero and the phase
increment value of each PAW is determined by the FTW. The
POW is added to the PAW to produce the instantaneous phase
of the NCO. See the Setting Up the NCO FTW and POW section
for more information.
Use the following two methods to synchronize multiple PAWs
within the chip:
• Using the SPI. Use the DDC NCO soft reset bit in the DDC
synchronization control register (Register 0x0300, Bit 4) to
reset all the PAWs in the chip, which is accomplished by
setting the DDC NCO soft reset bit high and then setting
this bit low. This method can only be used to synchronize
DDC channels within the same pair (A/B or C/D) of a
AD9694 chip.
• Using the SYSREF± pin. When the SYSREF± pin is enabled
in the SYSREF± control registers (Register 0x0120 and
Register 0x0121) and the DDC synchronization is enabled
in the DDC synchronization control register (Register 0x0300,
Bits[1:0]), any subsequent SYSREF± event resets all the
PAWs in the chip. This method can be used to synchronize
DDC channels within the same AD9694 chip or DDC
channels within separate AD9694 chips.
Mixer
The NCO is accompanied by a mixer. The NCO mixer operation
is similar to that of an analog quadrature mixer. It performs the
downconversion of input signals (real or complex) by using the
NCO frequency as a local oscillator. For real input signals, this
mixer performs a real mixer operation (with two multipliers). For
complex input signals, the mixer performs a complex mixer
operation (with four multipliers and two adders). The mixer
adjusts its operation based on the input signal (real or complex)
provided to each individual channel. The selection of real or
complex inputs can be controlled individually for each DDC
block using Bit 7 of the DDC control registers (Register 0x0310
and Register 0x0330) in conjunction with the pair index register
(Register 0x0009).
Rev. B | Page 41 of 96
AD9694
Data Sheet
FIR FILTERS
OVERVIEW
Four sets of decimate by 2, low-pass, half-band, finite impulse
response (FIR) filters (labeled HB1 FIR, HB2 FIR, HB3 FIR,
and HB4 FIR in Figure 72) follow the frequency translation
stage. After the carrier of interest is tuned down to dc (carrier
frequency = 0 Hz), these filters efficiently lower the sample rate,
while providing sufficient alias rejection from unwanted adjacent
carriers around the bandwidth of interest.
HB1 FIR is always enabled and cannot be bypassed in DDC
mode. The HB2, HB3, and HB4 FIR filters are optional and can
be bypassed for higher output sample rates.
Table 18 shows the different bandwidths selectable by including
different half-band filters. In all cases, the DDC filtering stage
on the AD9694 provides 100 dB of stop band alias rejection.
Table 19 shows the amount of stop band alias rejection for multiple
pass-band ripple/cutoff points. The decimation ratio of the filtering
stage of each DDC can be controlled individually through Bits[1:0]
of the DDC control registers (Register 0x0310 and Register 0x0330)
in conjunction with the pair index register (Register 0x0009).
Table 18. DDC Filter Characteristics
Half-Band
Filter
Selection
HB1
HB1 + HB2
HB1 + HB2 +
HB3
HB1 + HB2 +
HB3 + HB4
1
Real Output
Output
Sample
Decimation Rate
Ratio
(MSPS)
1
500
2
250
4
125
Decimation
Ratio
2
4
8
8
16
62.5
Complex (I/Q) Output
Output Sample
Rate (MSPS)
250 (I) + 250 (Q)
125 (I) + 125 (Q)
62.5 (I) + 62.5 (Q)
Alias
Protected
Bandwidth
(MHz)
200
100
50
Ideal SNR
Improvement 1
(dB)
1
4
7
31.25 (I) + 31.25 (Q)
25
10
PassBand
Ripple
(dB)
100
Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)).
Table 19. DDC Filter Alias Rejection
Alias Rejection
(dB)
>100
95
90
85
80
25.07
19.3
10.7
1
Pass-Band Ripple/Cutoff
Point (dB)
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