14-Bit, 1300 MSPS/625 MSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9695
Data Sheet
FEATURES
APPLICATIONS
JESD204B (Subclass 1) coded serial digital outputs
Lane rates up to 16 Gbps
1.6 W total power at 1300 MSPS
800 mW per ADC channel
SNR = 65.6 dBFS at 172 MHz (1.59 V p-p input range)
SFDR = 78 dBFS at 172.3 MHz (1.59 V p-p input range)
Noise density
−153.9 dBFS/Hz (1.59 V p-p input range)
−155.6 dBFS/Hz (2.04 V p-p input range)
0.95 V, 1.8 V, and 2.5 V supply operation
No missing codes
Internal ADC voltage reference
Flexible input range
1.36 V p-p to 2.04 V p-p (1.59 V p-p typical)
2 GHz usable analog input full power bandwidth
>95 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
2 integrated digital downconverters per ADC channel
48-bit NCO
Programmable decimation rates
Differential clock input
SPI control
Integer clock divide by 2 and divide by 4
Flexible JESD204B lane configurations
On-chip dithering to improve small signal linearity
Communications
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, WCDMA, GSM, LTE
General-purpose software radios
Ultrawideband satellite receiver
Instrumentation
Oscilloscopes
Spectrum analyzers
Network analyzers
Integrated RF test solutions
Radars
Electronic support measures, electronic counter measures,
and electronic counter-counter measures
High speed data acquisition systems
DOCSIS 3.0 CMTS upstream receive paths
Hybrid fiber coaxial digital reverse path receivers
Wideband digital predistortion
FUNCTIONAL BLOCK DIAGRAM
ADC
CORE
VREF
ADC
CORE
DRVDD1
(0.95V)
DRVDD2
(1.8V)
SPIVDD
(1.8V)
14
SIGNAL
MONITOR
BUFFER
DVDD
(0.95V)
14
DIGITAL DOWNCONVERTER
DIGITAL DOWNCONVERTER
CROSSBAR MUX
BUFFER
FAST
DETECT
VIN+B
VIN–B
AVDD3 AVDD1_SR
(2.5V)
(0.95V)
CROSSBAR MUX
VIN+A
VIN–A
AVDD2
(1.8V)
PROGRAMMABLE
FIR FILTER
AVDD1
(0.95V)
JESD204B
LINK
AND
Tx
OUTPUTS
4
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SYNCINB±
PDWN/STBY
JESD204B
SUBCLASS 1
CONTROL
CLOCK
DISTRIBUTION
FD_A/GPIO_A0
GPIO MUX
CLK+
CLK–
÷2
SPI AND
CONTROL
REGISTERS
FD_B/GPIO_B0
AD9695
÷4
AGND
SDIO SCLK
CSB
DRGND
DGND
15660-001
SYSREF±
Figure 1.
Rev. C
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Technical Support
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AD9695
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DDC General Description ........................................................ 42
Applications ...................................................................................... 1
DDC Frequency Translation .................................................... 45
Functional Block Diagram .............................................................. 1
DDC Decimation Filters ........................................................... 53
Revision History ............................................................................... 3
DDC Gain Stage ......................................................................... 60
General Description ......................................................................... 4
DDC Complex to Real Conversion ......................................... 61
Product Highlights ........................................................................... 4
DDC Mixed Decimation Settings ............................................ 62
Specifications .................................................................................... 5
DDC Example Configurations ................................................. 64
DC Specifications ......................................................................... 5
DDC Power Consumption ....................................................... 67
AC Specifications—1300 MSPS ................................................. 6
Signal Monitor ................................................................................ 68
AC Specifications—625 MSPS ................................................... 8
SPORT Over JESD204B ............................................................ 69
Digital Specifications ................................................................... 9
Digital Outputs ............................................................................... 71
Switching Specifications ............................................................ 10
Introduction to the JESD204B Interface ................................. 71
Timing Specifications ................................................................ 11
JESD204B Overview .................................................................. 71
Absolute Maximum Ratings ......................................................... 13
Functional Overview ................................................................. 72
Thermal Characteristics ............................................................ 13
JESD204B Link Establishment ................................................. 72
ESD Caution................................................................................ 13
Physical Layer (Driver) Outputs .............................................. 74
Pin Configuration and Function Descriptions .......................... 14
Setting Up the AD9695 Digital Interface ................................ 75
Typical Performance Characteristics ........................................... 16
Deterministic Latency.................................................................... 81
1300 MSPS ................................................................................... 16
Subclass 0 Operation ................................................................. 81
625 MSPS ..................................................................................... 21
Subclass 1 Operation ................................................................. 81
Equivalent Circuits ......................................................................... 25
Multichip Synchronization ........................................................... 83
Theory of Operation ...................................................................... 27
Normal Mode ............................................................................. 83
ADC Architecture ...................................................................... 27
Timestamp Mode ....................................................................... 83
Analog Input Considerations ................................................... 27
SYSREF± Input........................................................................... 85
Voltage Reference....................................................................... 30
SYSREF± Setup/Hold Window Monitor................................ 87
DC Offset Calibration ................................................................ 30
Latency ............................................................................................. 89
Clock Input Considerations...................................................... 30
End to End Total Latency ......................................................... 89
Power-Down/Standby Mode .................................................... 33
Example Latency Calculations ................................................. 89
Temperature Diode .................................................................... 33
LMFC Referenced Latency ....................................................... 89
ADC Overrange and Fast Detect.................................................. 34
Test Modes ...................................................................................... 91
ADC Overrange .......................................................................... 34
ADC Test Modes ........................................................................ 91
Fast Threshold Detection (FD_A and FD_B) ........................ 34
JESD204B Block Test Modes .................................................... 92
ADC Application Modes and JESD204B Tx Converter
Mapping ........................................................................................... 35
Serial Port Interface (SPI) ............................................................. 94
Programmable Finite Impulse Response (FIR) Filters.............. 37
Hardware Interface .................................................................... 94
Supported Modes ....................................................................... 37
SPI Accessible Features ............................................................. 94
Programming Instructions ....................................................... 39
Memory Map .................................................................................. 95
Digital Downconverter (DDC)..................................................... 42
Reading the Memory Map Register Table .............................. 95
DDC I/Q Input Selection .......................................................... 42
Memory Map Registers ............................................................. 96
DDC I/Q Output Selection ....................................................... 42
Applications Information ........................................................... 134
Configuration Using the SPI .................................................... 94
Rev. C | Page 2 of 136
Data Sheet
AD9695
Power Supply Recommendations .......................................... 134
Outline Dimensions .....................................................................136
Layout GuideLines ................................................................... 135
Ordering Guide .........................................................................136
AVDD1_SR (Pin 57) and AGND_SR (Pin 56 and Pin 60) ... 135
REVISION HISTORY
6/2020—Rev. B to Rev. C
Changes to Table 48 ........................................................................97
12/2019—Rev. A to Rev. B
Changes to Input Common Mode Section..................................28
Added DDC Power Consumption Section and Table 31;
Renumbered Sequentially ..............................................................67
Changes to Table 35 ........................................................................76
Changes to Table 36 ........................................................................77
Changes to Table 37 ........................................................................78
Changes to Table 48 ........................................................................96
10/2017—Rev. 0 to Rev. A
Changes to Table 5 .......................................................................... 10
Change to Theory of Operation Section ...................................... 27
Changes to Table 47......................................................................130
Updated Outline Dimensions .....................................................135
9/2017—Revision 0: Initial Version
Rev. C | Page 3 of 136
AD9695
Data Sheet
GENERAL DESCRIPTION
The AD9695 is a dual, 14-bit, 1300 MSPS/625 MSPS analog-todigital converter (ADC). The device has an on-chip buffer and a
sample-and-hold circuit designed for low power, small size, and
ease of use. This product is designed to support communications
applications capable of direct sampling wide bandwidth analog
signals of up to 2 GHz. The −3 dB bandwidth of the ADC input
is 2 GHz. The AD9695 is optimized for wide input bandwidth,
high sampling rate, excellent linearity, and low power in a small
package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. The analog input and clock signals
are differential inputs. The ADC data outputs are internally
connected to four digital downconverters (DDCs) through a
crossbar mux. Each DDC consists of multiple signal processing
stages: a 48-bit frequency translator (numerically controlled
oscillator (NCO)), and decimation filters. The NCO has the option
to select up to 16 preset bands over the general-purpose input/
output (GPIO) pins, or use a coherent fast frequency hopping
mechanism for band selection. Operation of the AD9695 between
the DDC modes is selectable via SPI-programmable profiles.
In addition to the DDC blocks, the AD9695 has several functions
that simplify the automatic gain control (AGC) function in a
communications receiver. The programmable threshold detector
allows monitoring of the incoming signal power using the fast
detect control bits in Register 0x0245 of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to
avoid an overrange condition at the ADC input. In addition to
the fast detect outputs, the AD9695 also offers signal
monitoring capability. The signal monitoring block provides
additional information about the signal being digitized by the
ADC.
The user can configure the Subclasss 1 JESD204B-based high
speed serialized output using either one lane, two lanes, or four
lanes, depending on the DDC configuration and the acceptable
lane rate of the receiving logic device. Multidevice synchronization
is supported through the SYSREF± and SYNCINB± input pins.
The AD9695 has flexible power-down options that allow
significant power savings when desired. All of these features
can be programmed using a 3-wire serial port interface (SPI)
and or PDWN/STBY pin.
The AD9695 is available in a Pb-free, 64-lead LFCSP and is
specified over the −40°C to +105°C junction temperature range.
This product may be protected by one or more U.S. or
international patents.
Note that, throughout this data sheet, multifunction pins, such
as FD_A/GPIO_A0, are referred to either by the entire pin
name or by a single function of the pin, for example, FD_A,
when only that function is relevant.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
Rev. C | Page 4 of 136
Low power consumption per channel.
JESD204B lane rate support up to 16 Gbps.
Wide, full power bandwidth supports intermediate
frequency (IF) sampling of signals up to 2 GHz.
Buffered inputs ease filter design and implementation.
Four integrated wideband decimation filters and NCO
blocks supporting multiband receivers.
Programmable fast overrange detection.
On-chip temperature diode for system thermal management.
Data Sheet
AD9695
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS
(AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speed grade), DCS off (AD9695-625
speed grade), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ)
range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C
(TA = 25°C for the AD9695-1300 speed grade).
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error 1
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Voltage
INPUT-REFERRED NOISE
ANALOG INPUTS
Differential Input Voltage Range
Common-Mode Voltage (VCM)
Differential Input Resistance
Differential Input Capacitance
Analog Full-Power Bandwidth
POWER SUPPLY
AVDD1
AVDD2
AVDD3
AVDD1_SR
DVDD
DRVDD1
DRVDD2
SPIVDD 2
IAVDD1
IAVDD2
IAVDD3
IAVDD1_SR
IDVDD
IDRVDD1 3
IDRVDD2
ISPIVDD
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers) 4
Power-Down Dissipation
Standby 5
Min
14
−0.48
−2.9
−2.64
−0.7
−7
1300 MSPS
Typ
Guaranteed
5
0
±1
±0.18
625 MSPS
Max
Min
14
Typ
Max
Unit
Bits
Guaranteed
5
0
+0.25
±2.22
+2.6
±0.18
+2.5
+0.8
±2
+5
Codes
% FSR
% FSR
% FSR
LSB
LSB
±9
69
±6
123
ppm/°C
ppm/°C
0.5
3.8
0.5
2.7
V
LSB rms
±1
+0.48
+2.9
+2.64
0.8
5
−0.25
−2.6
−2.5
−0.8
−5
1.36
1.59
1.41
200
1.75
2
2.04
1.36
1.7
1.41
200
1.75
2
2.04
V p-p
V
Ω
pF
GHz
0.93
1.71
2.44
0.93
0.93
0.93
1.71
1.71
0.95
1.8
2.5
0.95
0.95
0.95
1.8
1.8
304
450
55
15
218
146
25
2
0.98
1.89
2.56
0.98
0.98
0.98
1.89
1.89
383
500
61
27
400
229
29
5
0.93
1.71
2.44
0.93
0.93
0.93
1.71
1.71
0.95
1.8
2.5
0.95
0.95
0.95
1.8
1.8
182
267
29
9
103
103
28
2
0.98
1.89
2.56
0.98
0.98
0.98
1.89
1.89
257
292
35
15
293
176
35
5
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
1.39
1.6
215
890
2
0.86
0.98
200
740
1.35
W
mW
mW
DC offset calibration on (Register 0x0701, Bit 7 = 1 and Register 0x073B, Bit 7 = 0).
The voltage level on the SPIVDD rail and on the DRVDD2 rail must be the same.
3
All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used.
4
Default mode. No DDCs used.
5
Can be controlled by SPI.
1
2
Rev. C | Page 5 of 136
AD9695
Data Sheet
AC SPECIFICATIONS—1300 MSPS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 1300 MSPS,
DCS on, buffer current settings specified in Table 11, unless otherwise noted. Minimum and maximum specifications are guaranteed for
the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 40°C (TA = 25°C for
the AD9695-1300 speed grade).
Table 2.
Parameter 1
ANALOG INPUT FULL SCALE
NOISE DENSITY 2
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10.3 MHz
fIN = 172.3 MHz
fIN = 340 MHz
fIN = 750 MHz
fIN = 1000 MHz
fIN = 1400 MHz
fIN = 1700 MHz
fIN = 1980 MHz
SIGNAL-TO-NOISE-AND-DISTORTION
RATIO (SINAD)
fIN = 10.3 MHz
fIN = 172.3 MHz
fIN = 340 MHz
fIN = 750 MHz
fIN = 1000 MHz
fIN = 1400 MHz
fIN = 1700 MHz
fIN = 1980 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10.3 MHz
fIN = 172.3 MHz
fIN = 340 MHz
fIN = 750 MHz
fIN = 1000 MHz
fIN = 1400 MHz
fIN = 1700 MHz
fIN = 1980 MHz
SPURIOUS FREE DYNAMIC RANGE
(SFDR)
fIN = 10.3 MHz
fIN = 172.3MHz
fIN = 340 MHz
fIN = 750 MHz
fIN = 1000 MHz
fIN = 1400 MHz
fIN = 1700 MHz
fIN = 1980 MHz
Analog Input Full
Scale = 1.36 V p-p
Min
Typ
Max
1.36
−152.6
64.4
64.4
64.3
64.0
63.8
63.2
62.7
62.3
64.3
64.3
64.2
63.9
63.6
63.1
62.6
62.1
10.3
10.3
10.3
10.3
10.2
10.1
10.1
10.0
81
81
80
83
82
80
80
81
Analog Input Full Scale =
1.59 V p-p
Min
Typ
Max
1.59
−153.9
64.5
64.3
10.3
74
Analog Input Full Scale =
2.04 V p-p
Min
Typ
Max
2.04
−155.6
Unit
V p-p
dBFS/Hz
65.7
65.6
65.6
65.2
64.9
64.2
63.6
63.0
67.5
67.5
67.3
66.6
66.1
65.2
64.5
63.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
65.4
65.4
65.3
65.0
64.7
63.8
63.4
62.8
66.1
66.2
65.7
65.5
65.7
62.9
64.2
61.8
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
10.5
10.5
10.5
10.5
10.4
10.3
10.2
10.1
10.6
10.7
10.6
10.5
10.6
10.1
10.3
9.9
Bits
Bits
Bits
Bits
dBFS
dBFS
dBFS
dBFS
79
78
77
80
81
76
80
79
73
72
71
72
79
67
78
68
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Rev. C | Page 6 of 136
Data Sheet
Parameter 1
WORST OTHER, EXCLUDING 2ND OR
3RD HARMONIC
fIN = 10.3 MHz
fIN = 172.3 MHz
fIN = 340 MHz
fIN = 750 MHz
fIN = 1000 MHz
fIN = 1400 MHz
fIN = 1700 MHz
fIN = 1980 MHz
TWO-TONE INTERMODULATION
DISTORTION (IMD), AIN1 AND AIN2 =
−7.0 dBFS
fIN1 = 170.8 MHz, fIN2 = 173.8 MHz
fIN1 = 343.5 MHz, fIN2 = 346.5 MHz
CROSSTALK 3
Overrange Condition 4
ANALOG INPUT BANDWIDTH, FULL
POWER 5
AD9695
Analog Input Full
Scale = 1.36 V p-p
Min
Typ
Max
Analog Input Full Scale =
1.59 V p-p
Min
Typ
Max
−96
−95
−98
−95
−96
−90
−91
−90
−94
−96
−99
−95
−93
−89
−90
−90
−84
−83
>95
>95
2
−84
−82
>95
>95
2
−85
Analog Input Full Scale =
2.04 V p-p
Min
Typ
Max
Unit
−101
−95
−98
−92
−91
−86
−84
−77
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−83
−81
>95
>95
2
dBFS
dBFS
dB
dB
GHz
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Noise density is measured at a low analog input frequency (10 MHz).
3
Crosstalk is measured at 10 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel.
4
The overrange condition is specified with 3 dB of the full-scale input range.
5
Full power bandwidth is the bandwidth of operation to achieve proper ADC performance.
1
2
Rev. C | Page 7 of 136
AD9695
Data Sheet
AC SPECIFICATIONS—625 MSPS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS,
DCS off, buffer current setting specified in Table 11, unless otherwise noted. Minimum and maximum specifications are guaranteed for the
full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the
AD9695-625 speed grade).
Table 3.
Parameter 1
ANALOG INPUT FULL SCALE
NOISE DENSITY 2
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 10.3 MHz
fIN = 172.3 MHz
fIN = 340 MHz
fIN = 750 MHz
fIN = 1000 MHz
SIGNAL-TO-NOISE-AND-DISTORTION
RATIO (SINAD)
fIN = 10.3 MHz
fIN = 172.3 MHz
fIN = 340 MHz
fIN = 750 MHz
fIN = 1000 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10.3 MHz
fIN = 172.3 MHz
fIN = 340 MHz
fIN = 750 MHz
fIN = 1000 MHz
SPURIOUS FREE DYNAMIC RANGE
(SFDR)
fIN = 10.3 MHz
fIN = 172.3MHz
fIN = 340 MHz
fIN = 750 MHz
fIN = 1000 MHz
WORST OTHER, EXCLUDING 2ND OR
3RD HARMONIC
fIN = 10.3 MHz
fIN = 172.3 MHz
fIN = 340 MHz
fIN = 750 MHz
fIN = 1000 MHz
TWO-TONE INTERMODULATION
DISTORTION (IMD), AIN1 AND AIN2 =
−7.0 dBFS
fIN1 = 170.8 MHz, fIN2 = 173.8 MHz
fIN1 = 343.5 MHz, fIN2 = 346.5 MHz
CROSSTALK 3
Overrange Condition 4
Analog Input Full
Scale = 1.36 V p-p
Min
Typ
Max
1.36
−150.5
65.5
65.4
65.4
65.0
64.8
65.5
65.4
65.2
64.9
64.6
10.6
10.6
10.5
10.5
10.4
88
88
79
83
85
Analog Input Full Scale =
1.7 V p-p
Min
Typ
Max
1.7
−152.3
65.5
66.3
10.6
75
Analog Input Full Scale =
2.04 V p-p
Min
Typ
Max
2.04
−153.5
Unit
V p-p
dBFS/Hz
67.3
67.2
67.1
66.6
66.3
68.6
68.5
68.3
67.7
67.3
dBFS
dBFS
dBFS
dBFS
dBFS
66.9
67.0
67.0
65.4
65.0
67.2
68.0
67.9
67.0
67.0
dBFS
dBFS
dBFS
dBFS
dBFS
10.8
10.8
10.8
10.6
10.5
10.9
11.0
11.0
10.8
10.8
Bits
Bits
Bits
Bits
Bits
79
89
80
84
83
74
78
77
77
82
dBFS
dBFS
dBFS
dBFS
dBFS
−99
−99
−98
−100
−100
dBFS
dBFS
dBFS
dBFS
dBFS
−83
−84
>95
>95
dBFS
dBFS
dB
dB
−100
−101
−100
−98
−100
−101
−97
−102
−98
−98
−88
−89
>95
>95
−88
−89
>95
>95
Rev. C | Page 8 of 136
−90
Data Sheet
Parameter1
ANALOG INPUT BANDWIDTH, FULL
POWER5
AD9695
Analog Input Full
Scale = 1.36 V p-p
Min
Typ
Max
2
Analog Input Full Scale =
1.7 V p-p
Min
Typ
Max
2
Analog Input Full Scale =
2.04 V p-p
Min
Typ
Max
2
Unit
GHz
1
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Noise density is measured at a low analog input frequency (10 MHz).
Crosstalk is measured at 10 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel.
4
The overrange condition is specified with 3 dB of the full-scale input range.
5
Full power bandwidth is the bandwidth of operation to achieve proper ADC performance.
2
3
DIGITAL SPECIFICATIONS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS
(AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speed grade), DCS off (AD9695-625
speed grade), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature
(TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and
TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade).
Table 4.
Parameter
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Differential)
SYSREF INPUTS (SYSREF+, SYSREF−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Differential)
LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0,
FD_B/GPIO_B0)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
LOGIC OUTPUT (SDIO, FD_A, FD_B)
Logic Compliance
Logic 1 Voltage (IOH = 4 mA)
Logic 0 Voltage (IOL = 4 mA)
SYNCIN INPUTS (SYNCINB−, SYNCINB+)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Single-Ended per Pin)
DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3)
Logic Compliance
Differential Output Voltage
Differential Termination Impedance
Min
400
Typ
LVDS/LVPECL
800
0.65
32
Max
Unit
1600
mV p-p
V
kΩ
pF
0.9
400
LVDS/LVPECL
800
0.65
18
1
1800
2
mV p-p
V
kΩ
pF
CMOS
0.75 × SPIVDD
0
0.35 × SPIVDD
30
V
V
kΩ
CMOS
SPIVDD − 0.45
0
400
0.45
LVDS/LVPECL/CMOS
800
1800
0.65
2
18
1
V
V
mV p-p
V
kΩ
pF
SST
360
80
Rev. C | Page 9 of 136
520
100
770
1200
mV p-p
Ω
AD9695
Data Sheet
SWITCHING SPECIFICATIONS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, and sample rate = 625 MSPS
(AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speed grade), DCS off (AD9695-625
speed grade), unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ)
range of −40°C to +105°C. Typical specifications represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and
TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade).
Table 5.
Parameter
CLOCK
Clock Rate (at CLK+/CLK− Pins)
Maximum Sample Rate 1
Minimum Sample Rate 2
Clock Pulse Width 3
High
Low
OUTPUT PARAMETERS
Unit Interval (UI) 4
Rise Time (tR) (20% to 80% into 100 Ω Load)
Fall Time (tF) (20% to 80% into 100 Ω Load)
Phase-Locked Loop (PLL) Lock Time
Data Rate per Channel (NRZ) 5
LATENCY 6
Pipeline Latency
Fast Detect Latency
Wake-Up Time 7
Standby
Power-Down
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Out of Range Recovery Time
Min
1300 MSPS
Typ
Max
0.24
1400
240
2.8
156.25
156.25
62.5
1.6875
Min
625 MSPS
Typ
Max
0.24
640
240
2.8
156.25
156.25
76.9
28
28
5
13
62.5
16
1.6875
Unit
GHz
MSPS
MSPS
ps
ps
160
28
28
5
6.25
16
ps
ps
ps
ms
Gbps
56
26
56
26
Clock cycles
Clock cycles
400
15
400
15
us
ms
192
43
1
159.5
49.2
1
ps
fs rms
Clock cycles
The maximum sample rate is the clock rate after the divider.
The minimum sample rate operates at 240 MSPS. See SPI Register 0x011A to reduce the threshold of the clock detect circuit.
3
Clock duty stabilizer (DCS) on. See SPI Register 0x011C and 0x011E to enable DCS.
4
Baud rate = 1/UI. A subset of this range can be supported.
5
Default L = 4. This number can change based on the sample rate and decimation ratio.
6
No DDCs used. L = 4, M = 2, and F = 1.
7
Wake-up time is defined as the time required to return to normal operation from power-down mode.
1
2
Rev. C | Page 10 of 136
Data Sheet
AD9695
TIMING SPECIFICATIONS
Table 6.
Parameter
CLK+ to SYSREF+ TIMING REQUIREMENTS
tSU_SR
tH_SR
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tACCESS
Test Conditions/Comments
See Figure 3
Device clock to SYSREF+ setup time
Device clock to SYSREF+ hold time
See Figure 4
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Maximum time delay between falling edge of SCLK and output
data valid for a read operation
Time required for the SDIO pin to switch from an output to an
input relative to the CSB rising edge (not shown in Figure 4)
tDIS_SDIO
Min
10
N – 56
N+1
SAMPLE N
N – 54
N – 53
N–1
CLK–
CLK+
CLK–
SERDOUT0–
SERDOUT1–
SERDOUT1+
SERDOUT2–
SERDOUT2+
SERDOUT3–
SERDOUT3+
A
B
C
D
E
F
G
H
I
J
CONVERTER0
SAMPLE N – 56 MSB
A
B
C
D
E
F
G
H
I
J
CONVERTER0
SAMPLE N – 56 LSB
A
B
C
D
E
F
G
H
I
J
CONVERTER0
SAMPLE N – 55 MSB
A
B
C
D
E
F
G
H
I
J
CONVERTER0
SAMPLE N – 55 LSB
SAMPLE N – 56 AND N – 55
ENCODED INTO ONE
8-BIT/10-BIT SYMBOL
15660-002
CLK+
SERDOUT0+
Figure 2. Data Output Timing Diagram
CLK–
CLK+
tSU_SR
tH_SR
15660-003
SYSREF–
SYSREF+
Figure 3. SYSREF± Setup and Hold Timing Diagram
Rev. C | Page 11 of 136
Unit
−70
120
ps
ps
6
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
APERTURE DELAY
N – 55
Ma
x
4
2
40
2
2
10
10
Timing Diagrams
ANALOG
INPUT
SIGNAL
Typ
AD9695
Data Sheet
tDS
tS
tHIGH
tCLK
tDH
tACCESS
tH
tLOW
CSB
DON’T CARE
SDIO
DON’T CARE
DON’T CARE
R/W
A14
A13
A12
A11
A10
A9
A8
A7
Figure 4. SPI Timing Diagram
Rev. C | Page 12 of 136
D5
D4
D3
D2
D1
D0
DON’T CARE
15660-004
SCLK
Data Sheet
AD9695
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 7.
Parameter
Electrical
AVDD1 to AGND
AVDD1_SR to AGND
AVDD2 to AGND
AVDD3 to AGND
DVDD to DGND
DRVDD1 to DRGND
DRVDD2 to DRGND
SPIVDD to DGND
AGND to DRGND
AGND to DGND
DGND to DRGND
VIN±x to AGND
CLK± to AGND
SCLK, SDIO, CSB to DGND
PDWN/STBY to DGND
SYSREF± to AGND
SYNCINB± to DRGND
Junction Temperature Range
(TJ)
Storage Temperature Range,
Ambient (TA)
Rating
1.05 V
1.05 V
2.00 V
2.70 V
1.05 V
1.05 V
2.00 V
2.00 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
AGND − 0.3 V to AVDD3 + 0.3 V
AGND − 0.3 V to AVDD1 + 0.3 V
DGND − 0.3 V to SPIVDD + 0.3 V
DGND − 0.3 V to SPIVDD + 0.3 V
2.5 V
2.5 V
−40°C to +125°C
Typical θJA, θJB, and θJC are specified vs. the number of printed
circuit board (PCB) layers in different airflow velocities (in m/sec).
Airflow increases heat dissipation effectively reducing θJA and θJB.
In addition, metal in direct contact with the package leads and
exposed pad from metal traces, through holes, ground, and
power planes, reduces θJA. Thermal performance for actual
applications requires careful inspection of the conditions in
an application. The use of appropriate thermal management
techniques is recommended to ensure that the maximum
junction temperature does not exceed the limits shown in Table 7.
Table 8. Thermal Resistance
Package
Type
CP-64-17
Airflow
Velocity
(m/sec)
0
1.0
2.5
θJA1, 2 θJC_BOT1, 3
22.5 1.7
17.9
16.8
θJB1, 4
4.3
Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
Per MIL-Std 883, Method 1012.1.
4
Per JEDEC JESD51-8 (still air).
1
2
3
ESD CAUTION
−65°C to +150°C
θJC_TOP1, 3
7.6
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Rev. C | Page 13 of 136
θJT1,2
0.2
Unit
°C/W
°C/W
°C/W
AD9695
Data Sheet
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD1
AVDD2
AVDD2
AVDD1
AGND_SR
SYSREF–
SYSREF+
AVDD1_SR
AGND_SR
AVDD1
CLK–
CLK+
AVDD1
AVDD2
AVDD2
AVDD1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
AD9695
TOP VIEW
(Not to Scale)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AVDD1
AVDD1
AVDD2
AVDD3
VIN–B
VIN+B
AVDD3
AVDD2
AVDD2
AVDD2
SPIVDD
CSB
SCLK
SDIO
DVDD
DGND
NOTES
1. ANALOG GROUND. CONNECT THE EXPOSED PAD TO THE
ANALOG GROUND PLANE.
15660-005
FD_A/GPIO_A0
DRGND
DRVDD1
SYNCINB–
SYNCINB+
SERDOUT0–
SERDOUT0+
SERDOUT1–
SERDOUT1+
SERDOUT2–
SERDOUT2+
SERDOUT3–
SERDOUT3+
DRVDD1
DRGND
FD_B/GPIO_B0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD1
AVDD1
AVDD2
AVDD3
VIN–A
VIN+A
AVDD3
AVDD2
AVDD2
AVDD2
DRVDD2
VREF
SPIVDD
PDWN/STBY
DVDD
DGND
Figure 5. Pin Configuration (Top View)
Table 9. Pin Function Descriptions
Pin No.
1, 2, 47 to 49, 52,
55, 61, 64
3, 8 to 10, 39 to 41,
46, 50, 51, 62, 63
4, 7, 42, 45
5, 6
11
12
Mnemonic
AVDD1
Type
Power supply
Description
Analog Power Supply (0.95 V Nominal).
AVDD2
Power supply
Analog Power Supply (1.8 V Nominal).
AVDD3
VIN−A, VIN+A
DRVDD2
VREF
Power supply
Analog input
Power supply
Input/output
13, 38
14
SPIVDD
PDWN/STBY
Power supply
Digital control input
15, 34
16, 33
DVDD
DGND
17
FD_A/GPIO_A0
Power supply
Ground power
supply
CMOS output
Analog Power Supply (2.5 V Nominal).
ADC A Analog Input Complement/True.
Digital Driver Power Supply (1.8 V Nominal).
Reference Voltage Input (0.50 V)/Do Not Connect. This pin is configurable
through the SPI as a no connect pin or as an input. Do not connect this pin if
using the internal reference. This pin requires a 0.50 V reference voltage
input if using an external voltage reference source.
Digital Power Supply for SPI (1.8 V Nominal).
Power-Down Input (Active High). The operation of this pin depends on the
SPI mode and can be configured as power-down or standby.
Digital Power Supply (0.95 V Nominal).
Digital Control Ground Supply. These pins connect to the digital ground plane.
32
18, 31
FD_B/GPIO_B0
DRGND
19, 30
20
21
22, 23
DRVDD1
SYNCINB−
SYNCINB+
SERDOUT0−,
SERDOUT0+
SERDOUT1−,
SERDOUT1+
24, 25
CMOS output
Ground power
supply
Power supply
Digital input
Digital input
Data output
Fast Detect Output for Channel A (FD_A). General-purpose input/output
(GPIO) Pin A0 (GPIO_A0).
Fast Detect Output for Channel B (FD_B). GPIO Pin B0 (GPIO_B0).
Digital Driver Ground Supply. This pin connects to the digital driver ground
plane.
Digital Driver Power Supply (0.95 V Nominal).
Active Low JESD204B LVDS/CMOS Sync Input True.
Active Low JESD204B LVDS Sync Input Complement.
Lane 0 Output Data Complement/True.
Data output
Lane 1 Output Data Complement/True.
Rev. C | Page 14 of 136
Data Sheet
Pin No.
26, 27
AD9695
35
Mnemonic
SERDOUT2−
SERDOUT2+
SERDOUT3−,
SERDOUT3+
SDIO
36
37
43, 44
53, 54
56, 60
SCLK
CSB
VIN+B, VIN−B
CLK+, CLK−
AGND_SR
57
58, 59
AVDD1_SR
SYSREF+,
SYSREF−
EPAD
28, 29
Type
Data output
Description
Lane 2 Output Data Complement/True.
Data output
Lane 3 Output Data Complement/True.
Digital control
input/output
Digital control input
Digital control input
Analog input
Analog input
Ground power
supply
Power supply
Digital input
SPI Serial Data Input/Output.
Ground power
supply
SPI Serial Clock.
SPI Chip Select (Active Low).
ADC B Analog Input True/Complement.
Clock Input True/Complement.
Ground Reference for SYSREF±.
Analog Power Supply for SYSREF± (0.95 V Nominal).
Active High JESD204B LVDS System Reference Input Complement/True.
Analog Ground. Connect the exposed pad to the analog ground plane.
Rev. C | Page 15 of 136
AD9695
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
1300 MSPS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, sample rate = 625 MSPS
(AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speed grade), DCS off (AD9695-625
speed grade), buffer current setting specified in Table 11, dc offset calibration enabled, unless otherwise noted. Minimum and maximum
specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent
performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade).
10
AIN = 10.3MHz
SNR = 65.7dBFS
SFDR = 79.0dBFS
BUFFER CURRENT = 300µA
–10
AIN = 752.3MHz
SNR = 65.2dBFS
SFDR = 80.0dBFS
BUFFER CURRENT = 300µA
–10
AMPLITUDE (dBFS)
–50
–70
–90
–50
–70
–90
0
200
400
600
FREQUENCY (MHz)
–130
15660-305
–130
0
600
Figure 9. Single-Tone FFT with fIN =752.3 MHz
AIN = 172.3MHz
SNR = 65.6dBFS
SFDR = 78.0dBFS
BUFFER CURRENT = 300µA
AIN = 1002.3MHz
SNR = 64.9dBFS
SFDR = 81.0dBFS
BUFFER CURRENT = 300µA
–10
–30
–30
AMPLITUDE (dBFS)
–50
–70
–90
–110
–50
–70
–90
–130
0
200
400
600
FREQUENCY (MHz)
15660-306
–110
–130
0
200
400
600
FREQUENCY (MHz)
Figure 10. Single-Tone FFT with fIN = 1002.3 MHz
Figure 7. Single-Tone FFT with Analog Input Frequency (fIN) = 172.3 MHz
AIN = 342.3MHz
SNR = 65.6dBFS
SFDR = 77.0dBFS
BUFFER CURRENT = 300µA
–10
AIN = 1402.3MHz
SNR = 64.2dBFS
SFDR = 76.0dBFS
BUFFER CURRENT = 300µA
–10
–30
AMPLITUDE (dBFS)
–30
–50
–70
–90
–110
–50
–70
–90
–110
–130
0
200
400
FREQUENCY (MHz)
600
–130
15660-307
AMPLITUDE (dBFS)
15660-309
AMPLITUDE (dBFS)
400
FREQUENCY (MHz)
Figure 6. Single-Tone FFT with Analog Input Frequency (fIN) = 10.3 MHz
–10
200
15660-308
–110
–110
0
200
400
600
FREQUENCY (MHz)
Figure 11. Single-Tone FFT with fIN = 1402.3 MHz
Figure 8. Single-Tone FFT with fIN = 342.3 MHz
Rev. C | Page 16 of 136
15660-310
AMPLITUDE (dBFS)
–30
–30
Data Sheet
AD9695
67
AIN = 1702.3MHz
SNR = 63.6dBFS
SFDR = 80.0dBFS
BUFFER CURRENT = 300µA
–10
TJ = +105°C
ROOM
TJ = –40°C
66
65
SNR (dBFS)
AMPLITUDE (dBFS)
–30
–50
–70
64
63
–90
62
61
0
200
600
400
FREQUENCY (MHz)
0
15660-311
–130
500
1000
1500
2000
ANALOG INPUT FREQUENCY (MHz)
15660-314
–110
Figure 15. SNR vs. Analog Input Frequency (fIN) at Minimum, Room, and
Maximum Temperatures
Figure 12. Single-Tone FFT with fIN = 1702.3 MHz
90
AIN = 1980.3MHz
SNR = 63.0dBFS
SFDR = 79.0dBFS
BUFFER CURRENT = 300µA
–10
TJ = +105°C
ROOM
TJ = –40°C
85
80
SDFR (dBFS)
AMPLITUDE (dBFS)
–30
–50
–70
75
70
–90
65
60
0
200
600
400
FREQUENCY (MHz)
0
15660-312
–130
Figure 13. Single-Tone FFT with fIN = 1980.3 MHz
500
1000
1500
2000
ANALOG INPUT FREQUENCY (MHz)
15660-315
–110
Figure 16. SFDR vs. Analog Input Frequency (fIN) at Minimum, Room, and
Maximum Temperatures
85
fIN1 = 170.8MHz
fIN2 = 173.8MHz
IMD = –84dBFS
BUFFER CURRENT = 300µA
–10
SNR
SFDR
AMPLITUDE (dBFS)
75
70
–60
–110
60
500
700
900
1100
1300
SAMPLE RATE (MHz)
Figure 14. SNR/SFDR vs. Sample Rate, fIN =172.3 MHz
–160
0
200
400
600
FREQUENCY (MHz)
Figure 17. Two-Tone FFT; fIN1 = 170.8 MHz, fIN2 = 173.8 MHz
Rev. C | Page 17 of 136
15660-316
65
15660-313
SNR/SFDR (dBFS)
80
AD9695
0
Data Sheet
85
fIN1 = 343.5MHz
fIN2 = 346.5MHz
IMD = –82dBFS
BUFFER CURRENT = 300µA
SNR
SFDR
80
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
–40
–90
75
70
200
0
400
60
–40
15660-317
–140
600
FREQUENCY (MHz)
10
60
110
JUNCTION TEMPERATURE (°C)
15660-320
65
Figure 21. SNR/SFDR vs. Junction Temperature, fIN = 172.3 MHz
Figure 18. Two-Tone FFT; fIN1 = 343.5 MHz, fIN2 = 346.5 MHz
2
120
100
1
0
60
INL (LSB)
SNR/SFDR (dB)
80
40
20
–1
–2
0
SFDR (dBFS)
SNRFS
SNR (dBc)
SFDR (dBc)
–60
–40
0
–20
ANALOG INPUT AMPLITUDE (dBFS)
–4
0
15000
Figure 22. INL, fIN = 10.3 MHz
10
0.3
SFDR (dBFS)
SFDR (dBc)
IMD3 (dBc)
IMD3 (dBFS)
–10
0.2
0.1
DNL (LSB)
–30
–50
–70
0
–0.1
–90
–0.2
–110
–0.3
–75
–55
–35
–15
ANALOG INPUT AMPLITUDE (dB)
15660-319
SFDR/IMD3 (dB)
10000
OUTPUT CODE
Figure 19. SNR/SFDR vs. Analog Input Amplitude, fIN = 172.3 MHz
–130
–95
5000
15660-321
–80
–0.4
0
5000
10000
OUTPUT CODE
Figure 23. DNL, fIN = 10.3 MHz
Figure 20. SFDR/IMD3 vs. Analog Input Amplitude, fIN = 172.3 MHz
Rev. C | Page 18 of 136
15000
15660-322
–40
–100
–3
15660-318
–20
Data Sheet
AD9695
1.8
NUMBER OF HITS
15000
10000
0
–16
–13
–10
–7
–4
–1
2
5
8
11
14
16
CODE
1.4
1.2
500
15660-323
5000
1.6
700
900
15660-326
POWER CONSUMPTION (W)
20000
1300
1100
SAMPLE RATE (MHz)
Figure 24. Input Referred Noise Histogram
Figure 27. Total Power Dissipation vs. Sample Rate (fS)
66
0
–2
65
–8
–10
64
CLOCK AMPLITUDE
400mV
600mV
800mV
1000mV
1200mV
1400mV
1600mV
1800mV
2000mV
63
–12
62
–14
0
1000
2000
3000
4000
AIN FREQUENCY (MHz)
61
15660-019
–16
Figure 25. Full Power Bandwidth
0
1000
1500
2000
Figure 28. SNR vs. Analog Input Frequency at Different Clock Amplitudes
2.0
86
84
1.8
SFDR (dBFS)
82
1.6
80
78
76
BUFFER CURRENT
BUFFER CURRENT
BUFFER CURRENT
BUFFER CURRENT
74
1.2
–40
10
60
110
JUNCTION TEMPERATURE (°C)
Figure 26. Total Power Dissipation vs. Junction Temperature
= 460µA
= 400µA
= 360µA
= 300µA
72
0
500
1000
1500
ANALOG INPUT FREQUENCY (MHz)
2000
15660-328
1.4
15660-325
TOTAL POWER CONSUMPTION (W)
500
ANALOG INPUT FREQUENCY (MHz)
15660-327
–6
SNR (dBFS)
AMPLITUDE (dBFS)
–4
Figure 29. SFDR vs. Analog Input Frequency with Different Buffer Current Settings
Rev. C | Page 19 of 136
AD9695
Data Sheet
90
68
67
80
IAVDD3 (mA)
65
64
63
60
61
500
0
1000
1500
2000
ANALOG INPUT FREQUENCY (MHz)
15660-329
2.04V
1.81V
1.59V
1.36V
62
Figure 30. SNR vs. Analog Input Frequency with Different Analog Input FullScale Values
90
85
80
SFDR (dBFS)
70
75
70
60
0
500
1000
1500
ANALOG INPUT FREQUENCY (MHz)
2000
15660-330
2.04V
1.81V
1.59V
1.36V
65
Figure 31. SFDR vs. Analog Input Frequency with Different Analog Input FullScale Values
Rev. C | Page 20 of 136
50
300
350
400
450
BUFFER CURRENT SETTING (µA)
Figure 32. IAVDD3 vs. Buffer Control 1 Setting in Register 0x1A4C
15660-331
SNR (dBFS)
66
Data Sheet
AD9695
625 MSPS
AVDD1 = 0.95 V, AVDD1_SR = 0.95 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.95 V, DRVDD1 = 0.95 V, DRVDD2 = 1.8 V, SPIVDD =
1.8 V, clock divider = 2, default input full scale, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, sample rate = 625 MSPS
(AD9695-625 speed grade), sample rate = 1300 MSPS (AD9695-1300 speed grade), DCS on (AD9695-1300 speed grade), DCS off
(AD9695-625 speed grade), buffer current setting specified in Table 11, and dc offset calibration enabled, unless otherwise noted. Minimum
and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications
represent performance at TJ = 35°C (TA = 25°C for the AD9695-625 speed grade) and TJ = 40°C (TA = 25°C for the AD9695-1300 speed grade).
0
0
AIN = –1dBFS
SNR = 67.2dBFS
SFDR = 89dBFS
BUFFER CURRENT = 160µA
–20
AMPLITUDE (dBFS)
–40
–60
–80
–40
–60
–80
–100
–100
0
100
200
300
FREQUENCY (MHz)
–120
15660-006
–120
0
100
150
200
250
300
FREQUENCY (MHz)
Figure 33. Single-Tone FFT with Analog Input Frequency (fIN) = 172.3 MHz
Figure 36. Single-Tone FFT with fIN = 1000 MHz
0
100
AIN = –1dBFS
SNR = 67.1dBFS
SFDR = 80dBFS
BUFFER CURRENT = 160µA
–20
80
–40
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
50
15660-009
AMPLITUDE (dBFS)
–20
AIN = –1dBFS
SNR = 66.3dBFS
SFDR = 83dBFS
BUFFER CURRENT = 300µA
–60
–80
60
40
20
–100
100
200
300
FREQUENCY (MHz)
15660-007
0
0
250
450
550
750
650
850
SAMPLE RATE (MSPS)
Figure 34. Single-Tone FFT with fIN = 340 MHz
Figure 37. SNR/SFDR vs. Sample Rate, fIN =172.3 MHz
0
100
AIN = –1dBFS
SNR = 66.6dBFS
SFDR = 84dBFS
BUFFER CURRENT = 300µA
90
SNR/SFDR (dBFS)
–40
–60
–80
–100
80
70
60
SFDR (TJ = –40°C)
SNR (TJ = –40°C)
SFDR (ROOM)
SNR (ROOM)
SFDR (TJ = +105°C)
SNR (TJ = +105°C)
50
0
100
200
FREQUENCY (MHz)
Figure 35. Single-Tone FFT with fIN =750 MHz
300
40
15660-008
–120
0
250
500
750
ANALOG INPUT FREQUENCY (MHz)
1000
15660-011
–20
AMPLITUDE (dBFS)
350
15660-010
SNR
SFDR
–120
Figure 38. SNR/SFDR vs. Analog Input Frequency (fIN) at Minimum, Room,
and Maximum Temperatures
Rev. C | Page 21 of 136
AD9695
Data Sheet
0
100
AIN1 AND AIN2 = –7dBFS
SFDR = 88dBFS
BUFFER CURRENT = 160µA
90
–40
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
–20
–60
–80
80
70
60
–100
50
–120
40
–40
100
200
300
FREQUENCY (MHz)
10
15660-015
0
15660-012
SNR
SFDR
60
JUNCTION TEMPERATURE (°C)
Figure 39. Two-Tone FFT; fIN1 = 170.8 MHz, fIN2 = 173.8 MHz
Figure 42. SNR/SFDR vs. Junction Temperature, fIN = 172.3 MHz
4
0
AIN1 AND AIN2 = –7dBFS
SFDR = 89dBFS
BUFFER CURRENT = 160µA
–20
3
1
INL (LSB)
AMPLITUDE (dBFS)
2
–40
–60
0
–1
–80
–2
–100
0
100
200
300
FREQUENCY (MHz)
–4
15660-013
–120
0
5000
10000
15000
OUTPUT CODE
Figure 40. Two-Tone FFT; fIN1 = 343.5 MHz, fIN2 = 346.5 MHz
15660-016
–3
Figure 43. INL, fIN = 10.3 MHz
120
0.25
0.20
100
0.15
0.10
DNL (LSB)
60
40
0
–0.05
–0.15
20
–80
–60
–40
–20
0
ANALOG INPUT AMPLITUDE (dBFS)
Figure 41. SNR/SFDR vs. Analog Input Amplitude, fIN = 172.3 MHz
–0.25
0
5000
10000
OUTPUT CODE
Figure 44. DNL, fIN = 10.3 MHz
Rev. C | Page 22 of 136
15000
15660-017
–0.20
SFDR (dBFS)
SFDR (dBc)
0
–100
0.05
–0.10
15660-014
SFDR (dB)
80
Data Sheet
AD9695
1.4
6000
TOTAL POWER DISSIPATION (W)
4000
3000
2000
1000
1.2
1.0
0.8
0.6
0.4
0
250
N + 15
CODE
550
650
750
850
Figure 48. Total Power Dissipation vs. Sample Rate (fS)
68
67
–4
66
SNR (dBFS)
–2
–6
–8
65
CLOCK AMPLITUDE
400mV p-p
600mV p-p
800mV p-p
1000mV p-p
1200mV p-p
1400mV p-p
1600mV p-p
1800mV p-p
2000mV p-p
2200mV p-p
64
–10
63
–12
62
–14
0
1000
2000
3000
4000
AIN FREQUENCY (MHz)
15660-019
61
–16
0
200
400
600
800
1000
1200
ANALOG INPUT FREQUENCY (MHz)
15660-022
0
AMPLITUDE (dBFS)
450
SAMPLE RATE (MSPS)
Figure 45. Input Referred Noise Histogram
Figure 49. SNR vs. Analog Input Frequency at Different Clock Amplitudes
Figure 46. Full Power Bandwidth
1.4
100
1.2
90
1.0
SFDR (dBFS)
80
0.8
0.6
70
60
0.4
0
–40
BUFFER CURRENT
BUFFER CURRENT
BUFFER CURRENT
BUFFER CURRENT
50
0.2
10
60
110
JUNCTION TEMPERATURE (°C)
Figure 47. Total Power Dissipation vs. Junction Temperature
=
=
=
=
160µA
200µA
240µA
300µA
40
15660-020
TOTAL POWER DISSIPATION (W)
350
15660-018
N + 12
N+9
N+6
N+3
0
N–3
N–6
N–9
N – 12
N – 15
0
15660-021
0.2
0
200
400
600
800
1000
ANALOG INPUT FREQUENCY (MHz)
1200
15660-023
NUMBER OF HITS
5000
Figure 50. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (AIN < 1250 MHz)
Rev. C | Page 23 of 136
AD9695
Data Sheet
80
69
BUFFER CURRENT = 400µA
BUFFER CURRENT = 300µA
BUFFER CURRENT = 240µA
68
67
75
SNR (dBFS)
SFDR (dBFS)
66
70
65
64
63
65
62
1450
1650
60
650
15660-348
60
1250
1850
ANALOG INPUT FREQUENCY (MHz)
Figure 51. SFDR vs. Analog Input Frequency with Different Buffer Current
Settings (AIN > 1250 MHz), Register 0x1B03 = 0x02, Register 0x1B08 = 0xC1,
Register 0x1B10 = 0x1C
750
850
950
1050
1150
1250
ANALOG INPUT FREQUENCY (MHz)
15660-026
INPUT FULL-SCALE = 1.36V p-p
INPUT FULL-SCALE = 1.7V p-p
INPUT FULL-SCALE = 2.04V p-p
61
Figure 54. SNR vs. Analog Input Frequency with Different Analog Input
Full-Scale Values (AIN > 650 MHz)
85
70
69
80
68
75
SFDR (dBFS)
66
65
64
63
70
65
60
62
INPUT FULL-SCALE = 1.36V p-p
INPUT FULL-SCALE = 1.7V p-p
INPUT FULL-SCALE = 2.04V p-p
60
0
200
400
600
ANALOG INPUT FREQUENCY (MHz)
INPUT FULL-SCALE = 1.36V p-p
INPUT FULL-SCALE = 1.7V p-p
INPUT FULL-SCALE = 2.04V p-p
55
50
650
15660-024
61
Figure 52. SNR vs. Analog Input Frequency with Different Analog Input
Full-Scale Values (AIN < 650 MHz)
750
850
950
1050
1150
1250
ANALOG INPUT FREQUENCY (MHz)
15660-027
SNR (dBFS)
67
Figure 55. SFDR vs. Analog Input Frequency with Different Analog Input
Full-Scale Values (AIN > 650 MHz)
80
100
95
70
90
60
IAVDD3 (mA)
80
75
70
50
40
65
60
30
50
0
200
400
ANALOG INPUT FREQUENCY (MHz)
600
15660-025
INPUT FULL-SCALE = 1.36V p-p
INPUT FULL-SCALE = 1.7V p-p
INPUT FULL-SCALE = 2.04V p-p
55
Figure 53. SFDR vs. Analog Input Frequency with Different Analog Input
Full-Scale Values (AIN < 650 MHz)
Rev. C | Page 24 of 136
20
160
210
260
310
360
BUFFER CURRENT (µA)
Figure 56. IAVDD3 vs. Buffer Control 1 Setting in Register 0x1A4C
15660-028
SFDR (dBFS)
85
Data Sheet
AD9695
EQUIVALENT CIRCUITS
AVDD3
AVDD3
VIN+x
3.5pF
AVDD3
400Ω
EMPHASIS/SWING
CONTROL (SPI)
VCM
BUFFER
10pF
100Ω
DRVDD1
AVDD3
AVDD3
DATA+
SERDOUTx+
x = 0, 1, 2, 3
VIN–x
DRGND
OUTPUT
DRIVER
AIN
CONTROL
(SPI)
DATA–
SERDOUTx–
x = 0, 1, 2, 3
15660-029
3.5pF
DRGND
Figure 57. Analog Inputs
Figure 60. Digital Outputs
DRVDD1
AVDD1
CLK+
DRVDD1
15660-032
100Ω
25Ω
2.5kΩ
16kΩ
DRGND
DRVDD1
100Ω
SYNCINB+
CMOS
PATH
SYNCINB PIN
CONTROL (SPI)
10kΩ
AVDD1
1.9pF
25Ω
LEVEL
TRANSLATOR
DRGND
VCM = 0.65V
130kΩ
Figure 58. Clock Inputs
100Ω
SYNCINB–
100Ω
DRVDD1
10kΩ
1.9pF
AVDD1_SR
SYSREF+
DRGND
10kΩ
DRGND
15660-033
16kΩ
130kΩ
15660-030
CLK–
DRGND
Figure 61. SYNCINB± Inputs
1.9pF
130kΩ
LEVEL
TRANSLATOR
SPIVDD
10kΩ
1.9pF
ESD
PROTECTED
14808-026
SYSREF–
100Ω
AVDD1_SR
SCLK
56kΩ
ESD
PROTECTED
Figure 59. SYSREF± Inputs
SPIVDD
DGND
Figure 62. SCLK Input
Rev. C | Page 25 of 136
DGND
15660-034
130kΩ
AD9695
Data Sheet
SPIVDD
SPIVDD
ESD
PROTECTED
56kΩ
ESD
PROTECTED
PDWN/
STBY
CSB
56kΩ
ESD
PROTECTED
DGND
PDWN
CONTROL (SPI)
15660-035
DGND
DGND
DGND
Figure 63. CSB Input
15660-037
ESD
PROTECTED
Figure 65. PDWN/STBY Input
SPIVDD
SPIVDD
SDI
DGND
56kΩ
DGND
DGND
TEMPERATURE DIODE
VOLTAGE OUTPUT
AVDD2
SDO
DGND
EXTERNAL REFERENCE
VOLTAGE INPUT
VREF
15660-036
ESD
PROTECTED
VCM OUTPUT
SPIVDD
VREF PIN
CONTROL (SPI)
AGND
Figure 66. VREF Input/Output
Figure 64. SDIO Input
SPIVDD
SPIVDD
ESD
PROTECTED
NCO BAND SELECT
DGND
FD_A/GPIO_A0,
FD_B/GPIO_B0
SPIVDD
FD
JESD204B LMFC
56kΩ
ESD
PROTECTED
JESD204B SYNC~
DGND
DGND
DGND
FD PIN CONTROL (SPI)
Figure 67. FD_A/GPIO_A0 and FD_B/GPIO_B0
Rev. C | Page 26 of 136
15660-039
SDIO
15660-038
ESD
PROTECTED
Data Sheet
AD9695
THEORY OF OPERATION
The AD9695 has two analog input channels and up to four
JESD204B output lane pairs. The ADC samples wide bandwidth
analog signals of up to 2 GHz. The actual −3 dB roll-off of the
analog inputs is 2 GHz. The AD9695 is optimized for wide input
bandwidth, high sampling rate, excellent linearity, and low
power in a small package.
ultimately create a low-pass filter that limits unwanted
broadband noise. For more information, refer to the Analog
Dialogue article “Transformer-Coupled Front-End for
Wideband A/D Converters” (Volume 39, April 2005). In
general, the precise front-end network component values
depend on the application.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
Figure 68 shows the differential input return loss curve for the
analog inputs across a frequency range of 1 MHz to 10 GHz.
The reference impedance is 100 Ω.
The AD9695 has several functions that simplify the AGC
function in a communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to
avoid an overrange condition at the ADC input.
ADC ARCHITECTURE
The architecture of the AD9695 consists of an input buffered
pipelined ADC. The input buffer provides a termination
impedance to the analog input signal. This termination
impedance is set to 200 Ω. The equivalent circuit diagram of the
analog input termination is shown in Figure 57. The input
buffer is optimized for high linearity, low noise, and low power
across a wide bandwidth.
The input buffer provides a linear high input impedance (for
ease of drive) and reduces kickback from the ADC. The
quantized outputs from each stage are combined into a final
14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate with a new input
sample; at the same time, the remaining stages operate with the
preceding samples. Sampling occurs on the rising edge of the clock.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9695 is a differential buffer. The
internal common-mode voltage of the buffer is 1.41 V. The
clock signal alternately switches the input circuit between
sample mode and hold mode.
Either a differential capacitor or two single-ended capacitors
(or a combination of both) can be placed on the inputs to
provide a matching passive network. These capacitors
182.88Ω
–932.98mΩ
177.37Ω
–34.81Ω
157.29Ω
–65.95Ω
128.82Ω
–81.70Ω
102.55Ω
–84.58Ω
82.01Ω
1
–79.60Ω
2
3
6
4
5
CH1 AVG = 1
> CH1: START 1.0MHz
STOP 10.0000GHz
15660-200
The Subclass 1 JESD204B-based high speed, serialized output data
lanes can be configured in one-lane (L = 1), two-lane (L = 2), and
four-lane (L = 4) configurations, depending on the sample rate
and the decimation ratio. Multiple device synchronization is
supported through the SYSREF± and SYNCINB± input pins.
The SYSREF± pin in the AD9695 can also be used as a timestamp
of data as it passes through the ADC and out of the JESD204B
interface.
1: 1.000MHz
170.59nF
2: 100.000 MHz
45.72pF
3: 200.000MHz
12.07pF
4: 300.000MHz
6.49pF
5: 400.000MHz
4.70pF
6: 500.000MHz
4.00pF
Figure 68. AD9695 Different Input Return Loss
For best dynamic performance, the source impedances driving
VIN+x and VIN−x must be matched such that any commonmode settling errors are symmetrical. These errors are reduced
by the common-mode rejection of the ADC. An internal reference
buffer creates a differential reference that defines the span of the
ADC core.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. For the AD9695,
the available span is programmable through the SPI port from
1.36 V p-p to 2.04 V p-p differential, with 1.7 V p-p differential
being the default.
Differential Input Configurations
There are several ways to drive theAD9695, either actively or
passively. Optimum performance is achieved by driving the
analog input differentially.
For applications where SNR and SFDR are key parameters,
differential transformer coupling is the recommended input
configuration (see Figure 69 and Table 10) because the noise
performance of most amplifiers is not adequate to achieve the
true performance of the AD9695.
For low to midrange frequencies, a double balun or double
transformer network (see Figure 69 and Table 10) is recommended for optimum performance of the AD9695. For higher
frequencies in the second or third Nyquist zones, it is recommended to remove some of the front-end passive components
to ensure wideband operation (see Table 10).
Rev. C | Page 27 of 136
AD9695
Data Sheet
C2
R1
R3
C3
R2
MARKI
BAL-0006
C4
C2
ADC
R3
C3
15547-050
R1
200Ω
C1
R2
NOTES:
1. SEE TABLE 9 FOR COMPONENT VALUES
Figure 69. Differential Transformer-Coupled Configuration for the AD9695
Table 10. Differential Transformer-Coupled Input Configuration Component Values
Speed Grade
AD9695-625
AD9695-1300
Transformer
BAL-0006/BAL-0006SMG
BAL-0006/BAL-0006SMG
R1
25 Ω
25 Ω
R2
25 Ω
25 Ω
R3
10 Ω
10 Ω
C1
0.1 μF
0.1 μF
C2
0.1 μF
0.1 μF
C3
DNI1
DNI1
C4
DNI1
DNI1
DNI means do not insert.
The analog inputs of the AD9695 are internally biased to the
common mode, as shown in Figure 71.
For dc-coupled applications, the recommended operation
procedure is to export the common-mode voltage to the VREF pin
using the SPI writes listed in this section. The common-mode
voltage must be set by the exported value to ensure proper
ADC operation. Disconnect the internal common-mode buffer
from the analog input using Register 0x1908.
When performing SPI writes for dc coupling operation, use the
following register settings, in order:
1.
2.
3.
4.
5.
6.
7.
8.
Set Register 0x1908, Bit 2 to 1 to disconnect the internal
common-mode buffer from the analog input.
Set Register 0x18A6 to 0x00 to turn off the voltage
reference.
Set Register 0x18E6 to 0x00 to turn off the temperature
diode export.
Set Register 0x18E0 to 0x02.
Set Register 0x18E1 to 0x14.
Set Register 0x18E2 to 0x14.
Set Register 0x18E3, Bit 6 to 0x01 to turn on the VCM export.
Set Register 0x18E3, Bits[5:0] to the buffer current setting
(copy the buffer current setting from Register 0x1A4C and
Register 0x1A4D to improve the accuracy of the commonmode export).
Figure 70 shows the block diagram representation of a dccoupled application.
ADC
ADC
AMP A
VOCM
VREF
VOCM
ADC
AMP B
VCM EXPORT SELECT
SPI REGISTERS 0x1908,
0x18A6, 0x18E3, 0x18E6)
15660-041
Input Common Mode
Figure 70. DC-Coupled Application Using the AD9695
Analog Input Buffer Controls and SFDR Optimization
The AD9695 input buffer offers flexible controls for the analog
inputs, such as, buffer current, and input full-scale adjustment.
All the available controls are shown in Figure 71.
AVDD3
AVDD3
VIN+
3.5pF
100Ω
AVDD3
100Ω
AVDD3
VIN–
REG
(0x0008,
0x1908)
AVDD3
3.5pF
REG (0x0008, 0x1A4C,
0x1A4D, 0x1910)
Figure 71. Analog Input Controls
Rev. C | Page 28 of 136
15660-042
1
Frequency Range
0). The latency of this overrange indicator matches the
sample latency.
The AD9695 also records any overrange condition in any of the
eight virtual converters. For more information on the virtual
converters, refer to Figure 90. The overrange status of each virtual
converter is registered as a sticky bit in Register 0x563. The
contents of Register 0x563 can be cleared using Register 0x562,
by toggling the bits corresponding to the virtual converter to set
and reset position.
Lower Threshold Magnitude (dBFS) = 20 log (Threshold
Magnitude/213)
For example, to set an upper threshold of −6 dBFS, write 0xFFF
to Register 0x0247 and Register 0x0248. To set a lower threshold of
−10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A.
FAST THRESHOLD DETECTION (FD_A AND FD_B)
The fast detect bit is immediately set whenever the absolute value
of the input signal exceeds the programmable upper threshold
level. The FD bit is only cleared when the absolute value of the
input signal drops below the lower threshold level for greater
than the programmable dwell time. This feature provides
hysteresis and prevents the FD bit from excessively toggling.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located at Register 0x24B and Register 0x024C. See
the Memory Map section (Register 0x0040, and Register 0x0245 to
Register 0x024C in Table 48) for more details.
UPPER THRESHOLD
DWELL TIME
TIMER RESET BY
RISE ABOVE
LOWER
THRESHOLD
DWELL TIME
FD_A OR FD_B
Figure 89. Threshold Settings for FD_A and FD_B Signals
Rev. C | Page 34 of 136
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE
LOWER THRESHOLD
15660-060
MIDSCALE
LOWER THRESHOLD
Data Sheet
AD9695
ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING
The AD9695 contains a configurable signal path that allows
different features to be enabled for different applications. These
features are controlled using the chip application mode register,
Register 0x0200. The chip operating mode is controlled by
Bits[3:0] in this register, and the chip Q ignore is controlled by
Bit 5.
The AD9695 contains the following modes:
•
•
Full bandwidth mode: two 14-bit ADC cores running at
the full sample rate.
DDC mode: up to four digital downconverter (DDC)
channels.
Table 12 shows the number of virtual converters required and
the transport layer mapping when channel swapping is
disabled. Figure 90 shows the virtual converters and their
relationship to the DDC outputs when complex outputs are
used.
Each DDC channel outputs either two sample streams (I/Q) for
the complex data components (real + imaginary), or one sample
stream for real (I) data. The AD9695 can be configured to use up
to eight virtual converters, depending on the DDC configuration.
The I/Q samples are always mapped in pairs with the I samples
mapped to the first virtual converter and the Q samples
mapped to the second virtual converter. With this transport layer
mapping, the number of virtual converters are the same
whether a single real converter is used along with a digital
downconverter block producing I/Q outputs, or whether an
analog downconversion is used with two real converters
producing I/Q outputs.
After the chip application mode is selected, the output
decimation ratio is set using the chip decimation ratio in
Register 0x0201, Bits[3:0]. The output sample rate = ADC
sample rate/the chip decimation ratio.
To support the different application layer modes, the AD9695
treats each sample stream (real, I, or Q) as originating from
separate virtual converters.
Figure 91 shows a block diagram of the two scenarios described
for I/Q transport layer mapping.
Table 12. Virtual Converter Mapping
Number of
Virtual
Converters
Supported
1 to 2
1
2
2
4
4
8
Chip Operating
Mode
(Reg. 0x0200,
Bits[3:0])
Full bandwidth
mode (0x0)
One DDC mode
(0x1)
One DDC mode
(0x1)
Two DDC mode
(0x2)
Two DDC mode
(0x2)
Four DDC mode
(0x3)
Four DDC mode
(0x3)
Virtual Converter Mapping
Chip Q Ignore
(0x0200, Bit 5)
Real or
complex (0x0)
Real (I only)
(0x1)
Complex (I/Q)
(0x0)
Real (I only)
(0x1)
Complex (I/Q)
(0x0)
Real (I only)
(0x1)
Complex (I/Q)
(0x0)
0
ADC A
samples
DDC0 I
samples
DDC0 I
samples
DDC0 I
samples
DDC0 I
samples
DDC0 I
samples
DDC0 I
samples
1
ADC B
samples
Unused
DDC0 Q
samples
DDC1 I
samples
DDC0 Q
samples
DDC1 I
samples
DDC0 Q
samples
2
Unused
3
Unused
4
Unused
5
Unused
6
Unused
7
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
DDC1 I
samples
DDC2 I
samples
DDC1 I
samples
DDC1 Q
samples
DDC3 I
samples
DDC1 Q
samples
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
DDC2 I
samples
DDC2 Q
samples
DDC3 I
samples
DDC3 Q
samples
Rev. C | Page 35 of 136
AD9695
Data Sheet
ADC A
SAMPLING
AT fS
REAL/Q
REAL/I
I/Q
CROSSBAR
MUX
REAL/Q
REAL/I
REAL/Q
REAL/Q
REAL/I
ADC B
SAMPLING
AT fS
REAL/Q
DDC 0
I
Q
DDC 1
I
DDC 2
I
Q
DDC 3
Q
REAL/I
CONVERTER 2
Q
Q
CONVERTER 3
I
Q
I
REAL/I
CONVERTER 0
Q
Q
CONVERTER 1
I
OUTPUT
INTERFACE
REAL/I
I
CONVERTER 4
Q
Q
CONVERTER 5
REAL/I
CONVERTER 6
Q
Q
CONVERTER 7
I
15660-061
REAL/I
REAL/I
Figure 90. DDCs and Virtual Converter Mapping
DIGITAL DOWNCONVERSION
M=2
I
CONVERTER 0
REAL
ADC
REAL
DIGITAL
DOWNCONVERSION
JESD204B
Tx
L LANES
JESD204B
Tx
L LANES
Q
CONVERTER 1
REAL
90°
PHASE
Q
ADC
Q
CONVERTER 1
Figure 91. I/Q Transport Layer Mapping
Rev. C | Page 36 of 136
15660-062
I
I/Q ANALOG MIXING
M=2
I
CONVERTER 0
ADC
Data Sheet
AD9695
PROGRAMMABLE FINITE IMPULSE RESPONSE (FIR) FILTERS
SUPPORTED MODES
•
The AD9695 supports the following modes of operation (the
asterisk symbol (*) denotes convolution):
•
•
PROGRAMMABLE FILTER (PFILT)
I (REAL)
ADC A
CORE
DINI [n]
48-TAP FIR
FILTER
xyI [n]
DOUTI [n]
I′ (REAL)
SIGNAL
PROCESSING
BLOCKS
Q (IMAG)
ADC B
CORE
DINQ [n]
48-TAP FIR
FILTER
xyQ [n]
DOUTQ [n]
JESD204B
INTERFACE
Q′ (IMAG)
15660-063
•
•
Real 48-tap filter for each I/Q channel (see Figure 92)
• DOUT_I[n] = DIN_I[n] * XY_I[n]
• DOUT_Q[n] = DIN_Q[n] * XY_Q[n]
Real 96-tap filter for on either I or Q channel (see Figure 93)
DOUT_I[n] = DIN_I[n] * XY_I_XY_Q[n]
• DOUT_Q[n] = DIN_Q[n]
Real set of two cascaded 24-tap filters for each I/Q channel
(see Figure 94)
• DOUT_I[n] = DIN_I[n] * X_I[n] * Y_I[n]
• DOUT_Q[n] = DIN_Q[n] * X_Q[n] * Y_Q[n]
Figure 92. Real 48-Tap Filter Configuration
PROGRAMMABLE FILTER (PFILT)
I (REAL)
ADC A
CORE
DINI [n]
96-TAP FIR
FILTER
xIyIxQyQ [n]
DOUTI [n]
I′ (REAL)
SIGNAL
PROCESSING
BLOCKS
Q (IMAG)
ADC B
CORE
DINQ [n]
DOUTQ [n]
Q′ (IMAG)
Figure 93. Real 96-Tap Filter Configuration
Rev. C | Page 37 of 136
JESD204B
INTERFACE
15660-064
•
Half complex filter using two real 48-tap filters for the I/Q
channels (see Figure 95)
• DOUT_I[n] = DIN_I[n]
• DOUT_Q[n] = DIN_Q[n] * XY_Q[n] + DIN_I[n] *
XY_I[n]
Full complex filter using four real 24-tap filters for the I/Q
channels (see Figure 96)
• DOUT_I[n] = DIN_I[n] * X_I[n] + DIN_Q[n] *
Y_Q[n]
• DOUT_Q[n] = DIN_Q[n] * X_Q[n] + DIN_I[n] *
Y_I[n]
AD9695
Data Sheet
PROGRAMMABLE FILTER (PFILT)
I (REAL)
ADC A
CORE
DINI [n]
24-TAP FIR
FILTER
xI [n]
DOUTI [n]
24-TAP FIR
FILTER
yI [n]
I′ (REAL)
SIGNAL
PROCESSING
BLOCKS
JESD204B
INTERFACE
24-TAP FIR
FILTER
yQ [n]
ADC B
CORE
DINQ [n]
24-TAP FIR
FILTER
xQ [n]
DOUTQ [n]
Q′ (IMAG)
15660-065
Q (IMAG)
Figure 94. Real, Two Cascaded, 24-Tap Filter Configuration
PROGRAMMABLE FILTER (PFILT)
I (REAL)
ADC A
CORE
DINI [n]
DOUTI [n]
0 TO 47
DELAY TAPS
48-TAP FIR
FILTER
xyI [n]
I′ (REAL)
SIGNAL
PROCESSING
BLOCKS
JESD204B
INTERFACE
+
ADC B
CORE
DINQ [n]
48-TAP FIR
FILTER
xyQ [n]
+
DOUTQ [n]
Q′ (IMAG)
15660-066
Q (IMAG)
Figure 95. 48-Tap Half Complex Filter Configuration
PROGRAMMABLE FILTER (PFILT)
I (REAL)
ADC A
CORE
DINI [n]
24-TAP FIR
FILTER
xI [n]
DOUTI [n]
+
I′ (REAL)
+
24-TAP FIR
FILTER
yI [n]
SIGNAL
PROCESSING
BLOCKS
JESD204B
INTERFACE
24-TAP FIR
FILTER
yQ [n]
ADC B
CORE
DINQ [n]
24-TAP FIR
FILTER
xQ [n]
+
DOUTQ [n]
Q′ (IMAG)
Figure 96. 24-Tap Full Complex Filter Configuration.
Rev. C | Page 38 of 136
15660-067
+
Q (IMAG)
Data Sheet
AD9695
PROGRAMMING INSTRUCTIONS
Table 13. Register 0x0DF8 Definition
Use the following procedure to set up the programmable FIR filter:
Bits
[7:3]
[2:0]
1.
2.
3.
4.
5.
6.
7.
Enable the sample clock to the device.
Configure the mode registers as follows:
a. Set the device index to Channel A (I path)
(Register 0x0008 = 0x01).
b. Set the I path mode (I mode) and gain in
Register 0x0DF8 and Register 0x0DF9 (see Table 13
and Table 14).
c. Set the device index to Channel B (Q path)
(Register 0x0008 = 0x02).
d. Set the Q path mode (Q mode) and gain in
Register 0x0DF8 and Register 0x0DF9.
Wait at least 5 µs to allow the programmable filter to power
up.
Program the I path coefficients to the internal shadow
registers as follows:
a. Set the device index to Channel A (I path)
(Register 0x0008 = 0x01).
b. Program the XI coefficients in Register 0x0E00 to
Register 0x0E2F (see Table 15 and Table 16).
c. Program the YI coefficients in Register 0x0F00 to
Register 0x0F2F (see Table 15 and Table 16).
d. Program the tapped delay in Register 0x0F30 (note
that this step is optional).
Program the Q path coefficients to the internal shadow
registers as follows:
a. Set the device index to Channel B (Q path)
(Register 0x0008 = 0x02).
b. Set the Q path mode and gain in Register 0x0DF8 and
Register 0x0DF9 (see Table 13 and Table 14).
c. Program the XQ coefficients in Register 0x0E00 to
Register 0x0E2F (see Table 15 and Table 16).
d. Program the YQ coefficients in Register 0x0F00 to
Register 0x0F2F (see Table 15 and Table 16)
e. Program the tapped delay in Register 0x0F30 (note
that this step is optional).
Set the chip transfer bit using either of the following
methods (note that setting the chip transfer bit applies the
programmed shadow coefficients to the filter):
a. Via the register map by setting the chip transfer bit
(Register 0x000F = 0x01).
b. Via a GPIO pin, as follows:
i. Configure one of the GPIO pins as the chip
transfer bit in Register 0x0040 to Register 0x0042.
ii. Toggle the GPIO pin to initiate the chip transfer
(the rising edge is triggered).
When the I or Q path mode register changes in
Register 0x0DF8, all coefficients must be reprogrammed.
Description
Reserved
Filter mode (I mode or Q mode)
000: filters bypassed
001: real 24-tap filter (X only)
010: real 48-tap filter (X and Y together)
100: real set of two cascaded 24-tap filters (X then Y
cascaded)
101: full complex filter using four real 24-tap filters for
the A/B channels (opposite channel must also be set to
101)
110: half complex filter using two real 48-tap filters +
48-tap delay line (X and Y together) (opposite
channel must also be set to 010)
111: real 96-tap filter (XI, YI, XQ, and YQ together)
(opposite channel must be set to 000)
Table 14. Register 0x0DF9 Definition
Bits
7
[6:4]
3
[2:0]
Description
Reserved
Y filter gain
110: −12 dB loss
111: −6 dB loss
000: 0 dB gain
001: 6 dB gain
010: 12 dB gain
Reserved
X filter gain
110: −12 dB loss
111: −6 dB loss
000: 0 dB gain
001: 6 dB gain
010: 12 dB gain
Table 15 and Table 16 show the coefficient tables in
Register 0x0E00 to Register 0x0F30. All coefficients are
Q1.15 format (sign bit + 15 fractional bits).
Rev. C | Page 39 of 136
AD9695
Data Sheet
Table 15. I Coefficient Table (Device Selection = 0x1) 1
Addr.
0x0E00
0x0E01
0x0E02
0x0E03
…
0x0E2E
0x0E2F
0x0F00
0x0F01
0x0F02
0x0F03
…
0x0F2E
0x0F2F
0x0F30
Single 24-Tap
Filter (I Mode
[2:0] = 0x1)
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
Unused
Unused
Unused
Unused
…
Unused
Unused
Unused
Single 48-Tap
Filter (I Mode
[2:0] = 0x2)
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
YI C24 [7:0]
YI C24 [15:8]
YI C25 [7:0]
YI C25 [15:8]
…
YI C47 [7:0]
YI C47 [15:0]
Unused
Two Cascaded
24-Tap Filters (I
Mode [2:0] = 0x4)
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
YI C0 [7:0]
YI C0 [15:8]
YI C1 [7:0]
YI C1 [15:8]
…
YI C23 [7:0]
YI C23 [15:0]
Unused
Full Complex
24-Tap Filters (I
Mode [2:0] = 0x5
and Q Mode
[2:0] = 0x5)
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
YI C0 [7:0]
YI C0 [15:8]
YI C1 [7:0]
YI C1 [15:8]
…
YI C23 [7:0]
YI C23 [15:0]
Unused
Half Complex
48-Tap Filters (I
Mode [2:0] = 0x6
and Q Mode
[2:0] = 0x2) 2
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
YI C24 [7:0]
YI C24 [15:8]
YI C25 [7:0]
YI C25 [15:8]
…
YI C47 [7:0]
YI C47 [15:0]
I path tapped delay
0: 0 tapped delay
(matches C0 in the
filter)
1: 1 tapped delays
…
47: 47 tapped delays
XI Cn means I Path X Coefficient n. YI Cn means I Path Y Coefficient n.
When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode.
3
When using the I path in 96-tap filter mode, the Q path must be in bypass mode.
1
2
Rev. C | Page 40 of 136
I Path 96-Tap Filter
(I Mode[2:0] = 0x7
and Q Mode
[2:0] = 0x0) 3
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
YI C24 [7:0]
YI C24 [15:8]
YI C25 [7:0]
YI C25 [15:8]
…
YI C47 [7:0]
YI C47 [15:0]
Unused
Q Path 96-Tap
Filter (I Mode
[2:0] = 0x0 and Q
Mode [2:0] = 0x7)3
XQ C48 [7:0]
XQ C48 [15:8]
XQ C49 [7:0]
XQ C49 [15:8]
…
XQ C71 [7:0]
XQ C71 [15:0]
YQ C72 [7:0]
YQ C72 [15:8]
YQ C73 [7:0]
YQ C73 [15:8]
…
YQ C95 [7:0]
YQ C95 [15:0]
Unused
Data Sheet
AD9695
Table 16. Q Coefficient Table (Device Selection = 0x2) 1
Addr.
0x0E00
0x0E01
0x0E02
0x0E03
…
0x0E2E
0x0E2F
0x0F00
0x0F01
0x0F02
0x0F03
…
0x0F2E
0x0F2F
0x0F30
1
2
3
Single 24-Tap
Filter (Q Mode
[2:0] = 0x1)
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
Unused
Unused
Unused
Unused
…
Unused
Unused
Unused
Single 48-Tap
Filter (Q Mode
[2:0] = 0x2)
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
YQ C24 [7:0]
YQ C24 [15:8]
YQ C25 [7:0]
YQ C25 [15:8]
…
YQ C47 [7:0]
YQ C47 [15:0]
Unused
Two Cascaded
24-Tap Filters (Q
Mode [2:0] = 0x4)
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
YQ C0 [7:0]
YQ C0 [15:8]
YQ C1 [7:0]
YQ C1 [15:8]
…
YQ C23 [7:0]
YQ C23 [15:0]
Unused
Full Complex
24-Tap Filters (Q
Mode [2:0] = 0x5
and I Mode
[2:0] = 0x5)
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
YQ C0 [7:0]
YQ C0 [15:8]
YQ C1 [7:0]
YQ C1 [15:8]
…
YQ C23 [7:0]
YQ C23 [15:0]
Unused
Half Complex
48-Tap Filters (Q
Mode [2:0] = 0x6
and I Mode
[2:0] = 0x2)2
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
YQ C24 [7:0]
YQ C24 [15:8]
YQ C25 [7:0]
YQ C25 [15:8]
…
YQ C47 [7:0]
YQ C47 [15:0]
Q path tapped
delay
0: 0 tapped delay
(matches C0 in the
filter)
1: 1 tapped delays
…
47: 47 tapped
delays
XQ Cn means Q Path X Coefficient n. YQ Cn means Q Path Y Coefficient n.
When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode.
When using the I path in 96-tap filter mode, the Q path must be in bypass mode.
Rev. C | Page 41 of 136
I Path 96-Tap
Filter (Q Mode
[2:0] = 0x0 and I
Mode [2:0] = 0x7) 3
XI C48 [7:0]
XI C48 [15:8]
XI C49 [7:0]
XI C49 [15:8]
…
XI C71 [7:0]
XI C71 [15:0]
YI C72 [7:0]
YI C72 [15:8]
YI C73 [7:0]
YI C73 [15:8]
…
YI C95 [7:0]
YI C95 [15:0]
Unused
Q Path 96-Tap
Filter (Q Mode
[2:0] = 0x7 and I
Mode [2:0] = 0x0)3
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
YQ C24 [7:0]
YQ C24 [15:8]
YQ C25 [7:0]
YQ C25 [15:8]
…
YQ C47 [7:0]
YQ C47 [15:0]
Unused
AD9695
Data Sheet
DIGITAL DOWNCONVERTER (DDC)
The AD9695 includes four digital downconverters (DDC 0 to
DDC 3) that provide filtering and reduce the output data rate.
This digital processing section includes an NCO, multiple
decimating FIR filters, a gain stage, and a complex to real
conversion stage. Each of these processing blocks has control lines
that allow it to be independently enabled and disabled to provide
the desired processing function. The digital downconverter can be
configured to output either real data or complex output data.
The DDCs output a 16-bit stream. To enable this operation, the
converter number of bits, N, is set to a default value of 16, even
though the analog core only outputs 14 bits. In full bandwidth
operation, the ADC outputs are the 14-bit word followed by two
zeros, unless the tail bits are enabled.
DDC I/Q INPUT SELECTION
The AD9695 has two ADC channels and four DDC channels.
Each DDC channel has two input ports that can be paired to
support both real and complex inputs through the I/Q crossbar
mux. For real signals, both DDC input ports must select the
same ADC channel (that is, DDC Input Port I = ADC Channel A
and DDC Input Port Q = ADC Channel A). For complex
signals, each DDC input port must select different ADC
channels (that is, DDC Input Port I = ADC Channel A and
DDC Input Port Q = ADC Channel B).
The inputs to each DDC are controlled by the DDC input selection registers (Register 0x0311, Register 0x0331, Register 0x0351
and Register 0x0371). See Table 48 for information on how to
configure the DDCs.
DDC I/Q OUTPUT SELECTION
Each DDC channel has two output ports that can be paired to
support both real and complex outputs. For real output signals,
only the DDC Output Port I is used (the DDC Output Port Q is
invalid). For complex I/Q output signals, both DDC Output
Port I and DDC Output Port Q are used.
The I/Q outputs to each DDC channel are controlled by the
DDC complex to real enable bit, Bit 3, in the DDC control
registers (Register 0x0310, Register 0x0330, Register 0x0350
and Register 0x370).
The chip Q ignore bit in the chip mode register (Register 0x0200,
Bit 5) controls the chip output muxing of all the DDC channels.
When all DDC channels use real outputs, set this bit high to
ignore all DDC Q output ports. When any of the DDC
channels are set to use complex I/Q outputs, the user must clear
this bit to use both DDC Output Port I and DDC Output Port
Q. For more information, see Figure 130.
DDC GENERAL DESCRIPTION
The four DDC blocks extract a portion of the full digital
spectrum captured by the ADC(s). They are intended for IF
sampling or oversampled baseband radios requiring wide
bandwidth input signals.
Each DDC block contains the following signal processing stages:
•
•
•
•
Frequency translation stage (optional)
Filtering stage
Gain stage (optional)
Complex to real conversion stage (optional)
Frequency Translation Stage (Optional)
This stage consists of a phase coherent NCO and quadrature
mixers that can be used for frequency translation of both real or
complex input signals. The phase coherent NCO allows an
infinite number of frequency hops that are all referenced back
to a single synchronization event. It also includes 16 shadow
registers for fast switching applications. This stage shifts a
portion of the available digital spectrum down to baseband.
Filtering Stage
After shifting down to baseband, this stage decimates the
frequency spectrum using multiple low pass finite impulse
response (FIR) filters for rate conversion. The decimation
process lowers the output data rate, which in turn reduces the
output interface rate.
Gain Stage (Optional)
Due to losses associated with mixing a real input signal down to
baseband, this stage compensates by adding an additional 0 dB
or 6 dB of gain.
Complex to Real Conversion Stage (Optional)
When real outputs are necessary, this stage converts the complex
outputs back to real by performing an fS/4 mixing operation
plus a filter to remove the complex component of the signal.
Figure 97 shows the detailed block diagram of the DDCs
implemented in the AD9695.
Figure 98 shows an example usage of one of the four DDC
channels with a real input signal and four half-band filters
(HB4 + HB3 + HB2 + HB1) used. It shows both complex
(decimate by 16) and real (decimate by 8) output options.
Rev. C | Page 42 of 136
Data Sheet
AD9695
COMPLEX TO REAL
CONVERSION (OPTIONAL)
COMPLEX TO REAL
CONVERSION (OPTIONAL)
Q CONVERTER 1
DECIMATION
FILTERS
Q
REAL/I
CONVERTER 2
Q CONVERTER 3
DDC 2
REAL/I
I
DECIMATION
FILTERS
Q
REAL/I
CONVERTER 4
JESD204B TRANSMIT INTERFACE
I/Q CROSSBAR MUX
REAL/I
ADC B
SAMPLING
AT fS
L
JESD204B
LANES
AT UP TO
16Gbps
Q CONVERTER 5
DDC 3
I
NCO
+
MIXER
(OPTIONAL)
REAL/I
DECIMATION
FILTERS
Q
SYSREF±
REAL/I
CONVERTER 6
Q CONVERTER 7
SYSREF
DCM = DECIMATION
15660-068
NCO CHANNEL
SELECTION
CIRCUITS
DECIMATION
FILTERS
REAL/I
CONVERTER 0
DDC 1
REAL/I
GPIO PINS
COMPLEX TO REAL
CONVERSION (OPTIONAL)
I
REAL/I
SYNCHRONIZATION
CONTROL CIRCUITS
COMPLEX TO REAL
CONVERSION (OPTIONAL)
REAL/I
NCO
+
MIXER
(OPTIONAL)
REGISTER MAP
CONTROLS
GAIN = 0 OR +6dB
Q
NCO
+
MIXER
(OPTIONAL)
SYSREF
PIN
GAIN = 0 OR +6dB
REAL/I
ADC A
SAMPLING
AT fS
REAL/Q
GAIN = 0 OR +6dB
I
NCO
+
MIXER
(OPTIONAL)
REAL/I
GAIN = 0 OR +6dB
DDC 0
REAL/I
NCO CHANNEL SELECTION
Figure 97. DDC Detailed Block Diagram
Rev. C | Page 43 of 136
AD9695
Data Sheet
ADC
ADC
SAMPLING
AT fS
REAL
REAL INPUT—SAMPLED AT fS
BANDWIDTH OF
INTEREST IMAGE
–fS/2
–fS/3
–fS/4
REAL
BANDWIDTH OF
INTEREST
fS/32
–fS/32
DC
fS/16
–fS/16
–fS/8
fS/8
fS/4
fS/3
fS/2
FREQUENCY TRANSLATION STAGE (OPTIONAL)
I
DIGITAL MIXER + NCO
FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND
((fS/3)/fS × 248) = +9.382513
(0x5555_5555_5555)
NCO TUNES CENTER OF
BANDWIDTH OF INTEREST
TO BASEBAND
cos(ωt)
REAL
48-BIT
NCO
90°
0°
–sin(ωt)
Q
DIGITAL FILTER
RESPONSE
–fS/2
–fS/3
–fS/4
fS/32
–fS/32
DC
fS/16
–fS/16
–fS/8
BANDWIDTH OF
INTEREST IMAGE
(–6dB LOSS DUE TO
NCO + MIXER)
BANDWIDTH OF INTEREST
(–6dB LOSS DUE TO
NCO + MIXER)
fS/8
fS/4
fS/3
fS/2
FILTERING STAGE
I
HALFBAND
FILTER
Q
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
I
HB1 FIR
HB2 FIR
HB3 FIR
HB4 FIR
HB1 FIR
HB2 FIR
HB3 FIR
HB4 FIR
4 DIGITAL HALF-BAND FILTERS
(HB4 + HB3 + HB2 + HB1)
2
HALFBAND
FILTER
Q
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
DIGITAL FILTER
RESPONSE
0dB OR 6dB GAIN
I
GAIN STAGE (OPTIONAL)
Q
0dB OR 6dB GAIN
COMPLEX TO REAL
CONVERSION STAGE (OPTIONAL)
–fS/32
fS/32
DC
–fS/16
fS/16
–fS/8
COMPLEX (I/Q) OUTPUTS
DECIMATE BY 16
GAIN STAGE (OPTIONAL)
fS/8
fS/4 MIXING + COMPLEX FILTER TO REMOVE Q
2
+6dB
2
+6dB
I
Q
fS/32
–fS/32
DC
fS/16
–fS/16
DOWNSAMPLE BY 2
I
REAL (I) OUTPUTS
+6dB
I
DECIMATE BY 8
Q
+6dB
Q
COMPLEX REAL/I
TO
REAL
–fS/8
fS/32
–fS/32
DC
–fS/16
fS/16
fS/8
Figure 98. DDC Theory of Operation Example (Real Input)
Rev. C | Page 44 of 136
15660-069
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
Data Sheet
AD9695
DDC FREQUENCY TRANSLATION
Variable IF Mode
DDC Frequency Translation General Description
NCO and mixers are enabled. NCO output frequency can be
used to digitally tune the IF frequency.
Frequency translation is accomplished by using a 48-bit
complex NCO with a digital quadrature mixer. This stage
translates either a real or complex input signal from an IF to a
baseband complex digital output (carrier frequency = 0 Hz).
0 Hz IF (ZIF) Mode
The mixers are bypassed, and the NCO is disabled.
fS/4 Hz IF Mode
The frequency translation stage of each DDC can be controlled
individually and supports four different IF modes using Bits[5:4]
of the DDC control registers (Register 0x0310, Register 0x0330,
Register 0x0350, and Register 0x0370). These IF modes are as
follows:
Test Mode
Input samples are forced to 0.999 to positive full scale. The
NCO is enabled. This test mode allows the NCOs to directly
drive the decimation filters.
Variable IF mode
0 Hz IF or zero IF (ZIF) mode
fS/4 Hz IF mode
Test mode
Figure 99 and Figure 100 show examples of the frequency
translation stage for both real and complex inputs.
NCO FREQUENCY TUNING WORD (FTW) SELECTION
48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096
I
ADC + DIGITAL MIXER + NCO
REAL INPUT—SAMPLED AT fS
REAL
cos(ωt)
ADC
SAMPLING
AT fS
REAL
48-BIT
NCO
90°
0°
COMPLEX
–sin(ωt)
Q
BANDWIDTH OF
INTEREST
BANDWIDTH OF
INTEREST IMAGE
–fS/2
–fS/3
–fS/4
–fS/8
fS/32
–fS/32
DC
–fS/16
fS/16
fS/8
fS/4
fS/3
fS/2
–6dB LOSS DUE TO
NCO + MIXER
48-BIT NCO FTW =
ROUND ((fS/3)/fS × 248) = +9.382513
(0x5555_5555_5555)
POSITIVE FTW VALUES
–fS/32
DC
fS/32
48-BIT NCO FTW =
ROUND ((fS/3)/fS × 248) = –9.382513
(0xAAAA_AAAA_AAAA)
NEGATIVE FTW VALUES
–fS/32
DC
fS/32
Figure 99. DDC NCO Frequency Tuning Word Selection—Real Inputs
Rev. C | Page 45 of 136
15660-070
•
•
•
•
The mixers and the NCO are enabled in special downmixing by
fS/4 mode to save power.
AD9695
Data Sheet
NCO FREQUENCY TUNING WORD (FTW) SELECTION
48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 248
QUADRATURE ANALOG MIXER +
2 ADCs + QUADRATURE DIGITAL
MIXER + NCO
QUADRATURE MIXER
ADC
SAMPLING
AT fS
+
I
I
I
Q
Q
REAL
90°
PHASE
48-BIT
NCO
90°
0°
COMPLEX INPUT—SAMPLED AT fS
Q
Q
ADC
SAMPLING
AT fS
Q
Q
I
I
–
–sin(ωt)
I
I
+
COMPLEX
Q
+
BANDWIDTH OF
INTEREST
IMAGE DUE TO
ANALOG I/Q
MISMATCH
–fS/3
–fS/4
–fS/8
fS/32
–fS/32
–fS/16
fS/16
DC
fS/8
fS/4
fS/3
fS/2
48-BIT NCO FTW =
ROUND ((fS/3)/fS × 248) = +9.382513
(0x5555_5555_5555)
POSITIVE FTW VALUES
fS/32
–fS/32
DC
Figure 100. DDC NCO Frequency Tuning Word Selection—Complex Inputs
Rev. C | Page 46 of 136
15660-071
–fS/2
Data Sheet
AD9695
DDC NCO Description
DDC NCO Coherent Mode
Each DDC contains one NCO. Each NCO enables the
frequency translation process by creating a complex
exponential frequency (e−jωct), which can be mixed with the
input spectrum to translate the desired frequency band of
interest to dc, where it can be filtered by the subsequent lowpass filter blocks to prevent aliasing.
This mode allows an infinite number of frequency hops where the
phase is referenced to a single synchronization event at time 0.
This mode is useful when phase coherency must be maintained
when switching between different frequency bands. In this mode,
the user can switch to any tuning frequency without the need to
reset the NCO. Although only one FTW is required, the NCO
contains 16 shadow registers for fast-switching applications.
Selection of the shadow registers is controlled by the CMOS
GPIO pins or through the register map of the SPI. In this mode,
the NCO can be set up by providing the following:
When placed in variable IF mode, the NCO supports two
different additional modes.
DDC NCO Programmable Modulus Mode
This mode supports >48-bit frequency tuning accuracy for
applications that require exact rational (M/N) frequency
synthesis at a single carrier frequency. In this mode, the NCO is
set up by providing the following:
Figure 101 shows a block diagram of one NCO and its
connection to the rest of the design. The coherent phase
accumulator block contains the logic that allows an infinite
number of frequency hops.
48-bit frequency tuning word (FTW)
48-bit Modulus A word (MAW)
48-bit Modulus B word (MBW)
48-bit phase offset word (POW)
NCO
NCO CHANNEL
SELECTION
FTW/POW
REGISTER
MAP
FTW/POW
WRITE INDEX
SYNCHRONIZATION
CONTROL CIRCUITS
I/O
CROSSBAR
MUX
48-BIT
MAW/MBW
MODULUS
ERROR
0
48-BIT
FTW/POW
0
1
48-BIT
FTW/POW
1
48-BIT
FTW/POW
15
15
COHERENT
PHASE
ACCUMULATOR
BLOCK
COS/SIN
GENERATOR
SYSREF
I
I
Q
Q
DIGITAL
QUADRATURE
MIXER
FTW = FREQUENCY TUNING WORD
POW = PHASE OFFSET WORD
MAW = MODULUS A WORD (NUMERATOR)
MBW = MODULUS B WORD (DENOMINATOR)
Figure 101. NCO + Mixer Block Diagram
Rev. C | Page 47 of 136
DECIMATION
FILTERS
15660-072
MAW/MBW
cos(x)
NCO
CHANNEL
SELECTION
CIRCUITS
Up to sixteen 48-bit FTWs.
Up to sixteen 48-bit POWs.
The 48-bit MAW must be set to zero in coherent mode.
–sin(x)
•
•
•
•
•
•
•
AD9695
Data Sheet
NCO FTW/POW/MAW/MAB Description
The NCO frequency value is determined by the following settings:
•
•
•
48-bit twos complement number entered in the FTW
48-bit unsigned number entered in the MAW
48-bit unsigned number entered in the MBW
M and N are integers reduced to their lowest terms. MAW and
MBW are integers reduced to their lowest terms. When MAW
is set to zero, the programmable modulus logic is automatically
disabled.
Frequencies between −fS/2 and +fS/2 (fS/2 excluded) are
represented using the following values:
•
•
•
Equation 1 to Equation 4 apply to the aliasing of signals in the
digital domain (that is, aliasing introduced when digitizing
analog signals).
FTW = 0x8000_0000_0000 and MAW = 0x0000_0000_0000
represents a frequency of –fS/2.
FTW = 0x0000_0000_0000 and MAW = 0x0000_0000_0000
represents dc (frequency is 0 Hz).
FTW = 0x7FFF_FFFF_FFFF and MAW = 0x0000_0000_0000
represents a frequency of +fS/2.
For example, if the ADC sampling frequency (fS) is 625 MSPS
and the carrier frequency (fC) is 208.6 MHz, then,
M 2089
mod( 417.8,1300 )
=
=
1300
N
6250
mod(2417.8,1300 )
FTW = floor 2 48
1300
= 0x5590_C0AD_03D9
NCO FTW/POW/MAW/MAB Programmable
Modulus Mode
MAW = mod(248 × 2089, 6250) = 0x0000_0000_1117
For programmable modulus mode, the MAW must be set to a
nonzero value (not equal to 0x0000_0000_0000). This mode is
only needed when frequency accuracy of >48 bits is required.
One example of a rational frequency synthesis requirement that
requires >48 bits of accuracy is a carrier frequency of 1/3 the
sample rate. When frequency accuracy of ≤48 bits is required,
coherent mode must be used (see the NCO FTW/POW/MAW/
MAB Coherent Mode section).
MBW = 0x0000_0000_186A
The actual carrier frequency can be calculated based on the
following equation:
f C _ ACTUAL =
mod( f c , f s ) M
=
=
fs
N
FTW = floor(248
MAW
MBW
248
mod( f c , f s )
fs
)
(1)
(2)
MAW = mod(248 × M, N)
(3)
MBW = N
(4)
where:
fC is the desired carrier frequency.
fS is the ADC sampling frequency.
M is the integer representing the rational numerator of the
frequency ratio.
N is the integer representing the rational denominator of the
frequency ratio.
FTW is the 48-bit twos complement number representing the
NCO FTW.
MAW is the 48-bit unsigned number representing the NCO
MAW (must be 10log(bandwidth/fS/2).
3
TB1 is only supported in DDC0 and DDC1.
2
Table 19. DDC Filter Configurations (fS = 1300 MSPS)1
ADC Sample
Rate (MSPS)
1300
1300
DDC Filter Configuration
HB1
TB12
Real (I) Output
Decimation Sample Rate
Ratio
(MSPS)
1
1300
N/A
N/A
1300
1300
HB2 + HB1
TB2 + HB1
2
3
650
433.33
1300
1300
1300
HB3 + HB2 + HB1
FB2 + HB1
TB2 + HB2 + HB1
4
5
6
325
260
216.67
1300
1300
1300
1300
1300
1300
1300
FB2 + TB12
HB4 + HB3 + HB2 + HB1
FB2 + HB2 + HB1
TB2 + HB3 + HB2 + HB1
HB2 + FB2 + TB12
FB2 + HB3 + HB2 + HB1
TB2 + HB4 + HB3 + HB2 + HB1
N/A
8
10
12
N/A
20
24
N/A
162.5
130
108.33
N/A
65
54.16
1
2
N/A means not applicable.
TB1 is only supported in DDC0 and DDC1.
Rev. C | Page 55 of 136
Complex (I/Q) Outputs
Decimation Sample Rate
Ratio
(MSPS)
2
650 (I) + 650 (Q)
433.33 (I) + 433.33
3
(Q)
4
325 (I) + 325 (Q)
216.67 (I) + 216.67
6
(Q)
8
162.5 (I) + 162.5 (Q)
10
130 (I) + 130 (Q)
108.33 (I) + 108.33
12
(Q)
15
86.67 (I) + 86.67 (Q)
16
81.25 (I) + 81.25 (Q)
20
65 (I) + 65 (Q)
24
54.16 (I) + 54.16 (Q)
30
43.44 (I) + 43.44 (Q)
40
32.5 (I) + 32.5 (Q)
48
27.08 (I) + 27.08 (Q)
Alias-Protected
Bandwidth
(MHz)
520
346.67
260
173.33
130
104
86.67
69.33
65
52
43.33
34.67
26
21.67
AD9695
Data Sheet
Table 20. DDC Filter Configurations (fS = 625 MSPS) 1
ADC Sample
Rate (MSPS)
625
625
DDC Filter Configuration
HB1
TB1 2
Real (I) Output
Decimation Sample Rate
Ratio
(MSPS)
1
625
N/A
N/A
625
HB2 + HB1
2
312.5
625
TB2 + HB1
3
208.33
625
HB3 + HB2 + HB1
4
156.25
625
625
625
625
625
625
625
625
FB2 + HB1
TB2 + HB2 + HB1
FB2 + TB12
HB4 + HB3 + HB2 + HB1
FB2 + HB2 + HB1
TB2 + HB3 + HB2 + HB1
HB2 + FB2 + TB12
FB2 + HB3 + HB2 + HB1
5
6
N/A
8
10
12
N/A
20
125
104.17
N/A
78.125
62.5
52.08
N/A
31.25
625
TB2 + HB4 + HB3 + HB2 + HB1
24
26.04
1
2
Complex (I/Q) Outputs
Decimation Sample Rate
Ratio
(MSPS)
2
312.5 (I) + 312.5 (Q)
208.33 (I) + 208.33
3
(Q)
156.25 (I) + 156.25
4
(Q)
104.17 (I) + 104.17
6
(Q)
78.125 (I) + 78.125
8
(Q)
10
62.5 (I) + 62.5 (Q)
12
52.08 (I) + 52.08 (Q)
15
41.67 (I) + 41.67 (Q)
16
39.06 (I) + 39.06 (Q)
20
31.25 (I) + 31.25 (Q)
24
26.04 (I) + 26.04 (Q)
30
20.83 (I) + 20.83 (Q)
15.625 (I) + 15.625
40
(Q)
48
13.02 (I) + 13.02 (Q)
Alias-Protected
Bandwidth
(MHz)
250
166.67
125
83.33
62.5
50
41.67
33.33
31.25
25
20.83
16.67
12.5
10.42
N/A means not applicable.
TB1 is only supported in DDC0 and DDC1.
20
HB4 Filter Description
0
–20
MAGNITUDE (dB)
The first decimate by 2, half-band, low-pass, FIR filter (HB4) uses
an 11-tap, symmetrical, fixed coefficient filter implementation
that is optimized for low power consumption. The HB4 filter is
only used when complex outputs (decimate by 16) or real outputs
(decimate by 8) are enabled; otherwise, it is bypassed. Table 21 and
Figure 107 show the coefficients and response of the HB4 filter.
Table 21. HB4 Filter Coefficients
Normalized
Coefficient
+0.006042
0
−0.049377
0
+0.293335
+0.5
–60
–80
–100
–120
Decimal
Coefficient (15-Bit)
+99
0
−809
0
+4806
+8192
Rev. C | Page 56 of 136
–140
–160
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
NORMALIZED FREQUENCY (× Π RAD/s)
Figure 107. HB4 Filter Response
0.9
1.0
15660-078
HB4 Coefficient
Number
C1, C11
C2, C10
C3, C9
C4, C8
C5, C7
C6
–40
Data Sheet
AD9695
HB3 Filter Description
Table 23. HB2 Filter Coefficients
The second decimate by 2, half-band, low-pass, FIR filter (HB3)
uses an 11-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption. The HB3
filter is only used when complex outputs (decimate by 8 or 16)
or real outputs (decimate by 4 or 8) are enabled; otherwise, it is
bypassed. Table 22 and Figure 108 show the coefficients and
response of the HB3 filter.
HB2 Coefficient
Number
C1, C19
C2, C18
C3, C17
C4, C16
C5, C15
C6, C14
C7, C13
C8, C12
C9, C11
C10
HB3 Coefficient
Number
C1, C11
C2, C10
C3, C9
C4, C8
C5, C7
C6
Normalized
Coefficient
+0.006638
0
−0.051056
0
+0.294418
+0.500000
Decimal Coefficient
(17-Bit)
+435
0
−3346
0
+19,295
+32,768
20
0
0
–20
–40
–60
–80
–100
–40
–120
–60
–140
–80
–160
0
–100
0.2
0.3
0.4
0.5
0.6
0.7
0.8
NORMALIZED FREQUENCY (× Π RAD/s)
–120
Figure 109. HB2 Filter Response
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
NORMALIZED FREQUENCY (× Π RAD/s)
0.9
1.0
15660-079
–140
–160
0.1
Figure 108. HB3 Filter Response
HB2 Filter Description
The third decimate by 2, half-band, low-pass, FIR filter (HB2)
uses a 19-tap, symmetrical, fixed coefficient filter implementation that is optimized for low power consumption.
The HB2 filter is only used when complex or real outputs
(decimate by 4, 8, or 16) is enabled; otherwise, it is bypassed.
Table 23 and Figure 109 show the coefficients and response of
the HB2 filter.
Rev. C | Page 57 of 136
0.9
1.0
15660-080
MAGNITUDE (dB)
–20
Decimal Coefficient
(18-Bit)
+88
0
−698
0
+2981
0
−9723
0
+40120
+65536
20
MAGNITUDE (dB)
Table 22. HB3 Filter Coefficients
Normalized
Coefficient
+0.000671
0
−0.005325
0
+0.022743
0
−0.074181
0
+0.306091
+0.5
AD9695
Data Sheet
HB1 Filter Description
20
Decimal Coefficient
(20-Bit)
−10
0
+38
0
−102
0
+232
0
−467
0
+862
0
−1489
0
+2440
0
−3833
0
+5831
0
−8679
0
12803
0
−19086
0
+29814
0
−53421
0
+166138
+262144
–60
–80
–100
–120
–140
–160
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
NORMALIZED FREQUENCY (× Π RAD/s)
15660-081
Normalized
Coefficient
−0.000019
0
+0.000072
0
−0.000195
0
+0.000443
0
−0.000891
0
+0.001644
0
−0.002840
0
+0.004654
0
−0.007311
0
+0.011122
0
−0.016554
0
0.024420
0
−0.036404
0
+0.056866
0
−0.101892
0
+0.316883
+0.5
–40
Figure 110. HB1 Filter Response
TB2 Filter Description
The TB2 uses a 26-tap, symmetrical, fixed coefficient filter
implementation that is optimized for low power consumption.
The TB2 filter is only used when decimation ratios of 6, 12, or
24 are required. Table 25 and Figure 111 show the coefficients
and response of the TB2 filter.
Table 25. TB2 Filter Coefficients
TB2 Coefficient
Number
C1, C26
C2, C25
C3, C24
C4, C23
C5, C22
C6, C21
C7, C20
C8, C19
C9, C18
C10, C17
C11, C16
C12, C15
C13, C14
Normalized
Coefficient
−0.000191
−0.000793
−0.001137
+0.000916
+0.006290
+0.009823
+0.000916
−0.023483
−0.043152
−0.019318
+0.071327
+0.201172
+0.297756
Decimal Coefficient
(19-Bit)
−50
+208
−298
+240
+1649
+2575
+240
−6156
−11312
−5064
+18698
+52736
+78055
20
0
–20
–40
–60
–80
–100
–120
–140
–160
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
NORMALIZED FREQUENCY (× Π RAD/s)
Figure 111. TB2 Filter Response
Rev. C | Page 58 of 136
0.9
1.0
15660-082
HB1 Coefficient
Number
C1, C63
C2, C62
C3, C61
C4, C60
C5, C59
C6, C58
C7, C57
C8, C56
C9, C55
C10, C54
C11, C53
C12, C52
C13, C51
C14, C50
C15, C49
C16, C48
C17, C47
C18, C46
C19, C45
C20, C44
C21, C43
C22, C42
C23, C41
C24, C40
C25, C39
C26, C38
C27, C37
C28, C36
C29, C35
C30, C34
C31, C33
C32
–20
MAGNITUDE (dB)
Table 24. HB1 Filter Coefficients
0
MAGNITUDE (dB)
The fourth and final decimate by 2, half-band, low-pass, FIR
filter (HB1) uses a 63-tap, symmetrical, fixed coefficient filter
implementation that is optimized for low power consumption.
The HB1 filter is always enabled and cannot be bypassed.
Table 24 and Figure 110 show the coefficients and response of
the HB1 filter.
Data Sheet
AD9695
TB1 Filter Description
20
TB1 Coefficient
Number
1, 76
2, 75
3, 74
4, 73
5, 72
6, 71
7, 70
8, 69
9, 68
10, 67
11, 66
12, 65
13, 64
14, 63
15, 62
16, 61
17, 60
18, 59
19, 58
20, 57
21, 56
22, 55
23, 54
24, 53
25, 52
26, 51
27, 50
28, 49
29, 48
30, 47
31, 46
32, 45
33, 44
34, 43
35, 42
36, 41
37, 40
38, 39
Normalized
Coefficient
−0.000023
−0.000053
−0.000037
+0.000090
+0.000291
+0.000366
+0.000095
−0.000463
−0.000822
−0.000412
+0.000739
+0.001665
+0.001132
−0.000981
−0.002961
−0.002438
+0.001087
+0.004833
+0.004614
−0.000871
−0.007410
−0.008039
+0.000053
+0.010874
+0.013313
+0.001817
−0.015579
−0.021590
−0.005603
+0.022451
+0.035774
+0.013541
−0.034655
−0.066549
−0.035213
+0.071220
+0.210777
+0.309200
Decimal Coefficient
(22-Bit)
−96
−224
−156
+379
+1220
+1534
+398
−1940
−3448
−1729
+3100
+6984
+4748
−4114
−12418
−10226
+4560
+20272
+19352
−3652
−31080
−33718
+222
+45608
+55840
+7620
−65344
−90556
−23502
+94167
+150046
+56796
−145352
−279128
−147694
+298720
+884064
+1296880
–20
Rev. C | Page 59 of 136
–40
–60
–80
–100
–120
–140
–160
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
NORMALIZED FREQUENCY (× Π RAD/s)
Figure 112. TB1 Filter Response
0.9
1.0
15660-083
Table 26. TB1 Filter Coefficients
0
MAGNITUDE (dB)
The TB1 decimate by 3, low-pass, FIR filter uses a 76-tap,
symmetrical, fixed coefficient filter implementation. Table 26
shows the TB1 filter coefficients, and Figure 112 shows the TB1
filter response. TB1 is only supported in DDC0 and DDC1.
AD9695
Data Sheet
FB2 Filter Description
20
FB2 Coefficient
Number
1, 48
2, 47
3, 46
4, 45
5, 44
6, 43
7, 42
8, 41
9, 40
10, 39
11, 38
12, 37
13, 36
14, 35
15, 34
16, 33
17, 32
18, 31
19, 30
20, 29
21, 28
22, 27
23, 26
24, 25
Normalized
Coefficient
+0.000007
−0.000004
−0.000069
−0.000244
−0.000544
−0.000870
−0.000962
−0.000448
+0.000977
+0.003237
+0.005614
+0.006714
+0.004871
−0.001011
−0.010456
−0.020729
−0.026978
−0.023453
−0.005608
+0.027681
+0.072720
+0.121223
+0.162346
+0.185959
Decimal Coefficient
(21-Bit)
7
−4
−72
−256
−570
−912
−1009
−470
+1024
+3394
+5887
+7040
+5108
−1060
−10964
−21736
−28288
−24592
−5880
+29026
+76252
+127112
+170232
+194992
–40
–60
–80
–100
–120
–140
–160
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
NORMALIZED FREQUENCY (× Π RAD/s)
0.9
1.0
15660-084
Table 27. FB2 Filter Coefficients
0
–20
MAGNITUDE (dB)
The FB2 decimate by 5, low-pass, FIR filter uses a 48-tap,
symmetrical, fixed coefficient filter implementation. Table 27
shows the FB2 filter coefficients, and Figure 113 shows the FB2
filter response.
Figure 113. FB2 Filter Response
DDC GAIN STAGE
Each DDC contains an independently controlled gain stage.
The gain is selectable as either 0 dB or 6 dB. When mixing a
real input signal down to baseband, it is recommended that the
user enable the 6 dB of gain to recenter the dynamic range of
the signal within the full scale of the output bits.
When mixing a complex input signal down to baseband, the
mixer has already recentered the dynamic range of the signal
within the full scale of the output bits, and no additional gain is
necessary. However, the optional 6 dB gain compensates for
low signal strengths. The downsample by 2 portion of the HB1
FIR filter is bypassed when using the complex to real
conversion stage. The TB1 filter does not have the 6 dB gain
stage.
Rev. C | Page 60 of 136
Data Sheet
AD9695
DDC COMPLEX TO REAL CONVERSION
the signal, the Q portion of the complex mixer is no longer
needed and is dropped. The TB1 filter does not support
complex to real conversion.
Each DDC contains an independently controlled complex to
real conversion block. The complex to real conversion block
reuses the last filter (HB1 FIR) in the filtering stage along with
an fS/4 complex mixer to upconvert the signal. After upconverting
Figure 114 shows a simplified block diagram of the complex to
real conversion.
GAIN STAGE
HB1 FIR
COMPLEX TO
REAL ENABLE
LOW-PASS
FILTER
I
2
0dB
OR
6dB
I
0 I/REAL
1
COMPLEX TO REAL CONVERSION
0dB
OR
6dB
I
cos(wt)
+
REAL
90°
fS/4
0°
–
sin(wt)
LOW-PASS
FILTER
2
Q
0dB
OR
6dB
Q
Q
15660-085
Q
0dB
OR
6dB
HB1 FIR
Figure 114. Complex to Real Conversion Block
Rev. C | Page 61 of 136
AD9695
Data Sheet
DDC MIXED DECIMATION SETTINGS
The AD9695 also supports DDCs with different decimation
rates. In this scenario, the chip decimation ratio must be set to
the lowest decimation ratio of all the DDC channels. Samples of
higher decimation ratio DDCs are repeated to match the chip
decimation ratio sample rate. Only mixed decimation ratios
that are integer multiples of 2 are supported. For example,
decimate by 1, 2, 4, 8, or 16 can be mixed together, decimate by
3, 6, 12, 24, or 48 can be mixed together, or decimate by 5, 10,
20, or 40 can be mixed together.
Table 28 shows the DDC sample mapping when the chip
decimation ratio is different than the DDC decimation ratio.
For example, if the chip decimation ratio is set to decimate by 4,
DDC0 is set to use the HB2 + HB1 filters (complex outputs,
decimate by 4) and DDC1 is set to use the HB4 + HB3 + HB2 +
HB1 filters (real outputs, decimate by 8), then DDC1 repeats its
output data 2 times for every one DDC0 output. The resulting
output samples are shown in Table 29.
Table 28. Sample Mapping when Chip Decimation Ratio (DCM) Does Not Match DDC DCM
Sample Index
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DDC DCM = Chip DCM
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
N + 16
N + 17
N + 18
N + 19
N + 20
N + 21
N + 22
N + 23
N + 24
N + 25
N + 26
N + 27
N + 28
N + 29
N + 30
N + 31
DDC DCM = 2 × Chip DCM
N
N
N+1
N+1
N+2
N+2
N+3
N+3
N+4
N+4
N+5
N+5
N+6
N+6
N+7
N+7
N+8
N+8
N+9
N+9
N + 10
N + 10
N + 11
N + 11
N + 12
N + 12
N + 13
N + 13
N + 14
N + 14
N + 15
N + 15
DDC DCM = 4 × Chip DCM
N
N
N
N
N+1
N+1
N+1
N+1
N+2
N+2
N+2
N+2
N+3
N+3
N+3
N+3
N+4
N+4
N+4
N+4
N+5
N+5
N+5
N+5
N+6
N+6
N+6
N+6
N+7
N+7
N+7
N+7
Rev. C | Page 62 of 136
DDC DCM = 8 × Chip DCM
N
N
N
N
N
N
N
N
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N+1
N+2
N+2
N+2
N+2
N+2
N+2
N+2
N+2
N+3
N+3
N+3
N+3
N+3
N+3
N+3
N+3
Data Sheet
AD9695
Table 29. Chip DCM = 4, DDC0 DCM = 4 (Complex), and DDC1 DCM = 8 (Real) 1
DDC Input Samples
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
1
Output Port I
I0[N]
I0[N]
I0[N]
I0[N]
I0[N + 1]
I0[N + 1]
I0[N + 1]
I0[N + 1]
I0[N + 2]
I0[N + 2]
I0[N + 2]
I0[N + 2]
I0[N + 3]
I0[N + 3]
I0[N + 3]
I0[N + 3]
DDC0
Output Port Q
Q0[N]
Q0[N]
Q0[N]
Q0[N]
Q0[N + 1]
Q0[N + 1]
Q0[N + 1]
Q0[N + 1]
Q0[N + 2]
Q0[N + 2]
Q0[N + 2]
Q0[N + 2]
Q0[N + 3]
Q0[N + 3]
Q0[N + 3]
Q0[N + 3]
DCM means decimation.
Rev. C | Page 63 of 136
Output Port I
I1[N]
I1[N]
I1[N]
I1[N]
I1[N]
I1[N]
I1[N]
I1[N]
I1[N + 1]
I1[N + 1]
I1[N + 1]
I1[N + 1]
I1[N + 1]
I1[N + 1]
I1[N + 1]
I1[N + 1]
DDC1
Output Port Q
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
AD9695
Data Sheet
DDC EXAMPLE CONFIGURATIONS
Table 30 describes the register settings for multiple DDC example configurations. Bandwidths listed are with 100 dB of stop band alias rejection.
Table 30. DDC Example Configurations (per ADC Channel Pair)
Chip
Application
Layer
One DDC
Chip
Decimation
Ratio
2
DDC
Input
Type
Complex
DDC
Output
Type
Complex
Bandwidth
Per DDC1
40% × fS
No. of Virtual
Converters
Required
2
Two DDCs
4
Complex
Complex
20% × fS
4
Two DDCs
4
Complex
Real
10% × fS
2
Two DDCs
4
Real
Real
10% × fS
2
Rev. C | Page 64 of 136
Register Settings
0x0200 = 0x01 (one DDC; I/Q selected)
0x0201 = 0x01 (chip decimate by 2)
0x0310 = 0x83 (complex mixer; 0 dB gain; variable IF;
complex outputs; HB1 filter)
0x0311 = 0x04 (DDC I Input = ADC Channel A; DDC Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0200 = 0x02 (two DDCs; I/Q selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x80 (complex mixer; 0 dB gain;
variable IF; complex outputs; HB2+HB1 filters)
0x0311, 0x0331 = 0x04 (DDC I input = ADC Channel A;
DDC Q input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
0x0200 = 0x22 (two DDCs; I only selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x89 (complex mixer; 0 dB gain;
variable IF; real output; HB3 + HB2 + HB1 filters)
0x0311, 0x0331 = 0x04 (DDC I Input = ADC Channel A;
DDC Q input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
0x0200 = 0x22 (two DDCs; I only selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x49 (real mixer; 6 dB gain; variable
IF; real output; HB3 + HB2 + HB1 filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
Data Sheet
AD9695
Chip
Application
Layer
Two DDCs
Chip
Decimation
Ratio
4
DDC
Input
Type
Real
DDC
Output
Type
Complex
Bandwidth
Per DDC1
20% × fS
No. of Virtual
Converters
Required
4
Two DDCs
8
Real
Real
5% × fS
2
Four DDCs
8
Real
Complex
10% × fS
8
Rev. C | Page 65 of 136
Register Settings
0x0200 = 0x02 (two DDCs; I/Q selected)
0x0201 = 0x02 (chip decimate by 4)
0x0310, 0x0330 = 0x40 (real mixer; 6 dB gain; variable
IF; complex output; HB2 + HB1 filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
0x0200 = 0x22 (two DDCs; I only selected)
0x0201 = 0x03 (chip decimate by 8)
0x0310, 0x0330 = 0x4A (real mixer; 6 dB gain; variable
IF; real output; HB4 + HB3 + HB2 + HB1 filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x05 (DDC1 I input = ADC Channel B; DDC1 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
0x0200 = 0x03 (four DDCs; I/Q selected)
0x0201 = 0x03 (chip decimate by 8)
0x0310, 0x0330, 0x0350, 0x0370 = 0x41 (real mixer; 6 dB
gain; variable IF; complex output; HB3 + HB2 + HB1 filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q
input = ADC Channel A)
0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q
input = ADC Channel B)
0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B,
0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 =
FTW and POW set as required by application for DDC2
0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B,
0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 =
FTW and POW set as required by application for DDC3
AD9695
Data Sheet
Chip
Application
Layer
Four DDCs
Chip
Decimation
Ratio
8
DDC
Input
Type
Real
DDC
Output
Type
Real
Bandwidth
Per DDC1
5% × fS
No. of Virtual
Converters
Required
4
Four DDCs
16
Real
Complex
5% × fS
8
1
fS is the ADC sample rate.
Rev. C | Page 66 of 136
Register Settings
0x0200 = 0x23 (four DDCs; I only selected)
0x0201 = 0x03 (chip decimate by 8)
0x0310, 0x0330, 0x0350, 0x0370 = 0x4A (real mixer; 6 dB
gain; variable IF; real output; HB4 + HB3 + HB2 + HB1
filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q
input = ADC Channel A)
0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q
input = ADC Channel B)
0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B,
0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 =
FTW and POW set as required by application for DDC2
0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B,
0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 =
FTW and POW set as required by application for DDC3
0x0200 = 0x03 (four DDCs; I/Q selected)
0x0201 = 0x04 (chip decimate by 16)
0x0310, 0x0330, 0x0350, 0x0370 = 0x42 (real mixer;
6 dB gain; variable IF; complex output; HB4 + HB3 +
HB2 + HB1 filters)
0x0311 = 0x00 (DDC0 I input = ADC Channel A; DDC0 Q
input = ADC Channel A)
0x0331 = 0x00 (DDC1 I input = ADC Channel A; DDC1 Q
input = ADC Channel A)
0x0351 = 0x05 (DDC2 I input = ADC Channel B; DDC2 Q
input = ADC Channel B)
0x0371 = 0x05 (DDC3 I input = ADC Channel B; DDC3 Q
input = ADC Channel B)
0x0316, 0x0317, 0x0318, 0x0319, 0x031A, 0x031B,
0x031D, 0x031E, 0x031F, 0x0320, 0x0321, 0x0322 =
FTW and POW set as required by application for DDC0
0x0336, 0x0337, 0x0338, 0x0339, 0x033A, 0x033B,
0x033D, 0x033E, 0x033F, 0x0340, 0x0341, 0x0342 =
FTW and POW set as required by application for DDC1
0x0356, 0x0357, 0x0358, 0x0359, 0x035A, 0x035B,
0x035D, 0x035E, 0x035F, 0x0360, 0x0361, 0x0362 =
FTW and POW set as required by application for DDC2
0x0376, 0x0377, 0x0378, 0x0379, 0x037A, 0x037B,
0x037D, 0x037E, 0x037F, 0x0380, 0x0381, 0x0382 =
FTW and POW set as required by application for DDC3
Data Sheet
AD9695
DDC POWER CONSUMPTION
Table 31 describes the typical and maximum DVDD and DRVDD1 power for certain DDC modes. fS = 1.3 GHz in all cases.
Table 31. DDC Power Consumption for Example Configurations
Number
of DDCs
2
2
2
2
4
4
4
DDC Decimation
Ratio
2
3
4
8
4
6
8
Number of
Lanes (L)
4
4
2
1
4
4
2
Number of Virtual
Converters (M)
4
4
4
4
8
8
8
Number of Octets
per Frame (F)
2
2
4
8
4
4
8
Rev. C | Page 67 of 136
DVDD Power (mW)
Typ
Max
209
380
206
379
205
379
200
375
236
407
230
404
227
400
DRVDD1 Power (mW)
Typ
Max
179
263
138
217
109
188
72
150
180
264
138
220
110
190
AD9695
Data Sheet
SIGNAL MONITOR
The signal monitor block provides additional information
about the signal being digitized by the ADC. The signal
monitor computes the peak magnitude of the digitized signal.
This information can be used to drive an AGC loop to optimize
the range of the ADC in the presence of real-world signals.
The results of the signal monitor block can be obtained either
by reading back the internal values from the SPI port or by
embedding the signal monitoring information into the JESD204B
interface as special control bits. A global, 24-bit programmable
period controls the duration of the measurement. Figure 115
shows the simplified block diagram of the signal monitor block.
FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
(SMPR)
0x0271, 00x272, 0x0273
DOWN
COUNTER
IS
COUNT = 1?
LOAD
FROM
INPUT
LOAD
LOAD
SIGNAL
MONITOR
HOLDING
REGISTER
TO SPORT OVER
JESD204B AND
MEMORY MAP
15660-086
CLEAR
MAGNITUDE
STORAGE
REGISTER
COMPARE
A>B
Figure 115. Signal Monitor Block
The peak detector captures the largest signal within the
observation period. The detector only observes the magnitude
of the signal. The resolution of the peak detector is a 13-bit
value, and the observation period is 24 bits and represents
converter output samples. The peak magnitude can be derived
by using the following equation:
The magnitude of the input port signal is monitored over a
programmable time period, which is determined by the signal
monitor period register (SMPR). The peak detector function is
enabled by setting Bit 1 of Register 0x0270 in the signal
monitor control register. The 24-bit SMPR must be
programmed before activating this mode.
After enabling peak detection mode, the value in the SMPR is
loaded into a monitor period timer, which decrements at the
decimated clock rate. The magnitude of the input signal is
compared with the value in the internal magnitude storage
register (not accessible to the user), and the greater of the two
is updated as the current peak level. The initial value of the
magnitude storage register is set to the current ADC input signal
magnitude. This comparison continues until the monitor period
timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding
register, which can be read through the memory map or output
through the SPORT over the JESD204B interface. The monitor
period timer is reloaded with the value in the SMPR, and the
countdown restarts. In addition, the magnitude of the first
input sample is updated in the magnitude storage register, and
the comparison and update procedure, as explained previously,
continues.
Peak Magnitude (dBFS) = 20log(Peak Detector Value/213)
Rev. C | Page 68 of 136
Data Sheet
AD9695
is to be inserted (CS = 1), only the most significant control bit is
used (see Example Configuration 1 and Example Configuration 2
in Figure 116). To select the SPORT over JESD204B option,
program Register 0x0559, Register 0x055A, and Register 0x058F.
See Table 48 for more information on setting these bits.
SPORT OVER JESD204B
The signal monitor data can also be serialized and sent over the
JESD204B interface as control bits. These control bits must be
deserialized from the samples to reconstruct the statistical data.
The signal control monitor function is enabled by setting Bits[1:0]
of Register 0x0279 and Bit 1 of Register 0x027A. Figure 116 shows
two different example configurations for the signal monitor
control bit locations inside the JESD204B samples. A maximum
of three control bits can be inserted into the JESD204B samples;
however, only one control bit is required for the signal monitor.
Control bits are inserted from MSB to LSB. If only one control bit
Figure 117 shows the 25-bit frame data that encapsulates the
peak detector value. The frame data is transmitted MSB first
with five 5-bit subframes. Each subframe contains a start bit
that can be used by a receiver to validate the deserialized data.
Figure 118 shows the SPORT over JESD204B signal monitor
data with a monitor period timer set to 80 samples.
16-BIT JESD204B SAMPLE SIZE (N' = 16)
EXAMPLE
CONFIGURATION 1
(N' = 16, N = 15, CS = 1)
1-BIT
CONTROL
BIT
(CS = 1)
15-BIT CONVERTER RESOLUTION (N = 15)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S[14]
X
S[13]
X
S[12]
X
S[11]
X
S[10]
X
S[9]
X
S[8]
X
S[7]
X
S[6]
X
S[5]
X
S[4]
X
S[3]
X
S[2]
X
S[1]
X
S[0]
X
CTRL
[BIT 2]
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
16-BIT JESD204B SAMPLE SIZE (N' = 16)
15
S[13]
X
14
13
S[12]
X
S[11]
X
12
S[10]
X
11
10
S[9]
X
9
S[8]
X
8
S[7]
X
7
S[6]
X
6
S[5]
X
5
S[4]
X
4
S[3]
X
S[2]
X
3
S[1]
X
2
1
0
S[0]
X
CTRL
[BIT 2]
X
TAIL
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
Figure 116. Signal Monitor Control Bit Locations
5-BIT SUBFRAMES
5-BIT IDLE
SUBFRAME
(OPTIONAL)
25-BIT
FRAME
IDLE
1
IDLE
1
IDLE
1
IDLE
1
IDLE
1
5-BIT IDENTIFIER START
0
SUBFRAME
ID[3]
0
ID[2]
0
ID[1]
0
ID[0]
1
5-BIT DATA
MSB
SUBFRAME
START
0
P[12]
P[11]
P[10]
P[9]
5-BIT DATA
SUBFRAME
START
0
P[8]
P[7]
P[6]
P5]
5-BIT DATA
SUBFRAME
START
0
P[4]
P[3]
P[2]
P1]
5-BIT DATA
LSB
SUBFRAME
START
0
P[0]
0
0
0
P[x] = PEAK MAGNITUDE VALUE
15660-088
EXAMPLE
CONFIGURATION 2
(N' = 16, N = 14, CS = 1)
Figure 117. SPORT over JESD204B Signal Monitor Frame Data
Rev. C | Page 69 of 136
15660-087
1
CONTROL
BIT
1 TAIL
(CS = 1)
BIT
14-BIT CONVERTER RESOLUTION (N = 14)
AD9695
Data Sheet
SMPR = 80 SAMPLES (0x0271 = 0x50; 0x0272 = 0x00; 0x0273 = 0x00)
80 SAMPLE PERIOD
PAYLOAD
25-BIT FRAME (N)
IDENT.
DATA
MSB
DATA
DATA
LSB
DATA
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
80 SAMPLE PERIOD
PAYLOAD
25-BIT FRAME (N + 1)
IDENT.
DATA
MSB
DATA
DATA
LSB
DATA
IDLE
IDLE
IDLE
IDLE
IDLE
80 SAMPLE PERIOD
IDENT.
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
Figure 118. SPORT over JESD204B Signal Monitor Example
Rev. C | Page 70 of 136
15660-089
PAYLOAD
25-BIT FRAME (N + 2)
Data Sheet
AD9695
DIGITAL OUTPUTS
•
INTRODUCTION TO THE JESD204B INTERFACE
The AD9695 digital outputs are designed to the JEDEC standard
JESD204B, serial interface for data converters. JESD204B is a
protocol to link the AD9695 to a digital processing device over
a serial interface with lane rates of up to 16 Gbps. The benefits
of the JESD204B interface over LVDS include a reduction in
required board area for data interface routing, and an ability to
enable smaller packages for converter and logic devices.
JESD204B OVERVIEW
•
•
•
K is the number of frames per multiframe
(AD9695 value = 4, 8, 12, 16, 20, 24, 28, or 32 )
S is the samples transmitted/single converter/frame cycle
(AD9695 value = set automatically based on L, M, F, and N΄)
HD is the high density mode (AD9695 = set automatically
based on L, M, F, and N΄)
CF is the number of control words/frame clock
cycle/converter device (AD9695 value = 0)
The JESD204B data transmit block assembles the parallel data
from the ADC into frames and uses 8-bit/10-bit encoding as
well as optional scrambling to form serial output data. Lane
synchronization is supported through the use of special control
characters during the initial establishment of the link. Additional
control characters are embedded in the data stream to maintain
synchronization thereafter. A JESD204B receiver is required to
complete the serial link. For additional details on the JESD204B
interface, refer to the JESD204B standard.
Figure 119 shows a simplified block diagram of the AD9695
JESD204B link. By default, the AD9695 is configured to use
two converters and four lanes. Converter A data is output to
SERDOUT0± and/or SERDOUT1±, and Converter B is output
to SERDOUT2± and/or SERDOUT3±. The AD9695 allows
other configurations, such as combining the outputs of both
converters onto a single lane, or changing the mapping of the
A and B digital output paths. These modes are customizable,
and can be set up via the SPI. Refer to the Memory Map section
for more details.
The AD9695 JESD204B data transmit block maps up to two
physical ADCs or up to eight virtual converters (when DDCs
are enabled) over a link. A link can be configured to use one,
two, or four JESD204B lanes. The JESD204B specification refers
to a number of parameters to define the link, and these parameters
must match between the JESD204B transmitter (the AD9695
output) and the JESD204B receiver (the logic device input).
By default in the AD9695, the 14-bit converter word from each
converter is broken into two octets (eight bits of data). Bit 13
(MSB) through Bit 6 are in the first octet. The second octet
contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits
can be configured as zeros or a pseudorandom number
sequence. The tail bits can also be replaced with control bits
indicating overrange, SYSREF±, or fast detect output.
The JESD204B link is described according to the following
parameters:
The two resulting octets can be scrambled. Scrambling is
optional; however, it is recommended to avoid spectral peaks
when transmitting similar digital data patterns. The scrambler
uses a self-synchronizing, polynomial-based algorithm defined
by the equation 1 + x14 + x15. The descrambler in the receiver is
a self synchronizing version of the scrambler polynomial.
•
•
•
•
•
L is the number of lanes/converter device (lanes/link)
(AD9695 value = 1, 2, or 4)
M is the number of converters/converter device (virtual
converters/link) (AD9695 value = 1, 2, 4, or 8)
F is the octets/frame (AD9695 value = 1, 2, 4, 8, or 16)
N΄ is the number of bits per sample (JESD204B word size)
(AD9695 value = 8 or 16)
N is the converter resolution (AD9695 value = 7 to 16)
CS is the number of control bits/sample
(AD9695 value = 0, 1, 2, or 3)
The two octets are then encoded with an 8-bit/10-bit encoder.
The 8-bit/10-bit encoder works by taking eight bits of data (an
octet) and encoding them into a 10-bit symbol. Figure 119
shows how the 14-bit data is taken from the ADC, how the tail
bits are added, how the two octets are scrambled, and how the
octets are encoded into two 10-bit symbols. Figure 120 shows the
default data format.
CONVERTER 0
CONVERTER A
INPUT
ADC A
MUX/
FORMAT
(SPI
REGISTERS
0x0561,
0x0564)
CONVERTER B
INPUT
JESD204B LINK
CONTROL
(L, M, F)
(SPI REGISTER
0x058B,
0x058E, 0x058C)
ADC B
LANE MUX
AND
MAPPING
(SPI
REGISTERS
0x05B0,
0x05B2,
0x05B3,
0x05B5,
0x05B6)
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
CONVERTER 1
15660-090
•
SYSREF±
SYNCINB±
Figure 119. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x00)
Rev. C | Page 71 of 136
AD9695
Data Sheet
JESD204B DATA
LINK LAYER TEST
PATTERNS
0x0574[2:0]
JESD204B
INTERFACE TEST
PATTERN
(0x0573,
0x0551 TO 0x0558)
MSB A13
A12
A11
A10
A9
A8
ADC
A7
A6
A5
A4
A3
A2
A1
LSB A0
OCTET1
TAIL BITS
0x0571[6]
OCTET0
JESD204B SAMPLE
CONSTRUCTION
MSB A13
A12
A11
A10
A9
A8
A7
LSB A6
A5
A4
A3
A2
A1
A0
C2
T
MSB S7
S6
S5
S4
S3
S2
S1
LSB S0
S7
S6
S5
S4
S3
S2
S1
S0
8-BIT/
10-BIT
ENCODER
SERIALIZER
a b
i j a b
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
i j
SYMBOL0 SYMBOL1
a b c d e f g h i j
a b c d e f g h i j
C2
C1
C0
15660-091
CONTROL BITS
FRAME
CONSTRUCTION
SCRAMBLER
1 + x14 + x15
(OPTIONAL)
OCTET1
ADC TEST PATTERNS
(0x0550,
0x0551 TO 0x0558)
OCTET0
JESD204B LONG
TRANSPORT TEST
PATTERN
0x0571[5]
Figure 120. ADC Output Datapath Showing Data Framing
TRANSPORT
LAYER
SAMPLE
CONSTRUCTION
FRAME
CONSTRUCTION
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATION
8-BIT/10-BIT
ENCODER
PHYSICAL
LAYER
CROSSBAR
MUX
SERIALIZER
Tx
OUTPUT
15660-092
PROCESSED
SAMPLES
FROM ADC
DATA LINK
LAYER
SYSREF±
SYNCINB±
Figure 121. Data Flow
FUNCTIONAL OVERVIEW
Data Link Layer
The block diagram in Figure 121 shows the flow of data
through the JESD204B hardware from the sample input to the
physical output. The processing can be divided into layers that
are derived from the open source initiative (OSI) model, widely
used to describe the abstraction layers of communications
systems. These layers are the transport layer, data link layer,
and physical layer (serializer and output driver).
The data link layer is responsible for the low level functions
of passing data across the link. These include optionally
scrambling the data, inserting control characters during the
initial lane alignment sequence (ILAS) and for frame and
multiframe synchronization monitoring, and encoding 8-bit
octets into 10-bit symbols. The data link layer is also responsible
for sending the ILAS, which contains the link configuration
data used by the receiver to verify the settings in the transport
layer.
Transport Layer
The transport layer handles packing the data (consisting of
samples and optional control bits) into JESD204B frames that
are mapped to 8-bit octets. The packing of samples into frames
are determined by the JESD204B configuration parameters for
number of lanes (L), number of converters (M), the number of
octets per lane per frame (F), the number of samples per
converter per frame (S), and the number of bits in a nibble
group (sometimes called the JESD204 word size − N’).
Samples are mapped in order starting from Converter 0, then
Converter 1, and so on until Converter M − 1. If S > 1, each
sample from the converter is mapped before mapping the
samples from the next converter. Each sample is mapped into
words formed by appending converter control bits, if enabled,
to the LSBs of each sample. The words are then padded with tail
bits, if necessary, to form nibble groups (NGs) of the appropriate
size as determined by the N’ parameter. The following equation
can be used to determine the number of tail bits within a nibble
group (JESD204B word):
T = N΄ − N − CS
Physical Layer
The physical layer consists of the high speed circuitry clocked at
the serial clock rate. In this layer, parallel data is converted into
one, two, or four lanes of high speed differential serial data.
JESD204B LINK ESTABLISHMENT
The AD9695 JESD204B transmitter (Tx) interface operates in
Subclass 0 or Subclass 1 as defined in the JEDEC Standard
JESD204B (July 2011 specification). The link establishment
process is divided into the following steps: code group synchronization, initial lane alignment sequence, and user data and error
correction.
Code Group Synchronization (CGS)
CGS is the process by which the JESD204B receiver finds the
boundaries between the 10-bit symbols in the stream of data.
During the CGS phase, the JESD204B transmit block transmits
/K/ characters (/K28.5/ symbols). The receiver must locate the
/K/ characters in its input data stream using clock and data
recovery (CDR) techniques.
Rev. C | Page 72 of 136
Data Sheet
AD9695
User Data and Error Detection
The receiver issues a synchronization request by asserting the
SYNCINB± pin of the AD9695 low. The JESD204B Tx then begins
sending /K/ characters. Once the receiver has synchronized, it
waits for the correct reception of at least four consecutive /K/
symbols. It then deasserts SYNCINB±. The AD9695 then
transmits an ILAS on the following local multiframe clock
(LMFC) boundary.
After the initial lane alignment sequence is complete, the user
data (ADC samples) is sent. During transmission of the user data,
a mechanism called character replacement monitors the frame
clock and multiframe clock alignment. This mechanism replaces
the last octet of a frame or multiframe with an /F/ or /A/
alignment characters when the data meets certain conditions.
These conditions are different for unscrambled and scrambled
data. The scrambling operation is enabled by default, but it can
be disabled using the SPI.
For more information on the code group synchronization
phase, refer to the JEDEC Standard JESD204B, July 2011,
Section 5.3.3.1.
For scrambled data, any 0xFC character at the end of a frame
is replaced by an /F/, and any 0x7C character at the end of a
multiframe is replaced with an /A/. The JESD204B receiver
(Rx) checks for /F/ and /A/ characters in the received data
stream and verifies that they only occur in the expected
locations. If an unexpected /F/ or /A/ character is found, the
receiver handles the situation by using dynamic realignment or
asserting the SYNCINB± signal for more than four frames to
initiate a resynchronization. For unscrambled data, if the final
octet of two subsequent frames are equal, the second octet is
replaced with an /F/ symbol if it is at the end of a frame, and an
/A/ symbol if it is at the end of a multiframe.
The SYNCINB± pin operation can also be controlled by the
SPI. The SYNCINB± signal is a differential dc-coupled LVDS
mode signal by default, but it can also be driven single-ended.
For more information on configuring the SYNCINB± pin
operation, refer to Register 0x572.
The SYNCINB± pins can also be configured to run in CMOS
(single-ended) mode by setting Bit 4 in Register 0x572. When
running SYNCINB± in CMOS mode, connect the CMOS
SYNCINB signal to Pin 21 (SYNCINB+) and leave Pin 20
(SYNCINB−) disconnected.
Initial Lane Alignment Sequence (ILAS)
The ILAS phase follows the CGS phase and begins on the next
LMFC boundary after SYNCINB± deassertion. The ILAS
consists of four mulitframes, with an /R/ character marking the
beginning and an /A/ character marking the end. The ILAS
begins by sending an /R/ character followed by 0 to 255 ramp
data for one multiframe. On the second multiframe, the link
configuration data is sent, starting with the third character. The
second character is a /Q/ character to confirm that the link
configuration data follows. All undefined data slots are filled
with ramp data. The ILAS sequence is never scrambled.
Insertion of alignment characters can be modified using SPI.
The frame alignment character insertion (FACI) is enabled by
default. More information on the link controls is available in
the Memory Map section, Register 0x571.
8-Bit/10-Bit Encoder
The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols
and inserts control characters into the stream when needed. The
control characters used in JESD204B are shown in Table 32.
The 8-bit/10-bit encoding ensures that the signal is dc balanced by
using the same number of ones and zeros across multiple symbols.
The ILAS sequence construction is shown in Figure 122. The
four multiframes include the following:
Multiframe 1 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
Multiframe 2 begins with an /R/ character followed by a
/Q/ character (/K28.4/), followed by link configuration
parameters over 14 configuration octets (see Table 32) and
ends with an /A/ character. Many of the parameter values
are of the value – 1 notation.
Multiframe 3 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
Multiframe 4 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
•
•
•
K
K
R
D
●●●
D
A
R
Q
C
●●●
C
D
●●●
D
A
R
D
●●●
D
A
R
D
●●●
D
A
D
END OF
MULTIFRAME
●●●
START OF
ILAS
●●●
●●●
●●●
START OF LINK
CONFIGURATION DATA
●●●
START OF
USER DATA
Figure 122. Initial Lane Alignment Sequence
Rev. C | Page 73 of 136
15660-093
•
The 8-bit/10-bit interface has options that can be controlled via
the SPI. These operations include bypass and invert. These options
are troubleshooting tools for the verification of the digital front
end (DFE). Refer to the Memory Map section, Register 0x572,
Bits[2:1] for information on configuring the 8-bit/10-bit
encoder.
AD9695
Data Sheet
Table 32. AD9695 Control Characters Used in JESD204B
Abbreviation
/R/
/A/
/Q/
/K/
/F/
1
Control Symbol
/K28.0/
/K28.3/
/K28.4/
/K28.5/
/K28.7/
8-Bit Value
000 11100
011 11100
100 11100
101 11100
111 11100
10-Bit Value,
RD1 = −1
001111 0100
001111 0011
001111 0100
001111 1010
001111 1000
10-Bit Value,
RD1 = +1
110000 1011
110000 1100
110000 1101
110000 0101
110000 0111
Description
Start of multiframe
Lane alignment
Start of link configuration data
Group synchronization
Frame alignment
RD means running disparity.
DRVDD1
SERDOUTx+
0.1µF
100Ω
DIFFERENTIAL
TRACE PAIR
100Ω
0.1µF
RECEIVER
SERDOUTx–
15660-094
OUTPUT SWING = 0.85 × DRVDD1 V p-p DIFFERENTIAL
ADJUSTABLE TO
1 × DRVDD1, 0.75 × DRVDD1
Figure 123. AC-Coupled Digital Output Termination Example
PHYSICAL LAYER (DRIVER) OUTPUTS
The AD9695 physical layer consists of drivers that are defined in
the JEDEC Standard JESD204B, July 2011. The differential digital
outputs are powered up by default. The drivers use a dynamic
100 Ω internal termination to reduce unwanted reflections.
15660-095
Digital Outputs, Timing, and Controls
Figure 124. Digital Outputs Data Eye, External 100 Ω Terminations at 16 Gbps
If there is no far end receiver termination, or if there is poor
differential trace routing, timing errors can result. To avoid
such timing errors, it is recommended that the trace length be
less than six inches, and that the differential output traces be
close together and at equal lengths.
Figure 125. Digital Outputs Jitter Histogram, External 100 Ω Terminations at
16 Gbps
15660-097
The AD9695 digital outputs can interface with custom ASICs
and field programmable gate array (FPGA) receivers, providing
superior switching performance in noisy environments. Single
point-to-point network topologies are recommended with a
single differential 100 Ω termination resistor placed as close to
the receiver inputs as possible.
15660-096
Place a 100 Ω differential termination resistor at each receiver
input to result in a nominal 0.85 × DRVDD1 V p-p swing at the
receiver (see Figure 123). The swing is adjustable through the
SPI registers. AC coupling is recommended to connect to the
receiver. See the Memory Map section (Register 0x05C0 to
Register 0x05C3 in Table 48) for more details.
Figure 126. Digital Outputs Bathtub Curve, External 100 Ω Terminations at
16 Gbps
Figure 124 to Figure 126 show an example of the digital output
data eye, jitter histogram, and bathtub curve for one AD9695
lane running at 16 Gbps. The format of the output data is twos
complement by default. To change the output data format, see
the Memory Map section (Register 0x0561).
Rev. C | Page 74 of 136
Data Sheet
AD9695
De-Emphasis
Table 34. AD9695 JESD204B Initialization
De-emphasis enables the receiver eye diagram mask to be met
in conditions where the interconnect insertion loss does not
meet the JESD204B specification. Use the de-emphasis feature
only when the receiver is unable to recover the clock due to
excessive insertion loss. Under normal conditions, it is disabled
to conserve power. Additionally, enabling and setting too high
a de-emphasis value on a short link can cause the receiver eye
diagram to fail. Use the de-emphasis setting with caution
because it can increase electromagnetic interference (EMI). See
the Memory Map section (Register 0x05C4 to Register 0x05CA
in Table 48) for more details.
Registe
r
0x1228
0x1228
0x1222
0x1222
0x1222
0x1262
0x1262
Phase-Locked Loop (PLL)
The PLL generates the serializer clock, which operates at the
JESD204B lane rate. The status of the PLL lock can be checked
in the PLL locked status bit (Register 0x056F, Bit 7). This read
only bit notifies the user if the PLL achieved a lock for the
specific setup. Register 0x056F also has a loss of lock (LOL)
sticky bit (Bit 3) that notifies the user that a loss of lock is
detected. The sticky bit can be reset by issuing a JESD204B link
restart (Register 0x0571, Bit 0 = 0x1, followed by Register 0x0571,
Bit 0 = 0x0). Refer to Table 34 for the reinitialization of the link
following a link power cycle.
The JESD204B lane rate control, Bits[7:4] of Register 0x056E,
must be set to correspond with the lane rate. Table 33 shows
the lane rates supported by the AD9695 using Register 0x056E.
Table 33. AD9695 Register 0x056E Supported Lane Rates
Value
0x00
0x10
0x30
0x50
Lane Rate
Lane rate = 6.75 Gbps to 13.5
Lane rate = 3.375 Gbps to 6.75 Gbps (default)
Lane rate = 13.5 Gbps to 16 Gbps
Lane rate = 1.6875 Gbps to 3.375 Gbps
To ensure proper operation of the AD9695 at startup, some SPI
writes are required to initialize the link. Additionally, these
registers must be written every time the ADC is reset. Any one
of the following resets warrants the initialization routine for the
digital interface:
Hard reset, as with power-up.
Power-up using the PDWN pin.
Power-up using the SPI via Register 0x0002, Bits[1:0].
SPI soft reset by setting Register 0x0000 = 0x81.
Datapath soft reset by setting Register 0x0001 = 0x02.
JESD204B link power cycle by setting Register 0x0571,
Bit 0 = 0x1, then 0x0.
The initialization SPI writes are as shown in Table 34.
Comment
Reset JESD204B start-up circuit
JESD204B start-up circuit in normal operation
JESD204B PLL force normal operation
Reset JESD204B PLL calibration
JESD204B PLL normal operation
Clear loss of lock bit
Loss of lock bit normal operation
The AD9695 has one JESD204B link. The serial outputs
(SERDOUT0± to SERDOUT3±) are considered to be part of
one JESD204B link. The basic parameters that determine the
link setup are
•
•
•
Number of lanes per link (L)
Number of converters per link (M)
Number of octets per frame (F)
If the internal DDCs are used for on-chip digital processing, M
represents the number of virtual converters. The virtual converter
mapping setup is shown in Table 11.
By default in the AD9695, the 14-bit converter word from each
converter is broken into two octets (eight bits of data). Bit 13
(MSB) through Bit 6 are in the first octet. The second octet
contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits
can be configured as zeros or a pseudorandom number
sequence. The tail bits can also be replaced with control bits
indicating overrange, SYSREF±, or fast detect output. Control
bits are filled and inserted MSB first such that enabling CS = 1
activates Control Bit 2, enabling CS = 2 activates Control Bit 2
and Control Bit 1, and enabling CS = 3 activates Control Bit 2,
Control Bit 1, and Control Bit 0.
The maximum lane rate allowed by the AD9695 is 16 Gbps.
The lane rate is related to the JESD204B parameters using the
following equation:
SETTING UP THE AD9695 DIGITAL INTERFACE
•
•
•
•
•
•
Valu
e
0x4F
0x0F
0x00
0x04
0x00
0x08
0x00
10
M × N '× × f OUT
8
Lane Rate =
L
where fOUT =
f ADC _ CLOCK
Decimation Ratio
The decimation ratio (DCM) is the parameter programmed in
Register 0x0201.
Use the following procedure to configure the output:
1.
2.
3.
4.
5.
6.
7.
Rev. C | Page 75 of 136
Power down the link.
Select the JESD204B link configuration options.
Configure the detailed options.
Set output lane mapping (optional).
Set additional driver configuration options (optional).
Power up the link.
Initialize the JESD204B link by issuing the commands
described in Table 34.
AD9695
Data Sheet
Register 0x056E must be programmed according to the lane
rate calculated. Refer to the Phase-Locked Loop (PLL) section
for more details.
Table 35 and Table 36 show the JESD204B output configurations
supported for both N΄ = 16, N’=12, and N΄ = 8 for a given
number of virtual converters. Take care to ensure that the serial
lane rate for a given configuration is within the supported
range of 1.6875 Gbps to 16 Gbps.
Table 35. JESD204B Output Configurations for N΄ = 16 1
Number
of Virtual
Converters
Supported
(Same as M)
1
JESD204B
Serial
Lane
Rate 2
20 × fOUT
Lane Rate =
3.375 Gbps to
6.75 Gbps
1, 2, 3, 4, 5, 6, 8
Lane Rate =
6.75 Gbps to
13.5 Gbps
1, 2, 3, 4
Lane Rate =
13.5 Gbps to
16 Gbps
1, 2
L
1
M
1
F
2
S
1
HD
0
N
8 to 16
N'
16
CS
0 to 3
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
1
1
4
2
0
8 to 16
16
0 to 3
1, 2, 3, 4
1, 2
1
2
1
1
1
1
8 to 16
16
0 to 3
10 × fOUT
1, 2, 3, 4
1, 2
1
2
1
2
2
0
8 to 16
16
0 to 3
5 × fOUT
1, 2, 3, 4
1, 2
1
4
1
1
2
1
8 to 16
16
0 to 3
5 × fOUT
1, 2, 3, 4
1, 2
1
4
1
2
4
0
8 to 16
16
0 to 3
40 × fOUT
2, 4, 5, 6, 8, 10,
12, 15, 16
2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1
2
4
1
0
8 to 16
16
0 to 3
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1
2
8
2
0
8 to 16
16
0 to 3
1, 2, 3, 4
1, 2
2
2
2
1
0
8 to 16
16
0 to 3
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
2
2
4
2
0
8 to 16
16
0 to 3
10 × fOUT
4, 8, 10, 12, 15,
16, 20, 24, 30
4, 8, 10, 12, 15,
16, 20, 24, 30
2, 4, 5, 6, 8, 10,
12, 15, 16
2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
1
4
2
1
1
1
8 to 16
16
0 to 3
10 × fOUT
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
1
4
2
2
2
0
8 to 16
16
0 to 3
80 × fOUT
8, 16, 20, 24, 30,
40, 48
4, 8, 10, 12, 15,
16, 20, 24, 30
4, 8, 10, 12, 15,
16, 20, 24, 30
2, 4, 5, 6, 8, 10,
12, 15, 16
2, 4, 5, 6, 8, 10,
12, 15, 16
16, 40, 48
4, 8, 10, 12, 16,
20, 24, 30
2, 4, 5, 6, 8, 10,
12, 15, 16
2, 4, 5, 6, 8, 10,
12, 15, 16
1, 2, 3, 4, 5, 6, 8
2, 4, 6, 8, 10, 12,
16
1, 2, 3, 4, 5, 6, 8
2, 4, 6, 8
1
4
8
1
0
8 to 16
16
0 to 3
1, 2, 3, 4
2
4
4
1
0
8 to 16
16
0 to 3
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
2
4
8
2
0
8 to 16
16
0 to 3
1, 2, 3, 4
1, 2
4
4
2
1
0
8 to 16
16
0 to 3
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
4
4
4
2
0
8 to 16
16
0 to 3
8, 16, 20, 24, 40,
48
4, 8, 10, 12, 16,
20, 24
2, 4, 6, 8, 10, 12,
16
2, 4, 6, 8, 10, 12,
16
4, 8, 12, 16, 20,
24
2, 4, 6, 8, 10, 12,
16
2, 4, 6, 8
4, 8, 12, 16
1
8
16
1
0
8 to 16
16
0 to 3
2, 4, 6, 8
2
8
8
1
0
8 to 16
16
0 to 3
2, 4
4
8
4
1
0
8 to 16
16
0 to 3
2, 4, 6, 8
2, 4
4
8
8
2
0
8 to 16
16
0 to 3
10 × fOUT
40 × fOUT
20 × fOUT
20 × fOUT
4
40 × fOUT
40 × fOUT
20 × fOUT
20 × fOUT
8
JESD204B Transport Layer Settings 3
Lane Rate =
1.6875 Gbps to
3.375 Gbps
2, 4, 5, 6, 8, 10,
12
2, 4, 5, 6, 8, 10,
12
1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4, 5, 6, 8
20 × fOUT
2
Supported Decimation Rates
160 × fOUT
80 × fOUT
40 × fOUT
40 × fOUT
8, 16, 20, 24, 40,
48
4, 8, 10, 12, 16,
20, 24
4, 8, 10, 12, 16,
20, 24
K
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter
device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the
virtual converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the
number of frames per multiframe.
3
fADC_CLK is the ADC sample rate; DCM = chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations
must be met due to internal clock divider requirements: SLR ≥1.6875 Gbps and SLR ≤15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple(20 × DCM × fOUT/SLR, DCM) ≤
64. When the SLR is ≤16,000 Mbps and >13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13,500 Mbps and ≥6750 Mbps, Register 0x056E must be
set to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is 13,500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤13,500 Mbps and ≥6750 Mbps,
Register 0x056E must be set to 0x00. When the SLR is
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