AD9780-EBZ

Dual 12-/14-/16-Bit, LVDS Interface, 500 MSPS DACs AD9780/AD9781/AD9783 FEATURES High dynamic range, dual DAC parts Low noise and intermodulation distortion Single carrier W-CDMA ACLR = 80 dBc @ 61.44 MHz IF Innovative switching output stage permits usable outputs beyond Nyquist frequency LVDS inputs with dual-port or optional interleaved singleport operation Differential analog current outputs are programmable from 8.6 mA to 31.7 mA full scale Auxiliary 10-bit current DACs with source/sink capability for external offset nulling Internal 1.2 V precision reference voltage source Operates from 1.8 V and 3.3 V supplies 315 mW power dissipation Small footprint, RoHS compliant, 72-lead LFCSP GENERAL DESCRIPTION The AD9780/AD9781/AD9783 include pin-compatible, high dynamic range, dual digital-to-analog converters (DACs) with 12-/14-/16-bit resolutions, and sample rates of up to 500 MSPS. The devices include specific features for direct conversion transmit applications, including gain and offset compensation, and they interface seamlessly with analog quadrature modulators such as the ADL5370. A proprietary, dynamic output architecture permits synthesis of analog outputs even above Nyquist by shifting energy away from the fundamental and into the image frequency. Full programmability is provided through a serial peripheral interface (SPI) port. Some pin-programmable features are also offered for those applications without a controller. PRODUCT HIGHLIGHTS 1. 2. 3. Low noise and intermodulation distortion (IMD) enable high quality synthesis of wideband signals. Proprietary switching output for enhanced dynamic performance. Programmable current outputs and dual auxiliary DACs provide flexibility and system enhancements. APPLICATIONS Wireless infrastructure W-CDMA, CDMA2000, TD-SCDMA, WiMAX Wideband communications LMDS/MMDS, point-to-point RF signal generators, arbitrary waveform generators FUNCTIONAL BLOCK DIAGRAM CLKP CLKN DEINTERLEAVING LOGIC AD9783 DUAL LVDS DAC 16-BIT I DAC INTERFACE LOGIC 16-BIT Q DAC GAIN DAC GAIN DAC INTERNAL REFERENCE AND BIAS OFFSET DAC OFFSET DAC AUX1P AUX1N AUX2P AUX2N 06936-001 IOUT1P IOUT1N IOUT2P IOUT2N LVDS INTERFACE D[15:0] VIA, VIB SERIAL PERIPHERAL INTERFACE REFIO SDIO SCLK CSB Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. RESET SDO One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved. AD9780/AD9781/AD9783 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Product Highlights ........................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  DC Specifications ......................................................................... 3  Digital Specifications ................................................................... 4  AC Specifications.......................................................................... 4  Absolute Maximum Ratings............................................................ 5  Thermal Resistance ...................................................................... 5  ESD Caution .................................................................................. 5  Pin Configurations and Function Descriptions ........................... 6  Typical Performance Characteristics ............................................. 9  Terminology .................................................................................... 17  Theory of Operation ...................................................................... 18  Serial Peripheral Interface ......................................................... 18  General Operation of the Serial Interface ............................... 18  Instruction Byte .......................................................................... 18  MSB/LSB Transfers .................................................................... 19  Serial Interface Port Pin Descriptions ..................................... 19  SPI Register Map ............................................................................ 20  SPI Register Descriptions .............................................................. 21  SPI Port, RESET, and Pin Mode ............................................... 23  Parallel Data Port Interface ........................................................... 24  Optimizing the Parallel Port Timing ....................................... 24  Driving the CLK Input .............................................................. 26  Full-Scale Current Generation ................................................. 26  DAC Transfer Function ............................................................. 27  Analog Modes of Operation ..................................................... 27  Power Dissipation....................................................................... 29  Evaluation Board Schematics........................................................ 30  Outline Dimensions ....................................................................... 35  Ordering Guide .......................................................................... 35  REVISION HISTORY 6/08—Rev. 0 to Rev. A Changed Maximum Sample Rate to 500 MHz Throughout ....... 1 Changes to Table 3 ............................................................................ 4 Changes to Building the Array Section ....................................... 25 Changes to Determining the SMP Value Section....................... 25 Added Evaluation Board Schematics Section ............................. 30 Updated Outline Dimensions ....................................................... 35 11/07—Revision 0: Initial Version Rev. A | Page 2 of 36 AD9780/AD9781/AD9783 SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless otherwise noted. Table 1. Parameter RESOLUTION ACCURACY Differential Nonlinearity (DNL) Integral Nonlinearity (INL) MAIN DAC OUTPUTS Offset Error Gain Error (with Internal Reference) Full-Scale Output Current 1 Output Compliance Range Output Resistance Main DAC Monotonicity Guaranteed MAIN DAC TEMPERATURE DRIFT Offset Gain Reference Voltage AUX DAC OUTPUTS Resolution Full-Scale Output Current Output Compliance Range (Source) Output Compliance Range (Sink) Output Resistance AUX DAC Monotonicity Guaranteed REFERENCE Internal Reference Voltage Output Resistance ANALOG SUPPLY VOLTAGES AVDD33 CVDD18 DIGITAL SUPPLY VOLTAGES DVDD33 DVDD18 POWER CONSUMPTION fDAC = 500 MSPS, IF = 20 MHz fDAC = 500 MSPS, IF = 10 MHz Power-Down Mode SUPPLY CURRENTS 2 AVDD33 CVDD18 DVDD33 DVDD18 1 2 Min AD9780 Typ Max 12 ±0.13 ±0.25 Min AD9781 Typ Max 14 ±0.5 ±1 Min AD9783 Typ Max 16 ±2 ±4 Unit Bits LSB LSB –0.001 8.66 –1.0 0 ±2 20.2 10 +0.001 31.66 +1.0 –0.001 8.66 –1.0 0 ±2 20.2 10 +0.001 31.66 +1.0 –0.001 8.66 –1.0 0 ±2 20.2 10 +0.001 31.66 +1.0 % FSR % FSR mA V MΩ 0.04 100 30 10 –2 0 0.8 1 +2 1.6 1.6 –2 0 0.8 0.04 100 30 10 +2 1.6 1.6 1 –2 0 0.8 0.04 100 30 10 +2 1.6 1.6 1 ppm/°C ppm/°C ppm/°C Bits mA V V MΩ 1.2 5 3.13 1.70 3.13 1.70 3.3 1.8 3.3 1.8 V×I 440 3 55 34 13 68 3.47 1.90 3.47 1.90 V×I 5 58 38 15 85 3.13 1.70 3.13 1.70 1.2 5 3.3 1.8 3.3 1.8 V×I 440 3 55 34 13 68 3.47 1.90 3.47 1.90 V×I 5 58 38 15 85 3.13 1.70 3.13 1.70 1.2 5 3.3 1.8 3.3 1.8 V×I 440 3 55 34 13 68 3.47 1.90 3.47 1.90 V×I 35 58 38 15 85 V kΩ V V V V mW mW mW mA mA mA mA Based on a 10 kΩ external resistor. fDAC = 500 MSPS, fOUT = 20 MHz. Rev. A | Page 3 of 36 AD9780/AD9781/AD9783 DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA maximum sample rate, unless otherwise noted. Table 2. Parameter DAC CLOCK INPUT (CLKP, CLKN) Peak-to-Peak Voltage at CLKP and CLKN Common-Mode Voltage Maximum Clock Rate SERIAL PERIPHERAL INTERFACE (CMOS INTERFACE) Maximum Clock Rate (SCLK) Minimum Pulse Width High Minimum Pulse Width Low DIGITAL INPUT DATA (LVDS INTERFACE) Input Voltage Range, VIA or VIB Input Differential Threshold, VIDTH Input Differential Hysteresis, VIDTHH to VIDTHL Input Differential Input Impedance, RIN Maximum LVDS Input Rate (per DAC) Min 400 300 500 Typ 800 400 Max 1600 500 Unit mV mV MSPS MHz ns ns mV mV mV Ω MSPS 40 12.5 12.5 800 −100 20 80 500 120 1600 +100 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD33 = 3.3 V, DVDD18 = 1.8 V, CVDD18 = 1.8 V, IOUTFS = 20 mA, maximum sample rate, unless otherwise noted. Table 3. Parameter SPURIOUS FREE DYNAMIC RANGE (SFDR) fDAC = 500 MSPS, fOUT = 20 MHz fDAC = 500 MSPS, fOUT = 120 MHz fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode) fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode) T WO-TONE INTERMODULATION DISTORTION (IMD) fDAC = 500 MSPS, fOUT = 20 MHz fDAC = 500 MSPS, fOUT = 120 MHz fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode) fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode) ONE-TONE NOISE SPECTRAL DENSITY (NSD) fDAC = 500 MSPS, fOUT = 40 MHz fDAC = 500 MSPS, fOUT = 120 MHz fDAC = 500 MSPS, fOUT = 380 MHz (Mix Mode) fDAC = 500 MSPS, fOUT = 480 MHz (Mix Mode) W-CDMA ADJACENT CHANNEL LEAKAGE RATIO (ACLR), SINGLE CARRIER fDAC = 491.52 MSPS, fOUT = 20 MHz fDAC = 491.52 MSPS, fOUT = 80 MHz fDAC = 491.52 MSPS, fOUT = 411.52 MHz fDAC = 491.52 MSPS, fOUT = 471.52 MHz AD9780 Min Typ Max 79 67 55 58 91 80 69 60.5 −157 −154.5 −153 −152 AD9781 Min Typ Max 78 66 58 62 93 75 70 61.5 −162 −156.5 −153 −152 AD9783 Min Typ Max 80 68 62 59 86 79 64 66 −165 −157 −154 −153 Unit dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc −81 −80 −71 −69 −82.5 −82.5 −68 −69 −82 −81 −69 −70 dBc dBc dBc dBc Rev. A | Page 4 of 36 AD9780/AD9781/AD9783 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD33, DVDD33 DVDD18, CVDD18 AGND DGND CGND REFIO IOUT1P, IOUT1N, IOUT2P, IOUT2N, AUX1P, AUX1N, AUX2P, AUX2N D15 to D0 CLKP, CLKN CSB, SCLK, SDIO, SDO Junction Temperature Storage Temperature With Respect to AGND, DGND, CGND AGND, DGND, CGND DGND, CGND AGND, CGND AGND, DGND AGND AGND Rating −0.3 V to +3.6 V −0.3 V to +1.98 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to AVDD33 + 0.3 V −1.0 V to AVDD33 + 0.3 V THERMAL RESISTANCE Thermal resistance is tested using a JEDEC standard 4-layer thermal test board with no airflow. Table 5. Package Type CP-72-1 (Exposed Pad Soldered to PCB) θJA 25 Unit °C/W DGND CGND DGND −0.3 V to DVDD33 + 0.3 V −0.3 V to CVDD18 + 0.3 V –0.3 V to DVDD33 + 0.3 V +125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. A | Page 5 of 36 AD9780/AD9781/AD9783 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 D11P D11N D10P D10N D9P D9N D8P D8N D7P D7N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 PIN 1 INDICATOR AD9780 (TOP VIEW) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FS ADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 NC NC NC NC NC NC NC NC D0N D0P NOTES 1. NC = NO CONNECT 2. EXPOSED PAD MUST BE SOLDERED TO PCB AND CONNECTED TO AVSS. D6P D6N D5P D5N D4P D4N DCOP DCON DVDD33 DVSS DCIP DCIN D3P D3N D2P D2N D1P D1N 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Figure 2. AD9780 Pin Configuration Table 6. AD9780 Pin Function Descriptions Pin No. 1, 6 2, 5 3, 4 7, 28, 48 8, 47 9 to 24, 31 to 38 25, 26 27 29, 30 39 to 46 49 50 51 52 53 54 55 56, 57, 71, 72 58, 61, 64, 67, 70 59 60 62, 63 65, 66 68 69 Heat Sink Pad Mnemonic CVDD18 CVSS CLKP, CLKN DVSS DVDD18 D11P, D11N to D0P, D0N DCOP, DCON DVDD33 DCIP, DCIN NC SDO SDIO SCLK CSB RESET FS ADJ REFIO AVDD33 AVSS IOUT2P IOUT2N AUX2P, AUX2N AUX1N, AUX1P IOUT1N IOUT1P N/A Description Clock Supply Voltage (1.8 V). Clock Supply Return. Differential DAC Sampling Clock Input. Digital Common. Digital Supply Voltage (1.8 V). LVDS Data Inputs. D11 is the MSB, D0 is the LSB. Differential Data Clock Output. LVDS clock at the DAC sample rate. Digital Input and Output Pad Ring Supply Voltage (3.3 V). Differential Data Clock Input. LVDS clock aligned with input data. No Connection. Leave these pins floating. Serial Port Data Output. Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode). Serial Port Clock Input. Serial Port Chip Select (Active Low). Chip Reset (Active High). Full-Scale Current Output Adjust. Analog Reference Input/Output (1.2 V Nominal). Analog Supply Voltage (3.3 V). Analog Common. DAC Current Output. Full-scale current is sourced when all data bits are 1s. Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. Differential Auxiliary DAC Current Output (Channel 2). Differential Auxiliary DAC Current Output (Channel 1). Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. DAC Current Output. Full-scale current is sourced when all data bits are 1s. The heat sink pad on the bottom of the package should be soldered to the PCB plane that carries AVSS. Rev. A | Page 6 of 36 06936-002 AD9780/AD9781/AD9783 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 D13P D13N D12P D12N D11P D11N D10P D10N D9P D9N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 PIN 1 INDICATOR AD9781 (TOP VIEW) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FS ADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 NC NC NC NC D0N D0P D1N D1P D2N D2P NOTES 1. NC = NO CONNECT 2. EXPOSED PAD MUST BE SOLDERED TO PCB AND CONNECTED TO AVSS. D8P D8N D7P D7N D6P D6N DCOP DCON DVDD33 DVSS DCIP DCIN D5P D5N D4P D4N D3P D3N 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Figure 3. AD9781 Pin Configuration Table 7. AD9781 Pin Function Descriptions Pin No. 1, 6 2, 5 3, 4 7, 28, 48 8, 47 9 to 24, 31 to 42 25, 26 27 29, 30 43 to 46 49 50 51 52 53 54 55 56, 57, 71, 72 58, 61, 64, 67, 70 59 60 62, 63 65, 66 68 69 Heat Sink Pad Mnemonic CVDD18 CVSS CLKP, CLKN DVSS DVDD18 D13P, D13N to D0P, D0N DCOP, DCON DVDD33 DCIP, DCIN NC SDO SDIO SCLK CSB RESET FS ADJ REFIO AVDD33 AVSS IOUT2P IOUT2N AUX2P, AUX2N AUX1N, AUX1P IOUT1N IOUT1P N/A Description Clock Supply Voltage (1.8 V). Clock Supply Return. Differential DAC Sampling Clock Input. Digital Common. Digital Supply Voltage (1.8 V). LVDS Data Inputs. D13 is the MSB, D0 is the LSB. Differential Data Clock Output. LVDS clock at the DAC sample rate. Digital Input and Output Pad Ring Supply Voltage (3.3 V). Differential Data Clock Input. LVDS clock aligned with input data. No Connection. Leave these pins floating. Serial Port Data Output. Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode). Serial Port Clock Input. Serial Port Chip Select (Active Low). Chip Reset (Active High). Full-Scale Current Output Adjust. Analog Reference Input/Output (1.2 V Nominal). Analog Supply Voltage (3.3 V). Analog Common. DAC Current Output. Full-scale current is sourced when all data bits are 1s. Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. Differential Auxiliary DAC Current Output (Channel 2). Differential Auxiliary DAC Current Output (Channel 1). Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. DAC Current Output. Full-scale current is sourced when all data bits are 1s. The heat sink pad on the bottom of the package should be soldered to the PCB plane that carries AVSS. Rev. A | Page 7 of 36 06936-003 AD9780/AD9781/AD9783 AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 D15P D15N D14P D14N D13P D13N D12P D12N D11P D11N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 PIN 1 INDICATOR AD9783 (TOP VIEW) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 FS ADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 D0N D0P D1N D1P D2N D2P D3N D3P D4N D4P NOTES 1. EXPOSED PAD MUST BE SOLDERED TO PCB AND CONNECTED TO AVSS. D10P D10N D9P D9N D8P D8N DCOP DCON DVDD33 DVSS DCIP DCIN D7P D7N D6P D6N D5P D5N 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Figure 4. AD9783 Pin Configuration Table 8. AD9783 Pin Function Descriptions Pin No. 1, 6 2, 5 3, 4 7, 28, 48 8, 47 9 to 24, 31 to 46 25, 26 27 29, 30 49 50 51 52 53 54 55 56, 57, 71, 72 58, 61, 64, 67, 70 59 60 62, 63 65, 66 68 69 Heat Sink Pad Mnemonic CVDD18 CVSS CLKP, CLKN DVSS DVDD18 D15P, D15N to D0P, D0N DCOP, DCON DVDD33 DCIP, DCIN SDO SDIO SCLK CSB RESET FS ADJ REFIO AVDD33 AVSS IOUT2P IOUT2N AUX2P, AUX2N AUX1N, AUX1P IOUT1N IOUT1P N/A Description Clock Supply Voltage (1.8 V). Clock Supply Return. Differential DAC Sampling Clock Input. Digital Common. Digital Supply Voltage (1.8 V). LVDS Data Inputs. D15 is the MSB, D0 is the LSB. Differential Data Clock Output. LVDS clock at the DAC sample rate. Digital Input and Output Pad Ring Supply Voltage (3.3 V). Differential Data Clock Input. LVDS clock aligned with input data. Serial Port Data Output. Serial Port Data Input (4-Wire Mode) or Bidirectional Serial Data Line (3-Wire Mode). Serial Port Clock Input. Serial Port Chip Select (Active Low). Chip Reset (Active High). Full-Scale Current Output Adjust. Analog Reference Input/Output (1.2 V Nominal). Analog Supply Voltage (3.3 V). Analog Common. DAC Current Output. Full-scale current is sourced when all data bits are 1s. Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. Differential Auxiliary DAC Current Output (Channel 2). Differential Auxiliary DAC Current Output (Channel 1). Complementary DAC Current Output. Full-scale current is sourced when all data bits are 0s. DAC Current Output. Full-scale current is sourced when all data bits are 1s. The heat sink pad on the bottom of the package should be soldered to the PCB plane that carries AVSS. Rev. A | Page 8 of 36 06936-004 AD9780/AD9781/AD9783 TYPICAL PERFORMANCE CHARACTERISTICS 1.5 1.0 0.5 0.4 0.2 0 –0.2 0 –0.4 LSB LSB 06936-005 –0.5 –1.0 –1.5 –2.0 –2.5 –0.6 –0.8 –1.0 –1.2 –1.4 0 16,384 32,768 CODE 49,152 65,535 0 16,384 32,768 CODE 49,152 65,535 Figure 5. AD9783 INL, TA = 85°C, FS = 20 mA Figure 8. AD9783 DNL, TA = 85°C, FS = 20 mA 5 4 3 2 0.4 0.2 0 –0.2 –0.4 LSB –0.6 –0.8 –1.0 LSB 1 0 –1 –1.2 –2 06936-006 –1.4 0 16,384 32,768 CODE 49,152 65,535 0 16,384 32,768 CODE 49,152 65,535 Figure 6. AD9783 INL, TA = 25°C, FS = 20 mA Figure 9. AD9783 DNL, TA = 25°C, FS = 20 mA 5 4 3 2 1.0 0.8 0.6 0.4 0.2 LSB 1 0 –1 –2 06936-007 LSB 0 –0.2 –0.4 –0.6 –0.8 0 16,384 32,768 CODE 49,152 65,535 0 16,384 32,768 CODE 49,152 65,535 Figure 7. AD9783 INL, TA = −40°C, FS = 20 mA Figure 10. AD9783 DNL, TA = −40°C, FS = 20 mA Rev. A | Page 9 of 36 06936-010 –3 –1.0 06936-009 –3 –1.6 06936-008 –1.6 AD9780/AD9781/AD9783 0.4 0.3 0.2 0.1 0 –0.060 0.059 LSB LSB –0.1 –0.2 –0.3 –0.4 –0.5 0 4096 8192 CODE 12,288 16,383 06936-011 –0.179 –0.297 0 4096 8192 CODE 12,288 16,383 Figure 11. AD9781 INL, TA = 85°C, FS = 20 mA Figure 14. AD9781 DNL, TA = 85°C, FS = 20 mA 0.6 0.4 0.2 0.1 0 –0.1 0 LSB LSB –0.2 –0.4 –0.6 –0.8 06936-012 –0.2 –0.3 –0.4 0 4096 8192 CODE 12288 16,383 0 4096 8192 CODE 12,288 16,383 Figure 12. AD9781 INL, TA = −40°C, FS = 20 mA Figure 15. AD9781 DNL, TA = −40°C, FS = 20 mA 0.2 0.1 0 –0.1 0.2 0.1 0 –0.1 LSB LSB –0.2 –0.3 –0.4 –0.5 –0.6 –0.2 –0.3 –0.4 –0.5 –0.6 06936-013 0 1024 2048 CODE 3072 4096 0 1024 2048 CODE 3072 4096 Figure 13. AD9780 INL, TA = −40°C, FS = 20 mA Figure 16. AD9780 INL, TA = 85°C, FS = 20 mA Rev. A | Page 10 of 36 06936-016 06936-015 –1.0 –0.5 06936-014 –0.6 –0.416 AD9780/AD9781/AD9783 90 85 80 75 250MSPS 400MSPS 100 95 90 85 80 +25°C –40°C SFDR (dBc) SFDR (dBc) 70 65 60 55 50 45 06936-017 75 70 65 60 +85°C 500MSPS 55 50 45 0 50 100 150 200 250 300 350 400 450 500 0 25 50 75 100 125 150 175 200 225 250 fOUT (MHz) fOUT (MHz) Figure 17. AD9783 SFDR vs. fOUT Over fDAC in Baseband and Mix Modes, FS = 20 mA 100 95 90 85 80 20mA 30mA Figure 20. AD9783 SFDR vs. fOUT Over Temperature, at 500 MSPS, FS = 20 mA 100 95 90 85 80 250MSPS SFDR (dBc) IMD (dBc) 75 70 65 60 55 50 45 06936-018 75 70 65 60 400MSPS 10mA 55 50 45 500MSPS 0 25 50 75 100 125 150 175 200 225 250 0 50 100 150 200 250 300 350 400 450 500 fOUT (MHz) fOUT (MHz) Figure 18. AD9783 SFDR vs. fOUT Over Analog Output, TA = 25°C, at 500 MSPS Figure 21. AD9783 IMD vs. fOUT Over fDAC in Baseband and Mix Modes, FS = 20 mA 100 95 90 85 10mA 20mA 100 95 90 85 80 SFDR (dBc) –3dBFS 80 IMD (dBc) 75 70 65 60 55 50 45 06936-019 75 70 65 60 55 50 45 30mA –6dBFS 0dBFS 0 25 50 75 100 125 150 175 200 225 250 0 25 50 75 100 125 150 175 200 225 250 fOUT (MHz) fOUT (MHz) Figure 19. AD9783 SFDR vs. fOUT Over Digital Input Level, TA = 25°C, at 500 MSPS, FS = 20 mA Figure 22. AD9783 IMD vs. fOUT Over Analog Output, TA = 25°C, at 500 MSPS Rev. A | Page 11 of 36 06936-022 40 40 06936-021 40 40 06936-020 40 40 AD9780/AD9781/AD9783 100 95 90 85 80 –3dBFS –6dBFS –140 –143 –146 –149 NSD (dBm/Hz) IMD (dBc) 75 70 65 60 55 50 45 06936-023 –152 –155 –158 –161 –164 –167 400MSPS 500MSPS 250MSPS 0dBFS 0 30 60 90 120 150 180 210 240 0 50 100 150 200 250 300 350 400 450 500 fOUT (MHz) fOUT (MHz) Figure 23. AD9783 IMD vs. fOUT Over Digital Input Level, TA = 25°C, at 500 MSPS, FS = 20 mA 100 95 90 85 80 +85°C Figure 26. AD9783 Eight-Tone NSD vs. fOUT Over fDAC Baseband and Mix Modes, FS = 20 mA –140 –143 –146 –149 NSD (dBm/Hz) IMD (dBc) 75 70 65 60 55 50 45 –40°C +25°C –152 –155 –158 –161 –164 –167 +25°C +85°C –40°C 06936-024 0 30 60 90 120 150 180 210 240 0 25 50 75 100 125 150 175 200 225 250 fOUT (MHz) fOUT (MHz) Figure 24. AD9783 IMD vs. fOUT Over Temperature, at 500 MSPS, FS = 20 mA Figure 27. AD9783 One-Tone NSD vs. fOUT Over Temperature, at 500 MSPS, FS = 20 mA –140 –143 –146 –140 –143 –146 –149 250MSPS –149 NSD (dBm/Hz) –152 –155 –158 –161 –164 –167 06936-025 NSD (dBm/Hz) –152 –155 –158 –161 –164 –167 –40°C 0 25 50 75 100 125 150 175 200 225 250 06936-028 500MSPS +85°C 400MSPS +25°C –170 0 50 100 150 200 250 300 350 400 450 500 –170 fOUT (MHz) fOUT (MHz) Figure 25. AD9783 One-Tone NSD vs. fOUT Over fDAC Baseband and Mix Modes, FS = 20 mA Figure 28. AD9783 Eight-Tone NSD vs. fOUT Over Temperature, at 500 MSPS, FS = 20 mA Rev. A | Page 12 of 36 06936-027 40 –170 06936-026 40 –170 AD9780/AD9781/AD9783 –50 –55 –60 –65 245.76MSPS –70 –75 –80 –85 –90 491.52MSPS –50 –55 –60 –65 –70 –3dB –75 –80 –85 –90 0dB ACLR (dBc) 06936-029 fOUT (MHz) fOUT (MHz) Figure 29. AD9783 ACLR for First Adjacent Band One-Carrier W-CDMA Baseband and Mix Modes, FS = 20 mA –50 –55 –60 –65 –70 245.76MSPS –75 –80 –85 –90 491.52MSPS Figure 32. AD9783 ACLR for First Adjacent Channel Two-Carrier W-CDMA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS, FS = 20 mA –50 –55 –60 –65 –70 –75 –80 0dB –85 –90 –3dB ACLR (dBc) 06936-030 fOUT (MHz) fOUT (MHz) Figure 30. AD9783 ACLR for Second Adjacent Band One-Carrier W-CDMA Baseband and Mix Modes, FS = 20 mA –50 –55 –60 –65 –70 –75 –80 –85 –90 245.76MSPS 491.52MSPS Figure 33. AD9783 ACLR for Second Adjacent Channel Two-Carrier W-CDMA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS, FS = 20 mA –50 –55 –60 –65 –70 –75 –80 0dB 06936-034 ACLR (dBc) ACLR (dBc) –3dB –85 06936-031 0 100 200 300 400 500 –90 0 100 200 300 400 500 fOUT (MHz) fOUT (MHz) Figure 31. AD9783 ACLR for Third Adjacent Band One-Carrier W-CDMA Baseband and Mix Modes, FS = 20 mA Figure 34. AD9783 ACLR for Third Adjacent Channel Two-Carrier W-CDMA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS, FS = 20 mA Rev. A | Page 13 of 36 06936-033 0 100 200 300 400 500 ACLR (dBc) 0 100 200 300 400 500 06936-032 0 100 200 300 400 500 ACLR (dBc) 0 100 200 300 400 500 AD9780/AD9781/AD9783 –50 –55 –60 –65 –70 –75 –80 –85 –90 0dB 1.0 0.5 0 –0.5 AMPLITUDE (dBm) –1.0 –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 –4.5 ACLR (dBc) NORMAL MODE –3dB MIX MODE fOUT (MHz) 06936-035 0 100 200 300 400 500 0 60 120 180 240 300 360 420 480 540 600 fOUT (MHz) Figure 35. AD9783 ACLR for First Adjacent Channel Four-Carrier W-CDMA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS, FS = 20 mA –50 –55 –60 –65 –70 –75 –80 –85 –90 0dB –3dB Figure 38. Nominal Power in the Fundamental, FS = 20 mA, at 500 MSPS, FS = 20 mA 0.8 0.6 0.4 0.2 ACLR (dBc) LSB 0 –0.2 –0.4 –0.6 06936-039 06936-040 fOUT (MHz) 06936-036 0 100 200 300 400 500 –0.8 0 4096 8192 CODE 12,288 16,383 Figure 36. AD9783 ACLR for Second Adjacent Channel Four-Carrier W-CDMA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS, FS = 20 mA –50 –55 –60 Figure 39. AD9781 INL, FS = 20 mA 0.1 0 –0.1 ACLR (dBc) –65 –70 –75 –80 0dB –3dB LSB –0.2 –0.3 –0.4 –85 –90 –0.5 06936-037 0 100 200 300 400 500 0 4096 8192 CODE 12,288 16,383 fOUT (MHz) Figure 37. AD9783 ACLR for Third Adjacent Channel Four-Carrier W-CDMA Over Digital Input Level Baseband and Mix Modes, at 491.52 MSPS, FS = 20 mA Figure 40. AD9781 DNL, FS = 20 mA Rev. A | Page 14 of 36 06936-038 –5.0 AD9780/AD9781/AD9783 100 95 90 85 80 –50 –55 –60 –65 –70 –75 –80 –85 06936-041 SFDR (dBc) 75 70 65 60 55 50 45 40 0 50 100 150 200 250 300 350 400 450 500 ACLR (dBc) FIRST ADJACENT CHANNEL SECOND ADJACENT CHANNEL 0 100 200 300 THIRD ADJACENT CHANNEL fOUT (MHz) fOUT (MHz) Figure 41. AD9781 SFDR vs. fOUT in Baseband and Mix Modes, at 500 MSPS, FS = 20 mA 100 95 90 85 80 IMD @ 500MSPS Figure 44. AD9781 ACLR for One-Carrier W-CDMA Baseband and Mix Modes, at 491.52 MSPS, FS = 20 mA 0.2 0.1 0 –0.1 LSB IMD (dBc) 75 70 65 60 55 50 45 06936-042 –0.2 –0.3 –0.4 –0.5 –0.6 0 60 120 180 240 300 360 420 480 540 600 0 1024 2048 CODE 3072 4096 fOUT (MHz) Figure 42. AD9781 IMD vs. fOUT in Baseband and Mix Modes, at 500 MSPS, FS = 20 mA –140 –142 –144 –146 –148 –150 1-TONE Figure 45. AD9780 INL, FS = 20 mA 0.04 0.02 0 –0.02 LSB NSD (dBm/Hz) –152 –154 –156 –158 –160 –162 –164 –166 –168 06936-043 –0.04 –0.06 –0.08 –0.10 –0.12 8-TONE 0 50 100 150 200 250 300 350 400 450 500 0 1024 2048 CODE 3072 4096 fOUT (MHz) Figure 43. AD9781 One-Tone, Eight-Tone NSD vs. fOUT in Baseband and Mix Modes, at 500 MSPS, FS = 20 mA Figure 46. AD9780 DNL, FS = 20 mA Rev. A | Page 15 of 36 06936-046 –170 06936-045 40 06936-044 –90 400 500 AD9780/AD9781/AD9783 100 95 90 85 80 NSD (dBm/Hz) SFDR (dBc) –140 –142 –144 –146 –148 –150 –152 –154 –156 –158 –160 –162 –164 –166 –168 06936-047 75 70 65 60 55 50 45 40 0 50 100 150 200 250 300 350 400 450 500 1-TONE 8-TONE 0 50 100 150 200 250 300 350 400 450 500 fOUT (MHz) fOUT (MHz) Figure 47. AD9780 SFDR vs. fOUT in Baseband and Mix Modes, at 500 MSPS, FS = 20 mA 100 95 90 85 80 75 70 65 60 55 50 45 40 35 0 50 100 150 200 250 300 350 400 450 500 06936-048 Figure 49. AD9780 One-Tone, Eight-Tone NSD vs. fOUT in Baseband and Mix Modes, at 500 MSPS, FS = 20 mA –50 –55 –60 –65 –70 –75 –80 –85 –90 SECOND ADJACENT CHANNEL THIRD ADJACENT CHANNEL FIRST ADJACENT CHANNEL fOUT (MHz) fOUT (MHz) Figure 48. AD9780 IMD vs. fOUT in Baseband and Mix Modes, at 500 MSPS, FS = 20 mA Figure 50. AD9780 ACLR for One-Carrier W-CDMA Baseband and Mix Modes, at 491.52 MSPS, FS = 20 mA Rev. A | Page 16 of 36 06936-050 30 ACLR (dBc) IMD (dBc) 0 100 200 300 400 500 06936-049 –170 AD9780/AD9781/AD9783 TERMINOLOGY Linearity Error or Integral Nonlinearity (INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Monotonicity A DAC is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of zero. For IOUTA, 0 mA output is expected when the inputs are all 0s. For IOUTB, 0 mA output is expected when all inputs are set to 1s. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the difference between the output when all inputs are set to 1s and the output when all inputs are set to 0s. Output Compliance Range Output compliance range is the range of allowable voltage at the output of a current-output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per degree Celsius. For reference drift, the drift is reported in ppm per degree Celsius. Power Supply Rejection Power supply rejection is the maximum change in the full-scale output as the supplies are varied from minimum to maximum specified voltages. Settling Time Settling time is the time required for the output to reach and remain within a specified error band around its final value, measured from the start of the output transition. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels, between the peak amplitude of the output signal and the peak spurious signal between dc and the frequency equal to half the input data rate. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured fundamental. It is expressed as a percentage or in decibels. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Adjacent Channel Leakage Ratio (ACLR) ACLR is the ratio in dBc between the measured power within a channel relative to its adjacent channel. Complex Image Rejection In a traditional two-part upconversion, two images are created around the second IF frequency. These images usually waste transmitter power and system bandwidth. By placing the real part of a second complex modulator in series with the first complex modulator, either the upper or lower frequency image near the second IF can be rejected. Rev. A | Page 17 of 36 AD9780/AD9781/AD9783 THEORY OF OPERATION The AD9780/AD9781/AD9783 have a combination of features that make them very attractive for wired and wireless communications systems. The dual DAC architecture facilitates easy interface to common quadrature modulators when designing single sideband transmitters. In addition, the speed and performance of the devices allow wider bandwidths and more carriers to be synthesized than in previously available products. All features and options are software programmable through the SPI port. The Phase 1 instruction byte defines whether the upcoming data transfer is a read or write, the number of bytes in the data transfer, and a reference register address for the first byte of the data transfer. A logic high on the CSB pin followed by a logic low resets the SPI port to its initial state and defines the start of the instruction cycle. From this point, the next eight rising SCLK edges define the eight bits of the instruction byte for the current communication cycle. The remaining SCLK edges are for Phase 2 of the communication cycle, which is the data transfer between the serial port controller and the system controller. Phase 2 can be a transfer of one, two, three, or four data bytes as determined by the instruction byte. Using multibyte transfers is usually preferred, although singlebyte data transfers are useful to reduce CPU overhead or when only a single register access is required. All serial port data is transferred to and from the device in synchronization with the SCLK pin. Input data is always latched on the rising edge of SCLK, whereas output data is always valid after the falling edge of SCLK. Register contents change immediately upon writing to the last bit of each transfer byte. Anytime synchronization is lost, the device has the ability to asynchronously terminate an I/O operation whenever the CSB pin is taken to logic high. Any unwritten register content data is lost if the I/O operation is aborted. Taking CSB low then resets the serial port controller and restarts the communication cycle. SERIAL PERIPHERAL INTERFACE SDO SDIO SCLK CSB AD9783 SPI PORT 06936-051 Figure 51. SPI Port The serial peripheral interface (SPI) port is a flexible, synchronous serial communications port allowing easy interface to many industry-standard microcontrollers and microprocessors. The port is compatible with most synchronous transfer formats, including both the Motorola SPI and Intel® SSR protocols. The interface allows read and write access to all registers that configure the AD9780/AD9781/AD9783. Single or multiple byte transfers are supported as well as MSB-first or LSB-first transfer formats. Serial data input/output can be accomplished through a single bidirectional pin (SDIO) or through two unidirectional pins (SDIO/SDO). The serial port configuration is controlled by Register 0x00, Bits[7:6]. It is important to note that any change made to the serial port configuration occurs immediately upon writing to the last bit of this byte. Therefore, it is possible with a multibyte transfer to write to this register and change the configuration in the middle of a communication cycle. Care must be taken to compensate for the new configuration within the remaining bytes of the current communication cycle. Use of a single-byte transfer when changing the serial port configuration is recommended to prevent unexpected device behavior. INSTRUCTION BYTE The instruction byte contains the information shown in Table 9. Table 9. MSB B7 R/W B6 N1 B5 N0 B4 A4 B3 A3 B2 A2 B1 A1 LSB B0 A0 Bit 7, R/W, determines whether a read or a write data transfer occurs after the instruction byte write. Logic 1 indicates a read operation. Logic 0 indicates a write operation. Bits[6:5], N1 and N0, determine the number of bytes to be transferred during the data transfer cycle. The bits decode as shown in Table 10. Table 10. Byte Transfer Count N1 0 0 1 1 N0 0 1 0 1 Description Transfer one byte Transfer two bytes Transfer three bytes Transfer four bytes GENERAL OPERATION OF THE SERIAL INTERFACE There are two phases to any communication cycle with the AD9780/AD9781/AD9783: Phase 1 and Phase 2. Phase 1 is the instruction cycle, which writes an instruction byte into the device. This byte provides the serial port controller with information regarding Phase 2 of the communication cycle: the data transfer cycle. Rev. A | Page 18 of 36 AD9780/AD9781/AD9783 Bits[4:0], A4, A3, A2, A1, and A0, determine which register is accessed during the data transfer of the communication cycle. For multibyte transfers, this address is a starting or ending address depending on the current data transfer mode. For MSB-first format, the specified address is an ending address or the most significant address in the current cycle. Remaining register addresses for multiple byte data transfers are generated internally by the serial port controller by decrementing from the specified address. For LSB-first format, the specified address is a beginning address or the least significant address in the current cycle. Remaining register addresses for multiple byte data transfers are generated internally by the serial port controller by incrementing from the specified address. Serial Port Data I/O (SDIO) Data is always written into the device on this pin. However, SDIO can also function as a bidirectional data output line. The configuration of this pin is controlled by Register 0x00, Bit 7. The default is Logic 0, which configures the SDIO pin as unidirectional. Serial Port Data Output (SDO) Data is read from this pin for protocols that use separate lines for transmitting and receiving data. The configuration of this pin is controlled by Register 0x00, Bit 7. If this bit is set to a Logic 1, the SDO pin does not output data and is set to a high impedance state. INSTRUCTION CYCLE CSB DATA TRANSFER CYCLE MSB/LSB TRANSFERS The serial port can support both MSB-first and LSB-first data formats. This functionality is controlled by Register 0x00, Bit 6. The default is Logic 0, which is MSB-first format. When using MSB-first format (LSBFIRST = 0), the instruction and data bit must be written from MSB to LSB. Multibyte data transfers in MSB-first format start with an instruction byte that includes the register address of the most significant data byte. Subsequent data bytes are loaded into sequentially lower address locations. In MSB-first mode, the serial port internal address generator decrements for each byte of the multibyte data transfer. When using LSB-first format (LSBFIRST = 1), the instruction and data bit must be written from LSB to MSB. Multibyte data transfers in LSB-first format start with an instruction byte that includes the register address of the least significant data byte. Subsequent data bytes are loaded into sequentially higher address locations. In LSB-first mode, the serial port internal address generator increments for each byte of the multibyte data transfer. Use of a single-byte transfer when changing the serial port data format is recommended to prevent unexpected device behavior. SCLK R/W N1 N0 A4 A3 A2 A1 A0 D7 D6N D5N D3 0 D20 D10 D00 06936-052 SDIO SDO D7 D6N D5N D3 0 D2 0 D10 D00 Figure 52. Serial Register Interface Timing Diagram, MSB First INSTRUCTION CYCLE CSB DATA TRANSFER CYCLE SCLK A0 A1 A2 A3 A4 N0 N1 R/W D00 D10 D20 D4 N D5N D6N D7N 06936-053 SDIO SDO D00 D10 D2 0 D4 N D5N D6N D7N Figure 53. Serial Register Interface Timing Diagram, LSB First tS CSB fSCLK –1 SERIAL INTERFACE PORT PIN DESCRIPTIONS Chip Select Bar (CSB) Active low input starts and gates a communication cycle. It allows more than one device to be used on the same serial communication lines. CSB must stay low during the entire communication cycle. Incomplete data transfers are aborted anytime the CSB pin goes high. SDO and SDIO pins go to a high impedance state when this input is high. tPWH SCLK tPWL tDS SDIO INSTRUCTION BIT 7 INSTRUCTION BIT 6 Figure 54. Timing Diagram for SPI Write Register CSB Serial Clock (SCLK) The serial clock pin is used to synchronize data to and from the device and to run the internal state machines. The maximum frequency of SCLK is 40 MHz. All data input is registered on the rising edge of SCLK. All data is driven out on the falling edge of SCLK. SCLK 06936-055 tDV SDIO SDO DATA BIT N DATA BIT N – 1 Figure 55. Timing Diagram for SPI Read Register Rev. A | Page 19 of 36 06936-054 tDH AD9780/AD9781/AD9783 SPI REGISTER MAP Table 11. Register Name SPI Control Data Control Power-Down Setup and Hold Timing Adjust Seek Mix Mode DAC1 FSC DAC1 FSC MSBs AUXDAC1 AUXDAC1 MSB DAC2 FSC DAC2 FSC MSBs AUXDAC2 AUXDAC2 MSB BIST Control BIST Result 1 Low BIST Result 1 High BIST Result 2 Low BIST Result 2 High Hardware Version Addr 0x00 0x02 0x03 0x04 0x05 0x06 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F Default 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xF9 0x01 0x00 0x00 0xF9 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 N/A Bit 7 SDIO_DIR DATA PD_DCO Bit 6 LSBFIRST Bit 5 RESET Bit 4 INVDCO PD_AUX1 Bit 3 Bit 2 Bit 1 Bit 0 PD_INPT PD_AUX2 SET[3:0] AUX1SGN AUX1DIR AUX2SGN BISTEN AUX2DIR BISTRD PD_DAC2 PD_DAC1 HLD[3:0] SAMP_DLY[4:0] LVDS low LVDS high SEEK DAC1MIX[1:0] DAC2MIX[1:0] DAC1FSC[7:0] DAC1FSC[9:8] AUXDAC1[7:0] AUXDAC1[9:8] DAC2FSC[7:0] DAC2FSC[9:8] AUXDAC2[7:0] AUXDAC2[9:8] PD_BIAS PD_CLK BISTCLR BISTRES1[7:0] BISTRES1[15:8] BISTRES2[7:0] BISTRES2[15:8] VERSION[3:0] DEVICE[3:0] Rev. A | Page 20 of 36 AD9780/AD9781/AD9783 SPI REGISTER DESCRIPTIONS Reading these registers returns previously written values for all defined register bits, unless otherwise noted. Table 12. Register SPI Control Address 0x00 Bit 7 6 Name SDIO_DIR LSBFIRST Function 0, operate SPI in 4-wire mode. The SDIO pin operates as an input only pin. 1, operate SPI in 3-wire mode. The SDIO pin operates as a bidirectional data line. 0, MSB first per SPI standard. 1, LSB first per SPI standard. Only change LSB/MSB order in single-byte instructions to avoid erratic behavior due to bit order errors. 0, execute software reset of SPI and controllers, reload default register values except Register 0x00. 1, set software reset, write 0 on the next (or any following) cycle to release the reset. 0, DAC input data is twos complement binary format. 1, DAC input data is unsigned binary format. 1, inverts the data clock output. Used for adjusting timing of input data. 1, power down data clock output driver circuit. 1, power down input. 1, power down AUX2 DAC 1, power down AUX1 DAC. 1, power down voltage reference bias circuit. 1, power down DAC clock input circuit. 1, power down DAC2. 1, power down DAC1. 4-bit value used to determine input data setup timing. 4-bit value used to determine input data hold timing. 5-bit value used to optimally position input data relative to internal sampling clock. One of the LVDS inputs is above the input voltage limits of the IEEE reduced link specification. One of the LVDS inputs is below the input voltage limits of the IEEE reduced link specification. Indicator bit used with LVDS_SET and LVDS_HLD to determine input data timing margin. 00, selects normal mode, DAC1. 01, selects return-to-zero mode, DAC1. 10, selects return-to-zero mode, DAC1. 11, selects mix mode, DAC1. 00, selects normal mode, DAC2. 01, selects return-to-zero mode, DAC2. 10, selects return-to-zero mode, DAC2. 11, selects mix mode, DAC2. DAC1 full-scale 10-bit adjustment word. 0x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA. 0x200, sets DAC full-scale output current to the nominal value of 20.0 mA. 0x000, sets DAC full-scale output current to the minimum value of 8.66 mA. 5 RESET Data Control 0x02 7 4 7 6 5 4 3 2 1 0 7:4 3:0 4:0 2 1 0 DATA INVDCO PD_DCO PD_INPT PD_AUX2 PD_AUX1 PD_BIAS PD_CLK PD_DAC2 PD_DAC1 SET[3:0] HLD[3:0] SAMP_DLY[4:0] LVDS low LVDS high SEEK DAC1MIX[1:0] Power-Down 0x03 Setup and Hold Timing Adjust Seek 0x04 0x05 0x06 Mix Mode 0x0A 3:2 1:0 DAC2MIX[1:0] DAC1 FSC 0x0B 0x0C 7:0 1:0 DAC1FSC[9:0] Rev. A | Page 21 of 36 AD9780/AD9781/AD9783 Register AUXDAC1 Address 0x0D 0x0E Bit 7:0 1:0 Name AUXDAC1[9:0] Function AUXDAC1 output current adjustment word. 0x3FF, sets AUXDAC1 output current to 2.0 mA. 0x200, sets AUXDAC1 output current to 1.0 mA. 0x000, sets AUXDAC1 output current to 0.0 mA. 0, AUX1P output pin is active. 1, AUX1N output pin is active. 0, configures AUXDAC1 output to source current. 1, configures AUXDAC1 output to sink current. DAC2 full-scale 10-bit adjustment word. 0x3FF, sets DAC full-scale output current to the maximum value of 31.66 mA. 0x200, sets DAC full-scale output current to the nominal value of 20.0 mA. 0x000, sets DAC full-scale output current to the minimum value of 8.66 mA. AUXDAC2 output current adjustment word. 0x3FF, sets AUXDAC2 output current to 2.0 mA. 0x200, sets AUXDAC2 output current to 1.0 mA. 0x000, sets AUXDAC2 output current to 0.0 mA. 0, AUX2P output pin is active. 1, AUX2N output pin is active. 0, configures AUXDAC2 output to source current. 1, configures AUXDAC2 output to sink current. 1, enables and starts built-in self-test. 1, transfers BIST result registers to SPI for readback. 1, reset BIST logic and clear BIST result registers. 16-bit result generated by BIST 1. 16-bit result generated by BIST 2. Read only register; indicates the version of the chip. Read only register; indicates the device type. 0x0E 7 6 AUX1SGN AUX1DIR DAC2FSC[9:0] DAC2 FSC 0x0F 0x10 7:0 1:0 AUXDAC2 0x11 0x12 7:0 1:0 AUXDAC2[9:0] 0x12 7 6 AUX2SGN AUX2DIR BISTEN BISTRD BISTCLR BISTRES1[15:0] BISTRES2[15:0] VERSION[3:0] DEVICE[3:0] BIST Control 0x1A BIST Result 1 BIST Result 2 Hardware Version 0x1B 0x1C 0x1D 0x1E 0x1F 7 6 5 7:0 7:0 7:0 7:0 7:4 3:0 Rev. A | Page 22 of 36 AD9780/AD9781/AD9783 SPI PORT, RESET, AND PIN MODE In general, when the AD9780/AD9781/AD9783 are powered up, an active high pulse applied to the RESET pin should follow. This ensures the default state of all control register bits. In addition, once the RESET pin goes low, the SPI port can be activated; thus, CSB should be held high. For applications without a controller, the AD9780/AD9781/ AD9783 also supports pin mode operation, which allows some functional options to be pin selected without the use of the SPI port. Pin mode is enabled anytime the RESET pin is held high. In pin mode, the four SPI port pins take on secondary functions, as shown in Table 13. Table 13. SPI Pin Functions (Pin Mode) Pin Name SDIO CSB SDO Pin Mode Function DATA (Register 0x02, Bit 7), bit value (1/0) equals pin state (high/low). Enable mix mode. If CSB is high, Register 0x0A is set to 0x05, putting both DAC1 and DAC2 into mix mode. Enable full power-down. If SDO is high, Register 0x03 is set to 0xFF. Rev. A | Page 23 of 36 AD9780/AD9781/AD9783 PARALLEL DATA PORT INTERFACE The parallel port data interface consists of up to 18 differential LVDS signals, DCO, DCI, and up to 16 data lines (D[15:0]), as shown in Figure 56. DCO is the output clock generated by the AD9780/AD9781/AD9783 that is used to clock out the data from the digital data engine. The data lines transmit the multiplexed I and Q data words for the I and Q DACs, respectively. DCI provides timing information about the parallel data and signals the I/Q status of the data. As diagrammed in Figure 56, the incoming LVDS data is latched by an internally generated clock referred to as the data sampling signal (DSS). DSS is a delayed version of the main DAC clock signal, CLKP/CLKN. Optimal positioning of the rising and falling edges of DSS with respect to the incoming data signals results in the most robust transmission of the DAC data. Positioning the edges of DSS with respect to the data signals is achieved by selecting the value of a programmable delay element, SMP. A procedure for determining the optimal value of SMP is given in the Optimizing the Parallel Port Timing section. In addition to properly positioning the DSS edges, maximizing the opening of the eye in the clock input (DCIP/DCIN) and data signals improves the reliability of the data port interface. The two sources of degradation that reduce the eye in the clock input and data signals are the jitter on these signals and the skew between them. Therefore, it is recommended that the clock input signals be generated in the same manner as the data signals with the same output driver and data line routing. In other words, it should be implemented as a 17th data line with an alternating (010101 …) bit sequence. D15:D0 FF FF RETIMING AND DEMUX I DAC OPTIMIZING THE PARALLEL PORT TIMING Before outlining the procedure for determining the delay for SMP (that is, the positioning of DSS with respect to the data signals), it is worthwhile to describe the simplified block diagram of the digital data port. As can be seen in Figure 57, the data signals are sampled on the rising and falling edges of DSS. From there, the data is demultiplexed and retimed before being sent to the DACs. The clock input signal provides timing information about the parallel data, as well as indicating the destination (that is, I DAC or Q DAC) of the data. A delayed version of DCI is generated by a delay element, SET, and is referred to as DDCI. DDCI is sampled by a delayed version of the DSS signal, labeled as DDSS in Figure 56. DDSS is simply DSS delayed by a period of time, HLD. The pair of delays, SET and HLD, allows accurate timing information to be extracted from the clock input. Increasing the delay of the HLD block results in the clock input being sampled later in its cycle. Increasing the delay of the SET block results in the clock input being sampled earlier in its cycle. The result of this sampling is stored and can be queried by reading the SEEK bit. Because DSS and the clock input signal are the same frequency, the SEEK bit should be a constant value. By varying the SET and HLD delay blocks and seeing the effect on the SEEK bit, the setup-and-hold timing of DSS with respect to clock input (and, hence, data) can be measured. DATA DCIP/DCIN I0 Q0 I1 Q1 I2 Q2 tHLD0 tHLD0 06936-072 DSS SAMPLE 1 SAMPLE 2 SAMPLE 3 SAMPLE 4 SAMPLE 5 SAMPLE 6 Q DAC Figure 57. Timing Diagram of Parallel Interface DCIP/DCIN SET_DLY HLD_DLY DDCI FF DDSS SMP_DLY CLK CLOCK DISTRIBUTION SEEK DSS DCOP/DCON 06936-071 The incremental units of SET, HLD, and SMP are in units of real time, not fractions of a clock cycle. The nominal step size for SET and HLD is 80 ps. The nominal step size for SMP is 160 ps. Note that the value of SMP refers to Register 0x05, Bits[4:0], SET refers to Register 0x04, Bits[7:4], and HLD refers to Register 0x04, Bits[3:0]. A procedure for configuring the device to ensure valid sampling of the data signals follows. Generally speaking, the procedure begins by building an array of setup-and-hold values as the sample delay is swept through a range of values. Based on this information, a value of SMP is programmed to establish an optimal sampling point. This new sampling point is then double-checked to verify that it is optimally set. Figure 56. Digital Data Port Block Diagram Rev. A | Page 24 of 36 AD9780/AD9781/AD9783 Building the Array The following procedure is used to build the array: 1. 2. Set the values of SMP, SET, and HLD to 0. Read and record the value of the SEEK bit. With SMP and SET set to 0, increment the HLD value until the SEEK bit toggles, and then record the HLD value. This measures the hold time as shown in Figure 57. With SMP and HLD set to 0, increment the SET value until the SEEK bit toggles, and then record the SET value. This measures the setup time as shown in Figure 57. Set the value of SET and HLD to 0. Increment the value of SMP and record the value of the SEEK bit. Increment HLD until the SEEK bit toggles, and then record the HLD value. Set HLD to 0 and increment SET until the SEEK bit toggles, and then record the SET value. Repeat Step 4 and Step 5 until the procedure has been completed for SMP values from 0 to 31. Table 14 shows example arrays taken at DAC sample rates of 200 MHz, 400 MHz, and 600 MHz. It should be noted that the delay from the DCO input to the DCI output of the data source has a profound effect on when the SEEK bit toggles over the range of SMP values. Therefore, the tables generated in any particular system do not necessarily match the example timing data arrays in Table 14. As may be seen in Table 14, at 600 MHz the device has only two working SMP settings. There is no way to monitor timing margin in real time, so the output must be interrupted to check or correct timing errors. The device should therefore not be clocked above 500 MHz in applications where 100% up time is a requirement. 3. 4. 5. Determining the SMP Value Once the timing data array has been built, the value of SMP can be determined using the following procedure: 1. Look for the SMP value that corresponds to the 0-to-1 transition of the SEEK bit in the table. In the 600 MHz case from Table 14, this occurs for an SMP value of 6. Look for the SMP value that corresponds to the 1-to-0 transition of the SEEK bit in the table. In the 600 MHz case from Table 14, this occurs for an SMP value of 11. The same two values found in Step 1 and Step 2 indicate the valid sampling window. In the 500 MHz case, this occurs for an SMP value of 11. The optimal SMP value in the valid sampling window is where the following two conditions are true: SET < HLD and |HLD − SET| is the smallest value. In the 600 MHz case, the optimal SMP value is 7. After programming the calculated value of SMP (referred to as SMPOPTIMAL), the configuration should be tested to verify that there is sufficient timing margin. This can be accomplished by ensuring that the SEEK bit reads back as a 1 for SMP values equal to SMPOPTIMAL + 1 and SMPOPTIMAL − 1. Also, it should be noted that the sum of SET and HLD should be a minimum of 8. If the sum is lower than this, you should check for excessive jitter on the clock input line and check that the frequency of the clock input does not exceed the data sheet maximum of 500 MHz (or 1000 Mbps). As mentioned previously, low jitter and skew between the input data bits and DCI are critical for reliable operation at the maximum input data rates. Figure 58 shows the eye diagram for the input data signals that were used to collect the data in Table 14. 6. Note that while building the table, a value for either SET or HLD may not be found to make the SEEK bit toggle. In this case, assume a value of 15. Table 14. Timing Data Arrays fDACCLK = 200 MHz SMP SEEK SET HLD 2. fDACCLK = 400 MHz SEEK SET HLD fDACCLK = 600 MHz SEEK SET HLD 3. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 6 8 10 12 15 15 15 15 15 15 15 15 15 1 4 6 8 10 12 13 15 15 15 15 15 15 15 15 1 1 1 1 15 15 15 15 15 13 11 9 7 5 3 1 0 15 15 15 15 15 15 15 13 11 9 7 5 3 1 0 15 15 15 15 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 4 6 8 10 12 14 1 3 4 6 8 10 12 0 2 4 6 7 9 11 13 15 2 4 6 8 9 11 11 11 11 13 11 9 7 4 2 1 13 11 9 7 5 3 1 15 13 11 9 7 5 3 1 0 11 9 7 5 3 2 2 2 2 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 2 3 5 8 10 1 2 4 7 9 1 2 4 6 9 11 1 3 5 7 9 1 2 4 7 9 10 1 1 1 1 11 9 7 5 2 1 9 7 4 2 1 10 8 7 4 2 0 8 7 5 2 1 10 8 6 4 2 0 8 8 8 8 4. Rev. A | Page 25 of 36 AD9780/AD9781/AD9783 coupled, as described in this section. Alternatively, it can be transformer-coupled and clamped, as shown in Figure 60. TTL OR CMOS CLK INPUT 0.1µF 50Ω CLKP 1 V1: 296mV V2: –228mV ΔV: –524mV VCM = 400mV Figure 60. TTL or CMOS DAC CLK Drive Circuit 06936-076 CH1 100mV 125ps/DIV 2.12ns 20GSPS IT 2.5ps/PT A CH1 58mV Figure 58. Eye Diagram of Data Source Used in Building the 600 MHz Timing Data Array of Table 14 A simple bias network for generating the 400 mV commonmode voltage is shown in Figure 61. It is important to use CVDD18 and CGND for the clock bias circuit. Any noise or other signal coupled onto the clock is multiplied by the DAC digital input signal and can degrade the DAC’s performance. VCM = 400mV CVDD18 1kΩ 287Ω 0.1µF 1nF CGND 06936-058 Over temperature, the valid sampling window shifts. Therefore, when attempting operation of the device over 500 MHz, the timing must be optimized again whenever the device undergoes a temperature change of more than 20oC. Another consideration in the timing of the digital data port is the propagation delay variation from the clock output (DCOP/DCON) to the clock input. If this varies significantly over time (more than 25% of SET or HLD) due to temperature changes or other effects, repeat this timing calibration procedure. At sample rates of ≤400 MSPS, the interface timing margin is sufficient to allow for a simplified procedure. In this case, the SEEK bit can be recorded as SMP is swept through the range from 0 to 31. The center of the first valid sampling window can then be chosen as the optimal value of SMP. Using the 400 MHz case from Table 14 as an example, the first valid sampling window occurs for SMP values of 7 to 13. The center of this window is 10, so 10 can be used as the optimal SMP value. 1nF Figure 61. DAC CLK VCM Generator Circuit FULL-SCALE CURRENT GENERATION Internal Reference Full-scale current on the I DAC and Q DAC can be set from 8.66 mA to 31.66 mA. Initially, the 1.2 V band gap reference is used to set up a current in an external resistor connected to FS ADJ (Pin 54). A simplified block diagram of the reference circuitry is shown in Figure 62. The recommended value for the external resistor is 10 kΩ, which sets up an IREFERENCE in the resistor of 120 μA, which in turn provides a DAC output fullscale current of 20 mA. Because the gain error is a linear function of this resistor, a high precision resistor improves gain matching to the internal matching specification of the devices. Internal current mirrors provide a current-gain scaling, where I DAC or Q DAC gain is a 10-bit word in the SPI port register. The default value for the DAC gain registers gives a full-scale current output (IFS) of approximately 20 mA, where IFS is equal to IFS = (86.6 + (0.220 × DAC gain)) × 1000/R DRIVING THE CLK INPUT The CLK input requires a low jitter differential drive signal. It is a PMOS input differential pair powered from the 1.8 V supply; therefore, it is important to maintain the specified 400 mV input common-mode voltage. Each input pin can safely swing from 200 mV p-p to 1 V p-p about the 400 mV common-mode voltage. While these input levels are not directly LVDS-compatible, CLK can be driven by an offset ac-coupled LVDS signal, as shown in Figure 59. 0.1µF LVDS_P_IN 50Ω VCM = 400mV 50Ω 06936-056 AD9783 CLKP REFIO 0.1µF FS ADJ 10kΩ CURRENT SCALING DAC FULL-SCALE REFERENCE CURRENT 06936-059 1.2V BAND GAP I DAC GAIN I DAC LVDS_N_IN 0.1µF CLKN Q DAC GAIN Q DAC Figure 59. LVDS DAC CLK Drive Circuit Figure 62. Reference Circuitry If a clean sine clock is available, it can be transformer-coupled to CLKP and CLKN as shown in Figure 60. Use of a CMOS or TTL clock is also acceptable for lower sample rates. It can be routed through a CMOS-to-LVDS translator, and then acRev. A | Page 26 of 36 06936-057 CLKN 50Ω BAV99ZXCT HIGH SPEED DUAL DIODE AD9780/AD9781/AD9783 35 ANALOG MODES OF OPERATION The AD9780/AD9781/AD9783 use a proprietary quad-switch architecture that lowers the distortion of the DAC by eliminating a code-dependent glitch that occurs with conventional dual-switch architectures. This architecture eliminates the code-dependent glitches, but creates a constant glitch at a rate of 2 × fDAC. For communications systems and other applications requiring good frequency domain performance from the DAC, this is seldom problematic. The quad-switch architecture also supports two additional modes of operation: mix mode and return-to-zero mode. The waveforms of these two modes are shown in Figure 64. In mix mode, the output is inverted every other half clock cycle. This effectively chops the DAC output at the sample rate. This chopping has the effect of frequency shifting the sinc roll-off from dc to fDAC. Additionally, there is a second subtle effect on the output spectrum. The shifted spectrum is also shaped by a second sinc function with a first null at 2 × fDAC. The reason for this shaping is that the data is not continuously varying at twice the clock rate, but is simply repeated. In return-to-zero mode, the output is set to midscale every other half clock cycle. The output is similar to the DAC output in normal mode except that the output pulses are half the width and half the area. Because the output pulses have half the width, the sinc function is scaled in frequency by two and has a first null at 2 × fDAC. Because the area of the pulses is half that of the pulses in normal mode, the output power is half the normal mode output power. INPUT DATA DAC CLK D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 30 25 IFS (mA) 20 15 10 0 256 512 DAC GAIN CODE 768 1024 Figure 63. IFS vs. DAC Gain Code DAC TRANSFER FUNCTION Each DAC output of the AD9780/AD9781/AD9783 drives two complementary current outputs, IOUTP and IOUTN. IOUTP provides a near IFS when all bits are high. For example, DAC CODE = 2N − 1 where N = 12/14/16 bits for AD9780/AD9781/AD9783 (respectively), while IOUTN provides no current. The current output appearing at IOUTP and IOUTN is a function of both the input code, and IFS and can be expressed as IOUTP = (DAC DATA/2N) × IFS IOUTN = ((2N − 1) − DAC DATA)/2N × IFS where DAC DATA = 0 to 2 − 1 (decimal representation). The two current outputs typically drive a resistive load directly or via a transformer. If dc coupling is required, IOUTP and IOUTN should be connected to matching resistive loads (RLOAD) that are tied to analog common (AVSS). The single-ended voltage output appearing at the IOUTP and IOUTN pins is VOUTP = IOUTP × RLOAD VOUTN = IOUTN × RLOAD (3) (4) N 06936-060 5 (1) (2) QUAD-SWITCH DAC OUTPUT (fS MIX MODE) t Note that to achieve the maximum output compliance of 1 V at the nominal 20 mA output current, RLOAD must be set to 50 Ω. Also note that the full-scale value of VOUTP and VOUTN should not exceed the specified output compliance range to maintain specified distortion and linearity performance. There are two distinct advantages to operating the AD9780/ AD9781/AD9783 differentially. First, differential operation helps cancel common-mode error sources associated with IOUTP and IOUTN, such as noise, distortion, and dc offsets. Second, the differential code-dependent current and subsequent output voltage (VDIFF) is twice the value of the single-ended voltage output (VOUTP or VOUTN), providing 2× signal power to the load. VDIFF = (IOUTP – IOUTN) × RLOAD (5) Figure 64. Mix Mode and Return-to-Zero Mode DAC Waveforms The functions that shape the output spectrums for the three modes of operation, normal mode, mix mode, and return-tozero mode, are shown in Figure 65. Switching between the analog modes reshapes the sinc roll-off inherent at the DAC output. This ability to change modes in the AD9780/AD9781/ AD9783 makes the parts suitable for direct IF applications. The user can place a carrier anywhere in the first three Nyquist zones depending on the operating mode selected. The performance and maximum amplitude in all three Nyquist zones is Rev. A | Page 27 of 36 06936-061 QUAD-SWITCH DAC OUTPUT (RETURN-TOZERO MODE) t AD9780/AD9781/AD9783 impacted by this sinc roll-off depending on where the carrier is placed, as shown in Figure 65. 0 MIX RETURN-TO-ZERO 0mA TO 2mA SINK OR SOURCE POSITIVE OR NEGATIVE 0mA TO 2mA VBIAS AUXP AUXN 06936-063 –10 Figure 66. Auxiliary DAC Functional Diagram T(f) (dB) NORMAL –20 –30 0 0.5 1.0 (fS) 1.5 2.0 Figure 65. Transfer Function for Each Analog Operating Mode Auxiliary DACs Two auxiliary DACs are provided on the AD9780/AD9781/ AD9783. A functional diagram is shown in Figure 66. The auxiliary DACs are current output devices with two output pins, AUXP and AUXN. The active pin can be programmed to either source or sink current. When either sinking or sourcing, the full-scale current magnitude is 2 mA. The available compliance range at the auxiliary DAC outputs depends on whether the output is configured to sink or source current. When sourcing current, the compliance voltage is 0 V to 1.6 V, but when sinking current, the output compliance voltage is reduced to 0.8 V to 1.6 V. Either output can be used, but only one output of the AUX DAC (P or N) is active at any time. The inactive pin is always in a high impedance state (>100 kΩ). QUADRATURE MODULATOR V+ 06936-062 –40 In a single sideband transmitter application, the combination of the input referred dc offset voltage of the quadrature modulator and the DAC output offset voltage can result in local oscillator (LO) feedthrough at the modulator output, which degrades system performance. The auxiliary DACs can be used to remove the dc offset and the resulting LO feedthrough. The circuit configuration for using the auxiliary DACs for performing dc offset correction depends on the details of the DAC and modulator interface. An example of a dc-coupled configuration with lowpass filtering is shown in Figure 67. AD9783 AUX DAC1 OR DAC2 QUAD MOD I OR Q INPUTS AD9783 DAC1 OR DAC2 OPTIONAL PASSIVE FILTERING 06936-064 25Ω TO 50Ω 25Ω TO 50Ω Figure 67. DAC DC-Coupled to Quadrature Modulator with a Passive DC Shift Rev. A | Page 28 of 36 AD9780/AD9781/AD9783 POWER DISSIPATION Figure 68 through Figure 73 show the power dissipation of the part in single DAC and dual DAC modes. 0.50 0.45 0.40 0.35 POWER (W) 0.50 0.45 0.40 0.35 POWER (W) 0.30 0.25 0.20 0.15 0.10 0.05 0 100 200 300 400 500 06936-065 0.30 0.25 0.20 0.15 0.10 0.05 0 0 100 200 300 400 500 CLOCK SPEED (MSPS) CLOCK SPEED (MSPS) Figure 68. Power Dissipation, I Data Only, Single DAC Mode 0.200 0.175 0.150 0.125 0.100 0.075 DVDD18 0.050 CVDD 0.025 06936-066 Figure 71. Power Dissipation, I and Q Data, Dual DAC Mode 0.200 0.175 0.150 0.125 0.100 DVDD18 0.075 0.050 0.025 06936-069 06936-070 POWER (W) POWER (W) CVDD 0 0 100 200 300 400 500 0 0 100 200 300 400 500 CLOCK SPEED (MSPS) CLOCK SPEED (MSPS) Figure 69. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply, I Data Only 0.200 0.175 0.150 0.125 AVDD33 0.100 0.075 0.050 0.025 06936-067 Figure 72. Power Dissipation, Digital 1.8 V Supply, Clock 1.8 V Supply, I and Q Data, Dual DAC Mode 0.200 0.175 0.150 0.125 0.100 0.075 0.050 0.025 0 DVDD33 AVDD33 POWER (W) DVDD33 0 0 100 200 300 400 500 POWER (W) 0 100 200 300 400 500 CLOCK SPEED (MSPS) CLOCK SPEED (MSPS) Figure 70. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply, I Data Only Figure 73. Power Dissipation, Digital 3.3 V Supply, Analog 3.3 V Supply, I and Q Data, Dual DAC Mode Rev. A | Page 29 of 36 06936-068 0 TP7 BLACK J7 J587 5VIN B1 TP8 BLACK J8 J587 J587 CCASE C66 100UF 10V B2 L1 J1 L1812 J587 VR4 ADP3333ARM-1.8 CCASE 10UF C36 0.1UF J587 TP1 RED CVDD18 C15 C37 0.1UF AD9780/AD9781/AD9783 C21 100UF 10V EXC-CL4532U1 5VIN 2IN SD GND R30 R0805 DNP 1 OUT 7 3 EVALUATION BOARD SCHEMATICS C49 0.1UF L2 J2 L1812 J587 VR5 ADP3333ARM-1.8 CCASE C38 0.1UF TP2 RED DVDD18 C16 10UF C42 0.1UF 5VIN 2 IN SD GND OUT R29 R0805 DNP C22 100UF 10V EXC-CL4532U1 1 C50 0.1UF 7 3 L3 J3 J587 VR1 ADP3333ARM-3.3 CCASE C39 0.1UF L1812 TP3 RED DVDD33 C17 10UF C43 0.1UF 06936-077 Figure 74. Power Distribution EXC-CL4532U1 Rev. A | Page 30 of 36 R18 R0805 5VIN 2 IN SD GND OUT DNP C23 100UF 10V 1 C46 0.1UF 7 3 L4 J4 J587 CCASE VR2 ADP3333ARM-3.3 C40 0.1UF L1812 TP4 RED AVDD33 EXC-CL4532U1 C18 C44 0.1UF C24 100UF 10V 10UF 5VIN 2 IN SD GND OUT R19 R0805 DNP 1 C47 0.1UF 7 3 L6 J6 J587 CCASE VR3 ADP3333ARM-3.3 C41 0.1UF L1812 TP6 RED DVCC33 EXC-CL4532U1 C26 100UF 10V C19 10UF C45 0.1UF 5VIN 2 IN SD GND OUT R28 DNP R0805 1 C48 0.1UF 7 3 DVDD33 SW1 SPI_CSB 2 74HC14 74HC14 3 10 74HC14 5 8 74HC14 1 U8 2 3 74HC125 R17 10K R0805 1 SW2 U9 11 U9 R12 7.5K 3 2 12 13 U9 1 R0805 U9 R11 7.5K SPI_CLK 2 74HC14 6 9 74HC14 DVDD33 1 SW3 U9 U9 3 4 R0805 P1 R13 7.5K R0805 1 2 3 4 5 6 L7 10UH L1210 SPI_SDI 2 SW4 3 2 1 3 SPI_SDO 1 U1 1 U8 11 12 13 3 2 74HC125 U8 8 U1 R0805 R0805 10 9 74HC125 6 R26 10K 74HC125 4 U8 5 R0805 R0805 R0805 DVDD33 C9 0.1UF C0402 DVDD33 C10 0.1UF C0402 06936-078 Figure 75. SPI Interface Rev. A | Page 31 of 36 SW5 1 2 5 R27 10K 3 6 4 DVDD33 DVDD33 2 RST GND VCC MR RESET R14 20K R15 20K R16 20K A1 3 2 1 SW6 4 3 14 U1 7 1 4 AD9780/AD9781/AD9783 C0402 C51 0.1UF DVDD33 DVDD33 DVDD18 CVDD18 CVDD18 AVDD33 C53 C63 C28 C56 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C25 AVDD33 C29 10UF C52 C60 C59 1000PF 100PF 100PF 0.1UF 0.1UF C57 C58 C7 C8 1000PF 1000PF 100PF 100PF 0.1UF 0.1UF 10UF C62 C61 C0402 C0402 10UF C3 0.1UF 1000PF C1 C2 C0402 1000PF DVDD33 C64 C4 C0402 C0402 100PF C65 100PF 0.1UF DVDD18 CVDD18 C0402 1000PF AD9780/AD9781/AD9783 CLKP CLKN DVSS D13P D13N D12P D12N D11P D11N D10P D10N D9P D9N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ADTL1-12 R0402 U7 R0402 3 ADT2-1T-1P 2 3 2 S4 P 1 4 5 2:1 1 CVDD18 CVSS CLKP CLKN CVSS CVDD18 DVSS DVDD18 D13P D13N D12P D12N D11P D11N D10P D10N D9P D9N AVDD33 R1 49.9-0.5% 4 5 R2 49.9-0.5% S T2 T3 5 P 4 TC1-1-13M AUX1P AUX1N ADTL1-12 3 4 5 S P 1 1 2 3 T5 T6 5 1 2 S 3 4 2:1 TC2-1T DVDD33 D8P D8N D7P D7N D6P D6N DCOP DCON ADT2-1T-1P 2 3 4 5 2:1 1 2 R0402 R0402 06936-079 Figure 76. Main Schematic Rev. A | Page 32 of 36 DCIP DCIN AUX2N AUX2P R3 49.9-0.5% R4 49.9-0.5% D5P D5N D4P D4N D3P D3N DVSS S7 T7 T8 5 P 4 TC1-1-13M 1 2 S 3 1 2 3 2:1 4 T10 T11 5 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 D8P D8N D7P D7N D6P D6N DCOP DCON DVDD33 DVSS IDCIP DCIN D5P D5N D4P D4N D3P D3N AVDD33 AVDD33 AVSS IOUT1P IOUT1N AVSS AUX1P AUX1N AVSS AUX2N AUX2P AVSS IOUT2N IOUT2P AVSS AVDD33 AVDD33 REFIO 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 TC2-1T FS ADJ RESET CSB SCLK SDIO SDO DVSS DVDD18 NC NC NC NC D0N D0P D1N DIP D2N D2P R5 R0603 S8 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 DVSS SDO SDIO SCLK CSB RESET D2P D2N D1P D1N D0P D0N NC NC NC NC DVDD18 10K-0.1% C0402 C6 0.1UF C27 4.7UF 16V DVDD18 DVDD18 C20 C0402 C0402 C55 C0402 C54 100PF 1000PF C5 0.1UF 10UF 06936-080 Figure 77. Data Input Detail Rev. A | Page 33 of 36 D12_N D13_N D14_N D15_N AD9780/AD9781/AD9783 D15_P D14_P D13_P D12_P D06_P D07_P D00_P D01_P D02_P D03_P D04_P D05_P DCLKI_P DCLKO_P D08_P D09_P D10_P D11_P G1 S1 G3 S3 G5 S5 G7 S7 G9 S9 G11 S11 G13 S13 G15 S15 G17 S17 G19 S19 G21 S21 G23 S23 G25 S25 G27 S27 G29 S29 G31 S31 G33 S33 G35 S35 G37 S37 G39 S39 G41 S41 G43 S43 G45 S45 G47 S47 G49 Jack G2 S2 G4 S4 G6 S6 G8 S8 G10 S10 G12 S12 G14 S14 G16 S16 G18 S18 G20 S20 G22 S22 G24 S24 G26 S26 G28 S28 G30 S30 G32 S32 G34 S34 G36 S36 G38 S38 G40 S40 G42 S42 G44 S44 G46 S46 G48 S48 G50 Jack FCN-268 F024-G/0 D J9 L9 L1210 L1210 L8 10UH 10UH D05_N D04_N D03_N D02_N D01_N D00_N D07_N D06_N D11_N D10_N D09_N D08_N DCLKO_N DCLKI_N AD9780/AD9781/AD9783 CVDD18 R0402 C13 0.1UF C11 DNP R0402 C0402 R6 1K C0402 TC1-1-13M 4 P 5 T1 C0402 R0402 R0402 R10 25 AUX1_P CLK_N CLK_P R8 25 AUX2_P S9 AUX1_N S10 3 S 2 1 S1 S12 AUX2_N 06936-081 Figure 78. AUX DAC and Clock Input Circuit Details R0402 Rev. A | Page 34 of 36 R9 VAL R7 300 C0402 S11 C12 0.1UF C14 0.1UF AD9780/AD9781/AD9783 OUTLINE DIMENSIONS 10.00 BSC SQ 0.60 0.42 0.24 0.60 0.42 0.24 55 54 72 1 PIN 1 INDICATOR TOP VIEW 9.75 BSC SQ 0.50 BSC PIN 1 INDICATOR (BOTTOM VIEW) EXPOSED PAD 4.70 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF 37 36 18 19 8.50 REF EXPOSED PAD MUST BE SOLDERED TO PCB AND CONNECTED TO AVSS. COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 Figure 79. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm × 10 mm, Very Thin Quad (CP-72-1) Dimensions shown in millimeters ORDERING GUIDE Model AD9780BCPZ 1 AD9780BCPZRL1 AD9781BCPZ1 AD9781BCPZRL1 AD9783BCPZ1 AD9783BCPZRL1 AD9780-EBZ1 AD9781-EBZ1 AD9783-EBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ 72-Lead LFCSP_VQ Evaluation Board Evaluation Board Evaluation Board Package Option CP-72-1 CP-72-1 CP-72-1 CP-72-1 CP-72-1 CP-72-1 Z = RoHS Compliant Part. Rev. A | Page 35 of 36 111507-A 0.30 0.23 0.18 AD9780/AD9781/AD9783 NOTES ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06936-0-6/08(A) Rev. A | Page 36 of 36