AD9992

12-Bit CCD Signal Processor with Precision Timing Generator AD9992 FEATURES 1.8 V AFETG core Internal LDO regulator and charge pump circuitry Compatibility with 3 V or 1.8 V systems 24 programmable vertical clock outputs Correlated double sampler (CDS) with −3 dB, 0 dB, +3 dB, and +6 dB gain 6 dB to 42 dB, 10-bit variable gain amplifier (VGA) 12-bit, 40 MHz ADC Black level clamp with variable level control Complete on-chip timing generator Precision Timing core with 400 ps resolution On-chip 3 V horizontal and RG drivers General-purpose outputs (GPOs) for shutter and system support On-chip driver for external crystal On-chip sync generator with external sync input 105-lead CSP_BGA package, 8 mm × 8 mm, 0.65 mm pitch GENERAL DESCRIPTION The AD9992 is a highly integrated CCD signal processor for digital still camera applications. It includes a complete analog front end with analog to digital conversion combined with a full-function programmable timing generator. The timing generator is capable of supporting up to 24 vertical clock signals to control advanced CCDs. A Precision Timing™ core allows adjustment of high speed clocks with approximately 400 ps resolution at 40 MHz operation. The AD9992 also contains eight general-purpose inputs/outputs that can be used for shutter and system functions. The AD9992 is specified at pixel rates of up to 40 MHz. The analog front end includes black level clamping, CDS, VGA, and a 12-bit analog-to-digital converter (ADC). The timing generator provides all the necessary CCD clocks: RG, H-clocks, V-clocks, sensor gate pulses, substrate clock, and substrate bias control. Operation is programmed using a 3-wire serial interface. The AD9992 is specified over an operating temperature range of −25°C to +85°C. APPLICATIONS Digital still cameras FUNCTIONAL BLOCK DIAGRAM REFT REFB AD9992 6dB TO 42dB CCDIN CDS –3dB, 0dB, +3dB, +6dB 3V INPUT 1.8V OUTPUT 1.8V INPUT 3V OUTPUT RG HL 8 H1 TO H8 24 XV1 TO XV24 XSUBCK VERTICAL TIMING CONTROL 8 05891-001 VREF 12-BIT ADC 12 DOUT VGA CLAMP LDO REG CHARGE PUMP INTERNAL CLOCKS HORIZONTAL DRIVERS PRECISION TIMING GENERATOR SL INTERNAL REGISTERS SCK SDATA SYNC GENERATOR GPO1 TO GPO8 HD VD SYNC CLI CLO Figure 1. Rev. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2007 Analog Devices, Inc. All rights reserved. AD9992 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Digital Specifications ................................................................... 4 Analog Specifications................................................................... 5 Timing Specifications .................................................................. 6 Absolute Maximum Ratings............................................................ 7 Thermal Resistance ...................................................................... 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 11 Equivalent Circuits ......................................................................... 12 Terminology .................................................................................... 13 System Overview ............................................................................ 14 High Speed Precision Timing Core........................................... 15 Horizontal Clamping and Blanking......................................... 19 Horizontal Timing Sequence Example.................................... 25 Vertical Timing Generation ...................................................... 26 Vertical Sequences (VSEQ) ....................................................... 29 Vertical Timing Example........................................................... 45 Shutter Timing Control ............................................................. 47 Substrate Clock Operation (SUBCK) ...................................... 47 Field Counters............................................................................. 50 General-Purpose Outputs (GPOs) .......................................... 51 GP Look-Up Tables (LUT)........................................................ 55 Complete Exposure/Readout Operation Using Primary Counter and GPO Signals ......................................................... 56 Manual Shutter Operation Using Enhanced SYNC Modes.. 58 Analog Front End Description and Operation ...................... 62 Power-Up Sequence for Master Mode..................................... 64 Standby Mode Operation .......................................................... 67 CLI Frequency Change.............................................................. 67 Circuit Layout Information........................................................... 69 Typical 3 V System ..................................................................... 69 Typical 1.8 V System .................................................................. 69 External Crystal Application .................................................... 69 Serial Interface Timing .............................................................. 72 Layout of Internal Registers ...................................................... 73 Updating New Register Values ................................................. 74 Complete Register Listing ............................................................. 75 Outline Dimensions ....................................................................... 92 Ordering Guide .......................................................................... 92 REVISION HISTORY 10/07—Rev. B to Rev. C Changes to Vertical Timing Generation Section........................ 26 Changes to Vertical Sequences (VSEQ) Section......................... 29 Changes to Vertical Timing Example Section ............................ 45 Changes to Power-Up Sequence for Master Mode Section ...... 64 Changes to Figure 80...................................................................... 70 Changes to Figure 81...................................................................... 71 9/07—Rev. A to Rev. B Added Figure 2.................................................................................. 4 Deleted Endnote in Table 3 ............................................................. 5 Added Address 0x17 Bit 17 Information to Table 30................. 75 7/07—Rev. 0 to Rev. A Changes to Table 3 and Related Endnote.......................................5 Added Slave Mode and SHP/SHD Information to Table 4..........6 Changes to Table 5.............................................................................7 Changes to Table 7.............................................................................8 Changes to Figure 18...................................................................... 17 Changes to Figure 75...................................................................... 66 Changes to Figure 81...................................................................... 71 1/06—Revision 0: Initial Version Rev. C | Page 2 of 92 AD9992 SPECIFICATIONS Table 1. Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE INPUTS AVDD (AFE Analog Supply) TCVDD (Timing Core Supply) CLIVDD (CLI Input Supply) RGVDD (RG, HL Driver) HVDD1/HVDD2 (H1 to H8 Drivers) 1 DVDD (Digital Logic) DRVDD (Parallel Data Output Drivers) IOVDD (Digital I/O) XVVDD (Vertical Output Drivers) CP1P8 (CP Supply Input) LDOIN (LDO Supply Input) POWER SUPPLY CURRENTS—40 MHz OPERATION AVDD (1.8 V) TCVDD (1.8 V) CLIVDD (3 V) RGVDD (3.3 V, 20 pF RG Load, 20 pF HL Load) HVDD1/HVDD2 (3.3 V, 480 pF Total Load on H1 to H8)1 DVDD (1.8 V) DRVDD (3 V, 10 pF Load on Each DOUT Pin) IOVDD (3 V, Depends on Load and Output Frequency of Digital I/O) XVVDD (3 V, Depends on Load and Output Frequency of XV Signals) POWER SUPPLY CURRENTS—STANDBY MODE OPERATION Standby1 Mode Standby2 Mode Standby3 Mode MAXIMUM CLOCK RATE (CLI) 1 Min −25 −65 1.6 1.6 1.6 2.7 2.7 1.6 1.6 1.6 1.6 1.6 2.25 Typ Max +85 +150 Unit °C °C V V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz 1.8 1.8 3.0 3.0 3.0 1.8 3.0 3.0 3.0 1.8 3.0 27 5 1.5 10 59 9.5 6 2 2 12 5 1.5 2.0 2.0 3.6 3.6 3.6 2.0 3.6 3.6 3.6 2.0 3.6 40 The total power dissipated by the HVDD (or RGVDD) supply can be approximated using the equation Total HVDD Power = [CL × HVDD × Pixel Frequency] × HVDD Reducing the capacitive load and/or reducing the HVDD supply reduces the power dissipation. CL is the total capacitance seen by all H-outputs. Rev. C | Page 3 of 92 AD9992 DIGITAL SPECIFICATIONS IOVDD = 1.6 V to 3.6 V, RGVDD = HVDD = 2.7 V to 3.6 V, CL = 20 pF, TMIN to TMAX, unless otherwise noted. Table 2. Parameter LOGIC INPUTS (IOVDD) High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance LOGIC OUTPUTS (IOVDD, XVDD) High Level Output Voltage @ IOH = 2 mA Low Level Output Voltage @ IOL = 2 mA RG and H-DRIVER OUTPUTS (HVDD, RGVDD) High Level Output Voltage @ Maximum Current Low Level Output Voltage @ Maximum Current Maximum Output Current (Programmable) Maximum Load Capacitance (for Each Output) Symbol VIH VIL IIH IIL CIN VOH VOL VOH VOL Min VDD − 0.6 0.6 10 10 10 VDD − 0.5 0.5 VDD − 0.5 0.5 18 60 Typ Max Unit V V μA μA pF V V V V mA pF 800mV MAXIMUM 500mV TYP RESET TRANSIENT 200mV MAX OPTICAL BLACK PIXEL MAXIMUM INPUT LIMIT = LESSER OF 2.2V or AVDD + 0.2V +1.8V TYP (AVDD) +1.3V TYP (AVDD – 0.5V) DC RESTORE VOLTAGE 1V MAXIMUM INPUT SIGNAL RANGE (0dB CDS GAIN) 05891-091 0V (AVSS) MINIMUM INPUT LIMIT (AVSS – 0.2V) Figure 2. Input Signal Characteristics (See Allowable OB Pixel Amplitude in Table 3) Rev. C | Page 4 of 92 AD9992 ANALOG SPECIFICATIONS AVDD = 1.8 V, fCLI = 40 MHz, typical timing specifications, TMIN to TMAX, unless otherwise noted. Table 3. Parameter CDS Allowable CCD Reset Transient CDS Gain Accuracy −3.0 dB CDS Gain 0 dB CDS Gain +3 dB CDS Gain +6 dB CDS Gain Maximum Input Range Before Saturation −3 dB CDS Gain 0 dB CDS Gain +3 dB CDS Gain +6 dB CDS Gain Allowable OB Pixel Amplitude (See Figure 2) 0 dB CDS Gain (Default) +6 dB CDS Gain VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Low Gain (VGA Code 15, Default) Maximum Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level (Code 0) Maximum Clamp Level (Code 1023) ADC Resolution Differential Nonlinearity (DNL) No Missing Codes Integral Nonlinearity (INL) Full-Scale Input Voltage VOLTAGE REFERENCE Reference Top Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Low Gain (VGA Code 15) Maximum Gain (VGA Code 1023) Peak Nonlinearity, 1.0 V Input Signal Total Output Noise Power Supply Rejection (PSR) Min Typ 0.5 Max 0.8 −2.3 +0.5 3.4 6.0 Unit V dB dB dB dB Test Conditions/Comments The limit is the lower of AVDD + 0.2 V or 2.2 V. VGA gain = 6.3 dB (Code 15, default value). −3.3 −0.5 2.4 5.0 −2.8 0 2.9 5.5 1.4 1.0 0.7 0.5 VGA gain = 6.3 dB (Code 15, default value). V p-p V p-p V p-p V p-p +200 +100 1024 Guaranteed 6.3 42.4 1024 0 255 12 −1.0 mV mV Steps −100 −50 dB dB Steps Measured at ADC output. LSB LSB Bits LSB LSB V V V Includes entire signal chain. 0 dB CDS gain. Gain = (0.0358 × Code) + 5.76 dB. 6 dB VGA gain, 0 dB CDS gain applied. AC-grounded input, 6 dB VGA gain applied. Measured with step change on supply. ±0.5 +1.0 Guaranteed 1 4 2.0 1.4 0.4 5.8 41.9 6.3 42.4 0.1 0.5 50 6.8 42.9 0.2 dB dB % LSB rms dB Rev. C | Page 5 of 92 AD9992 TIMING SPECIFICATIONS CL = 20 pF, AVDD = DVDD = TCVDD = 1.8 V, DRVDD = 3.0 V, fCLI = 40 MHz, unless otherwise noted. Table 4. Parameter MASTER CLOCK (See Figure 15) CLI Clock Period CLI High/Low Pulse Width Delay from CLI Rising Edge to Internal Pixel Position 0 SLAVE MODE SPECIFICATIONS (See Figure 76) VD Falling Edge to HD Falling Edge in Slave Mode HD Edge to CLI Rising Edge (Only Valid if OSC_RSTB = LO) HD Edge to CLO Rising Edge (Only Valid if OSC_RSTB = HI) Inhibit Region for SHP Edge Location AFE CLPOB PULSE WIDTH (See Figure 22 and Figure 32) 1 , 2 AFE SAMPLE LOCATION (See Figure 16 and Figure 19)1 SHP Sample Edge to SHD Sample Edge DATA OUTPUTS (See Figure 20 and Figure 21) Output Delay from DCLK Rising Edge Inhibited Area for DOUTPHASE Edge Location Pipeline Delay from SHP/SHD Sampling to DOUT SERIAL INTERFACE (See Figure 83) Maximum SCK Frequency (Must Not Exceed CLI Frequency) SL to SCK Setup Time SCK to SL Hold Time SDATA Valid to SCK Rising Edge Setup SCK Falling Edge to SDATA Valid Hold INHIBIT REGION FOR SHP AND SHD WITH RESPECT TO H-CLOCK EDGE PLACEMENT (see Figure 19) for H*POL = 1 RETIME = 0, MASK = 0 RETIME = 0, MASK = 1 RETIME = 1, MASK = 0 RETIME = 1, MASK = 1 1 2 Symbol tCONV tCLIDLY tVDHD tHDCLI tHDCLO tSHPINH Min 25 10 Typ Max Unit ns ns ns ns ns ns Edge location Pixels ns ns Edge location Cycles MHz ns ns ns ns 12.5 6 15 0 3 3 48 2 11 VD period − 5 × tCONV tCONV − 2 tCONV − 2 63 20 12.5 1 tS1 tOD tDOUTINH SHDLOC + 1 16 SHDLOC + 15 fSCLK tLS tLH tDS tDH 40 10 10 10 10 tSHDINH tSHDINH tSHPINH tSHPINH H*NEGLOC – 15 H*POSLOC – 15 H*NEGLOC – 15 H*POSLOC – 15 H*NEGLOC – 0 H*POSLOC – 0 H*NEGLOC – 0 H*POSLOC – 0 Edge location Edge location Edge location Edge location Parameter is programmable. Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve good clamp performance. Rev. C | Page 6 of 92 AD9992 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVDD TCVDD HVDD1/HVDD2 RGVDD DVDD DRVDD IOVDD XVVDD CLIVDD CP1P8 RG Output H1 to H8, HL Output Digital Outputs Digital Inputs SCK, SL, SDATA REFT, REFB, CCDIN Junction Temperature Lead Temperature, 10 sec With Respect To AVSS TCVSS HVSS1/HVSS2 RGVSS DVSS DRVSS DVSS DVSS TCVSS CPVSS RGVSS HVSS1/HVSS2 DVSS DVSS DVSS AVSS Rating −0.2 V to +2.2 V −0.2 V to +2.2 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.2 V to +2.2 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.3 V to +3.9 V −0.2 V to +2.2 V −0.3 V to RGVDD + 0.3 V −0.3 V to HVDD + 0.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to IOVDD + 0.3 V −0.2 V to AVDD + 0.2 V 150°C 350°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 6. Thermal Resistance Package Type 106-Lead CSP_BGA θJA 40.3 Unit °C/W ESD CAUTION Rev. C | Page 7 of 92 AD9992 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS A1 CORNER INDEX AREA 1 TOP VIEW (Not to Scale) 2 3 4 5 6 7 8 9 10 11 A B C D E F G H J L 05891-003 AD9992 K Figure 3. Pin Configuration Table 7. Pin Function Descriptions Pin No. A1 B2 C2 B1 B4 C1 D2 C3 D3 E2 D1 E7 E6 E5 E3 E1 F2 F3 F7 G3 F5 F6 G2 F1 G1 G5 H2 H1 G6 G7 J2 J1 L1 L2 Mnemonic GPO8 GPO7 GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 SYNC VD HD RSTB IOVDD IOVSS XVVDD XSUBCK XV1 XV2 XV3 XV4 XV5 XV6 XV7 XV8 XV9 XV10 XV11 XV12 XV13 XV14 XV15 XV16 XV17 XV18 Type 1 DIO DIO DIO DIO DIO DIO DIO DIO DI DIO DIO DI P P P DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO DO Description General-Purpose Output 8 General-Purpose Output 7 General-Purpose Output 6 General-Purpose Output 5 General-Purpose Output 4 General-Purpose Output 3 General-Purpose Output 2 General-Purpose Output 1 External System Sync Input Vertical Sync Pulse (input for slave mode, output for master mode) Horizontal Sync Pulse (input for slave mode, output for master mode) External Reset Input (active low pulse to reset, internal pull-up resistor) Digital I/O Supply: 1.8 V, 3.0 V (GPO, SUBCK, HD/VD, SL, SCK, SDATA, SYNC, RSTB) Digital I/O Ground XV Output Supply: 1.8 V, 3.0 V CCD Substrate Clock CCD Vertical Clock 1 CCD Vertical Clock 2 CCD Vertical Clock 3 CCD Vertical Clock 4 CCD Vertical Clock 5 CCD Vertical Clock 6 CCD Vertical Clock 7 CCD Vertical Clock 8 CCD Vertical Clock 9 CCD Vertical Clock 10 CCD Vertical Clock 11 CCD Vertical Clock 12 CCD Vertical Clock 13 CCD Vertical Clock 14 CCD Vertical Clock 15 CCD Vertical Clock 16 CCD Vertical Clock 17 CCD Vertical Clock 18 Rev. C | Page 8 of 92 AD9992 Pin No. L3 K1 K2 K3 J3 H3 L4 K4 L6 K6 J6 L7 K7 J7 L8 K8 J8 L9 K9 J9 L10 K10 L11 K11 J10 J11 H10 H11 H9 G11 G9 F10 F11 E11 E10 F9 E9 D11 C11 D10 C10 D9 C9 B11 A11 B10 A10 B9 B8 A8 C8 B7 A7 Mnemonic XV19 XV20 XV21 XV22 XV23 XV24 DVDD DVSS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DCLK DRVSS DRVDD CP3P3 CPFCT CPFCB CPVSS CP1P8 CPCLI LDO3P2EN LDOVSS LDO1P8EN SENSE LDOOUT LDOIN H1 H2 HVSS1 HVDD1 H3 H4 H5 H6 HVSS2 HVDD2 H7 H8 HL RGVSS RGVDD RG TCVSS TCVDD Type 1 DO DO DO DO DO DO P P DO DO DO DO DO DO DO DO DO DO DO DO DO P P P AO AO P P DI DI P DI AI AO P DO DO P P DO DO DO DO P P DO DO DO P P DO P P Description CCD Vertical Clock 19 CCD Vertical Clock 20 CCD Vertical Clock 21 CCD Vertical Clock 22 CCD Vertical Clock 23 CCD Vertical Clock 24 Digital Logic Supply: 1.8 V Digital Logic Ground Data Output 0 (LSB) Data Output 1 Data Output 2 Data Output 3 Data Output 4 Data Output 5 Data Output 6 Data Output 7 Data Output 8 Data Output 9 Data Output 10 Data Output 11 (MSB) Data Clock Output Data Driver Ground Data Driver Supply: 1.8 V, 3.0 V Charge Pump 3.3 V Output Charge Pump Flying Capacitor Top Charge Pump Flying Capacitor Bottom Charge Pump Ground Charge Pump 1.8 V Input Charge Pump Clock Input LDO 3.2 V Output Enable LDO Ground LDO 1.8 V Output Enable LDO Output Sense LDO Output Voltage LDO 3.3 V Input CCD Horizontal Clock 1 CCD Horizontal Clock 2 H-Driver Ground 1 H-Driver Supply 1: 3.3 V CCD Horizontal Clock 3 CCD Horizontal Clock 4 CCD Horizontal Clock 5 CCD Horizontal Clock 6 H-Driver Ground 2 H-Driver Supply 2: 3.3 V CCD Horizontal Clock 7 CCD Horizontal Clock 8 CCD Last Horizontal Clock RG Driver Ground RG Driver Supply: 3.3 V CCD Reset Gate Clock Analog Ground for Timing Core Timing Core Supply: 1.8 V Rev. C | Page 9 of 92 AD9992 Pin No. C7 C6 C5 B6 A6 B5, A5 A4 A3 C4 A2 B3 A9, G10, K5, J4, J5, L5 1 Mnemonic CLIVDD CLO CLI AVDD CCDIN AVSS REFT REFB SL SDATA SCK NC Type 1 P DO DI P AI P AO AO DI DI DI Description CLI Input Supply: 3.0 V Clock Output for Crystal Reference Clock Input AFE Supply: 1.8 V CCD Signal Input Analog Supply Ground Voltage Reference Top Bypass Voltage Reference Bottom Bypass 3-Wire Serial Load Pulse (internal pull-up resistor) 3-Wire Serial Data Input 3-Wire Serial Clock Not Internally Connected DIO = digital input/output, DI = digital input, P = power, DO = digital output, AI = analog input, AO = analog output. Rev. C | Page 10 of 92 AD9992 TYPICAL PERFORMANCE CHARACTERISTICS 500 450 400 350 POWER (mW) 150 +3dB CDS RMS OUTPUT NOISE (LSB) 3.3V/1.8V 3.0V/1.8V 0dB CDS 100 –3dB CDS 300 250 200 150 100 50 05891-004 2.7V/1.8V 50 20 25 30 FREQUENCY (MHz) 35 40 0 5 10 15 20 25 30 CDS + VGA GAIN (dB) 35 40 45 Figure 4. Power vs. Frequency (AVDD = TCVDD = DVDD = 1.8 V, All Other Supplies at 2.7 V, 3.0 V, or 3.3 V) 1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) Figure 6. Output Noise vs. Total Gain (CDS + VGA) 5 4 3 2 1 0 –1 –2 0.2 0 –0.2 –0.4 –0.6 –0.8 05891-089 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 0 500 1000 1500 2000 2500 CODE 3000 3500 4000 Figure 5. Typical Differential Nonlinearity (DNL) Performance Figure 7. Typical Integral Nonlinearity (INL) Performance Rev. C | Page 11 of 92 05891-090 –1.0 05891-006 0 15 0 AD9992 EQUIVALENT CIRCUITS AVDD IOVDD CCDIN R 330Ω DIGITAL INPUT AVSS AVSS 05891-008 IOVSS Figure 8. CCDIN DVDD DRVDD Figure 10. Digital Inputs HVDD OR RGVDD DATA RG, H1 TO H8 THREESTATE DOUT THREE-STATE OUTPUT 05891-009 05891-010 DVSS DRVSS HVSS OR RGVSS Figure 9. Digital Data Outputs Figure 11. H1 to H8, HL, RG Drivers Rev. C | Page 12 of 92 05891-011 AD9992 TERMINOLOGY Differential Nonlinearity (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Therefore, every code must have a finite width. No missing codes guaranteed to 12-bit resolution indicates that all 4096 codes must be present over all operating conditions. Peak Nonlinearity Peak nonlinearity, a full signal chain specification, refers to the peak deviation of the output of the AD9992 from a true straight line. The point used as zero scale occurs 0.5 LSB before the first code transition. Positive full scale is defined as a level 1 LSB and 0.5 LSB beyond the last code transition. The deviation is measured from the middle of each particular output code to the true straight line. The error is then expressed as a percentage of the 2 V ADC full-scale signal. The input signal is always appropriately amplified to fill the full-scale range of the ADC. Total Output Noise The rms output noise is measured using histogram techniques. The standard deviation of the ADC output codes is calculated in LSB and represents the rms noise level of the total signal chain at the specified gain setting. The output noise can be converted to an equivalent voltage using the relationship 1 LSB = (ADC Full Scale/2n Codes) where n is the bit resolution of the ADC. For the AD9992, 1 LSB is 0.488 mV. Power Supply Rejection (PSR) The PSR is measured with a step change applied to the supply pins. The PSR specification is calculated from the change in data outputs for a given step change in the supply voltage. Rev. C | Page 13 of 92 AD9992 SYSTEM OVERVIEW Figure 12 shows the typical system block diagram for the AD9992 in master mode. The CCD output is processed by AD9992 AFE circuitry, which consists of a CDS, VGA, black level clamp, and ADC. The digitized pixel information is sent to the digital image processor chip, which performs the postprocessing and compression. To operate the CCD, all CCD timing parameters are programmed into the AD9992 from the system microprocessor through the 3-wire serial interface. The AD9992 generates the CCD’s horizontal and vertical clocks and internal AFE clocks from the master clock, CLI, which is provided by the image processor or external crystal,. External synchronization is provided by a sync pulse from the microprocessor, which resets the internal counters and resyncs the VD and HD outputs. V-DRIVER H1 TO H8, HL, RG DOUT CCD CCDIN Alternatively, the AD9992 can operate in slave mode. In slave mode, the VD and HD are provided externally from the image processor, and all AD9992 timing synchronizes with VD and HD. H-drivers for H1 to H8, HL, and RG are included in the AD9992, allowing these clocks to be directly connected to the CCD. An H-driver voltage of up to 3.3 V is supported. An external V-driver is required for the vertical transfer clocks, the sensor gate pulses, and the substrate clock. The AD9992 includes programmable general-purpose outputs (GPO), which can trigger mechanical shutter and strobe (flash) circuitry. Figure 13 and Figure 14 show the maximum horizontal and vertical counter dimensions for the AD9992. All internal horizontal and vertical clocking is controlled by these counters, which specify line and pixel locations. Maximum HD length is 8192 pixels per line; maximum VD length is 8192 lines per field. MAXIMUM COUNTER DIMENSIONS XV1 TO XV24, XSUBCK AD9992 AFETG DCLK HD, VD CLI GPO1 TO GPO8 DIGITAL IMAGE PROCESSING ASIC 13-BIT HORIZONTAL = 8192 PIXELS MAX SERIAL INTERFACE MICROPROCESSOR 05891-012 SYNC 13-BIT VERTICAL = 8192 LINES MAX Figure 12. Typical System Block Diagram, Master Mode Figure 13. Vertical and Horizontal Counters MAX VD LENGTH IS 8192 LINES VD MAX HD LENGTH IS 8192 PIXELS HD Figure 14. Maximum VD/HD Dimensions Rev. C | Page 14 of 92 05891-014 CLI 05891-013 AD9992 HIGH SPEED PRECISION TIMING CORE The AD9992 generates high speed timing signals using the flexible Precision Timing core. This core is the foundation for generating timing used for both the CCD and the AFE; it includes the reset gate RG, horizontal drivers H1 to H8, HL, and SHP/SHD sample clocks. A unique architecture makes it routine for the system designer to optimize image quality by providing precise control over the horizontal CCD readout and the AFE correlated double sampling. The high speed timing of the AD9992 operates the same way in either master or slave mode configuration. For more information on synchronization and pipeline delays, see the Power-Up Sequence for Master Mode section. clock is not available, it is possible to use a 2× reference clock by programming the CLIDIVIDE register (AFE Register Address 0x0D). The AD9992 then internally divides the CLI frequency by 2. The AD9992 includes a master clock output (CLO) which is the inverse of CLI. This output should be used as a crystal driver. A crystal can be placed between the CLI and CLO pins to generate the master clock for the AD9992. High Speed Clock Programmability Figure 16 shows when the high speed clocks RG, H1 to H8, SHP, and SHD are generated. The RG pulse has programmable rising and falling edges and can be inverted using the polarity control. Horizontal Clock H1 has programmable rising and falling edges and polarity control. In HCLK Mode 1, H3, H5, and H7 are equal to H1. H2, H4, H6, and H8 are always inverses of H1. The edge location registers are each six bits wide, allowing selection of all 64 edge locations. Figure 19 shows the default timing locations for all high speed clock signals. P[32] P[48] P[64] = P[0] Timing Resolution The Precision Timing core uses a 1× master clock input (CLI) as a reference. This clock should be the same as the CCD pixel clock frequency. Figure 15 illustrates how the internal timing core divides the master clock period into 64 steps or edge positions. Using a 40 MHz CLI frequency, the edge resolution of the Precision Timing core is approximately 0.4 ns. If a 1× system POSITION CLI P[0] P[16] tCLIDLY ONE PIXEL PERIOD Figure 15. High Speed Clock Resolution from CLI, Master Clock Input 1 CCD SIGNAL 2 3 RG 5 H1, H3, H5, H7 4 6 H2, H4, H6, H8 7 HL PROGRAMMABLE CLOCK POSITIONS: 8 Figure 16. High Speed Clock Programmable Locations (HCLKMODE = 001) Rev. C | Page 15 of 92 05891-016 1SHP SAMPLE LOCATION. 2SHD SAMPLE LOCATION. 3RG RISING EDGE. 4RG FALLING EDGE. 5H1 RISING EDGE. 6H1 FALLING EDGE. 7HL RISING EDGE. 8HL FALLING EDGE. 05891-015 NOTES 1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS. 2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (tCLIDLY). AD9992 H-Driver and RG Outputs In addition to the programmable timing positions, the AD9992 features on-chip output drivers for the RG, HL, and H1 to H8 outputs. These drivers are powerful enough to drive the CCD inputs directly. The H-driver and RG current can be adjusted for optimum rise/fall time for a particular load by using the drive strength control registers (Address 0x35 and Address 0x36). The 3-bit drive setting for each output is adjustable in 4.3 mA increments: 0 = three-state; 1 = 4.3 mA; 2 = 8.6 mA; 3 = 12.9 mA; and 4, 5, 6, 7 = 17.2 mA. As shown in Figure 16, when HCLK Mode 1 is used, the H2, H4, H6, and H8 outputs are inverses of the H1, H3, H5, and H7 outputs, respectively. Using the HCLKMODE register (Address 0x23, Bits [9:7]), it is possible to select a different configuration. Table 9 shows a comparison of the different programmable settings for each HCLK mode. Figure 17 and Figure 18 show the settings for HCLK Mode 2 and HCLK Mode 3, respectively. It is recommended that all H1 to H8 outputs on the AD9992 be used together for maximum flexibility in drive strength settings. A typical CCD with H1 and H2 inputs should only have the AD9992 H1, H3, H5, and H7 outputs connected together to drive the CCD’s H1, and the H2, H4, H6, and H8 outputs connected together to drive the CCD’s H2. Similarly, a CCD with H1, H2, H3, and H4 inputs should have • • • • H1 and H3 connected to the CCD’s H1. H2 and H4 connected to the CCD’s H2. H5 and H7 connected to the CCD’s H3. H6 and H8 connected to the CCD’s H4. Table 8. Timing Core Register Parameters for H1, H2, HL, RG, SHP, SHD Parameter Polarity Positive Edge Negative Edge Sampling Location Drive Strength Length 1b 6b 6b 6b 3b Range High/low 0 to 63 edge location 0 to 63 edge location 0 to 63 edge location 0 to 4 current steps Description Polarity control for H1, H2, HL, and RG (0 = inversion, 1 = no inversion) Positive edge location for H1, H2, HL, and RG Negative edge location for H1, H2, HL, and RG Sampling location for internal SHP and SHD signals Drive current for H1 to H8 , HL, and RG outputs (4.3 mA per step) Table 9. HCLK Modes, Selected by Address 0x23, Bits[9:7] HCLKMODE Mode 1 Mode 2 Mode 3 Invalid Selection Register Value 001 010 100 000, 011, 101, 110, 111 1 H1, H3, H5, H7 4 H2, H4, H6, H8 3 2 Description H1 edges are programmable, with H3 = H5 = H7 = H1, H2 = H4 = H6 = H8 = inverse of H1 H1 edges are programmable, with H3 = H5 = H7 = H1 H2 edges are programmable, with H4 = H6 = H8 = H2 H1 edges are programmable, with H3 = H1 and H2 = H4 = inverse of H1 H5 edges are programmable, with H7 = H5 and H6 = H8 = inverse of H5 Invalid register settings Figure 17. HCLK Mode 2 Operation Rev. C | Page 16 of 92 05891-017 H1 TO H8 PROGRAMMABLE LOCATIONS: 1H1 RISING EDGE. 2H1 FALLING EDGE. 3H2 RISING EDGE. 4H2 FALLING EDGE. AD9992 1 2 H1, H3 H2, H4 3 4 H5, H7 H6, H8 H1 TO H8 PROGRAMMABLE EDGES: 1H1 RISING EDGE. 2H1 FALLING EDGE. 3H5 RISING EDGE. 4H5 FALLING EDGE. Figure 18. HCLK Mode 3 Operation POSITION CLI P[0] P[16] P[32] P[48] 05891-018 P[64] = P[0] RGr[0] RGf[16] RG H1r[0] H1f[32] 48 63 H1 tSHDINH tSHDINH H2 tS2 CCD SIGNAL SHPLOC[32] tS1 SHP SHDLOC[0] tSHPINH SHD 1 12 DOUTPHASEP tDOUTINH 05891-093 NOTES: 1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD. TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN. 2. CERTAIN POSITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS. 3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE. 4. THE tSHPINH AREA FROM 50 TO 62 ONLY APPLIES IN SLAVE MODE. 5. THE tSHDINH AREA WLL APPLY TO EITHER H1 RISING OR FALLING EDGE, DEPENDING ON THE VALUE OF THE H1HBLK MASKING POLARITY. 6. THE tSHDINH AREA CAN ALSO BE CHANGED TO A tSHPINH AREA IF THE H1HBLKRETIME BIT = 1. Figure 19. High Speed Timing Default Locations Digital Data Outputs The AD9992 data output and DCLK phase are programmable using the DOUTPHASE registers (Address 0x38, Bits [11:0]). DOUTPHASEP (Bits [5:0]) selects any edge location from 0 to 63, as shown in Figure 20. DOUTPHASEN (Bits [11:6]) does not actually program the phase of the data outputs but is used internally and should always be programmed to a value of DOUTPHASEP plus 32 edges. For example, if DOUTPHASEP is set to 0, DOUTPHASEN should be set to 32 (0x20). Normally, the DOUT and DCLK signals track in phase, based on the contents of the DOUTPHASE registers. The DCLK output phase can also be held fixed with respect to the data outputs by changing the DCLKMODE register high (Address 0x38, Bit 12). In this mode, the DCLK output remains at a fixed phase equal to a delayed version of CLI while the data output phase is still programmable. The pipeline delay through the AD9992 is shown in Figure 21. After the CCD input is sampled by SHD, there is a 16-cycle delay until the data is available. Rev. C | Page 17 of 92 AD9992 P[0] PIXEL PERIOD P[16] P[32] P[48] P[64] = P[0] DCLK tOD DOUT Figure 20. Digital Output Phase Adjustment Using DOUTPHASEP Register CLI tCLIDLY N CCDIN N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10 N + 11 N + 12 N + 13 N + 14 N + 15 N + 16 N + 17 SAMPLE PIXEL N SHD (INTERNAL) ADC DOUT (INTERNAL) N – 17 N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 05891-020 NOTES 1. DATA OUTPUT (DOUT) AND DCLK PHASE ARE ADJUSTABLE WITH RESPECT TO THE PIXEL PERIOD. 2. WITHIN ONE CLOCK PERIOD, THE DATA TRANSITION CAN BE PROGRAMMED TO 64 DIFFERENT LOCATIONS. 3. DCLK CAN BE INVERTED WITH RESPECT TO DOUT BY USING THE DCLKINV REGISTER. N–1 N N+1 tDOUTINH DCLK PIPELINE LATENCY = 16 CYCLES DOUT N – 17 N – 16 N – 15 N – 14 N – 13 N – 12 N – 11 N – 10 N–9 N–8 N–7 N–6 N–5 N–4 N–3 N–2 N–1 N N+1 Figure 21. Digital Data Output Pipeline Delay Rev. C | Page 18 of 92 05891-021 NOTES 1. TIMING VALUES SHOWN ARE SHDLOC = 0, WITH DCLKMODE = 0. 2. HIGHER VALUES OF SHD AND/OR DOUT PHASE SHIFTS DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION. 3. RECOMMENDED VALUE FOR DOUT PHASE IS TO USE SHPLOC OR UP TO 15 EDGES FOLLOWING SHPLOC. AD9992 HORIZONTAL CLAMPING AND BLANKING The horizontal clamping and blanking pulses of the AD9992 are fully programmable to suit a variety of applications. Individual control is provided for CLPOB, PBLK, and HBLK in the different regions of each field. This allows the dark pixel clamping and blanking patterns to be changed at each stage of the readout to accommodate different image transfer timing and high speed line shifts. CLPOB and PBLK Masking Areas Additionally, the AD9992 allows the CLPOB and PBLK signals to be disabled in certain lines in the field without changing any of the existing CLPOB pattern settings. To use CLPOB (or PBLK) masking, the CLPMASKSTART (PBLKMASKSTART) and CLPMASKEND (PBLKMASKEND) registers are programmed to specify the start and end lines in the field where the CLPOB (PBLK) patterns are ignored. The three sets of start and end registers allow up to three CLPOB (PBLK) masking areas to be created. The CLPOB and PBLK masking registers are not specific to a certain V-sequence; they are always active for any existing field of timing. During operation, to disable the CLPOB masking feature, these registers must be set to the maximum value of 0x1FFF or a value greater than the programmed VD length. Note that to disable CLPOB (and PBLK) masking during power-up, it is recommended to set CLPMASKSTART (PBLKMASKSTART) to 8191 and CLPMASKEND (PBLKMASKEND) to 0. This prevents any accidental masking caused by register update events. Individual CLPOB and PBLK Patterns The AFE horizontal timing consists of CLPOB and PBLK, as shown in Figure 22. These two signals are programmed independently using the registers listed in Table 10. The start polarity for the CLPOB (and PBLK) signal is CLPOBPOL (PBLKPOL), and the first and second toggle positions of the pulse are CLPOBTOG1 (PBLKTOG1) and CLPOBTOG2 (PBLKTOG2). Both signals are active low and should be programmed accordingly. A separate pattern for CLPOB and PBLK can be programmed for each vertical sequence. As described in the Vertical Timing Generation section, several V-sequences can be created, each containing a unique pulse pattern for CLPOB and PBLK. Figure 48 shows how the sequence change positions divide the readout field into different regions. By assigning a different V-sequence to each region, the CLPOB and PBLK signals can change with each change in the vertical timing. Table 10. CLPOB and PBLK Pattern Registers Register CLPOBPOL PBLKPOL CLPOBTOG1 CLPOBTOG2 PBLKTOG1 PBLKTOG2 CLPMASKSTART CLPMASKEND PBLKMASKSTART PBLKMASKEND Length 1b 1b 13b 13b 13b 13b 13b 13b 13b 13b Range High/low High/low 0 to 8191 pixel locations 0 to 8191 pixel locations 0 to 8191 pixel locations 0 to 8191 pixel locations 0 to 8191 line locations 0 to 8191 line locations 0 to 8191 line locations 0 to 8191 line locations Description Starting polarity of CLPOB for each V-sequence. Starting polarity of PBLK for each V-sequence. First CLPOB toggle position within line for each V-sequence. Second CLPOB toggle position within line for each V-sequence. First PBLK toggle position within line for each V-sequence. Second PBLK toggle position within line for each V-sequence. CLPOB masking area—starting line within field (maximum of three areas). CLPOB masking area—ending line within field (maximum of three areas). PBLK masking area—starting line within field (maximum of three areas). PBLK masking area—ending line within field (maximum of three areas). Rev. C | Page 19 of 92 AD9992 HD 2 CLPOB 1 PBLK ACTIVE 3 ACTIVE 05891-022 1START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW). 2FIRST TOGGLE POSITION. 3SECOND TOGGLE POSITION. PROGRAMMABLE SETTINGS: Figure 22. Clamp and Preblank Pulse Placement VD 0 HD 1 2 NO CLPOB SIGNAL FOR LINES 6 TO 8 597 598 NO CLPOB SIGNAL FOR LINE 600 CLPOB 05891-023 CLPMASKSTART1 = 6 CLPMASKEND1 = 8 CLPMASKSTART2 = CLPMASKEND2 = 600 Figure 23. CLPOB Masking Example Individual HBLK Patterns The HBLK programmable timing shown in Figure 24 is similar to CLPOB and PBLK; however, there is no start polarity control. Only the toggle positions are used to designate the start and stop positions of the blanking period. Additionally, there are separate masking polarity controls for H1, H2, and HL that designate the polarity of the horizontal clock signals during the blanking period. Setting HBLKMASK_H1 high sets H1, and therefore H3, H5, and H7, low during the blanking, as shown in Figure 25. As with the CLPOB and PBLK signals, HBLK registers are available in each V-sequence, allowing different blanking signals to be used with different vertical timing sequences. The AD9992 supports three modes of HBLK operation. HBLK Mode 0 supports basic operation and some support for special HBLK patterns. HBLK Mode 1 supports pixel mixing HBLK operation. HBLK Mode 2 supports advanced HBLK operation. The following sections describe each mode in detail. Register parameters are described in detail in Table 11. HBLK Mode 0 Operation There are six toggle positions available for HBLK. Normally, only two of the toggle positions are used to generate the standard HBLK interval. However, the additional toggle positions can be used to generate special HBLK patterns, as shown in Figure 26. The pattern in this example uses all six toggle positions to generate two extra groups of pulses during the HBLK interval. By changing the toggle positions, different patterns can be created. Separate toggle positions are available for even and odd lines. If alternation is not needed, the same values should be loaded into the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines. Rev. C | Page 20 of 92 AD9992 HD HBLKTOGE1 HBLKTOGE2 BASIC HBLK PULSE IS GENERATED USING HBLKTOGE1 AND HBLKTOGE2 REGISTERS (HBLKALT = 0) Figure 24. Typical Horizontal Blanking Pulse Placement (HBLKMODE = 0) HD HBLK H1/H3/H5/H7 THE POLARITY OF H1/H3/H5/H7 DURING BLANKING IS PROGRAMMABLE (H2/H4/H6/H8 AND HL ARE SEPARATELY PROGRAMMABLE) H1/H3/H5/H7 05891-025 H2/H4/H6/H8 Figure 25. HBLK Masking Polarity Control HBLKTOGE2 HBLKTOGE1 HBLKTOGE4 HBLKTOGE3 HBLKTOGE6 HBLKTOGE5 HBLK H1/H3 H2/H4 SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS (HBLKALT = 0) Figure 26. Using Multiple Toggle Positions for HBLK (HBLKMODE = 0) Rev. C | Page 21 of 92 05891-026 05891-024 HBLK BLANK BLANK AD9992 Table 11. HBLK Pattern Registers Register HBLKMODE Length 2b Range 0 to 2 HBLK modes Description Enables different HBLK toggle position operation. 0: Normal mode. Six toggle positions available for even and odd lines. If even/odd alternation is not needed, set toggles for even/odd the same. 1: Pixel mixing mode. In addition to the six toggle positions, the HBLKSTART, HBLKEND, HBLKLEN, and HBLKREP registers can be used to generate HBLK patterns. If even/odd alternation is not need, set toggles for even/odd the same. 2: Advanced HBLK mode. Divides HBLK interval into six repeat areas. Uses HBLKSTARTA/B/C and RA*H*REPA/B/C registers. 3: Test mode only. Do not access. Start location for HBLK in HBLK Mode 1 and HBLK Mode 2. End location for HBLK in HBLK Mode 1 and HBLK Mode 2. HBLK length in HBLK Mode 1 and HBLK Mode 2. Number of HBLK repetitions in HBLK Mode 1 and HBLK Mode 2. Masking polarity for H1, H3, H5, H7 during HBLK. Masking polarity for H2, H4, H6, H8 during HBLK. Masking polarity for HL during HBLK. First HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1. Second HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1. Third HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1. Fourth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1. Fifth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1. Sixth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1. First HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1. Second HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1. Third HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1. Fourth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1. Fifth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1. Sixth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1. HBLK Repeat Area 0. Number of H1 repetitions for HBLKSTARTA/B/C in HBLK Mode 2 for even lines; odd lines defined using HBLKALT_PAT. [3:0] RA0H1REPA. Number of H1 pulses following HBLKSTARTA. [7:4] RA0H1REPB. Number of H1 pulses following HBLKSTARTB. [11:8] RA0H1REPC. Number of H1 pulses following HBLKSTARTC. HBLK Repeat Area 1. Number of H1 repetitions for HBLKSTARTA/B/C. HBLK Repeat Area 2. Number of H1 repetitions for HBLKSTARTA/B/C. HBLK Repeat Area 3. Number of H1 repetitions for HBLKSTARTA/B/C. HBLK Repeat Area 4. Number of H1 repetitions for HBLKSTARTA/B/C. HBLK Repeat Area 5. Number of H1 repetitions for HBLKSTARTA/B/C. HBLK Repeat Area 0. Number of H2 repetitions for HBLKSTARTA/B/C in HBLK Mode 2 for even lines; odd lines defined using HBLKALT_PAT. [3:0] RA0H2REPA. Number of H2 pulses following HBLKSTARTA. [7:4] RA0H2REPB. Number of H2 pulses following HBLKSTARTB. [11:8] RA0H2REPC. Number of H2 pulses following HBLKSTARTC. HBLK Repeat Area 1. Number of H2 repetitions for HBLKSTARTA/B/C. HBLK Repeat Area 2. Number of H2 repetitions for HBLKSTARTA/B/C. HBLK Repeat Area 3. Number of H2 repetitions for HBLKSTARTA/B/C. HBLK Repeat Area 4. Number of H2 repetitions for HBLKSTARTA/B/C. HBLK Repeat Area 5. Number of H2 repetitions for HBLKSTARTA/B/C. HBLK Repeat Area Start Position A for HBLK Mode 2. Set to 8191 if not used. HBLK Repeat Area Start Position B for HBLK Mode 2. Set to 8191 if not used. HBLK Repeat Area Start Position C for HBLK Mode 2. Set to 8191 if not used. HBLK Mode 2, Odd Field Repeat Area 0 pattern, selected from even field repeat areas previously defined. Rev. C | Page 22 of 92 HBLKSTART HBLKEND HBLKLEN HBLKREP HBLKMASK_H1 HBLKMASK_H2 HBLKMASK_HL HBLKTOGO1 HBLKTOGO2 HBLKTOGO3 HBLKTOGO4 HBLKTOGO5 HBLKTOGO6 HBLKTOGE1 HBLKTOGE2 HBLKTOGE3 HBLKTOGE4 HBLKTOGE5 HBLKTOGE6 RA0H1REPA/B/C 13b 13b 13b 13b 1b 1b 1b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 12b 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixels 0 to 8191 repetitions High/low High/low High/low 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 15 HCLK pulses for each A, B, and C RA1H1REPA/B/C RA2H1REPA/B/C RA3H1REPA/B/C RA4H1REPA/B/C RA5H1REPA/B/C RA0H2REPA/B/C 12b 12b 12b 12b 12b 12b 0 to 15 HCLK pulses 0 to 15 HCLK pulses 0 to 15 HCLK pulses 0 to 15 HCLK pulses 0 to 15 HCLK pulses 0 to 15 HCLK pulses for each A, B, and C RA1H2REPA/B/C RA2H2REPA/B/C RA3H2REPA/B/C RA4H2REPA/B/C RA5H2REPA/B/C HBLKSTARTA HBLKSTARTB HBLKSTARTC HBLKALT_PAT1 12b 12b 12b 12b 12b 13b 13b 13b 3b 0 to 15 HCLK pulses 0 to 15 HCLK pulses 0 to 15 HCLK pulses 0 to 15 HCLK pulses 0 to 15 HCLK pulses 0 to 8191 pixel location 0 to 8191 pixel location 0 to 8191 pixel location 0 to 5 even repeat area AD9992 Register HBLKALT_PAT2 HBLKALT_PAT3 HBLKALT_PAT4 HBLKALT_PAT5 HBLKALT_PAT6 Length 3b 3b 3b 3b 3b Range 0 to 5 even repeat area 0 to 5 even repeat area 0 to 5 even repeat area 0 to 5 even repeat area 0 to 5 even repeat area HBLKTOGE2 HBLKSTART HBLKTOGE1 HBLKTOGE3 Description HBLK Mode 2, Odd Field Repeat Area 1 pattern. HBLK Mode 2, Odd Field Repeat Area 2 pattern. HBLK Mode 2, Odd Field Repeat Area 3 pattern. HBLK Mode 2, Odd Field Repeat Area 4 pattern. HBLK Mode 2, Odd Field Repeat Area 5 pattern. HBLKTOGE4 HBLKEND HBLK HBLKLEN HBLKREP = 3 H1/H3 H2/H4 05891-027 HBLKREP NUMBER 1 HBLKREP NUMBER 2 HBLKREP NUMBER 3 H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS Figure 27. HBLK Repeating Pattern Using HBLKMODE = 1 HBLK Mode 1 Operation Multiple repeats of the HBLK signal are enabled by setting HBLKMODE to 1. In this mode, the HBLK pattern can be generated using a different set of registers: HBLKSTART, HBLKEND, HBLKLEN, and HBLKREP, along with the six toggle positions (see Figure 27). Separate toggle positions are available for even and odd lines. If alternation is not needed, the same values should be loaded into the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines. Bits [7:4]) is set to a value between 1 and 15. When this register is set to 0, the wide HCLK feature is disabled. The reduced frequency occurs only for H1 to H8 pulses that are located within the HBLK area. The HCLK_WIDTH register is generally used in conjunction with special HBLK patterns to generate vertical and horizontal mixing in the CCD. Note that the wide HCLK feature is available only in HBLK Mode 0 and HBLK Mode 1. HBLK Mode 2 does not support wide HCLKs. Table 12. HCLK Width Register Register HCLK_WIDTH Length 4b Description Controls H1 to H8 pulse widths during HBLK as a fraction of pixel rate 0: Same frequency as pixel rate 1: 1/2 pixel frequency, that is, doubles the HCLK pulse width 2: 1/4 pixel frequency 3: 1/6 pixel frequency 4: 1/8 pixel frequency 5: 1/10 pixel frequency … 15: 1/30 pixel frequency Generating HBLK Line Alternation HBLK Mode 0 and HBLK Mode 1 provide the ability to alternate different HBLK toggle positions on even and odd lines. HBLK line alternation can be used in conjunction with V-pattern odd/even alternation or on its own. Separate toggle positions are available for even and odd lines. If even/odd line alternation is not required, the same values should be loaded into the registers for even (HBLKTOGE) and odd (HBLKTOGO) lines. Increasing H-Clock Width During HBLK HBLK Mode 0 and HBLK Mode 1 allow the H1 to H8 pulse widths to be increased during the HBLK interval. As shown in Figure 28, the H-clock frequency can be reduced by a factor of 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30. To enable this feature, the HCLK_WIDTH register (Address 0x34, Rev. C | Page 23 of 92 AD9992 HBLK H1/H3 1/FPIX H2/H4 05891-028 2 × (1/FPIX) H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN), 1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLKWIDTH REGISTER Figure 28. Generating Wide H-Clock Pulses During HBLK Interval HD CREATE UP TO 3 GROUPS OF TOGGLES A, B, C COMMON IN ALL REPEAT AREAS A B C MASK A, B, C PULSES IN ANY REPEAT AREA BY SETTING RA*H*REP* = 0 CHANGE NUMBER OF A, B, C PULSES IN ANY REPEAT AREA USING RA*H*REP* REGISTERS H1 H2 REPEAT AREA 0 HBLKSTART REPEAT AREA 1 REPEAT AREA 2 REPEAT AREA 3 REPEAT AREA 4 REPEAT AREA 5 HBLKEND Figure 29. HBLK Mode 2 Operation HD HBLKLEN HBLK HBLKSTARTA HBLKSTARTB HBLKSTARTC H1 ALL RA*H*REPA/B/C REGISTERS = 2 TO CREATE TWO HCLK PULSES RA0H1REPA RA0H1REPB H2 RA0H1REPC RA1H1REPA RA1H1REPB RA1H1REPC HBLKSTART RA0H2REPA RA0H2REPB RA0H2REPC RA1H2REPA RA1H2REPB RA1H2REPC HBLKEND 05891-030 REPEAT AREA 0 HBLKREP = 2 TO CREATE TWO REPEAT AREAS REPEAT AREA 1 Figure 30. HBLK Mode 2 Registers Rev. C | Page 24 of 92 05891-029 AD9992 HBLK Mode 2 Operation HBLK Mode 2 allows more advanced HBLK pattern operation. If multiple areas of HCLK pulses that are unevenly spaced apart from one another are needed, HBLK Mode 2 can be used. Using a separate set of registers, HBLK Mode 2 can divide the HBLK region into up to six repeat areas (see Table 11). As shown in Figure 30, each repeat area shares a common group of toggle positions, HBLKSTARTA, HBLKSTARTB, and HBLKSTARTC. However, the number of toggles following each start position can be unique in each repeat area by using the RA*H1REP* and RA*H2REP* registers. As shown in Figure 29, setting the RA*H1REPA/RA*H1REPB/RA*H1REPC or RA*H2REPA/ RA*H2REPB/RA*H2REPC registers to 0 masks HCLK groups from appearing in a particular repeat area. Figure 30 shows only two repeat areas being used, although six are available. It is possible to program a separate number of repeat area repetitions for H1 and H2, but generally the same value is used for both H1 and H2. Figure 30 shows an example of RA0H1REPA/RA0H1REPB/ RA0H1REPC = RA0H2REPA/RA0H2REPB/RA0H2REPC = RA1H1REPA/RA1H1REPB/RA1H1REPC = RA1H2REPA/ RA1H2REPB/RA1H2REPC = 2. Furthermore, HBLK Mode 2 allows a different HBLK pattern on even and odd lines. The HBLKSTARTA, HBLKSTARTB, and HBLKSTARTC registers, as well as the RA*H1REPA/RA*H1REPB /RA*H1REPC and RA*H2REPA/ RA*H2REPB/RA*H2REPC registers, define operation for the even lines. For separate control of the odd lines, the HBLKALT_PAT registers specify up to six repeat areas on the odd lines by reordering the repeat areas used for the even lines. New patterns are not available, but the order of the previously defined repeat areas on the even lines can be changed for the odd lines to accommodate advanced CCD operation. HORIZONTAL TIMING SEQUENCE EXAMPLE Figure 31 shows an example CCD layout. The horizontal register contains 28 dummy pixels, which occur on each line clocked from the CCD. In the vertical direction, there are 10 optical black (OB) lines at the front of the readout and two at the back of the readout. The horizontal direction has four OB pixels in the front and 48 in the back. Figure 32 shows the basic sequence layout to be used during the effective pixel readout. The 48 OB pixels at the end of each line are used for the CLPOB signals. PBLK is optional and is often used to blank the digital outputs during the HBLK time. HBLK is used during the vertical shift interval. Because PBLK is used to isolate the CDS input (see the Analog Preblanking section), the PBLK signal should not be used during CLPOB operation. The change in the offset behavior that occurs during PBLK impacts the accuracy of the CLPOB circuitry. The HBLK, CLPOB, and PBLK parameters are programmed in the V-sequence registers. More elaborate clamping schemes, such as adding in a separate sequence to clamp in the entire shield OB lines, can be used. This requires configuring a separate V-sequence for clocking out the OB lines. The CLPMASK registers are also useful for disabling the CLPOB on a few lines without affecting the setup of the clamping sequences. It is important that CLPOB be used only during valid OB pixels. During other portions on the frame timing, such as vertical blanking or SG line timing, the CCD does not output valid OB pixels. Any CLPOB pulse that occurs during this time causes errors in clamping operation and changes in the black level of the image. 2 VERTICAL OB LINES V EFFECTIVE IMAGE AREA 10 VERTICAL OB LINES H 4 OB PIXELS HORIZONTAL CCD REGISTER 05891-031 48 OB PIXELS 28 DUMMY PIXELS Figure 31. Example CCD Configuration Rev. C | Page 25 of 92 AD9992 OPTICAL BLACK HD OPTICAL BLACK CCD OUTPUT SHP SHD H1/H3/H5/H7 H2/H4/H6/H8 HBLK PBLK CLPOB VERTICAL SHIFT DUMMY EFFECTIVE PIXELS OPTICAL BLACK VERT. SHIFT NOTES 1. PBLK ACTIVE (LOW) SHOULD NOT BE USED DURING CLPOB ACTIVE (LOW). Figure 32. Horizontal Sequence Example VERTICAL TIMING GENERATION The AD9992 provides a flexible solution for generating vertical CCD timing and can support multiple CCDs and different system architectures. The vertical transfer clocks are used to shift each line of pixels into the horizontal output register of the CCD. The AD9992 allows these outputs to be individually programmed into various readout configurations by using a 4-step process. Figure 33 shows an overview of how the vertical timing is generated in four steps. 1. 2. The individual pulse patterns for XV1 to XV24 are created by using the vertical pattern group registers. The V-pattern groups are used to build the sequences, which is when additional information is added. 3. The readout for an entire field is constructed by dividing the field into different regions and then assigning a sequence to each region. Each field can contain up to nine different regions to accommodate different steps of the readout, such as high speed line shifts and unique vertical line transfers. The total number of V-patterns, V-sequences, and fields is programmable but limited by the number of registers. 4. The MODE registers allow the different fields to be combined in any order for various readout configurations. Rev. C | Page 26 of 92 05891-032 AD9992 1 CREATE THE VERTICAL PATTERN GROUPS, UP TO FOUR TOGGLE POSITIONS FOR EACH OUTPUT. XV1 XV2 VPAT0 XV3 V-SEQUENCE 0 (VPAT0, 1 REP) XV23 XV24 2 BUILD THE V-SEQUENCES BY ADDING START POLARITY, LINE START POSITION, NUMBER OF REPEATS, ALTERNATION, GROUP A/B/C/D INFORMATION, AND HBLK/CLPOB PULSES. XV1 XV2 XV3 XV23 XV24 XV1 XV2 XV1 XV2 VPAT1 XV3 V-SEQUENCE 1 (VPAT1, 2 REP) XV3 XV23 XV24 XV23 XV24 XV1 XV2 V-SEQUENCE 2 (VPAT1, N REP) XV3 XV23 XV24 4 USE THE MODE REGISTERS TO CONTROL WHICH FIELDS ARE USED, AND IN WHAT ORDER (MAXIMUM OF SEVEN FIELDS CAN BE COMBINED IN ANY ORDER). 3 BUILD EACH FIELD BY DIVIDING INTO DIFFERENT REGIONS AND ASSIGNING A DIFFERENT V-SEQUENCE TO EACH (MAXIMUM OF NINE REGIONS IN EACH FIELD). FIELD 0 FIELD0 FIELD1 FIELD2 REGION 0: USE V-SEQUENCE 2 REGION 0: USE V-SEQUENCE 3 REGION 1: USE V-SEQUENCE 0 REGION 0: USE V-SEQUENCE 3 REGION 1: USE V-SEQUENCE 2 REGION 2: USE V-SEQUENCE 3 REGION 1: USE V-SEQUENCE 2 FIELD3 FIELD4 REGION 3: USE V-SEQUENCE 0 REGION 2: USE V-SEQUENCE 1 FIELD5 FIELD1 FIELD4 FIELD2 REGION 2: USE V-SEQUENCE 1 REGION 4: USE V-SEQUENCE 2 FIELD1 FIELD2 05891-033 Figure 33. Summary of Vertical Timing Generation Rev. C | Page 27 of 92 AD9992 Vertical Pattern Groups (VPAT) The vertical pattern groups define the individual pulse patterns for each XV1 to XV24 output signal. Table 13 summarizes the registers available for generating each of the V-pattern groups. The first, second, third, and fourth toggle positions (XVTOG1, XVTOG2, XVTOG3, and XVTOG4) are the pixel locations within the line where the pulse transitions. All toggle positions are 13-bit values, allowing their placement anywhere in the horizontal line. More registers are included in the vertical sequence registers to specify the output pulses. VPOL specifies the start polarity for each signal; VSTART specifies the start position of the V-pattern group within the line; VLEN designates the total length of the V-pattern group, which determines the number of pixels between each of the pattern repetitions when repetitions are used. The VSTART position is actually an offset value for each toggle position. The actual pixel location for each toggle, measured from the HD falling edge (Pixel 0), is equal to the VSTART value plus the toggle position. When the selected V-output is designated as a VSG pulse, either the XVTOG1/XVTOG2 or XVTOG3/XVTOG4 pair is selected using V-Sequence Address 0x02, VSGPATSEL. All four toggle positions are not simultaneously available for VSG pulses. Unused V-channels must have their toggle positions programmed to either 0 or maximum value. This prevents unpredictable behavior because the default values of the V-pattern group registers are unknown. Table 13. Vertical Pattern Group Registers Register XVTOG1 XVTOG2 XVTOG3 XVTOG4 Length 13b 13b 13b 13b Description First toggle position within line for each XV1 to XV24 output, relative to VSTART value. Second toggle position, relative to VSTART value Third toggle position, relative to VSTART value Fourth toggle position, relative to VSTART value START POSITION OF VERTICAL PATTERN GROUP IS PROGRAMMABLE IN VERTICAL SEQUENCE REGISTERS. HD 4 XV1 1 2 3 XV2 1 2 3 XV24 1 2 3 Figure 34. Vertical Pattern Group Programmability Rev. C | Page 28 of 92 05891-034 PROGRAMMABLE SETTINGS: 1START POLARITY (LOCATED IN V-SEQUENCE REGISTERS). 2FIRST TOGGLE POSITION. 3SECOND TOGGLE POSITION (THIRD AND FOURTH TOGGLE POSITIONS ALSO AVAILABLE FOR MORE COMPLEX PATTERNS). 4TOTAL PATTERN LENGTH FOR ALL VERTICAL OUTPUTS (LOCATED IN VERTICAL SEQUENCE REGISTERS). AD9992 VERTICAL SEQUENCES (VSEQ) The vertical sequences are created by selecting one of the V-pattern groups and adding repeats, start position, horizontal clamping, and blanking information. The V-sequences are programmed using the registers shown in Table 14. Figure 35 shows how the different registers are used to generate each V-sequence. The VPATSELA, VPATSELB, VPATSELC, and VPATSELD registers select which V-pattern is used in a given V-sequence. Having four groups available allows different vertical outputs to be mapped to different V-patterns. The selected V-pattern group can have repetitions added for high speed line shifts or for line binning by using the VREP registers for odd and even lines. Generally, the same number of repetitions is programmed into both registers. If a different number of repetitions is required on odd and even lines, separate values can be used for each register (see the Generating Line Alternation for V-Sequences and HBLK section). The VSTARTA and VSTARTB registers specify where in the line the V-pattern group starts. The VMASK_EN register is used with the FREEZE/RESUME registers to enable optional masking of the V-outputs. Either or both of the FREEZE1/RESUME1 and FREEZE2/RESUME2 registers can be enabled. The line length (in pixels) is programmable using the HDLEN registers. Each V-sequence can have a different line length to accommodate various image readout techniques. The maximum number of pixels per line is 8192. The last line of the field is programmed separately using the HDLASTLEN register, which is located in the field register section. 1 HD 2 3 XV1 TO XV24 V-PATTERN GROUP 4 VREP 2 4 VREP 3 CLPOB 5 HBLK 6 PROGRAMMABLE SETTINGS FOR EACH VERTICAL SEQUENCE: 1START POSITION IN THE LINE OF SELECTED V-PATTERN GROUP. 2HD LINE LENGTH. 3V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP. 4NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED). 5START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS. 6MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL. Figure 35. V-Sequence Programmability Rev. C | Page 29 of 92 05891-035 AD9992 Table 14. Summary of V-Sequence Registers (see Table 10 and Table 11 for the CLPOB, PBLK, and HBLK Pattern Registers) Register HOLD VMASK_EN CONCAT_GRP Length 4b 4b 4b Description Use in conjunction with VMASK_EN. 1: HOLD function instead of FREEZE/RESUME function. Enables the masking of XV1 to XV24 outputs at the locations specified by the FREEZE/RESUME registers. 1: Enable masking for all groups. One bit for each set of Freeze and Resume Positions 1 to 4. Combines toggle positions of Groups A/B/C/D when enabled. Only Group A settings for start, polarity, length, and repetition are used when this mode is selected. 0: Disable. 1: Enable the addition of all toggle positions from VPATSELA/B/C/D. 2: Test mode only. Do not use. … 15: Test mode only. Do not use. Selects line alternation for V-output repetitions. Note separate controls for Group A and Groups B/C/D. 0: Disable alternation. Group A uses VREPA_1, Groups B/C/D use VREP _EVEN for all lines. 1: 2-line. Group A alternates VREPA_1 and VREPA_2. Groups B/C/D alternate VREP_EVEN and VREP_ODD. 2: 3-line. Group A alternates VREPA_1, VREPA_2, and VREPA_3. Groups B/C/D follow a VREP_EVEN, VREP_ODD, VREP_ODD, VREP_EVEN, VREP_ODD, VREP_ODD pattern. 3: 4-line. Group A alternates VREPA_1, VREPA_2, VREPA_3, VREPA_4. Groups B/C/D follow 2-line alternation. Enables a separate pattern length to be used during the last repetition of the V-sequence. One bit for each group (A, B, C, and D). Set bit high to enable. Group A is the LSB. Recommended value is enabled. Enables a final toggle position to be added at the end of the V-sequence. The toggle position is shared by all V-outputs in the same group. One bit for each group. Set bit high to enable. Group A is the LSB. HD line length for even lines in the V-sequence. HD line length for odd lines in the V-sequence. Group A start polarity bits for each XV1 to XV24 output. Group B start polarity bits for each XV1 to XV24 output. Group C start polarity bits for each XV1 to XV24 output. Group D start polarity bits for each XV1 to XV24 output. Assigns each XV1 to XV12 output to either Group A/B/C/D. Two bits for each signal. Bits [1:0] are for XV1, Bits [3:2] are for XV2 … Bits [23:22] are for XV12. 0: Assign to Group A 1: Assign to Group B 2: Assign to Group C 3: Assign to Group D Assigns each XV13 to XV24 output to either Group A/B/C/D. Two bits for each signal. Bits [1:0] are for XV13, Bits [3:2] are for XV14 … Bits [23:22] are for XV24. 0: Assign to Group A. 1: Assign to Group B. 2: Assign to Group C. 3: Assign to Group D. Selected V-pattern for Group A. Selected V-pattern for Group B. Selected V-pattern for Group C. Selected V-pattern for Group D. Start position for the selected V-Pattern Group A. Start position for the selected V-Pattern Group B. Start position for the selected V-Pattern Group C. Start position for the selected V-Pattern Group D. Length of selected V-Pattern Group A. Length of selected V-Pattern Group B. Length of selected V-Pattern Group C. Length of selected V-Pattern Group D. Number of repetitions for the V-Pattern Group A for first lines (even). Number of repetitions for the V-Pattern Group A for second lines (odd). Rev. C | Page 30 of 92 VREP_MODE 2b LASTREPLEN_EN LASTTOG_EN HDLENE HDLENO VPOL_A VPOL_B VPOL_C VPOL_D GROUPSEL_0 4b 4b 13b 13b 24b 24b 24b 24b 24b GROUPSEL_1 24b VPATSELA VPATSELB VPATSELC VPATSELD VSTARTA VSTARTB VSTARTC VSTARTD VLENA VLENB VLENC VLEND VREPA_1 VREPA_2 5b 5b 5b 5b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b AD9992 Register VREPA_3 VREPA_4 VREPB_ODD VREPC_ODD VREPD_ODD VREPB_EVEN VREPC_EVEN VREPD_EVEN FREEZE1 FREEZE2 FREEZE3 FREEZE4 RESUME1 RESUME2 RESUME3 RESUME4 LASTREPLEN_A LASTREPLEN_B LASTREPLEN_C LASTREPLEN_D LASTTOG_A LASTTOG_B LASTTOG_C LASTTOG_D VSEQALT_EN VALT_MAP VALTSEL0_EVEN VALTSEL1_EVEN VALTSEL0_ODD VALTSEL1_ODD SPC_PAT_EN Length 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 13b 1b 1b 18b 18b 18b 18b 1b Description Number of repetitions for the V-Pattern Group A for third lines. Number of repetitions for the V-Pattern Group A for fourth lines. Number of repetitions for the V-Pattern Group B for odd lines. Number of repetitions for the V-Pattern Group C for odd lines. Number of repetitions for the V-Pattern Group D for odd lines. Number of repetitions for the V-Pattern Group B for even lines. Number of repetitions for the V-Pattern Group C for even lines. Number of repetitions for the V-Pattern Group D for even lines. Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL0_EVEN [12:0] register when special VSEQALT_EN mode is enabled. Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL1_EVEN [12:0] register when special VSEQALT_EN mode is enabled. Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL0_ODD [12:0] register when special VSEQALT_EN mode is enabled. Pixel location where the V-outputs freeze or hold (see VMASK_EN). Also used as VALTSEL1_ODD [12:0] register when special VSEQALT_EN mode is enabled. Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL0_EVEN [17:13] register when S within line for each XV1 to XV24 output when special VSEQALT_EN mode is enabled. Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL1_EVEN [17:13] register when special VSEQALT_EN mode is enabled. Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL0_ODD [17:13] register when special VSEQALT_EN mode is enabled. Pixel location where the V-outputs resume operation (see VMASK_EN). Also used as VALTSEL1_ODD [17:13] register when special VSEQALT_EN mode is enabled. Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN. Should be programmed to a value equal to the VLENA register. Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN. Should be programmed to a value equal to the VLENB register. Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN. Should be programmed to a value equal to the VLENC register. Separate length for last repetition of vertical pulses. Must be enabled using LASTREPLEN_EN. Should be programmed to a value equal to the VLEND register. Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN. Note that the toggle position is common for all vertical signals. Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN. Note that the toggle position is common for all vertical signals. Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN. Note that the toggle position is common for all vertical signals. Optional fifth toggle position for the vertical signals. Must be enabled using LASTTOG_EN. Note that the toggle position is common for all vertical signals. Special V-sequence alternation mode is enabled when this register is programmed high. Enables the use of FREEZE/RESUME register locations to specify the VALTSEL0 and VALTSEL1 registers. Must be enabled if VSEQALT mode is enabled. Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Groups A/B/C/D into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments. Select lines for special V-sequence alternation mode for even lines. Used to concatenate VPAT Groups A/B/C/D into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments. Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Groups A/B/C/D into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments. Select lines for special V-sequence alternation mode for odd lines. Used to concatenate VPAT Groups A/B/C/D into unique merged patterns. Setting is used to specify one segment, with up to a maximum of 18 segments. Enable special V-pattern to be inserted into one repetition of a VPATA series. SPC_PAT_EN [0]: Set to 1 to enable VPATB to be used as special pattern insertion. SPC_PAT_EN [1]: Set to 1 to enable VPATC to be used as special pattern insertion. SPC_PAT_EN [2]: Set to 1 to enable VPATD to be used as special pattern insertion. Rev. C | Page 31 of 92 AD9992 HD XV1 TO XV8 USE V-PATTERN GROUP A XV1 XV8 XV9, XV10 USE V-PATTERN GROUP B XV9 XV10 Figure 36. Using Separate Group A and Group B V-Patterns HD V-PATTERN GROUP A XV1 V-PATTERN GROUP B V-PATTERN GROUP C V-PATTERN GROUP D XV24 Figure 37. Combining Multiple V-Patterns Using CONCAT_GRP = 1 HD V-PATTERN GROUP A XV1 V-PATTERN GROUP B XV10 05891-038 GROUP A REP 1 GROUP A REP 2 GROUP A REP 3 Figure 38. Combining Group A and Group B V-Patterns with Repetition Group A/Group B/Group C/Group D Selection The AD9992 has the flexibility to use four different V-pattern groups in a vertical sequence. In general, the vertical outputs use the same V-pattern group during a particular sequence. It is possible to assign some of the outputs to a different V-pattern group, which can be useful in certain CCD readout modes. The GROUPSEL registers are used to select Group A, Group B, Group C, or Group D for each V-output. In general, only a single V-pattern group is needed for the vertical outputs; therefore, Group A should be selected for all outputs by default (GROUPSEL_0, GROUPSEL_1 = 0x00). In this configuration, all outputs use the V-pattern group specified by the VPATSELA register. If additional flexibility is needed, some outputs can be set to Group B, Group C, or Group D in the GROUPSEL registers. In this case, those selected outputs use the V-pattern group specified by the VPATSELB, VPATSELC, or VPATSELD registers. Figure 36 shows an example where outputs XV9 and XV10 are using a separate V-Pattern Group B to perform special CCD timing. Another application of the Group A, Group B, Group C, and Group D registers is to combine up to four different V-pattern groups together for more complex patterns. This is accomplished by setting the CONCAT_GRP register (Address 0x00, Bits [13:10]) equal to 0x01. This setting combines the toggle positions from the V-pattern groups specified by the VPATSELA, VPATSELB, VPATSELC, and VPATSELD registers for a maximum of up to 16 toggle positions. Example timing for the CONCAT_ GRP = 1 feature is shown in Figure 37. If only two groups are needed (up to eight toggle positions) for the specified timing, the VPATSELB, VPATSELC, and VPATSELD registers can be programmed to the same value. If only three groups are needed, VPATSELC and VPATSELD can be programmed to the same value. Following this approach Rev. C | Page 32 of 92 05891-037 05891-036 AD9992 conserves register memory if the four separate V-patterns are not needed. Note that when CONCAT_GRP is enabled, Group A settings are used only for start position, polarity, length, and repetitions. All toggle positions for Group A, Group B, Group C, and Group D are combined together and applied using the settings in the VSTARTA, VPOL_A, VLENA, and VREPA registers. Table 15. VALTSEL Bit Settings for Even and Odd Lines Parameter VALTSEL0_EVEN VALTSEL1_EVEN VALTSEL0_ODD VALTSEL1_ODD Resulting pattern for even lines Resulting pattern for odd lines VALTSEL Bit Settings 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 A B C D A B C D Special Vertical Sequence Alternation (SVSA) Mode The AD9992 has additional flexibility for combining four different V-pattern groups in a random sequence that can be programmed for specific CCD requirements. This mode of operation allows custom vertical sequences for CCDs that require more complex vertical timing patterns. For example, using the special vertical sequence alternation mode, it is possible to support random pattern concatenation, with additional support for odd/even line alternation. Figure 39 illustrates four common and repetitive vertical pattern segments, A through D, that are derived from the complete vertical pattern. Figure 40 illustrates how each group can be concatenated in an arbitrary order. To enable the SVSA mode, write the VSEQALT_EN bit, Address 0x20 Bit 13, equal to 0x01. The location of the VALTSEL registers is shared with the VPAT registers for XV24. When SVSA mode is enabled, the VALTSEL register function is selected. To create SVSA timing, divide the complete vertical timing pattern into four common and repetitive segments. Identify the related segments as VPATA, VPATB, VPATC, or VPATD. Up to four toggle positions for each segment can be programmed using the V-pattern registers. Table 15 shows how the segments are specified using a 2-bit representation. Each bit from VALTSEL0 and VALTSEL1 is combined to produce four values, corresponding to Pattern A, Pattern B, Pattern C, and Pattern D. When the entire pattern is divided, program VALTSEL0 (even and odd) [17:0] and VALTSEL1 (even and odd) [17:0] so that the segments are concatenated in the desired order. If separate odd and even lines are not required, set the odd and even registers to the same value. Figure 41 illustrates the process of using six vertical pattern segments that have been concatenated into a small, merged pattern. Program the register VREPA_1 to specify the number of segments to concatenate into each merged pattern. The maximum number of segments that can be concatenated to create a merged pattern is 18. Program VLENA, VLENB, VLENC, VLEND to be of equal length. Finally, program HBLK to generate the proper H-clock timing using the procedure for HBLK Mode 2 described in the HBLK Mode 2 Operation section. It is important to note that because the FREEZE/RESUME registers are used to specify the VALTSEL registers, the VALT_MAP register must be enabled when using the special VALT mode. Table 16. VALTSEL Register Locations1 Register Function When VSEQALT_EN = 1 VALTSEL0_EVEN [12:0] VALTSEL0_EVEN [17:13] VALTSEL1_EVEN [12:0] VALTSEL1_EVEN [17:13] VALTSEL0_ODD [12:0] VALTSEL0_ODD [17:13] VALTSEL1_ODD [12:0] VALTSEL1_ODD [17:13] 1 Register Location VSEQ register FREEZE1 [12:0] VSEQ register RESUME1 [17:13] VSEQ register FREEZE2 [12:0] VSEQ register RESUME2 [17:13] VSEQ register FREEZE3 [12:0] VSEQ register RESUME3 [17:13] VSEQ register FREEZE4 [12:0] VSEQ register RESUME4 [17:13] The VALT_MAP register must be set to 1 to enable the use of VALTSEL registers. Rev. C | Page 33 of 92 AD9992 V-PATTERN A XV1 V-PATTERN B V-PATTERN C V-PATTERN D XV2 XV3 XV23 VLENA VLENB VLENC VLEND 05891-039 NOTES 1. EACH SEGMENT MUST BE THE SAME LENGTH. VLENA = VLENB = VLENC = VLEND. Figure 39. Vertical Timing Divided Into Four Segments: VPATA, VPATB, VPATC, and VPATD HD COMBINED V-PATTERN ABBDACC A BCBDABA A Figure 40. Concatenating Each VPAT Group in Arbitrary Order HD XV1 TO XV23 A C B D D A SEGMENT 1 XV1 SEGMENT 2 SEGMENT 3 SEGMENT4 SEGMENT 5 SEGMENT 6 XV2 XV3 XV23 VPATA VALTSEL0_EVEN VALTSEL1_EVEN 0 0 VPATC 0 1 VPATB 1 0 VPATD 1 1 VPATD 1 1 VPATA 0 0 05891-041 NOTES 1. SIX V-PATTERN SEGMENTS CONCATENATED INTO A MERGED PATTERN. 2. COMMON AND REPETITIVE VTP SEGMENTS DERIVED FROM THE COMPLETE VTP PATTERN. 3. VALTSEL REGISTERS SPECIFY SEGMENT ORDER TO CREATE THE CONCATENATED MERGED PATTERN. Figure 41. Special V-Sequence Alternation Mode Using VALTSEL Registers to Specify Segment Order Rev. C | Page 34 of 92 05891-040 NOTES 1. ABLE TO CONCATENATE PATTERNS TOGETHER ARBITRARILY. 2. EACH PATTERN CAN HAVE UP TO FOUR TOGGLES PROGRAMMED. 3. MAY CONCATENATE UP TO 18 PATTERNS INTO A MERGED PATTERN. 4. ODD AND EVEN LINES CAN HAVE A DIFFERENT PATTERN CONCATENATION SPECIFIED BY VALTSEL EVEN AND ODD REGISTERS. AD9992 Using the LASTREPLEN_EN The LASTREPLEN_EN register (Address 0x00, Bits [19:16] in the sequence registers) is used to enable a separate pattern length to be used in the final repetition of several pulse repetitions. It is recommended that the LASTREPLEN_EN register bits be set high (enabled) and the LASTREPLEN_A, LASTREPLEN_B, LASTREPLEN_C, and LASTREPLEN_D registers be set to a value equal to the VLENA, VLENB, VLENC, and VLEND register values, respectively. odd and even lines. Only the number of repeats can be different in odd and even lines, while the V-pattern group remains the same. There are separate controls for the assigned Group A, Group B, Group C, and Group D patterns. All groups can support odd and even line alternation. Group A uses the VREPA_1 register and the VREPA_2 register; Group B, Group C, and Group D use the corresponding VREP_ODD register and VREP_EVEN register. With the additional VREPA_3 register and VREPA_4 register, Group A can also support 3-line and 4-line alternation. As discussed in the Generating HBLK Line Alternation section, the HBLK signal can be alternated for odd and even lines. Figure 42 shows an example of V-pattern group repetition alternation and HBLK Mode 0 alternation used together. Generating Line Alternation for V-Sequences and HBLK During low resolution readout, some CCDs require a different number of vertical clocks on alternate lines. The AD9992 can support this by using the VREP registers. This allows a different number of V-pattern group repetitions to be programmed on HD VREPA_1 = 2 (OR VREPB/C/D_EVEN = 2) XV1 VREPA_2 = 5 (OR VREPB/C/D_ODD = 5) VREPA_1 = 2 (OR VREPB/C/D_EVEN = 2) XV2 XV24 XVTOGE1 HBLK XVTOGE2 XVTOGO1 XVTOGO2 XVTOGE1 XVTOGE2 Figure 42. Odd/Even Line Alternation of V-Pattern Group Repetitions and HBLK Toggle Positions Rev. C | Page 35 of 92 05891-042 NOTES 1. THE NUMBER OF REPEATS FOR V-PATTERN GROUPS A/B/C/D CAN BE ALTERNATED ON ODD AND EVEN LINES. 2. GROUP A ALSO SUPPORTS 3- AND 4-LINE ALTERNATION USING THE ADDITIONAL VREPA_3 AND VREPA_4 REGISTERS. 3. THE HBLK TOGGLE POSITIONS CAN BE ALTERNATED BETWEEN ODD AND EVEN LINES TO GENERATE DIFFERENT HBLK PATTERNS. AD9992 Vertical Masking Using FREEZE/RESUME Registers As shown in Figure 43 and Figure 44, the FREEZE/RESUME registers are used to temporarily mask the V-outputs. The pixel locations to begin the masking (FREEZE) and end the masking (RESUME) create an area in which the vertical toggle positions are ignored. At the pixel location specified in the FREEZE register, the V-outputs are held static at their current dc state, high or low. The V-outputs are held until the pixel location that is specified by the RESUME register is reached, at which point the signals continue with any remaining toggle positions, if any exist. Four sets of FREEZE/RESUME registers are provided, allowing the vertical outputs to be interrupted up to four times in the same line. The FREEZE and RESUME Position 1 to Position 4 are enabled independently and applied to all groups (Group A, Group B, Group C, and Group D) using the VMASK_EN register. Note that when masking is enabled, Group A, Group B, Group C, and Group D use the same FREEZE/RESUME positions. Note that the FREEZE/RESUME registers are also used as the VALTSEL0 and VALTSEL1 registers during special vertical alternation mode. HD NO MASKING AREA XV1 XV24 Figure 43. No FREEZE/RESUME HD V-MASKING AREA FREEZE RESUME XV1 XV24 NOTES 1. ALL TOGGLE POSITIONS WITHIN THE FREEZE/RESUME MASKING AREA ARE IGNORED. H-COUNTER CONTINUES TO COUNT DURING MASKING. 2. FOUR SEPARATE MASKING AREAS ARE AVAILABLE, USING FREEZE1/RESUME1, FREEZE2/RESUME2, FREEZE3/RESUME3, AND FREEZE4/RESUME4 REGISTERS. Figure 44. Using FREEZE/RESUME Rev. C | Page 36 of 92 05891-044 05891-043 AD9992 Hold Area Using FREEZE/RESUME Registers The FREEZE/RESUME registers can also be used to create a hold area in which the V-outputs are temporarily held and later continued, starting at the point where they were held. As shown in Figure 45, this is different from the VMASK_EN register because the V-outputs continue from where they stopped rather than from where they would have been. The hold area temporarily stops the pixel counter for the V-outputs, while the V-masking allows the counter to continue in the masking area. HD FREEZE HOLD AREA FOR GROUP A RESUME XV1 XV8 XV9 XV10 NOTES 1. WHEN HOLD = 1 FOR ANY V-SEQUENCE GROUP, THE FREEZE AND RESUME REGISTERS ARE USED TO SPECIFY THE HOLD AREA. 2. ABOVE EXAMPLE: XV1 TO XV10 ARE ASSIGNED TO GROUP A. HOLD BIT FOR GROUP A = 1. 3. H-COUNTER FOR GROUP A (XV1 TO XV10) STOPS DURING HOLD AREA. Figure 45. Hold Area for Group A Rev. C | Page 37 of 92 05891-045 AD9992 Special Pattern Insertion Additional flexibility is available using the SPC_PAT_EN registers, which allows a Group B, Group C, or Group D pattern to be inserted into a series of Group A repetitions. This feature is useful when a different pattern is needed at the start, end, or middle of a sequence. Figure 46 shows an example of a sweep region using VPATA with multiple repetitions where a single repetition of VPATB has been added into the middle of the sequence. Figure 47 shows more detail on how to set the registers to achieve the desired timing. Note that VREPB is used to specify which repetition number has the special pattern inserted instead of VPATA. VPATB always has priority over VPATC or VPATD if more than one SPC_PAT_EN bit is enabled (SPC_PAT_EN [0] has priority). VD SCP1 SCP2 HD LINE 0 LINE 1 LINE 2 LINE 24 LINE 25 XV1 TO XV24 REGION 0 REGION 1: SWEEP REGION REGION 2 05891-046 PATTERN B INSERTED DURING PATTERN A REPETITIONS Figure 46. Example of Special Pattern Insertion HD REP 1 REP 2 REP 3 REP 4 REP 5 REP N XV1 V-PATTERN A REGISTER SETTINGS: SPC_PAT_EN[0] = 1 VREPA = N VREPB = 4 V-PATTERN B V-PATTERN A DESCRIPTION: V-PATTERN B IS USED AS SPECIAL PATTERN TOTAL NUMBER OF REPS USED FOR SEQUENCE (N REPS) REP 4 USES V-PATTERN B INSTEAD OF V-PATTERN A 05891-047 NOTES 1. VSTARTB MUST BE SET EQUAL TO VSTARTA. Figure 47. Example of Special Pattern Insertion, Detail Rev. C | Page 38 of 92 AD9992 Complete Field: Combining V-Sequences After the V-sequences are created, they are combined to create different readout fields. A field consists of up to nine regions, and within each region, a different V-sequence can be selected. Figure 48 shows how the sequence change positions (SCP) designate the line boundary for each region and how the SEQ registers then select which V-sequence is used in each region. Registers to control the VSG outputs are also included in the field registers. Table 17 summarizes the registers used to create the fields. The SEQ registers, one for each region, select which V-sequences are active in each region. The MULT_SWEEP registers, one for each region, are used to enable sweep mode and/or multiplier mode in any region. The SCP registers create the line boundaries for each region. The VDLEN register specifies the total number of lines in the field. The HDLEN register specifies the total number of Table 17. Field Registers (CLPOB, PBLK Masking Shown in Table 10) Register SEQx MULT_SWEEP Length 5b 2b Range 0 to 31 V-sequence number 0 to 3 Description Selected V-sequence for each region in the field. Enables multiplier mode and/or sweep mode for each region. 0: Multiplier off, sweep off. 1: Multiplier off, sweep on. 2: Multiplier on, sweep off. 3: Multiplier on, sweep on. Sequence change position for each region. Total number of lines in each field. Length in pixels of the last HD line in each field. VSGPATSEL selects which V-pattern toggle positions are used. When set to 0, Toggle 1 and Toggle 2 are used. When set to 1, Toggle 3 and Toggle 4 are used. [0]: XV1 selection (0 = use XVTOG1, XVTOG2; 1 = use XVTOG3, XVTOG4). … [23]: XV24 selection. Set high to mask each individual VSG output. [0]: XV1 mask. … [23]: XV24 mask. Selects the line in the field where the VSG signals are active. Selects a second line in the field to repeat the VSG signals. If not used, set this equal to SGACTLINE1 or to the maximum value. pixels per line, and the HDLASTLEN register specifies the number of pixels in the last line of the field. The VPATSECOND register is used to add a second V-pattern group to the XV1 to XV10 outputs in the vertical sensor gate (VSG) line. The SGMASK register is used to enable or disable each individual VSG output. There are two bits for each VSG output to enable separate masking in SGACTLINE1 and SGACTLINE2. Setting a masking bit high masks the output; setting it low enables the output. The VSGPATSEL register assigns one of the eight SG patterns to each VSG output. Individual SG patterns are created separately using the SG pattern registers. The SGACTLINE1 register specifies which line in the field contains the VSG outputs. The optional SGACTLINE2 register allows the same VSG pulses to be repeated on a different line. Separate masking is not available for SGACTLINE1 and SGACTLINE2. SCP VDLEN HDLASTLEN VSGPATSEL 13b 13b 13b 24b 0 to 8191 line number 0 to 8191 lines 0 to 8191 pixels High/low SGMASK 24b High/low, each VSG SGACTLINE1 SGACTLINE2 13b 13b 0 to 8191 line number 0 to 8191 line number Rev. C | Page 39 of 92 AD9992 SCP0 SCP1 SCP2 SCP3 SCP4 SCP5 SCP8 VD REGION 0 HD REGION 1 REGION 2 REGION 3 REGION 4 REGION 8 XV1 TO XVN SEQ0 SEQ1 SGACTLINE1 SEQ2 SEQ3 SEQ4 SEQ8 VSG FIELD SETTINGS: 1. SEQUENCE CHANGE POSITIONS (SCP0 TO SCP8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD. 2. SEQ0 TO SEQ8 SELECT THE DESIRED V-SEQUENCE FOR EACH REGION. 3. SGACTLINE1 REGISTER SELECTS WHICH HD LINE IN THE FIELD CONTAINS THE SENSOR GATE PULSE(S). Figure 48. Complete Field Divided into Regions VD SCP1 SCP2 HD LINE 0 LINE 1 LINE 2 LINE 24 LINE 25 XV1 TO XVN REGION 0 REGION 1: SWEEP REGION REGION 2 05891-049 Figure 49. Example of Sweep Region for High Speed Vertical Shift Sweep Mode Operation The AD9992 contains an additional mode of vertical timing operation called sweep mode. This mode is used to generate a large number of repetitive pulses that span across multiple HD lines. An example of where this mode is needed is at the start of the CCD readout operation. At the end of the image exposure before the image is transferred by the sensor gate pulses, the vertical interline CCD registers should be free of all charge. This can be accomplished by quickly shifting out any charge using a long series of pulses from the vertical outputs. Depending on the vertical resolution of the CCD, up to 3000 clock cycles may be needed to shift the charge out of each vertical CCD line. This operation spans across multiple HD line lengths. Normally, the AD9992 vertical timing must be contained within one HD line length, but when sweep mode is enabled, the HD boundaries are ignored until the region is finished. To enable sweep mode within any region, program the appropriate SWEEP register to high. Figure 49 shows an example of the sweep mode operation. The number of vertical pulses needed depends on the vertical resolution of the CCD. The toggle positions for the XV1 to XV24 signals are generated using the V-pattern registers (shown in Table 13). A single pulse is created using the polarity and toggle position registers. The number of repetitions is then programmed to match the number of vertical shifts required by the CCD. Repetitions are programmed into the V-sequence registers (shown in Table 14) by using the VREP registers. This produces a pulse train of the appropriate length. Normally, the pulse train is truncated at the end of the HD line length, but when sweep mode is enabled for this region, the HD boundaries are ignored. In Figure 49, the sweep region occupies 23 HD lines. After the sweep mode region is complete, normal sequence operation resumes in the next region. When using sweep mode, be sure to set the region boundaries (using the sequence change positions) to the appropriate lines to prevent the sweep operation from overlapping the next V-sequence. Rev. C | Page 40 of 92 05891-048 AD9992 Multiplier Mode To generate very wide vertical timing pulses, a vertical region can be configured into a multiplier region. This mode uses the V-pattern registers in a slightly different manner. Multiplier mode can be used to support unusual CCD timing requirements, such as vertical pulses that are wider than the 13-bit V-pattern toggle position counter. In general, the 13-bit toggle position counter can be used with the sweep mode feature to support very wide pulses; however, multiplier mode can be used to generate even wider pulses. The start polarity and toggle positions are still used in the same manner as the standard V-pattern group programming, but VLEN is used differently. Instead of using the pixel counter (HD counter) to specify the toggle position locations (XVTOG1, XVTOG2, XVTOG3, and XVTOG4) of the V-pattern group, the VLEN is multiplied with the XVVTOG position to allow very long pulses to be generated. To calculate the exact toggle position, which is counted in pixels after the start position, use the following equation: Multiplier Mode Toggle Position = XVTOG × VLEN Table 18. Multiplier Mode Register Parameters Register MULTI VPOL XVTOG VLEN VREP Length 1b 1b 13b 13b 13b Range High/low High/low 0 to 8191 pixel location 0 to 8191 pixels 0 to 8191 pixel location Description High enables multiplier mode. Starting polarity of XV1 to XV10 signals in each V-pattern group. Toggle positions for XV1 to XV10 signals in each V-pattern group. Used as multiplier factor for toggle position counter. VREP_EVEN/VREP_ODD must be set to the same value as the highest XVTOG value. Because the XVTOG register is multiplied by VLEN, the resolution of the toggle position placement is reduced. If VLEN = 4, the toggle position precision is reduced to 4-pixel increments instead of to single-pixel increments. Table 18 summarizes how the V-pattern group registers are used in multiplier mode operation. In multiplier mode, the VREP registers must always be programmed to the same value as the highest toggle position. Figure 50 illustrates this operation. The first toggle position is 2, and the second toggle position is 9. In nonmultiplier mode, this causes the V-sequence to toggle at Pixel 2 and then at Pixel 9 within a single HD line. However, in multiplier mode, toggle positions are multiplied by the value of VLEN (in this case, 4); therefore, the first toggle occurs at Pixel 8, and the second toggle occurs at Pixel 36. Sweep mode has also been enabled to allow the toggle positions to cross the HD line boundaries. START POSITION OF VPAT GROUP IS STILL PROGRAMMED IN THE V-SEQUENCE REGISTERS HD 3 VLEN 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 5 5 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 PIXEL NUMBER 1 2 3 4 5 6 7 8 4 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 4 XV1 TO XV10 1 2 2 MULTIPLIER MODE V-PATTERN GROUP PROPERTIES: 1START POLARITY (STARTPOL = 0). 2FIRST, SECOND, AND THIRD TOGGLE POSITIONS (XVTOG1 = 2, XVTOG2 = 9). 3LENGTH OF VPAT COUNTER (VLEN = 4); THIS IS THE MINIMUM RESOLUTION FOR TOGGLE POSITION CHANGES. 4TOGGLE POSITIONS OCCUR AT LOCATION EQUAL TO (XVTOG × VLEN). 5IF SWEEP REGION IS ENABLED, THE V-PULSES MAY ALSO CROSS THE HD BOUNDRIES, AS SHOWN ABOVE. Figure 50. Example of Multiplier Region for Wide Vertical Pulse Timing Rev. C | Page 41 of 92 05891-050 AD9992 Vertical Sensor Gate (Shift Gate) Patterns In an interline CCD, the vertical sensor gate (VSG) pulses are used to transfer the pixel charges from the light-sensitive image area into light-shielded vertical registers. From the lightshielded vertical registers, the image is clocked out line-by-line using the vertical transfer pulses (XV signals) in conjunction with the high speed horizontal clocks. The AD9992 has 24 vertical signals, and each signal can be assigned as a VSG pulse instead of an XV pulse. Table 19 summarizes the VSG control registers, which are mostly located in the field registers space (see Table 17). The VSGSELECT register (Address 0x1C in the fixed address space) determines which vertical outputs are assigned as VSG pulses. When a signal is selected to be a VSG pulse, only the starting polarity and two of the V-pattern toggle positions are used. The VSGPATSEL register in the sequence registers is used to assign either XVTOG1 and XVTOG2 or XVTOG3 and XVTOG4 to the VSG signal. Note that only two of the four V-pattern toggle positions are available when a vertical signal is selected to be a VSG pulse. The SGACTLINE1 and SGACTLINE2 registers are used to select which line in the field is the VSG line. The VSG active line location is used to reference when the substrate clocking (SUBCK) signal begins to operate in each field. For more information, see the Substrate Clock Operation (SUBCK) section. Also located in the field registers, the SGMASK register selects which individual VSG pulses are active in a given field. Therefore, all SG patterns to be preprogrammed into the V-pattern registers and the appropriate pulses for the different fields can be enabled separately. Table 19. VSG Control Registers (Also see Field Registers in Table 17) Register VSGSELECT (Located in Fixed Address Space, 0x1C) Length 24b Range High/low Description Selection of VSG signals from XV signals. Set to 1 to make signal a VSG. [0]: XV1 selection (0 = XV pulse; 1 = VSG pulse). [1]: XV2 selection. … [23]: XV24 selection. When VSG signal is selected using the VSGSELECT register, VSGPATSEL selects which V-pattern toggle positions are used. When set to 0, Toggle 1 and Toggle 2 are used. When set to 1, Toggle 3 and Toggle 4 are used. [0]: XV1 selection (0 = use XVTOG1, XVTOG2; 1 = use XVTOG3, XVTOG4). [1]: XV2 selection. … [23]: XV24 selection. Set high to mask each individual VSG output. [0]: XV1 mask. … [23]: XV24 mask. Selects the line in the field where the VSG signals are active. Selects a second line in the field to repeat the VSG signals. If not used, set this equal to SGACTLINE1 or to the maximum value. VSGPATSEL 24b High/low SGMASK 24b High/low, each VSG SGACTLINE1 SGACTLINE2 13b 13b 0 to 8191 line number 0 to 8191 line number VD 4 HD 1 VSG PATTERN 2 3 05891-051 PROGRAMMABLE SETTINGS FOR EACH PATTERN: 1START POLARITY OF PULSE (FROM VPOL IN SEQUENCE REGISTERS). 2FIRST TOGGLE POSITION (FROM V-PATTERN REGISTERS). 3SECOND TOGGLE POSITION (FROM V-PATTERN REGISTERS). 4ACTIVE LINE FOR VSG PULSES WITHIN THE FIELD (FROM FIELD REGISTERS). Figure 51. Vertical Sensor Gate Pulse Placement Rev. C | Page 42 of 92 AD9992 MODE Registers The MODE registers are used to select the field timing of the AD9992. Typically, all of the field, V-sequence, and V-pattern information is programmed into the AD9992 at startup. During operation, the MODE registers allow the user to select any combination of field timing to meet the requirements of the system. The advantage of using the MODE registers in conjunction with preprogrammed timing is that it greatly reduces the system programming requirements during camera operation. Only a few register writes are required when the camera operating mode is changed, rather than having to program all of the vertical timing information with each camera mode change. A basic still camera application can require six fields of vertical timing—one for draft mode operation, one for autofocusing, and four for still image readout. All of the register timing information for the six fields is loaded at startup. Then, during camera operation, the MODE registers select which field timing is active, depending on how the camera is being used. Table 20 shows how the MODE registers are used. The MODE register (Address 0x2A) specifies how many total fields are used. Any value from 1 to 7 can be selected using these three bits. The other two registers (0x2B and 0x2C) are used to select Table 20. MODE Registers—VD Updated Address 2A 2B Name MODE FIELD0 FIELD1 FIELD2 FIELD3 FIELD4 FIELD5 FIELD6 Length 3b 5b 5b 5b 5b 5b 5b 5b Description Total number of fields to cycle through. Set from 1 to 7. Selected FIELD (from FIELD registers in configurable memory) for the first field to cycle through. Selected FIELD (from FIELD registers in configurable memory) for the second field to cycle through. Selected FIELD (from FIELD registers in configurable memory) for the third field to cycle through. Selected FIELD (from FIELD registers in configurable memory) for the fourth field to cycle through. Selected FIELD (from FIELD registers in configurable memory) for the fifth field to cycle through. Selected FIELD (from FIELD registers in configurable memory) for the sixth field to cycle through. Selected FIELD (from FIELD registers in configurable memory) for the seventh field to cycle through. which of the programmed fields are used and in which order. Up to seven fields can be used in a single MODE write. The AD9992 starts with the field timing specified by FIELD0 and, on the next VD, switches to the timing specified by FIELD1 and so on. After completing the total number of fields specified by MODE, the AD9992 repeats by starting at the first field. This continues until a new write to the MODE register occurs. Figure 54 shows example MODE register settings for different field configurations. Note that only a write to Address 0x2C properly resets the field counter. Therefore, when changing the values in any of the mode registers, it is recommended that all three registers be updated together in the same field (VD period). Caution The MODE registers are SCK updated by default. If they are configured as VD-updated registers by writing Address 0xB4 = 0x03FF and Address 0xB5 = 0xFC00, the new MODE information is updated on the second VD falling edge after the write occurs, rather than on the first VD falling edge (see Figure 53). 2C Rev. C | Page 43 of 92 AD9992 VD MODE WRITE REGISTER WRITE A MODE UPDATE MODE FIELD NUMBER 4 (DRAFT) 4 (DRAFT) 0 (STILL 1ST FIELD) 1 (STILL 2ND FIELD) 2 Figure 52. Update of MODE Register, SCK Updated (Default Setting) VD MODE WRITE REGISTER WRITE A B MODE UPDATE MODE FIELD NUMBER 4 (DRAFT) 4 (DRAFT) 0 (STILL 1ST FIELD) 1 (STILL 2ND FIELD) 2 EXAMPLE MODE REGISTER CHANGE: REGISTER WRITE A––WRITE TO MODE REGISTERS 0x2A, 0x2B, 0x2C TO SPECIFY CHANGE FROM DRAFT MODE (FIELD4) TO STILL MODE (FIELD0/1/2/3). REGISTER WRITE B––WRITE TO VGA GAIN OR ANY NEW REGISTER VALUES NEEDED FOR STILL FRAME OPERATION, SUCH AS NEW FIELD INFORMATION. 05891-053 NOTES 1. NEW MODE INFORMATION IS UPDATED AT SECOND VD FALLING EDGE AFTER SERIAL WRITE A. Figure 53. Update of MODE Register if Changed to VD-Updated Register EXAMPLE 1: TOTAL FIELDS = 3, FIRST FIELD = FIELD0, SECOND FIELD = FIELD1, THIRD FIELD = FIELD2 MODE SETTINGS: 0x2A = 0x3 0x2B = 0x820 0x2C = 0x0 FIELD0 FIELD1 FIELD2 EXAMPLE 2: TOTAL FIELDS = 1, FIRST FIELD = FIELD3 MODE SETTINGS: 0x2A = 0x1 0x2B = 0x3 0x2C = 0x0 FIELD3 EXAMPLE 3: TOTAL FIELDS = 4, FIRST FIELD = FIELD5, SECOND FIELD = FIELD1, THIRD FIELD = FIELD4, FOURTH FIELD = FIELD2 MODE SETTINGS: 0x2A = 0x4 0x2B = 0x11025 0x2C = 0x0 FIELD5 FIELD1 FIELD4 FIELD2 05891-054 Figure 54. Using the MODE Registers to Select Field Timing Rev. C | Page 44 of 92 05891-052 EXAMPLE MODE REGISTER CHANGE: REGISTER WRITE A––WRITE TO MODE REGISTERS 0x2A, 0x2B, 0x2C TO SPECIFY CHANGE FROM DRAFT MODE (FIELD4) TO STILL MODE (FIELD0/1/2/3). ALSO WRITE TO VGA GAIN OR ANY NEW REGISTER VALUES NEEDED FOR STILL FRAME OPERATION, SUCH AS NEW FIELD INFORMATION. AD9992 VERTICAL TIMING EXAMPLE To better understand how AD9992 vertical timing generation is used, consider the example CCD timing chart in Figure 55. This example illustrates a CCD using a general 3-field readout technique. As described in the Complete Field: Combining VSequences section, each readout field must be divided into separate regions to perform each step of the readout. The sequence change positions (SCP) determine the line boundaries for each region, and the SEQx registers assign a particular V-sequence to each region. The V-sequences contain the specific timing information required in each region: XV1 to XV6 pulses (using V-pattern groups), HBLK/CLPOB timing, and VSG patterns for the SG active lines. This timing example requires four regions for each of the three fields, labeled Region 0, Region 1, Region 2, and Region 3. Because the AD9992 allows many individual fields to be programmed, FIELD0, FIELD1, and FIELD2 can be used to meet the requirements of this timing example. The four regions for each field are very similar in this example, but the individual registers for each field allow flexibility to accommodate other timing charts. Region 0 is a high speed, vertical shift region. Sweep mode can be used to generate this timing operation with the desired number of high speed vertical pulses needed to clear any charge from the CCD vertical registers. Region 1 consists of only two lines and uses standard singleline, vertical shift timing. The timing of this region is the same as the timing in Region 3. Region 2 is the sensor gate line where the VSG pulses transfer the image into the vertical CCD registers. This region may require the use of the second V-pattern group for the SG active line. Region 3 also uses the standard single-line, vertical shift timing, the same timing as Region 1. Four regions are required in each of the three fields. The timing for Region 1 and Region 3 is essentially the same, reducing the complexity of the register programming. Other registers need to be used during the actual readout operation. These include the MODE registers, shutter control registers (PRIMARY_ACTION, SUBCK, GPO for MSHUT, and VSUB control), and AFE gain register. Important Note Regarding Signal Polarities When programming the AD9992 to generate the XV1 to XV24 and SUBCK signals, the external V-driver circuit usually inverts these signals. Carefully check the required timing signals needed at the input and the output of the V-driver circuit being used and adjust the polarities of the AD9992 outputs accordingly. Rev. C | Page 45 of 92 AD9992 EXPOSURE (tEXP) FIRST FIELD READOUT THIRD FIELD READOUT SECOND FIELD READOUT VD HD XV1 XV2 XV3 XV4 XV5 XV6 2 5 8 11 14 17 20 N–4 N–1 Figure 55. CCD Timing Example—Dividing Each Field into Regions REGION 0 REGION 1 FIELD 0 REGION 2 REGION 3 N–5 N–2 REGION 0 REGION 1 REGION 3 REGION 2 FIELD 1 REGION 0 REGION 1 REGION 3 REGION 2 FIELD 2 05891-055 N–3 N CCD OUT 1 4 7 10 13 16 3 6 9 12 15 18 21 Rev. C | Page 46 of 92 SUBCK MSHUT OPEN OPEN CLOSED VSUB AD9992 SHUTTER TIMING CONTROL The AD9992 supports the generation of electronic shuttering (SUBCK) and also features flexible general-purpose outputs (GPO) to control mechanical shuttering, CCD substrate bias switching, and strobe circuitry. In the following documentation, the terms sense gate (SG) and vertical sense gate (VSG) are used interchangeably. SUBCK: Low Speed Operation Normal and high precision shutter operations are used when the exposure time is less than 1 field. For exposure times greater than 1 field, the low speed (LS) shutter features can be used. The AD9992 includes a field counter (primary field counter) to regulate long exposure times. The primary field counter must be activated (Address 0x70) to serve as the trigger for the LS operation. The durations of the LS exposure and read are specified by the SGMASK_NUM and SUBCKMASK_NUM register (Address 0x74), respectively. As shown in Figure 58, this mode suppresses the SUBCK and VSG outputs for up to 8192 fields (VD periods). To activate an LS shutter operation, trigger the start of the exposure by writing to the PRIMARY_ACTION register bits according to the desired effect. When the primary counter is activated, the next VD period becomes the first active period of the exposure for which the VSG and SUBCK masks are applied. Optionally, if the SUBCKMASK_SKIP1 register is enabled, the AD9992 ignores the first VSG and SUBCK masks in subsequent fields. This is generally desired so that the exposure time begins in the field after the exposure operation is initiated. Figure 58 shows operation with SUBCKMASK_SKIP1 = 1. If the PRIMARY_ACTION register is used while the SUBCKMASK_NUM and SGMASK_NUM registers are set to 0, the behavior of the SUBCK and VSG signals are not different from the normal shutter or high precision shutter operations. Therefore, the primary field counter can be used for other tasks (described in the General-Purpose Outputs (GPOs) section) without disrupting the normal activity. In addition, there exists a secondary field counter that has no effect on the SUBCK and VSG signals. These counters are described in detail in the Field Counters section. SUBSTRATE CLOCK OPERATION (SUBCK) The CCD image exposure time is controlled by the substrate clock signal (SUBCK), which pulses the CCD substrate to clear out accumulated charge. The AD9992 supports three types of electronic shuttering: normal, high precision, and low speed. Along with the SUBCK pulse placement, the AD9992 can accommodate different readout configurations to further suppress the SUBCK pulses during multiple field readouts. The SUBCK signal is a programmable string of pulses, each occupying a line following the primary sense gate active line, SGACTLINE1 (registers are shown in Table 21). The SUBCK signal has programmable pulse width, line placement, and number of pulses to accurately control the exposure time. SUBCK: Normal Operation By default, the AD9992 operates in the normal SUBCK configuration, in which the SUBCK signal is pulsing in every VD field (see Figure 56). The SUBCK pulse occurs once per line, and the total number of repetitions within the field determines the length of the exposure time. The SUBCK pulse polarity and toggle positions within a line are programmable using the SUBCK_POL and SUBCK_TOG1 registers (see Table 21). The number of SUBCK pulses per field is programmed in the SUBCKNUM register (Address 0x75). As shown in Figure 56, the SUBCK pulses always begin in the line following the SG-active line, which is specified in the SGACTLINE registers for each field. The SUBCK_POL, SUBCK_TOG1, SUBCK_TOG2, SUBCKNUM, and SUBCKSTARTLINE registers are updated at the start of the line after the sensor gate line, as described in the Updating New Register Values section. SUBCK Start Line By default, the SUBCK pulses begin in the line following SGACTLINE1. For applications where the SUBCK pulse should be suppressed for one or more lines following the VSG line, the SUBCKSTARTLINE register can be programmed. This register setting delays the start of the SUBCK pulses until the specified number of lines following SGACTLINE1. SUBCK: High Precision Operation High precision shuttering is used in the same manner as normal shuttering but uses an additional register to control the last SUBCK pulse. In this mode, the SUBCK still pulses once per line, but the last SUBCK in the field has an additional SUBCK pulse, whose location is determined by the SUBCKHP_TOG registers, as shown in Figure 57. Finer resolution of the exposure time is possible using this mode. Leaving the SUBCKHP_TOG registers set to its maximum value (0xFFFFFF) disables the last SUBCK pulse (default setting). Caution A value of 1 should not be used in the SUBCKSTARTLINE register. A value of 0 is used to specify the SUBCK pulses to begin in the next line after the SG line. A value of 2 is used to specify the SUBCK pulses to begin two lines after the SG line, and so on. Rev. C | Page 47 of 92 AD9992 Read After Exposure To read the CCD data after exposure, the SG should resume normal activity while the SUBCK remains null. By default, the AD9992 generates the VSG pulses in every field. When only a single exposure and a single frame read are desired, such as is the case in the preview mode, the VSG and SUBCK pulses can operate in every field. Other applications require that more frames are read, in which case SUBCK must be masked until the readout is finished. Table 21. SUBCK and Exposure/Read Register Parameters Register SGMASK_NUM SUBCKMASK_NUM SUBCKMASK_SKIP1 SUBCKSTARTLINE 1 SUBCKNUM1 SG_SUPPRESS1 SUBCK_TOG1 SUBCK_TOG2 SUBCK_POL SUBCKHP_TOG1 SUBCKHP_TOG2 1 The SUBCKMASK_NUM register specifies the total number of fields (exposure and read) to mask SUBCK. A 2-field CCD frame read mode typically requires two additional fields of SUBCK masking (SUBCKMASK_NUM = 2). A 3-field, 6-phase CCD requires three additional fields of SUBCK masking after the read begins (SUBCKMASK_NUM = 3). Note that the SUBCKMASK_SKIP1 register setting allows SUBCK pulses at the beginning of the field of exposure. Length 13b 13b 1b 13b 13b 1b 13b 13b 1b 13b 13b Range 0 to 8191 fields 0 to 8191 fields On/off 0, 2 to 8191 line locations 1 to 8191 pulses On/off 0 to 8191 pixel locations 0 to 8191 pixel locations Low/high 0 to 8191 pixel locations 0 to 8191 pixel locations Description Exposure duration (number of fields to suppress VSG) for LS operation. Exposure plus readout duration (number of fields to suppress SUBCK) for LS. Suppress SG/SUBCK masks for one field (default = 0). Typically set to 1. Line location to start the SUBCK pulses, relative to SGLINE location. A value of 1 is invalid. See the SUBCK Start Line section. Total number of SUBCKs per field, at 1 pulse per line. Must be