MPC9992AC

Freescale Semiconductor Technical Data 3.33.3 V Differential ECL/PECL PLL V Differential ECL/PECL PLL Clock Generator Clock Generator The MPC9992 is a 3.3 V compatible, PLL based PECL clock driver. Using SiGe technology and a fully differential design ensures optimum skew and PLL jitter performance. The performance of the MPC9992 makes the device ideal for workstation, mainframe computer and telecommunication applications. With output frequencies up to 400 MHz and output skews less than 100 ps the device meets the needs of the most demanding clock applications. The MPC9992 offers a differential PECL input and a crystal oscillator interface. All control signals are LVCMOS compatible. MPC9992 DATA Rev 5, SHEET 06/2005 MPC9992 MPC9992 3.3 V DIFFERENTIAL ECL/PECL CLOCK GENERATOR Features • • • • • • • • • • • 7 differential outputs, PLL based clock generator SiGe technology supports minimum output skew (max. 100 ps) Supports up to two generated output clock frequencies with a maximum clock frequency up to 400 MHz Selectable crystal oscillator interface and PECL compatible clock input SYNC pulse generation PECL compatible differential clock inputs and outputs Single 3.3 V (PECL) supply Ambient temperature range 0°C to +70°C Standard 32 lead LQFP package Pin and function compatible to the MPC992 32-lead Pb-free Package Available FA SUFFIX 32-LEAD LQFP PACKAGE CASE 873A-04 AC SUFFIX 32-LEAD LQFP PACKAGE Pb-FREE PACKAGE CASE 873A-04 Functional Description The MPC9992 utilizes PLL technology to frequency lock its outputs onto an input reference clock. The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match the VCO frequency range. The MPC9992 features frequency programmability between the three output banks outputs as well as the output to input relationships. Output frequency ratios of 2:1, 3:1, 3:2 and 5:2 can be realized. The two banks of outputs and the feedback frequency divider can be programmed by the FSEL[2:0] pins of the device. The VCO_SEL pin provides an extended PLL input reference frequency range. The SYNC pulse generator monitors the phase relationship between the QA[3:0] and QB[2:0] output banks. The SYNC generator output signals the coincident edges of the two output banks. This feature is useful for non binary relationships between output frequencies. The REF_SEL pin selects the differential PECL compatible input pair or crystal oscillator interface as the reference clock signal. The PLL_EN control selects the PLL bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics do not apply. The MPC9992 requires an external reset signal for start-up and for PLL recovery in case the reference input is interrupted. Assertion of the reset signal forces all outputs to the logic low state. The MPC9992 is fully 3.3 V compatible and requires no external loop filter components. The differential clock input (PCLK) is PECL compatible and all control inputs accept LVCMOS compatible signals while the outputs provide PECL compatible levels with the capability to drive terminated 50 Ω transmission lines. The device is pin and function compatible to the MPC992 and is packaged in a 32-lead LQFP package. IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator © Freescale Semiconductor, Inc., 2005. All rights reserved. Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, Inc 1 MPC9992 MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator VCC XTAL_IN XTAL_OUT NETCOM Bank A All input resistors have a value of 50kΩ XTAL 1 0 PCLK PCLK Ref ÷4 VCO ÷2 PLL 800–1600 MHz VCC 1 0 QA1 QA1 0 ÷2, ÷4 1 ÷4, ÷6, ÷10 QA2 QA2 ÷16, ÷24, ÷40 QA3 QA3 Sync Pulse Bank B REF_SEL FB VCC VCO_SEL PLL_EN FSEL[1:0] QA0 QA0 QB0 QB0 QB1 QB1 QB2 QB2 VCC 2 Sync QSYNC QSYNC MR/STOP VCC QA2 QA2 QA3 QA3 QSYNC QSYNC VCC Figure 1. MPC9992 Logic Diagram 24 23 22 21 20 19 18 17 QA1 25 16 QB0 QA1 26 15 QB0 QA0 27 14 QB1 QA0 28 13 QB1 GND 29 12 QB2 VCC_PLL 30 11 QB2 MR/STOP 31 10 PLL_EN VCC 32 MPC9992 2 3 4 5 6 7 8 VCO_SEL FSEL0 FSEL1 REF_SEL PCLK PCKL XTAL_IN XTAL_OUT 9 1 GND Figure 2. MPC9992 32-Lead Package Pinout (Top View) IDT™ 3.3MPC9992 V Differential ECL/PECL PLL Clock Generator MPC9992 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, IncAdvanced Clock Drivers Device Data 2 Freescale Semiconductor 2 MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator NETCOM Table 1. MPC9992 PLL Configurations Frequency Ratio QA to QB Internal Feedback (M ⋅ VCO_SEL) VCO÷12 (4 ⋅ fREF) 3÷2 VCO÷48 VCO÷4 (8 ⋅ fREF) VCO÷8 (4 ⋅ fREF) 2÷1 VCO÷32 10–20 VCO÷8 (10 ⋅ fREF) VCO÷20 (4 ⋅ fREF) 5÷2 VCO÷80 1 16.6–33.3 VCO÷4 (12 ⋅ fREF) VCO÷12 (4 ⋅ fREF) 3÷1 VCO÷48 0 0 8.3–16.6 VCO÷16 (6 ⋅ fREF) VCO÷24 (4 ⋅ fREF) 3÷2 VCO÷96 1 0 1 12.5–25 VCO÷8 (8 ⋅ fREF) VCO÷16 (4 ⋅ fREF) 2÷1 VCO÷64 1 1 0 5–10 VCO÷16 (10 ⋅ fREF) VCO÷40 (4 ⋅ fREF) 5÷2 VCO÷160 1 1 1 8.3–16.6 VCO÷8 (12 ⋅ fREF) VCO÷24 (4 ⋅ fREF) 3÷1 VCO÷96 VCO_SEL FSEL_0 FSEL_1 fREF (MHz) QA[3:0] (NA) QB[2:0] (NB) 0 0 0 16.6–33.3 VCO÷8 (6 ⋅ fREF) 0 0 1 25–50 0 1 0 0 1 1 Table 2. Function Table (Configuration Controls) Control Default 0 1 REF_SEL 1 Selects PCLK, PCLK as PLL references signal input Selects the crystal oscillator as PLL reference signal input VCO_SEL 1 Selects VCO÷2. The VCO frequency is scaled by a factor Selects VCO÷4. The VCO frequency is scaled by a factor of 2 (high input frequency range) of 4 (low input frequency range). PLL_EN 1 Test mode with the PLL bypassed. The reference clock is Normal operation mode with PLL enabled. substituted for the internal VCO output. MPC9992 is fully static and no minimum frequency limit applies. All PLL related AC characteristics are not applicable. MR/STOP 0 Normal operation Reset of the device and output disable (output clock stop). The outputs are stopped in logic low state: Qx=L, Qx=H. The minimum reset period should be greater than one reference clock cycle. VCO_SEL and FSEL[1:0] control the operating PLL frequency range and input/output frequency ratios. See Table 1 for the device frequency configuration. Table 3. Pin Configuration Pin PCLK, PCLK I/O Input XTAL_IN, XTAL_OUT Type Function PECL Differential reference clock signal input Analog Crystal oscillator interface VCO_SEL Input LVCMOS VCO operating frequency select PLL_EN Input LVCMOS PLL Enable/Bypass mode select REF_SEL Input LVCMOS PLL reference signal input select MR/STOP Input LVCMOS Device reset and output clock disable (stop in logic low state) FSEL[1:0] Input LVCMOS Output and PLL feedback frequency divider select QA[0-3], QA[0–3] Output PECL Differential clock outputs (bank A) QB[0-2], QB[0–2] Output PECL Differential clock outputs (bank B) QSYNC, QSYNC Output PECL Differential clock outputs (bank C) GND Supply GND Negative power supply VCC Supply VCC Positive power supply. All VCC pins must be connected to the positive power supply for correct DC and AC operation VCC_PLL Supply VCC PLL positive power supply (analog power supply). It is recommended to use an external RC filter for the analog power supply pin VCC_PLL. Please see applications section for details IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Clock Drivers Device Data FreescaleAdvanced Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor 3 MPC9992MPC9992 3 MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator NETCOM Table 4. Absolute Maximum Ratings(1) Symbol Characteristics Min Max Unit VCC Supply Voltage –0.3 3.9 V VIN DC Input Voltage –0.3 VCC+0.3 V DC Output Voltage –0.3 VOUT IIN IOUT TS VCC+0.3 V DC Input Current ±20 mA DC Output Current ±50 mA 125 °C Storage Temperature –65 Condition 1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied. Table 5. General Specifications Symbol Characteristics Min Typ Max VTT Output Termination Voltage MM ESD Protection (Machine Model) 175 V HBM ESD Protection (Human Body Model) 2000 V CDM ESD Protection (Charged Device Model) 1000 V 200 LU Latch-Up Immunity CIN Input Capacitance θJA Thermal Resistance Junction to Ambient JESD 51-3, single layer test board VCC – 2 Unit θJC Thermal Resistance Junction to Case TJ Operating Junction Temperature(1) (continuous operation) MTBF = 9.1 years V mA 4.0 JESD 51-6, 2S2P multilayer test board 0 Condition pF Inputs 83.1 73.3 68.9 63.8 57.4 86.0 75.4 70.9 65.3 59.6 °C/W °C/W °C/W °C/W °C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 59.0 54.4 52.5 50.4 47.8 60.6 55.7 53.8 51.5 48.8 °C/W °C/W °C/W °C/W °C/W Natural convection 100 ft/min 200 ft/min 400 ft/min 800 ft/min 23.0 26.3 °C/W MIL-SPEC 883E Method 1012.1 110 °C 1. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are specified up to 110°C junction temperature allowing the MPC9992 to be used in applications requiring industrial temperature range. It is recommended that users of the MPC9992 employ thermal modeling analysis to assist in applying the junction temperature specifications to their particular application. IDT™ 3.3MPC9992 V Differential ECL/PECL PLL Clock Generator MPC9992 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, IncAdvanced Clock Drivers Device Data 4 Freescale Semiconductor 4 MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator NETCOM Table 6. DC Characteristics (VCC = 3.3 V ± 5%, GND = 0V, TA = 0°C to 70°C) Symbol Characteristics Differential PECL Clock Inputs (PCLK, VPP VCMR IIN AC Differential Input Voltage(2) Differential Cross Point Min Typ Max Unit Condition 0.2 1.3 V Differential operation 1.0 VCC-0.3 V Differential operation ±120 µA VIN = VCC or GND VCC + 0.3 V LVCMOS 0.8 V LVCMOS ±120 µA VIN = VCC or GND PCLK)(1) Voltage(3) Input Current(4) LVCMOS Control Inputs (VCO_SEL, PLL_EN, MR/STOP, REF_SEL, FSEL[1:0]) VIH Input High Voltage VIL Input Low Voltage IIN Input 2.0 Current(4) PECL Clock Outputs (QA[3:0], QA[3:0], QB[2:0], QB[2:0], QSYNC, QSYNC) VOH Output High Voltage VCC–1.025 VCC–0.880 V IOH = –30 mA VOL Output Low Voltage VCC–1.920 VCC–1.620 V IOL = –5 mA 2.955 VCC V VCC_PLL pin Supply Current and Voltage VCC_PLL PLL Supply Voltage ICC_PLL Maximum PLL Supply Current 9.0 12 mA VCC_PLL pin IGND(5) Maximum Supply Current 80 110 mA GND pins 1. VPP (DC) is the minimum differential input voltage swing required to maintain device functionality. 2. VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR (DC) range and the input swing lies within the VPP (DC) specification. 3. Inputs have pull-down resistors affecting the input current. 4. Equivalent to a termination of 50 Ω to VTT. 5. Does not include output drive current which is dependant on output termination methods. IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Clock Drivers Device Data FreescaleAdvanced Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor 5 MPC9992MPC9992 5 MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator NETCOM Table 7. AC Characteristics (VCC = 3.3 V ± 5%, GND = 0 V, TA = 0°C to +70°C)(1) Symbol fref Characteristics Min ÷32 feedback ÷48 feedback ÷64 feedback ÷80 feedback ÷96 feedback ÷160 feedback Input Reference Frequency Typ Max Unit 50.0 33.3 25.0 20.0 16.67 10.0 MHz MHz MHz MHz MHz MHz PLL locked 400 MHz PLL bypass 20 MHz 800 1600 MHz 200.0 100.0 66.6 50.0 40.0 33.3 16.6 400.0 200.0 133.3 100.0 80.0 66.6 33.3 MHz MHz MHz MHz MHz MHz MHz 25.0 16.67 12.5 10.0 8.33 5.0 Input Reference Frequency in PLL Bypass Mode(2) fXTAL Crystal Interface Frequency Range(3) fVCO VCO Frequency Range(4) fMAX Output Frequency VPP Differential Input Voltage(5) (peak-to-peak) VCMR VO(P-P) tPW,MIN tsk(O) DC 0.3 1.3 V (PCLK) 1.2 VCC–0.3 V Differential Output Voltage (peak-to-peak) (PCLK) 0.6 Input Reference Pulse Width Period Jitter(9) tr, tf ns 100 ps 52 % 30 79 ps 43 106 ps RMS (1 σ)(10) 86 212 ps ÷32 feedback ÷48 feedback ÷64 feedback ÷80 feedback ÷96 feedback ÷160 feedback 0.60-1.5 0.40-1.2 0.30-1.0 0.30-0.8 0.20-0.7 0.15-0.4 48 (9) I/O Phase Jitter(9) PLL Closed Loop Bandwidth (11) Maximum PLL Lock Time Output Rise/Fall Time 0.05 PLL locked V 2.0 Output Duty Cycle(8) Cycle-to-Cycle Jitter tLOCK (7) 0.8 Output-to-Output Skew tJIT(CC) BW ÷4 output ÷8 output ÷12 output ÷16 output ÷20 output ÷24 output ÷48 output Differential Input Crosspoint Voltage(6) tJIT(PER) tJIT(∅) 10 Condition 50 MHz MHz MHz MHz MHz MHz 10 ms 1.0 ns 20% to 80% 1. AC characteristics apply for parallel output termination of 50 Ω to VTT. 2. In bypass mode, the MPC9992 divides the input reference clock. 3. The crystal frequency range must both meet the interface frequency range and VCO lock range divided by the feedback divider ratio: fXTAL(min, max) = fVCO(min, max) ÷ (M ⋅ VCO_SEL) and 10 MHz ≤ fXTAL ≤ 20 MHz. 4. The input reference frequency must match the VCO lock range divided by the total feedback divider ratio: fref = fVCO ÷ (M ⋅ VCO_SEL) 5. VPP is the minimum differential input voltage swing required to maintain AC characteristics. 6. VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR (AC) range and the input swing lies within the VPP (AC) specification. 7. Calculation of reference duty cycle limits: DCREF,MIN = tPW,MIN ⋅ fREF ⋅ 100% and DCREF,MAX = 100% – DCREF, MIN. E.g. at fREF = 50 MHz the input duty cycle range is 10% < DC < 90%. 8. Output duty cycle for QAx and QBx outputs. The pulse width for the QSYNC output is equal to one QAx output period tQA ± 5%. 9. Jitter data is valid fref = 25 MHz. 10. See application section for a jitter calculation for other confidence factors than 1 σ. 11. –3 dB point of PLL transfer characteristics. IDT™ 3.3MPC9992 V Differential ECL/PECL PLL Clock Generator MPC9992 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, IncAdvanced Clock Drivers Device Data 6 Freescale Semiconductor 6 MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator NETCOM APPLICATIONS INFORMATION SYNC Output Description The MPC9992 has a system synchronization pulse output QSYNC. In configurations with the output frequency relationships are not integer multiples of each other QSYNC provides a signal for system synchronization purposes. The MPC9992 monitors the relationship between the A bank and the B bank of outputs. The QSYNC output is asserted (logic high) one QA period in duration. The placement of the pulse is dependent on the QA and QB output frequencies ratio. Figure 3 shows the waveforms for the QSYNC output. The QSYNC output is defined for all possible combinations of the bank A and bank B outputs. 2:1 Mode Qa Qb QSYNC 3:1 Mode Qa Qb QSYNC 3:2 Mode Qa Qb QSYNC 5:2 Mode Qa Qb QSYNC Figure 3. QSYNC Timing Diagram IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Clock Drivers Device Data FreescaleAdvanced Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor 7 MPC9992MPC9992 7 MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator Power Supply Filtering The MPC9992 is a mixed analog/digital product. Its analog circuitry is naturally susceptible to random noise, especially if this noise is seen on the power supply pins. Random noise on the VCC_PLL power supply impacts the device characteristics, for instance I/O jitter. The MPC9992 provides separate power supplies for the output buffers (VCC) and the phase-locked loop (VCC_PLL) of the device. The purpose of this design technique is to isolate the high switching noise digital outputs from the relatively sensitive internal analog phase-locked loop. In a digital system environment where it is more difficult to minimize noise on the power supplies a second level of isolation may be required. The simple but effective form of isolation is a power supply filter on the VCC_PLL pin for the MPC9992. Figure 4 illustrates a typical power supply filter scheme. The MPC9992 frequency and phase stability is most susceptible to noise with spectral content in the 100 kHz to 20 MHz range. Therefore the filter should be designed to target this range. The key parameter that needs to be met in the final filter design is the DC voltage drop across the series filter resistor RF. From the data sheet the ICC_PLL current (the current sourced through the VCC_PLL pin) is typically 9 mA (12 mA maximum), assuming that a minimum of 2.955 V must be maintained on the VCC_PLL pin. The resistor RF shown in Figure 4 must have a resistance of 10-15 Ω to meet the voltage drop criteria. Differential Pulse Generator Z = 50 Ω NETCOM RF = 10 – 15Ω CF = 22 µF RF VCC VCC_PLL CF 10 nF MPC9992 VCC 33...100 nF Figure 4. VCC_PLL Power Supply Filter The minimum values for RF and the filter capacitor CF are defined by the required filter characteristics: the RC filter should provide an attenuation greater than 40 dB for noise whose spectral content is above 100 kHz. In the example RC filter shown in Figure 4, the filter cut-off frequency is around 3-5 kHz and the noise attenuation at 100 kHz is better than 42 dB. As the noise frequency crosses the series resonant point of an individual capacitor its overall impedance begins to look inductive and thus increases with increasing frequency. The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL. Although the MPC9992 has several design features to minimize the susceptibility to power supply noise (isolated power and grounds and fully differential PLL) there still may be applications in which overall performance is being degraded due to system power supply noise. The power supply filter schemes discussed in this section should be adequate to eliminate power supply noise related problems in most designs. Z = 50 Ω Z = 50 Ω RT = 50 Ω MPC9992 DUT RT = 50 Ω VTT VTT Figure 5. MPC9992 AC Test Reference IDT™ 3.3MPC9992 V Differential ECL/PECL PLL Clock Generator MPC9992 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, IncAdvanced Clock Drivers Device Data 8 Freescale Semiconductor 8 MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator NETCOM PACKAGE DIMENSIONS PAGE 1 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Clock Drivers Device Data FreescaleAdvanced Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor 9 MPC9992MPC9992 9 MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator NETCOM PACKAGE DIMENSIONS PAGE 2 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE IDT™ 3.3MPC9992 V Differential ECL/PECL PLL Clock Generator MPC9992 Freescale Timing Solutions Organization has been acquired by Integrated Device Technology, IncAdvanced Clock Drivers Device Data 10 Freescale Semiconductor 10 MPC9992 3.3 V Differential ECL/PECL PLL Clock Generator NETCOM PACKAGE DIMENSIONS PAGE 3 OF 3 CASE 873A-04 ISSUE C 32-LEAD LQFP PACKAGE IDT™ 3.3 V Differential ECL/PECL PLL Clock Generator Clock Drivers Device Data FreescaleAdvanced Timing Solutions Organization has been acquired by Integrated Device Technology, Inc Freescale Semiconductor 11 MPC9992MPC9992 11 MPC9992 MPC92459 PART NUMBERS 900 3.3 VMHz Differential Low Voltage ECL/PECL LVDS PLL Clock Clock Synthesizer Generator INSERT PRODUCT NAME AND DOCUMENT TITLE NETCOM NETCOM Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 netcom@idt.com 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited Prime House Barnett Wood Lane Leatherhead, Surrey United Kingdom KT22 7DE +44 1372 363 339 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA XX-XXXX-XXXXX