AD9993-EBZ

Integrated Mixed-Signal Front End (MxFE) AD9993 Data Sheet FEATURES GENERAL DESCRIPTION Quad 14-bit 250 MSPS ADC SFDR = 83 dBc at 87 MHz input Dual 14-bit 500 MSPS DAC SFDR = 75 dBc at 20 MHz output On-chip PLL clock synthesizer Low power 1536 mW, 1 GHz master clock, on-chip synthesizer 500 MHz double data rate (DDR) LVDS interfaces for DACs and ADCs Small 12 mm × 12 mm lead-free BGA package The AD9993 is a mixed-signal front-end (MxFE®) device that integrates four 14-bit ADCs and two 14-bit DACs. Figure 1 shows the block diagram of the MxFE. The MxFE is programmable using registers accessed via a serial peripheral interface (SPI). ADC and DAC datapaths include FIFO buffers to absorb phase differences between LVDS lane clocks and the data converter sampling clocks. APPLICATIONS The MxFE DACs are part of the Analog Devices, Inc., high speed CMOS DAC core family. These DACs are designed to be used in wide bandwidth communication system transmitter (Tx) signal chains. Point to point microwave backhaul radios Wireless repeaters The MxFE ADCs are multistage pipelined CMOS ADC cores designed for use in communications receivers. FUNCTIONAL BLOCK DIAGRAM 2 ADC_A 14 DOUT3A_x TO DOUT0A_x 14 DOUT3B_x TO DOUT0B_x 4 2 ADC_B 14 DCO CLOCK DOUT3C_x TO DOUT0C_x LVDS BUFFER DOUT3D_x TO DOUT0D_x DCO_x STROBE 2 ADC_C 2 ADC_D 2 DAC_A 14 STROBE_x DIGITAL –ADC AND DAC DATAPATHS –CONTROLS –SPI REGISTERS –FIFO BUFFERS 14 14 DCI CLOCK DIN6A_x TO DIN0A_x LVDS BUFFER DIN6B_x TO DIN0B_x DCI_x 14 4 SPI_SCLK, SPI_CS, SPI_SDI, SPI_SDO RST 0 1 31.25MHz OR 62.5MHz DIV 250MHz CLOCK GENERATOR MxFE AD9993 12260-001 PLL ALERT 500MHz 500MHz DAC_B 14 250MHz 2 1GHz Figure 1. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014–2017 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9993 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 LVDS Interface Timing.............................................................. 22 Applications ....................................................................................... 1 LVDS Lane Testing Using PRBS ............................................... 23 General Description ......................................................................... 1 Power Mode Programming ....................................................... 23 Functional Block Diagram .............................................................. 1 Interrupt Request Operation .................................................... 23 Revision History ............................................................................... 3 Temperature Sensor ................................................................... 23 Specifications..................................................................................... 4 Start-Up Register Sequences ......................................................... 25 DC Specifications ......................................................................... 4 AC Specifications.......................................................................... 5 Power-Up Routine When Using the On-Chip Clock Synthesizer .................................................................................. 25 Digital Specifications ................................................................... 5 Power-Up Routine When Using External Clock ................... 25 Absolute Maximum Ratings ............................................................ 7 Applications Information .............................................................. 27 Thermal Resistance ...................................................................... 7 Direct Conversion Radio Application ..................................... 27 ESD Caution .................................................................................. 7 Register Map ................................................................................... 28 Pin Configuration and Function Descriptions ............................. 8 Register Descriptions ..................................................................... 30 Typical Performance Characteristics ........................................... 11 SPI Configuration Register ....................................................... 30 Receiver ADC Performance ...................................................... 11 Chip ID Register ......................................................................... 30 Transmitter DAC Performance................................................. 13 Chip Grade Register ................................................................... 31 Terminology .................................................................................... 15 Device Index Register ................................................................ 31 Theory of Operation ...................................................................... 16 Power Mode Control Register .................................................. 32 Product Description ................................................................... 16 Align ADC LVDS Clocks, ADC FIFO, DAC FIFO Register 32 SPI Port ........................................................................................ 16 Strobe Lane Control Register.................................................... 33 SPI Configuration Programming ............................................. 17 Output Mode Register ............................................................... 33 Register Update Transfer Method ............................................ 17 LVDS Tx Control Register ........................................................ 34 ADC Register Update Indexing ................................................ 17 VREF Control Register ................................................................. 34 ADCs ............................................................................................ 17 PRBS Generator Control Register ............................................ 35 ADC Architecture ...................................................................... 17 8-Bit Seed MSB of PRBS Generator for Lane 0 Register ....... 35 ADC Section Programming ...................................................... 17 8-Bit Seed MSB of PRBS Generator for Lane 1 Register ....... 36 Analog Input Considerations.................................................... 17 8-Bit Seed MSB of PRBS Generator for Lane 2 Register ....... 36 DACs ............................................................................................ 18 8-Bit Seed MSB of PRBS Generator for Lane 3 Register ....... 36 DAC Transfer Function ............................................................. 18 Synthesizer Status Register ........................................................ 37 DAC Output Compliance Voltage Range and AC Performance ................................................................................ 18 Loop Filter Control Signals Register........................................ 37 DAC Voltage Reference ............................................................. 19 Loop Filter Control Signals Register........................................ 38 DAC Gain Setting ....................................................................... 19 Integer Value of Synthesizer Divider Register ........................ 39 DAC Datapath Format Selection .............................................. 19 Synthesizer Control Register .................................................... 39 DAC Test Tone Generator DDS................................................ 19 Clock Generator Control Register ........................................... 39 Clocking ....................................................................................... 20 CLKGEN Control Register ....................................................... 40 On-Chip PLL Clock Multiplier ................................................ 20 DAC LVDS Rx Control Register .............................................. 40 Selecting Clocking Options....................................................... 21 DAC LVDS Current Bias Control Register ............................. 41 ADC Datapath and DAC Datapath FIFOs ............................. 21 DAC Cores Control Register .................................................... 42 LVDS Interfaces .......................................................................... 21 DAC Datapath Format Control Register ................................ 42 Loop Filter Control Signals Register........................................ 38 Rev. B | Page 2 of 56 Data Sheet AD9993 DAC IQ Calibration Control Register ......................................43 PRBS Detector Error Count 6 for DAC B Register ................ 48 DAC IQ Calibration Status Register .........................................43 Bits[7:0] of Temperature Sensor Data Readback Register ..... 49 DAC Rx FIFO Status 1 Register ................................................43 Bits[15:8] of Temperature Sensor Data Readback Register ... 49 PRBS Detector Control Register ...............................................44 Temperature Sensor Control Signals Register ........................ 49 PRBS Detector Error Count 0 for DAC A Register ................44 Interrupt Pin Control Register .................................................. 50 PRBS Detector Error Count 1 for DAC A Register ................44 DDS Control Register................................................................. 50 PRBS Detector Error Count 2 for DAC A Register ................45 DDS Tuning Word for Tone 1 Register .................................... 51 PRBS Detector Error Count 3 for DAC A Register ................45 DDS Tuning Word for Tone 1 Register .................................... 51 PRBS Detector Error Count 4 for DAC A Register ................45 DDS Tuning Word for Tone 1 Register .................................... 52 PRBS Detector Error Count 5 for DAC A Register ................46 DDS Tuning Word for Tone 1 Register .................................... 52 PRBS Detector Error Count 6 for DAC A Register ................46 Interrupt Status Register ............................................................ 53 PRBS Detector Error Count 0 for DAC B Register ................46 Interrupt Enable Register ........................................................... 53 PRBS Detector Error Count 1 for DAC B Register ................47 Interrupt Source Status Register ............................................... 54 PRBS Detector Error Count 2 for DAC B Register ................47 Global Device Update Register ................................................. 55 PRBS Detector Error Count 3 for DAC B Register ................47 Outline Dimensions ........................................................................ 56 PRBS Detector Error Count 4 for DAC B Register ................48 Ordering Guide ........................................................................... 56 PRBS Detector Error Count 5 for DAC B Register ................48 REVISION HISTORY 12/2017—Rev. A to Rev. B Changes to Figure 2 .......................................................................... 8 Changes to Table 6 ..........................................................................10 5/2014—Rev. 0 to Rev. A Changes to Ordering Guide ...........................................................56 5/2014—Revision 0: Initial Version Rev. B | Page 3 of 56 AD9993 Data Sheet SPECIFICATIONS DC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD = AVDD = 1.8 V, unless otherwise noted. Table 1. Parameter Tx DAC RESOLUTION Tx DAC OUTPUT CHARACTERISTICS Offset Error Gain Error Full-Scale Output Current (IOUTFS) Output Compliance Voltage Range Output Compliance Voltage Range Output Resistance Tx DAC TEMPERATURE DRIFT Gain Reference Voltage (VREF_DAC) REFERENCE (VREF_DAC) Internal Reference Voltage Rx ADC RESOLUTION Rx ADC CHARACTERISTICS Gain Error Peak-to-Peak Differential Input Voltage Range Input Capacitance Rx ADC FULL-SCALE VREF ADJUSTMENT COMMON-MODE VOLTAGE REFERENCE (A_CML, B_CML, C_CML, D_CML) ADC Common-Mode Voltage Output ANALOG SUPPLY VOLTAGES AVDD33 AVDD DIGITAL SUPPLY VOLTAGES DVDD POWER CONSUMPTION Single Tone Input, Single Tone Output AVDD33 AVDD DVDD Power-Down Mode OPERATING RANGE Test Conditions/Comments Min Typ 14 Max ±0.5 ±2.0 20.0 CML_A, CML_B connected to AVSS, setting of DAC_VCM_VREF_BIT[2:0] following reset CML_A, CML_B connected to a bypass capacitor, DAC_VCM_VREF_BIT[2:0] set to 010 −0.5 +0.5 % FSR % FSR mA V 0.0 1.0 V Gain using on-chip VREF_DAC On-chip VREF_DAC 0.95 Rev. B | Page 4 of 56 10 MΩ ±85 ±215 ppm/°C ppm/°C 1.0 14 1.05 ±1.0 1.75 Setting of VREF_FS_ADJ[4:0] at reset ADC inputs are not self biased Unit Bits V Bits % FSR V p-p 1.383 2.5 1.75 2.087 pF V 0.84 0.9 0.96 V 3.14 1.71 3.3 1.8 3.47 1.89 V V 1.62 1.8 1.98 V −40 1536 55 65 210 10.0 +25 +85 mW mA mA mA mA °C Data Sheet AD9993 AC SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD = AVDD = 1.8 V, DAC sampling rate = 500 MSPS and ADC sampling rate = 250 MSPS, unless otherwise specified. Table 2. Parameter DAC OUTPUT Spurious-Free Dynamic Range (SFDR) Two Tone Intermodulation Distortion (IMD3) Noise Spectral Density (NSD), Single Tone 256-QAM Adjacent Channel Power (ACP) ADC INPUT Signal to Noise Ratio (SNR) fIN = 87 MHz Spurious-Free Dynamic Range (SFDR) fIN = 10 MHz fIN = 87 MHz Two-Tone IMD3 Full Power Bandwidth Test Conditions/Comments Min Typ Max Unit fOUT = 20 MHz 75 dBc fOUT = 80 MHz 65 dBc fOUT = 80 MHz −160 dBm/Hz fCENTER = 50 MHz, single carrier, 3.375 MHz offset frequency 76 dBc 70 dBc 86 83 90 1000 dBc dBc dBc MHz Measured with −1.0 dBFS sine wave input Measured with −1.0 dBFS sine wave input fIN1 = 89 MHz, fIN2 = 92 MHz, AIN = −12 dBFS Bandwidth of operation in which proper ADC performance can be achieved DIGITAL SPECIFICATIONS TMIN to TMAX, AVDD33 = 3.3 V, DVDD = AVDD = 1.8 V, unless otherwise noted. Table 3. Parameter CMOS INPUT LOGIC LEVEL Input VIN Logic High Input VIN Logic Low CMOS OUTPUT LOGIC LEVEL Output VOUT Logic High Output VOUT Logic Low ADC AND DAC LVDS DATA INTERFACES ADC LVDS Transmitter Outputs DCO_P/DCO_N to Data Skew (tSKEW) Output Voltage High, VOH, Single Ended Output Voltage Low, VOL, Single Ended Output Differential Voltage Output Offset Voltage DAC LVDS Receiver Inputs Input Voltage Range, Single Ended Test Conditions/Comments Min Typ Max 1.8 0.0 V V 1.2 0.8 Data to DDR DCO_P/DCO_N transition delay Applies to output voltage, positive and negative, VOUTP and VOUTN Applies to VOUTP and VOUTN Specifications apply to DAC data inputs and DCI_P/DCI_N Applies to input voltage, positive and negative, VINP and VINN Input Differential Threshold Input Differential Hysteresis Receiver Differential Input Impedance 350 ps mV 1025 mV 200 1200 mV mV −100 1575 mV +100 mV mV Ω 25 Rev. B | Page 5 of 56 V V 1375 825 85 Unit 115 AD9993 Parameter CLOCK INPUT (CLKP, CLKN) Differential Peak to Peak Voltage Common Mode Voltage Master Clock Frequency REFCLK Input (REFCLK) Input VIN Logic High Input VIN Logic Low REFCLK Frequency Data Sheet Test Conditions/Comments Min Typ Max Unit 1000 mV V MHz 350 1.2 200 1.8 0.0 31.25 or 62.5 SERIAL PERIPHERAL INTERFACE (SPI) SPI_SCLK Frequency SPI_SCLK Pulse Width High SPI_SCLK Pulse Width Low Setup Time, SPI_SDI to SPI_SCLK Rising Edge Hold Time, SPI_SCLK Rising Edge to SPI_SDI Setup Time, SPI_CS to SPI_SCLK Rising Edge Hold Time, SPI_SCLK Rising Edge to SPI_CS Data Valid, SPI_SCLK Falling Edge to SPI_SDO V V MHz 25 Rev. B | Page 6 of 56 10 10 2 MHz ns ns ns 2 ns 2 ns 2 ns 2 ns Data Sheet AD9993 ABSOLUTE MAXIMUM RATINGS Rating −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +2.2 V −0.3 V to +2.2 V −0.3 V to AVDD + 0.3 V Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. −0.3 V to AVDD + 0.3 V Table 5. Thermal Resistances and Characterization Parameters Table 4. Parameter AVSS to DVSS AVDD33 to AVSS, DVSS AVDD to AVSS, DVSS DVDD to DVSS, AVSS CP, A_VINP, A_VINN, B_VINP, B_VINN, C_VINP, C_VINN, D_VINP, D_VINN, IBIAS_TEST to AVSS VREF_DAC, FSAJ_A, FSAJ_B, CML_A, CML_B, A_CML, B_CML, B_CML, D_CML to AVSS IOUTA_P, IOUTA_N, IOUTB_P, IOUTB_N to AVSS CLKP, CLKN, REFCLK to AVSS PDWN, ALERT, RST, MODE, SPI_SCLK, SPI_CS, SPI_SDI, SPI_SDO to DVSS LVDS Data Inputs to DVSS LVDS Data Outputs to DVSS STROBE_P, STROBE_N to DVSS DCI_N, DCI_P, DCO_N, DCO_P Junction Temperature Storage Temperature Range −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to DVDD + 0.3 V THERMAL RESISTANCE Package Type 196-Ball CSP_BGA ESD CAUTION −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V −0.3 V to DVDD + 0.3 V 125°C −65°C to +160°C Rev. B | Page 7 of 56 θJA 27.0 θJB 15.4 θJC 5.38 ψJT 0.11 ψJB 15.0 Unit ºC/W AD9993 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 2 3 4 5 6 7 8 9 A AVSS CLKP AVSS D_VINP C_CML C_VINP AVSS AVSS B_VINP B_CML A_VINP AVSS IBIAS_ TEST AVSS B CLKN REFCLK AVSS D_VINN D_CML C_VINN AVSS AVSS B_VINN A_CML A_VINN AVSS IOUTA_N IOUTA_P C AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVDD33 AVDD33 D LDO15 CP AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS AVSS IOUTB_N IOUTB_P E AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD AVDD F PDWN ALERT RST MODE AVDD33 AVSS AVSS AVSS AVSS AVSS AVSS VREF_DAC FSAJ_B FSAJ_A SPI_CS SPI_SDI SPI_SDO DVDD AVSS AVSS AVSS AVSS AVSS AVSS AVDD CML_B CML_A G SPI_SCLK 10 11 12 13 14 H DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS DVSS J DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD DVDD K DIN6B_N DIN4B_N DIN1B_N DOUT3D_P DOUT3D_N DOUT3C_P DCO_N DCO_P DOUT3B_P DOUT3A_N DOUT3A_P DIN1A_N DIN4A_N DIN6A_N L DIN6B_P DIN4B_P DIN1B_P DOUT1D_N DOUT2D_N DOUT1C_N DOUT3C_N DOUT3B_N DOUT1B_N DOUT2A_N DOUT1A_N DIN1A_P DIN4A_P DIN6A_P M DIN5B_N DIN3B_P DIN3B_N DOUT1D_P DOUT2D_P DOUT1C_P STROBE_N STROBE_P DOUT1B_P DOUT2A_P DOUT1A_P DIN3A_N DIN3A_P DIN5A_N N DIN5B_P DIN2B_N DIN0B_N DOUT0D_N DOUT0C_N DOUT2C_N DVSS DVSS DOUT2B_N DOUT0B_N DOUT0A_N DIN0A_N DIN2A_N DIN5A_P P DVSS DIN2B_P DIN0B_P DOUT0D_P DOUT0C_P DOUT2C_P DCI_N DCI_P DOUT2B_P DOUT0B_P DOUT0A_P DIN0A_P DIN2A_P DVSS Figure 2. Pin Configuration Table 6. Pin Function Descriptions Pin No. A1, A3, A7, A8, A12, A14, B3, B7, B8, B12, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C11, C12, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, F6, F7, F8, F9, F10, F11, G6, G7, G8, G9, G10, G11 A2 A4 A5 A6 A9 Mnemonic AVSS Description Analog Ground. CLKP D_VINP C_CML C_VINP B_VINP External Master Clock Input Positive. ADC D Input Voltage Positive. Common-Mode Level Bias Voltage Output ADC C. ADC C Input Voltage Positive. ADC B Voltage Input Positive. Rev. B | Page 8 of 56 12260-002 1 Data Sheet AD9993 Pin No. A10 A11 A13 B1 B2 B4 B5 B6 B9 B10 B11 B13 B14 C13, C14, F5 D1 D2 D13 D14 E1, E2, E3, E4, E5, E6, E7, E8, E9, E10, E11, E12, E13, E14, G12 F1 F2 F3 F4 F12 F13 F14 G1 G2 G3 G4 G5, J1, J2, J3, J4, J5, J6, J7, J8, J9, J10, J11, J12, J13, J14 G13 Mnemonic B_CML A_VINP IBIAS_TEST CLKN REFCLK D_VINN D_CML C_VINN B_VINN A_CML A_VINN IOUTA_N IOUTA_P AVDD33 LDO15 CP IOUTB_N IOUTB_P AVDD Description Common-Mode Level Bias Voltage Output for ADC B. ADC A Voltage Input Positive. Test. Connect to ground. External Master Clock Input Negative On-Chip PLL Synthesizer Reference Clock Input. ADC D Input Voltage Negative. Common-Mode Level Bias Voltage Output ADC D. ADC C Input Voltage Negative. ADC B Voltage Input Negative. Common-Mode Level Bias Voltage Output for ADC A. ADC A Voltage Input Negative. DAC A Output Current Negative. DAC A Output Current Positive. 3.3 V Analog Power Supply. On-Chip Regulator Output. Bypass with 4.7 µF capacitor to ground. Connection for On-Chip PLL Optional External Portion of Loop Filter. DAC B Output Current Negative. DAC B Output Current Positive. 1.8 V Analog Power Supply. PDWN ALERT RST MODE VREF_DAC FSAJ_B FSAJ_A SPI_SCLK SPI_CS SPI_SDI SPI_SDO DVDD Power-Down. Set to 1 to place the device in low power mode. Active Low Alarm Indicator Output, Open Drain. Reset Input, Active Low. Connect to ground. DAC A and DAC B Reference Voltage Input/Output. DAC B Full-Scale Current Output Adjust. DAC A Full-Scale Current Output Adjust. SPI Clock. SPI Chip Select, Active Low. SPI Serial Data Input. SPI Serial Data Output. 1.8 V Digital Supply. CML_B G14 CML_A H1, H2, H3, H4, H5, H6, H7, H8, H9, H10, H11, H12, H13, H14, N7, N8, P1, P14 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 DVSS DAC B Common-Mode Control. Connect to ground for DAC bias < 0.5 V. Connect a 0.1 µF capacitor between CML_B and ground for other DAC bias values ≥ 0.5 V. DAC A Common-Mode Control. Connect to ground for DAC bias < 0.5 V. Connect a 0.1 µF capacitor between CML_A and ground for other DAC bias values ≥ 0.5 V. Digital Ground. DIN6B_N DIN4B_N DIN1B_N DOUT3D_P DOUT3D_N DOUT3C_P DCO_N DCO_P DOUT3B_P DOUT3A_N DOUT3A_P DIN1A_N DIN4A_N DAC B Data Input Lane 6 Negative. DAC B Data Input Lane 4 Negative. DAC B Data Input Lane 1 Negative. ADC D Data Output Lane 3 Positive. ADC D Data Output Lane 3 Negative. ADC C Data Output Lane 3 Positive. LVDS Data Clock Output Negative. LVDS Data Clock Output Positive. ADC B Data Output Lane 3 Positive. ADC A Data Output Lane 3 Negative. ADC A Data Output Lane 3 Positive. DAC A Data Input Lane 1 Negative. DAC A Data Input Lane 4 Negative. Rev. B | Page 9 of 56 AD9993 Pin No. K14 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 L14 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 N1 N2 N3 N4 N5 N6 N9 N10 N11 N12 N13 N14 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 Data Sheet Mnemonic DIN6A_N DIN6B_P DIN4B_P DIN1B_P DOUT1D_N DOUT2D_N DOUT1C_N DOUT3C_N DOUT3B_N DOUT1B_N DOUT2A_N DOUT1A_N DIN1A_P DIN4A_P DIN6A_P DIN5B_N DIN3B_P DIN3B_N DOUT1D_P DOUT2D_P DOUT1C_P STROBE_N STROBE_P DOUT1B_P DOUT2A_P DOUT1A_P DIN3A_N DIN3A_P DIN5A_N DIN5B_P DIN2B_N DIN0B_N DOUT0D_N DOUT0C_N DOUT2C_N DOUT2B_N DOUT0B_N DOUT0A_N DIN0A_N DIN2A_N DIN5A_P DIN2B_P DIN0B_P DOUT0D_P DOUT0C_P DOUT2C_P DCI_N DCI_P DOUT2B_P DOUT0B_P DOUT0A_P DIN0A_P DIN2A_P Description DAC A Data Input Lane 6 Negative. DAC B Data Input Lane 6 Positive. DAC B Data Input Lane 4 Positive. DAC B Data Input Lane 1 Positive. ADC D Data Output Lane 1 Negative. ADC D Data Output Lane 2 Negative. ADC C Data Output Lane 1 Negative. ADC C Data Output Lane 3 Negative. ADC B Data Output Lane 3 Negative. ADC B Data Output Lane 1 Negative. ADC A Data Output Lane 2 Negative. ADC A Data Output Lane 1 Negative. DAC A Data Input Lane 1 Positive. DAC A Data Input Lane 4 Positive. DAC A Data Input Lane 6 Positive. DAC B Data Input Lane 5 Negative. DAC B Data Input Lane 3 Positive. DAC B Data Input Lane 3 Negative. ADC D Data Output Lane 1 Positive. ADC D Data Output Lane 2 Positive. ADC C Data Output Lane 1 Positive. LVDS Data Output Strobe Negative. LVDS Data Output Strobe Positive. ADC B Data Output Lane 1 Positive. ADC A Data Output Lane 2 Positive. ADC A Data Output Lane 1 Positive. DAC A Data Input Lane 3 Negative. DAC A Data Input Lane 3 Positive. DAC A Data Input Lane 5 Negative. DAC B Data Input Lane 5 Positive. DAC B Data Input Lane 2 Negative. DAC B Data Input Lane 0 Negative. ADC D Data Output Lane 0 Negative. ADC C Data Output Lane 0 Negative. ADC C Data Output Lane 2 Negative. ADC B Data Output Lane 2 Negative. ADC B Data Output Lane 0 Negative. ADC A Data Output Lane 0 Negative. DAC A Data Input Lane 0 Negative. DAC A Data Input Lane 2 Negative. DAC A Data Input Lane 5 Positive. DAC B Data Input Lane 2 Positive. DAC B Data Input Lane 0 Positive. ADC D Data Output Lane 0 Positive. ADC C Data Output Lane 0 Positive. ADC C Data Output Lane 2 Positive. LVDS Data Clock Input Negative. LVDS Data Clock Input Positive. ADC B Data Output Lane 2 Positive. ADC B Data Output Lane 0 Positive. ADC A Data Output Lane 0 Positive. DAC A Data Input Lane 0 Positive. DAC A Data Input Lane 2 Positive. Rev. B | Page 10 of 56 Data Sheet AD9993 TYPICAL PERFORMANCE CHARACTERISTICS RECEIVER ADC PERFORMANCE fADC = 250 MHz, unless otherwise specified. 0 IMD3 (dBc) IMD3 (dBFS) –20 –15 IMD3 (dBc AND dBFS) AMPLITUDE (dBFS) –30 –45 –60 –75 –90 2 3 6 4 5 –105 –120 –40 –60 –80 –100 30 45 60 75 90 105 120 FREQUENCY (MHz) Figure 3. Single Tone FFT, fIN = 87 MHz 100 90 80 85 SNR (dBFS) 95 60 40 –50 –40 –30 –20 –10 80 –70 –60 –50 –40 –30 –20 –10 0 65 20 –40 85 SNR (dBc) 90 –60 75 –100 70 –40 –30 INPUT AMPLITUDE (dBFS) –20 –10 65 20 12260-004 –50 120 80 –80 –60 100 95 –20 –70 80 Figure 7. Single Tone SNR vs. Input Frequency (fIN) SFDR (dBc) SFDR (dBFS) –80 60 fIN (MHz) Figure 4. Single Tone SNR and SFDR vs. Input Amplitude (AIN), fIN = 87 MHz 0 40 40 60 80 100 fIN (MHz) Figure 5. Two Tone SFDR vs. Input Amplitude (AIN), fIN1 = 89.12 MHz, fIN2 = 92.12 MHz Figure 8. Single Tone SNR vs. Input Frequency (fIN) Rev. B | Page 11 of 56 120 12206-011 –80 12206-010 70 SNR (dBc) SNR (dBFS) SFDR (dBc) SFDR (dBFS) INPUT AMPLITUDE (dBFS) SFDR (dBc AND dBFS) –60 75 20 –120 –90 –70 Figure 6. Two Tone IMD3 vs. Input Amplitude (AIN), fIN1 = 89.12 MHz, fIN2 = 92.12 MHz 120 0 –90 –80 INPUT AMPLITUDE (dBFS) 12260-007 SNR, SNRFS, SFDR (dBc), SFDR (dBFS) –120 –90 12206-003 15 12260-005 –135 AD9993 Data Sheet fADC = 250 MHz, unless otherwise specified. 100 ADC A ADC B ADC C ADC D AMPLITUDE (dBFS) 0 –15 95 –30 90 SFDR (dBFS) –45 –60 –75 –90 F2 – F1 2F1–+F1 F2 2F2 F1 + F2 2F2 + F1 2F1 – F2 –105 85 80 75 70 –120 30 45 60 90 75 105 120 60 100 FREQUENCY (MHz) 100 SNR (dBc) 90 85 80 75 70 160 180 200 220 ADC SAMPLING FREQUENCY (MSPS) 240 12260-008 65 140 160 180 200 220 240 Figure 11. Single Tone SFDR vs. ADC Sampling Freqency (fADC), fIN = 90.0 MHz, All Four ADCs ADC A ADC B ADC C ADC D 95 120 140 ADC SAMPLING FREQUENCY (MSPS) Figure 9. Two Tone FFT, fIN1 = 89.12 MHz, fIN2 = 92.12 MHz 60 100 120 12260-009 15 12206-012 65 –135 Figure 10. Single Tone SNR vs. ADC Sampling Freqency (fADC), fIN = 90.0 MHz, All Four ADCs Rev. B | Page 12 of 56 Data Sheet AD9993 TRANSMITTER DAC PERFORMANCE fDAC = 500 MHz, unless otherwise specified. –76.2dBc –75.9dBc –75.9dBc –76.2dBc –76.4dBc –75.5dBc 11.2dBm –76.3dBc –75.9dBc 2R AMPLITUDE (dBFS) 10dB/DIV –30 –40 –50 –60 –70 –80 –90 2 1 –100 #VBW 300kHz OFFSET FREQ INTEG BW 3.375MHz 750kHz 6.375MHz 5.25MHz 12MHz 6MHz 18MHz 6MHz 24MHz 6MHz LOWER dBc dBm –80.81 –92.04 –75.93 –87.16 –75.49 –86.72 –76.23 –87.46 –76.42 –87.65 START 1MHz #RES BW 1kHz SPAN 54MHz SWEEP 175.1ms UPPER dBc dBm –29.72 –40.95 –75.95 –87.18 –76.30 –87.53 –76.17 –87.41 –75.93 –87.16 Filter OFF OFF OFF OFF OFF MARKER 1R 1 2R 2 X AXIS 47.9MHz 48.0MHz 47.9MHz 96.4MHz AMPLITUDE –0.56dBm –83.28dB –0.56dBm –71.74dB –50 SFDR (dBc) –60 –70 –80 –55 –60 –65 –70 –90 0 50 100 150 200 250 fOUT (MHz) –80 150 200 250 –45 –50 –55 –50 –60 IMD3 (dBc) –55 –60 –65 –65 DACA –70 DACB –75 –70 –80 –75 –85 0 50 100 150 200 fOUT (MHz) 250 12206-019 –80 100 Figure 16. SFDR at Three DAC Sampling Frequencies (fDAC) vs. fOUT DAC: b, B, TEMP: +25°C DAC +25°C DAC: b, B, TEMP: +85°C DAC +85°C DAC: b, TEMP: –40°C DAC B, –40°C –45 50 fOUT (MHz) Figure 13. SFDR, 2nd and 3rd Harmonics vs. fOUT, Maximum IOUTFS (DAC Gain) –40 0 12206-020 –75 –90 0 50 100 150 fOUT (MHz) Figure 17. IMD3 vs. fOUT, Both DACs Figure 14. SFDR at Three Temperatures vs. fOUT Rev. B | Page 13 of 56 200 250 12260-022 –100 SFDR (dBc) TYPE FREQ FREQ FREQ FREQ fDAC = 250MHz, DAC B fDAC = 350MHz, DAC B fDAC = 500MHz, DAC B –45 12206-018 SFDR AND SECOND/THIRD HARMONIC (dBc) –40 SECOND HARMONIC (dBc) THIRD HARMONIC (dBc) SFDR (dBc) –50 TRACE 1 1 1 1 Figure 15. 1st Nyquist Zone Output Spectrum, fOUT = 48 MHz Figure 12. 5 MHz Bandwidth 256-QAM Adjacent Channel Power –40 STOP 250MHz SWEEP 300.2s (601pts) VBW 1kHz 12206-017 CENTER 50MHz #RES BW 30kHz 12206-021 –110 AD9993 Data Sheet fDAC = 500 MHz, unless otherwise specified. –45 –135 –50 –140 –55 NSD (dBm/Hz) –65 –70 –75 –80 50 100 150 200 250 fOUT (MHz) –150 –155 Figure 18. IMD3 at Three DAC Sampling Frequencies (fDAC) vs. fOUT –165 0 50 100 150 200 fOUT (MHz) Figure 19. NSD at Three Temperatures vs. fOUT Rev. B | Page 14 of 56 250 12206-024 0 –145 –160 fDAC = 300MHz, DAC B, EXTERNAL CLOCK fDAC = 400MHz, DAC B, EXTERNAL CLOCK fDAC = 500MHz, DAC B, EXTERNAL CLOCK –85 12206-023 IMD3 (dBc) –60 –90 fDAC = 500MHz, DAC A, +25°C, EXTERNAL CLOCK fDAC = 500MHz, DAC A, +85°C, EXTERNAL CLOCK fDAC = 500MHz, DAC A, –40°C, EXTERNAL CLOCK Data Sheet AD9993 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) INL is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Settling Time Settling time is the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. Differential Nonlinearity (DNL) DNL is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. Spurious-Free Dynamic Range (SFDR) SFDR is the difference, in decibels (dB), between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. Monotonicity A digital-to-analog converter is monotonic if the output either increases or remains constant as the digital input increases. Offset Error Offset error is the deviation of the output current from the ideal of zero. For IOUTx_P, 0 mA output is expected when the inputs are all 0s. For IOUTx_N, 0 mA output is expected when all inputs are set to 1. Gain Error Gain error is the difference between the actual and ideal output span. The actual span is determined by the output when all inputs are set to 1, minus the output when all inputs are set to 0. The ideal gain is calculated using the measured VREF. Therefore, the gain error does not include effects of the reference. Noise Spectral Density (NSD) Noise spectral density is the average noise power normalized to a 1 Hz bandwidth, with the DAC converting and producing an output tone. Signal-to-Noise Ratio (SNR) SNR is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency, excluding the first six harmonics and dc. The value for SNR is expressed in decibels. Signal to Noise and Distortion (SINAD) The ratio of the total signal power level (wanted signal + noise + distortion or SND) to unwanted signal power (noise + distortion or ND). Output Compliance Voltage Output compliance voltage is the range of allowable voltage at the output of a current output DAC. Operation beyond the maximum compliance limits can cause either output stage saturation or breakdown, resulting in nonlinear performance. Temperature Drift Temperature drift is specified as the maximum change from the ambient (25°C) value to the value at either TMIN or TMAX. For offset and gain drift, the drift is reported in ppm of fullscale range (FSR) per °C. For reference drift, the drift is reported in ppm per °C. Rev. B | Page 15 of 56 AD9993 Data Sheet THEORY OF OPERATION PRODUCT DESCRIPTION Figure 1 shows a block diagram of the MxFE. This product integrates four 14-bit ADCs and two 14-bit DACs. The DAC data interface consists of six DDR LVDS data lanes for each DAC and a shared DCI_P/DCI_N clock (hereafter referred to as DCI). The ADC data interface consists of four DDR LVDS data lanes for each ADC with a shared DCO_P/DCO_N clock (hereafter referred to as DCO) and a shared STROBE output. The MxFE control and status registers are written/read via an SPI interface. ADC and DAC datapaths include FIFO buffers to absorb phase differences between LVDS lane timing and the data converter sampling clocks. Internal AD9993 clock signals can be developed from an external clock signal or from the output of an on-chip PLL frequency multiplier driven by an external reference oscillator. SPI PORT The AD9993 provides a 4-wire synchronous serial communications SPI port that allows easy interfacing to ASICs, FPGAs, and industry-standard microcontrollers. The interface facilitates read/write access to all registers that configure the AD9993. Its data rate can be up to 25 MHz. SPI Port Signals SPI_SCLK (serial clock) is the serial shift clock. The serial clock pin synchronizes data to and from the device and runs the internal state machines. All address and input data bits are sampled on the rising edge of SPI_SCLK. All output data is driven out on the falling edge of SPI_SCLK. SPI_CS (chip select) is an active low control signal used by the SPI master to select the AD9993 SPI port. When SPI_CS is high, SPI_SDO is in a high impedance state. During the communication cycle, chip select must remain low. SPI_SDI (serial data input) is the address and data input, sampled on the rising edge of SPI_SCLK. SPI_SDO (serial data output) is the data output pin. Data is shifted out on the falling edge of SCLK Figure 20 shows a timing diagram for a single byte MSB first AD9993 SPI write operation. Each AD9993 register address is an 8-bit value. During the first SPI_SCLK cycle, SPI_SDI = 0, indicating that the operation is a data write. SPI_SDI is always held low for the next two clock cycles. The next 13 clock cycles are the first register address. The next eight clock cycles contain data to be written. The write operation ends when SPI_CS goes high. In this example, data for one 8-bit register is written. Multiple registers can be written in a single write operation by keeping SPI_CS low for multiple byte periods. The register address is automatically updated using an address counter as bytes are written while SPI_CS remains low. Figure 21 depicts an MSB first register read operation. Register data from the AD9993 appears on SPI_SDO starting on the SPI_SCLK cycle following the last bit of the 16-bit instruction header on SPI_SDI. Multiple registers can be read in a single read operation by keeping SPI_CS low for multiple byte periods. SPI_CS SPI_SCLK DON’T CARE DON’T CARE SPI_SDI DON’T CARE R/W W1 W0 A12 A11 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 DON’T CARE 16-BIT INSTRUCTION HEADER 12260-025 SPI_SDO DON’T CARE REGISTER DATA Figure 20. 4-Wire SPI Interface Timing, MSB First Write SPI_CS SPI_SCLK DON’T CARE DON’T CARE SPI_SDI DON’T CARE R/W W1 W0 A12 A11 A11 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 SPI_SDO DON’T CARE 16-BIT INSTRUCTION HEADER REGISTER DATA Figure 21. 4-Wire SPI Interface Timing, MSB First Read Rev. B | Page 16 of 56 DON’T CARE 12260-026 DON’T CARE Data Sheet AD9993 The SPI_CONFIG register controls AD9993 SPI interface operation. By default, the SPI bus operates MSB first. In MSB fist mode, the register address counter decrements automatically during multiple byte reads or writes. The SPI bus can be configured to run LSB first by setting the SPI_LSB_FIRSTx bits to 1. During LSB first multiple register read or write operations, the register address counter is incremented automatically. SPI registers can be reset to their Reset values by setting the self clearing SPI_SOFT_RESETx bits to 1. REGISTER UPDATE TRANSFER METHOD Changes to the writeable SPI registers labeled transfer in Table 10 do not take effect immediately when written to the device via the SPI. Values are held in a shadow register set until the self clearing CHIP_REGMAP_TRANSFER bit in the DEVICE_ UPDATE register is set. All changes to transfer register values then take effect simultaneously. ADC REGISTER UPDATE INDEXING In addition to the register transfer mechanism, the POWER_ MODES and FLEX_OUTPUT_MODE registers have an indexing mechanism. Each of the four ADC cores has its own page containing these registers. These pages can be programmed independently or simultaneously in any combination. ADC core register sets are addressed for a particular register map master/slave transfer by setting the SPI_ADC_x_INDEX bits in the DEVICE_INDEX register. Register data is transferred to the ADC core pages that have these bits set when the next transfer occurs. ADCs The MxFE ADCs are multistage pipelined CMOS ADC cores designed for use in communications receivers. A_CML, B_CML, C_CML, and D_CML pins. Using these common-mode voltage outputs to set the input common mode of each ADC is recommended. Optimum performance is achieved when the common-mode voltage of the analog input is set by the on-chip common mode references. The A_CML, B_CML, C_CML, and D_CML pins must be decoupled to ground by a 0.1 μF capacitor. ADC SECTION PROGRAMMING Each of the four ADCs has its power mode programmed by the indexed ADC_PDWN_MODE bit field of the POWER_ MODES register (see the ADC Register Update Indexing section). At reset, all four ADC cores are in power-down mode. ADC digital data output modes are programmed by the indexed FLEX_OUTPUT_MODE register (see the ADC Register Update Indexing section). Setting the DP_OUT_DATA_EN_N bit to 0 enables the data output of each ADC selected in the DEVICE_ INDEX register. At reset, ADC output data is disabled. Setting the DP_OUT_DATA_INV bit to 1 inverts the data output from selected ADCs. The DP_OUT_DFS bit field selects the output code for each selected ADC, offset binary (twos complement with the sine bit inverted), twos complement (reset value), or gray code. ANALOG INPUT CONSIDERATIONS The analog input to the AD9993 is a differential switched capacitor circuit that has been designed for optimum performance while processing a differential input signal. For baseband applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. An example is shown in Figure 22. To bias the analog input, the VCM voltage can be connected to the center tap of the secondary winding of the transformer. C2 R3 ADC ARCHITECTURE The AD9993 architecture consists of a dual front-end sampleand-hold circuit, followed by a pipelined switched capacitor ADC. The quantized outputs from each stage are combined into a final 14-bit result. 2V p-p The analog inputs of the AD9993 are not internally dc biased. In ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = 0.5 × AVDD (or 0.9 V) is recommended for optimum performance. Four on-board common-mode voltage references are included in the design, one for each AD9993 ADC, and are available from the 49.9Ω x_VINP C1 ADC R2 R1 0.1µF The input stage of each ADC core contains a differential sampling circuit that can be ac- or dc-coupled in differential or single-ended modes. Input Common-Mode Voltage (VCM) References R2 R1 R3 x_VINN x_CML 33Ω C2 0.1µF 12260-027 SPI CONFIGURATION PROGRAMMING Figure 22. Differential Transformer-Coupled Configuration Differential double balun coupling is used as the input configuration for AD9993 ADC performance characterization (see Figure 23). In this configuration, the input is ac-coupled and the VCM voltage is provided to each input through a 33 Ω resistor. These resistors compensate for losses in the input baluns to provide a 50 Ω impedance to the driver. Rev. B | Page 17 of 56 AD9993 Data Sheet PA S S R2 33Ω P 0.1µF 33Ω 0.1µF x_VINP C1 R1 ADC R2 R3 C2 x_VINN x_CML 33Ω 0.1µF 12260-028 2V p-p C2 R3 R1 0.1µF 0.1µF Figure 23. Differential Double Balun Input Configuration DACs In the double balun and transformer configurations, the value of the input capacitors and resistors is dependent on the input frequency and source impedance. Based on these parameters, the value of the input resistors and capacitors may need to be adjusted or some components may need to be removed. Table 7 displays recommended values to set the RC network for the 0 MHz to 100 MHz frequency range: The MxFE DACs are part of the Analog Devices high speed CMOS DAC core family. These DACs are designed to be used as part of wide bandwidth communication system transmitter signal chains. Table 7. Example RC Network The AD9993 DACs provide two differential current outputs: IOUTA_P/IOUTA_N, and IOUTB_P/IOUTB_N. Component R1 Series C1 Differential R2 Series C2 Shunt R3 Shunt Value 33 Ω 8.2 pF 0Ω 15 pF 49.9 Ω DAC TRANSFER FUNCTION The DAC output current equations are as follows: IOUTx_P = IOUTFS × DACx input code/214 IOUTx_N = IOUTFS × ((214 − 1) − DACx input code)/214 The values given in Table 7 are for each R1, R2, C1, C2, and R3 component shown in Figure 22 and Figure 23. where: DACx input code = 0 to 214 − 1. IOUTFS is the full-scale output current or DAC gain specified in Table 1. ADRF6518 as ADC Driver IOUTFS = 32 × IIREFx The ADRF6518 is a variable gain amplifier and low-pass filter that is designed to drive the analog inputs of analog-to-digital converters like the ones included in the AD9993. A principle application of the ADRF6518 is as part of the signal chain in a wideband radio receiver. Figure 32 shows a block diagram for a wideband microwave radio that includes the ADRF6518 and the AD9993. The low impedance (60 dBc IMD3. The output common-mode voltage can be adjusted to 900 mV (the AD9993 input common-mode voltage) without loss of drive capability by presenting the ADRF6518 VOCM pin with the desired common-mode voltage. The high input impedance of VOCM allows the AD9993 reference output (A_CML, B_CML, C_CML or D_CML) to be connected directly. where IREFx = VREFDAC/RFSADJ_x. Each DAC has its own IREFx set resistor, RFSADJ_x. RFSADJ_x resistors can be on or off chip at the discretion of the users. The nominal value of RFSADJ_x is 1.6 kΩ. The nominal value of VREFDAC is 1.0 V. VREFDAC can be selected as the on-chip band gap reference or as an external user supplied reference. DAC outputs have a sin(πfOUT/fDAC)/(πfOUT/fDAC) envelope response as a function frequency. This response is also referred to as a sinc envelope. DAC OUTPUT COMPLIANCE VOLTAGE RANGE AND AC PERFORMANCE Each DAC has a pair of differential current outputs. The compliance voltage range for each of these two outputs is specified in Table 1. Optimal DAC ac performance is achieved when the output common-mode voltage is between 0.0 V and 0.5 V. and the signal swing falls within the compliance range. Rev. B | Page 18 of 56 Data Sheet AD9993 BAND GAP TRIM 1.0V ±1% DAC_REF_EXT = 0 REG 0x039[0] CLKA DAC_A NOTE: DEFAULT VALUES FOR DAC A GAIN AND DAC B GAIN ARE SET AT FACTORY TRIM FOR IFS = 20mA WITH DAC_RSET_EN = 1 25Ω 25Ω IMEAS A DAC_CAL_IQ_SEL REG 0x03C[1] 1 –0.25V TO +0.25V CAL IQ 0 DAC_RSET_EN = 1 REG 0x039[1] IMEAS B DAC_B IOUTP 25Ω IOUTN 25Ω CLKB DAC_RSET_EN = 0 REG 0x039[1] 1.6kΩ TRIM ±3% IOUTP IOUTN –0.25V TO +0.25V ON CHIP 1.6kΩ ±2% 0.1µF 12260-029 1.6kΩ ±2% Figure 24. DACs, Band Gap Reference, On-Chip and Off-Chip RFSADJ_x, DAC Gain Setting, and IQ Calibration Selecting DAC Output Common-Mode Voltage DAC IQ Gain Calibration Two steps are required to select the common-mode output voltages for the two DACs. For a common-mode voltage less than 0.5 V, the CML_A and CML_B pins are grounded. For common-mode voltages that are greater than or equal to 0.5 V, connect a 0.1 µF capacitor between CML_A or CML_B and ground. The second step is to program the DAC_VCM_ VREF_BIT bit field. There are three common-mode level settings to choose from. This common-mode setting applies to both DACs. When board level RFSADJ_x resistors are used, the gains of the two DACs can be better matched by running the automatic DAC IQ gain calibration procedure. This is done by programming the DAC_CAL_IQ_CTRL register and observing the DAC_CAL_IQ_STAT register as follows: DAC VOLTAGE REFERENCE 3. The DACs use a single common voltage reference. An on-chip band gap reference is provided. Optionally, an off-chip voltage reference can be used. If an off-chip DAC reference is used, set the DAC_REF_EXT bit in the DAC_CTRL register to 1. After reset, the on-chip reference is selected. DAC DATAPATH FORMAT SELECTION DAC GAIN SETTING Figure 24 is a diagram of the AD9993 DACs gain setting section. It shows the two transmit DACs, the bypassable built-in 1.0 V band gap reference, and the selectable internal and board level RFSADJ_x resistors. By default, the on-chip band gap reference is selected. If using a board level. DAC reference voltage, write 1 to the DAC_REF_EXT bit of the DAC_CTRL register. Each DAC has its own RFSADJ_x set resistor. These resistors can be on or off chip at the discretion of the user. When the on-chip resistors are in use, their gain accuracy is factory calibrated. When the off-chip RFSADJ_x resistors are used, an on-chip IQ calibration scheme can be employed to maintain accuracy between DAC pairs. By default, the on-chip RFSADJ_x is selected. If using a board level RFSADJ_x, write 0 to the DAC_RSET_EN bit of the DAC_CTRL register. 1. 2. Write 0x23 to DAC_CAL_IQ_CTRL (power up the DAC clock, enable IQ calibration, and start IQ calibration). Read the DAC_CAL_IQ_DONE bit of the DAC_CAL_IQ_STAT register until it goes high. Write 0x4 to DAC_CAL_IQ_CTRL. At reset, the DAC_BINARY bit in the DAC_DP_FMT register is set to 0, selecting twos complement as the data input format for both DACs. To select binary offset, set the DAC_BINARY bit to 1. DAC TEST TONE GENERATOR DDS The AD9993 includes a tunable direct digital synthesizer for DAC output tone generation. When the DDS_EN bit of the DDS_CTRL register is set to 1, the DDS becomes the digital signal source for the two DACs. The DDS_CTRL register also has a clock inversion control and amplitude attenuation controls. At reset, the 32-bit DDS tuning word in the DDS_TW1_3, DDS_TW1_2, DDS_TW1_1, and DDS_TW1_0 registers is set to 0x19A00000. This value programs the DDS to produce a 50 MHz tone at both DAC outputs if the master clock frequency is 1 GHz (DAC sampling rate = 500 MSPS). The equation for DDS output frequency is Rev. B | Page 19 of 56 fDDS = (DDS_TW1/232) × fDAC AD9993 Data Sheet CLOCKING the master clock, the buffered VCO output signal is divided by 4 to produce the synthesized master clock signal. The clock signals for the LVDS lanes, the DACs, and the ADCs are developed from a single master clock signal. This signal is either input directly on the CLKP/CLKN pins or synthesized by an on-chip PLL multiplier using the REFCLK input signal as a reference. The ADC output and DAC input LVDS lanes run at the master clock frequency divided by 2 and are DDR. Data is clocked on both edges. The sampling rate of the ADCs is ¼ the master clock rate. The sampling rate of the DACs is ½ the master clock frequency. A 1 GHz master clock is shown in Figure 1. The reference clock of the on-chip PLL can be either 31.25 MHz or 62.5 MHz. When using a 62.5 MHz clock, a divide by 2 option is provided, as shown in Figure 25, such that the internal PLL reference clock can be set to 31.25 MHz. A programmable loop filter is integrated on chip. At reset, the on-chip loop filter bandwidth is set to 500 kHz. Lower loop bandwidth can be achieved using an external loop filter connected to the CP pin, as shown in Figure 25. An on-chip LDO provides the supply voltage for the VCO. At a 1 GHz master clock frequency, the other on-chip clock frequencies are as follows: At reset, the SYNTH_INT register contains the reset default value for the VCO output divider of 64 (shown in Figure 25). The PLL multiplier lock status can be read back on Bit 1 of the SYNTH_STAT register. Calibration status is also read from this register. Bits in the SYNTH_CTRL register are used to enable charge pump calibration and to start synthesizer calibration. Synthesizer calibration is required as part of the process of acquiring lock. Charge pump calibration and synthesizer calibration are steps described in the Power-Up Routine When Using the On-Chip Clock Synthesizer section. DCO (ADC DDR LVDS output lane clock): 500 MHz DCI (DAC DDR LVDS input lane clock): 500 MHz DAC sampling rate: 500 MSPS ADC sampling rate: 250 MSPS ON-CHIP PLL CLOCK MULTIPLIER Figure 25 shows a block diagram of the MxFE on-chip PLL clock multiplier. If the PLL clock multiplier is used to generate PROGRAMABLE REG 0x031 FIXED DIVIDER ÷64 DIVIDER ÷2 BYP_R3 REFCLK = 31.25MHz PFD R3 R1 EXT_CP _SEL C1 C2 C3 VDD = 1.8V VCO LDO BUF 0.1µF 1.5V BUF 0.1µF VCO 4GHz VCO CAL ON-CHIP LOOP FILTER PROGRAMABLE BY REG 0x02E TO REG 0x030 CP R110 487Ω C67 22nF C62 390pF NOTES 1. WHEN USING EXTERNAL LOOP FILTER SET C1, C2, C3, R1, AND R3 TO MIN OR MAX VALUES AS DEFINED IN REGISTER DESCRIPTION, AS DESIRED. Figure 25. On-Chip PLL Clock Multiplier Block Diagram Rev. B | Page 20 of 56 12260-030 • • • • PLL Synthesizer Control and Status Registers Data Sheet AD9993 MASTER CLOCK INPUT CLKP 100Ω 1.8V 8kΩ CLKN 200MHz TO 1000MHz Reg 0x034[1:0] CLKGEN_MODE 00 = INTERNAL 1GHz CLOCK 11 = EXTERNAL CLOCK (200MHz TO 1GHz) DIFF 15kΩ 15kΩ 8kΩ MUX 1 1 ÷2 0 REG 0x034[1:0] CLKGEN_MODE PLL Reg 0x033[5] CLKGEN_REFCLK_DIV1 TO DAC, ADC, AND LVDS Reg 0x031[7:0] SYNTH_INT Reg 0x031[7:0] PLL Input Freq | SYNTH_INT 31.25MHz | 0x80 62.5MHz | 0x40 12260-031 REFCLK = 31.25MHz OR 62.5MHz MUX 0 Figure 26. MxFE Clock Control SELECTING CLOCKING OPTIONS Figure 26 is a block diagram of the MxFE clocking system and its controls. Options of using either an external master clock or a master clock generated from the on-chip PLL are provided. CLKGEN_MODE[1:0] in the CLKGEN_CTRL2 register selects the PLL multiplier or CLKP/CLKN as the master clock source. ADC DATAPATH AND DAC DATAPATH FIFOS In the AD9993, data FIFOs are placed between the ADC core outputs and the LVDS buffers and drivers. Similarly, on the DAC side, data FIFOs are placed between the LVDS input buffers and the DAC cores. These FIFOs absorb the phase difference between DCI and the DAC sampling clock and between the ADC sampling clock and DCO. DAC sampling clock and DCI are locked in frequency but have an unknown phase relationship. The ADC sampling clock and DCO have the same characteristics. FIFOs are eight samples deep. During a start-up register sequence, both the DAC input datapath FIFOs and the ADC output data path FIFOs have their read and write pointers initialized (see the Start-Up Register Sequences section). This occurs after all clocks in the AD9993 are running and settled. The pointers are set four data samples apart. The ADC datapath FIFO depth can be read in the RXFIFO_WR_OFFSET bit field in the align register. The DAC datapath FIFO depth can be read as the RXFIFO_THERM[7:0] value in the DAC_FIFO_STS1 register. This value is a thermometer code. FIFO depths remain constant after initialization when all clocks are running properly. LVDS INTERFACES Each DAC has seven DDR LVDS input data lanes. Each DAC sample input requires the user to input two 7-bit words to the interface with appropriate zero stuffing. Each ADC has four DDR LVDS output data lanes. For each ADC output sample, four 4-bit words are output. LVDS ADC Data Link There are two LVDS ADC buses for the two ADCs. Each LVDS ADC Data bus has four lanes for 14-bit data output in two full DDR cycles. A strobe lane is shared by the four ADC LVDS links to identify the MSB of the 14-bit data. Figure 27 shows one LVDS ADC output data link with four lanes. Lane 0 to Lane 2 output the 12 MSBs of the 14-bit ADC data. Lane 3 carries the two LSBs of the 14-bit ADC data and an overrange bit. LVDS DAC Data Link There are two LVDS DAC data links for the dual DAC. Each LVDS DAC data link has seven lanes capable of transmitting 14-bit data in one DDR full cycle. Figure 28 shows one LVDS DAC input data link with seven lanes. Rev. B | Page 21 of 56 AD9993 Data Sheet ADC LVDS A/B/C/D DCO_P (DATA CLOCK OUTPUT PORT) LANE 3 D[–2] (SAMPLE N – 1) OVERRANGE (SAMPLE N) 0 D[–1] (SAMPLE N) D[–2] (SAMPLE N) OVERRANGE (SAMPLE N + 1) LANE 2 D[2] (SAMPLE N – 1) D[11] (SAMPLE N) D[8] (SAMPLE N) D[5] (SAMPLE N) D[2] (SAMPLE N) D[11] (SAMPLE N + 1) LANE 1 D[1] (SAMPLE N – 1) D[10] (SAMPLE N) D[7] (SAMPLE N) D[4] (SAMPLE N) D[1] (SAMPLE N) D[10] (SAMPLE N + 1) LANE 0 D[0] (SAMPLE N – 1) D[9] (SAMPLE N) D[6] (SAMPLE N) D[3] (SAMPLE N) D[0] (SAMPLE N) D[9] (SAMPLE N + 1) 12206-032 STROBE+ Figure 27. Output Sample Data Format LANE 6 D[6] (SAMPLE N – 1) D[13] (SAMPLE N) D[6] (SAMPLE N) D[13] (SAMPLE N + 1) D[6] (SAMPLE N + 1) D[13] (SAMPLE N + 2) LANE 5 D[5] (SAMPLE N – 1) D[12] (SAMPLE N) D[5] (SAMPLE N) D[12] (SAMPLE N + 1) D[5] (SAMPLE N + 1) D[12] (SAMPLE N + 2) LANE 4 D[4] (SAMPLE N – 1) D[11] (SAMPLE N) D[4] (SAMPLE N) D[11] (SAMPLE N + 1) D[4] (SAMPLE N + 1) D[11] (SAMPLE N + 2) LANE 3 D[3] (SAMPLE N – 1) D[10] (SAMPLE N) D[3] (SAMPLE N) D[10] (SAMPLE N + 1) D[3] (SAMPLE N + 1) D[10] (SAMPLE N + 2) LANE 2 D[2] (SAMPLE N – 1) D[9] (SAMPLE N) D[2] (SAMPLE N) D[9] (SAMPLE N + 1) D[2] (SAMPLE N + 1) D[9] (SAMPLE N + 2) LANE 1 D[1] (SAMPLE N – 1) D[8] (SAMPLE N) D[1] (SAMPLE N) D[8] (SAMPLE N + 1) D[1] (SAMPLE N + 1) D[8] (SAMPLE N + 2) LANE 0 D[0] (SAMPLE N – 1) D[7] (SAMPLE N) D[0] (SAMPLE N) D[7] (SAMPLE N + 1) D[0] (SAMPLE N + 1) D[7] (SAMPLE N + 2) 12206-033 DCI_P (DATA CLOCK INPUT PORT) Figure 28. DAC Input Sample Data Format LVDS INTERFACE TIMING Minimum 150 200 1000 Unit ps ps Ps DATA tSU tHOLD tSU tHOLD tSU tHOLD Figure 29. DAC Input LVDS Lane Timing ADC Output Interface DATA PERIOD DATA PERIOD DCO_P/ DCO_N STROBE_P/ STROBE_N DATA tSU tHOLD tSU tHOLD tSU tHOLD Figure 30. ADC Output LVDS Lane Timing Rev. B | Page 22 of 56 tSU tHOLD 12206-035 Table 8. DAC DDR LVDS Input Setup and Hold Times Relative to DCI (Guaranteed) CLOCK 12206-034 Table 8 specifies the setup and hold time requirements for DAC LVDS data lane inputs relative to DCI. Figure 29 shows a timing diagram for this interface. DDR DCI edges occur at the position within the data eye (the white region in Figure 29) listed in Table 8. Parameter |tSU| |tHOLD| Data Period DATA PERIOD DATA PERIOD DAC Input Interface Data Sheet AD9993 Table 9 specifies the time between the ADC LVDS data lane output transitions and the DDR DCO clock edge 50% transition point. Table 9. ADC DDR LVDS Data and Strobe Output Setup and Hold Times Relative to DCO (Guaranteed) Parameter |tSU| |tHOLD| Data Period Minimum 400 430 1000 Unit ps ps ps The eight events that trigger an interrupt (if enabled) are • • • • • • • • PLL lock lost PLL locked FIFO Warning 1 FIFO Warning 2 ADC A overrange ADC B overrange ADC C overrange ADC D overrange Interrupt Service Routine LVDS LANE TESTING USING PRBS One pseudorandom binary sequence (PRBS) generator is included for each ADC LVDS lane and one PRBS detector on each DAC LVDS lane. The designs for the generator and detector are implemented as a 23rd-order pseudorandom noise (PN23) sequence defined by the generator polynomial x23 + x18 + 1. The initial seed of the generator is programmable so that each lane can output different values if started simultaneously. The four seed registers are indexed as described in the ADC Register Update Indexing section. For the interrupt service routine, interrupt request management starts by selecting the set of events that require host intervention or monitoring using the bits in the INTEN register. For events requiring host intervention, upon ALERT activation, run the following routine to clear an interrupt request: 1. 2. Read the status of the latched bits in the INT register that are being monitored. Monitor the unlatched status bits in the INT_RAW register directly if needed. Perform any actions that may be required to clear the interrupt(s). Read the INT_RAW bits to verify that the actions taken have cleared the event. Clear the interrupt by writing 1 to the event flag bit in the INT register. DAC PRBS test results are read back on the DAC_A_PRBS_ERRx and DAC_B_PRBS_ERRx error counter registers. The DAC input PRBS error counters are enabled and the error counters cleared by the bits in the DAC_PRBS_CTRL register. ADC output lane PRBS generation is controlled by the bits in the PRBS_GEN_CTRL register. 3. POWER MODE PROGRAMMING TEMPERATURE SENSOR The AD9993 has a POWER_MODES register that allows the user to place sections of the chip into different power modes. The PDWN_PIN_FUNC bit programs the function of the PDWN pin. By default, assertion of PDWN causes the AD9993 to go into full power-down. The clock generator, indexed ADCs, DACs, and PLL synthesizer are all powered down at reset. The indexed ADCs have four power modes. See the ADC Register Update Indexing section for a definition of indexing. The AD9993 has a diode-based temperature sensor for measuring the temperature of the die. The temperature reading is accessed using the TS_RD_LSB and TS_RD_MSB registers. The temperature of the die can be calculated as INTERRUPT REQUEST OPERATION The AD9993 provides an interrupt request signal, ALERT. It is used to notify the user system of significant on-chip events. The ALERT pin is an open-drain, active low output. Eight different event flags provide visibility into the device. These raw events are located in the INT_RAW register. These raw events are always latched in the INT register. If the event is left unmasked, the latched event triggers an external interrupt on ALERT. INTEN is the interrupt enable register. When an event is masked, the INT register captures the event in latched form. A masked event does not cause ALERT to go true. 4. 5. TDIE = Die Temp[15:0] − 41,237 106 where: TDIE is the die temperature in degrees Celsius. Die Temp is the concatenated 16-bit contents of the TD_RD_LSB and TD_RD_MSB registers. The temperature accuracy is ±7°C typical over the −40°C to +85°C range with one point temperature calibration against a known temperature. A typical plot of the die temperature code readback vs. die temperature is shown in Figure 31. Rev. B | Page 23 of 56 AD9993 Data Sheet 51000 DIE CODE READBACK 49000 47000 45000 43000 41000 39000 35000 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) 12206-036 37000 Figure 31. Die Temperature Code Readback vs. Die Temperature Estimates of the ambient temperature can be made if the power dissipation of the device is known. Rev. B | Page 24 of 56 Data Sheet AD9993 START-UP REGISTER SEQUENCES POWER-UP ROUTINE WHEN USING THE ON-CHIP CLOCK SYNTHESIZER To power up the device, set the register settings as described in the following sections. Chip Power-Up SPI.Write(0x008, 0x00); power up all blocks DAC Setup SPI.Write(0x03A, 0x02); DAC data format offset binary Synchronize LVDS Interface SPI.Write(0x00A, 0x82); synchronize ADC data with DCO clock, self cleared but needs following SPI clock SPI.Write(0x00A, 0x81); realign Tx FIFO read and write pointers, self cleared but need following SPI clock SPI.Write(0x00A, 0x90); realign Rx FIFO read and write pointers, DCI clock must be present, self cleared but need following SPI clock Miscellaneous Clear Interrupt or SPI.Write(0x03A, 0x00); DAC data format twos complement SPI.Write(0x0F0, 0xFF) ADC Setup SPI.Write(0x013, 0x00); enable ADC LVDS output and offset binary Enable Interrupt SPI.Write(0x0F1, 0xFF) SPI.Write(0x055, 0x01); ALERT_PULLUP_EN (optional) or SPI.Write(0x013, 0x01); enable ADC LVDS output and twos complement SPI.Write(0x0FF, 0x01); transfer SPI.Write(0x039, 0x12); set DAC CML based on compliance range of 0.7 V and on-chip RFSADJ_x resistors SPI.Write(0x014, 0x01); set LVDS to 2 mA (optional: 1 mA is default) SPI.Write(0x0FF, 0x01); transfer Set this bit if using DAC compliance range > 0.7 V. Synthesizer Setup (62.5 MHz Reference Clock Input) SPI.Write(0x032, 0x01); SYNTH_CP_CAL_EN SPI.Write(0x0FF, 0x01); transfer SPI.Write(0x032, 0x11); start synthesizer calibration SPI.Write(0x0FF, 0x01); transfer SPI.Read(0x02D); synthesizer status 0x01; calibration in progress 0x04; calibration done, synthesizer no lock 0x06;calibration done, synthesizer locked Sythesizer Setup (31.25 MHz Reference Clock Input) SPI.Write(0x033, 0x20); CLKGEN_REFCLK_DIV1 SPI.Write(0x032, 0x01); synthesizer CP_CAL_EN SPI.Write(0x0FF, 0x01); transfer SPI.Write(0x032, 0x11); start synth calibration SPI.Write(0x0FF, 0x01); transfer SPI.Read(0x02D); synthesizer status 0x01; calibration in progress 0x04; calibration done, synthesizer no lock 0x06; calibration done, synthesizer locked SPI.Write(0x0ff, 0x001); data transfer POWER-UP ROUTINE WHEN USING EXTERNAL CLOCK Chip Power-Up SPI.Write(0x008, 0x00); power up all blocks DAC Setup SPI.Write(0x03A, 0x02); DAC data format offset binary or SPI.Write(0x03A, 0x00); DAC data format twos complement ADC Setup SPI.Write(0x013, 0x00); enable ADC LVDS output and offset binary or SPI.Write(0x013, 0x01); enable ADC LVDS output and twos complement SPI.Write(0x014, 0x01); set LVDS to 2 mA (optional: 1 mA is default) SPI.Write(0x0FF, 0x01); transfer External Clock Setup SPI.Write(0x034, 0x07); set external clock mode SPI.Write(0x0FF, 0x01); transfer Rev. B | Page 25 of 56 AD9993 Data Sheet Synchronize LVDS Interface SPI.Write(0x00A, 0x82); synchronize ADC data with DCO clock, self cleared but needs following SPI clock SPI.Write(0x00A, 0x81); realign Tx FIFO read and write pointers, self cleared but need following SPI clock SPI.Write(0x00A, 0x90); realign Rx FIFO read and write pointers, DCI clock must be present, self cleared but need following SPI clock. Miscellaneous Clear Interrupt Enable Interrupt SPI.Write(0x0F1, 0xFF) SPI.Write(0x055, 0x01); ALERT_PULLUP_EN (optional) SPI.Write(0x0FF, 0x01); transfer SPI.Write(0x039, 0x12); set DAC CML based on compliance range of 0.7 V and on-chip RFSADJ_x resistors, Set this bit if using DAC compliance range > 0.7 V SPI.Write(0x0FF, 0x001); data transfer SPI.Write(0x0F0, 0xFF) Rev. B | Page 26 of 56 Data Sheet AD9993 APPLICATIONS INFORMATION DIRECT CONVERSION RADIO APPLICATION A direct conversion radio application of the MxFE is shown in Figure 32. The DAC output signals, IOUTA_P/IOUTA_N and IOUTB_P/IOUTB_N, are differential currents. At 500 MSPS, DAC output signals fall within the 1st Nyquist zone (dc to 250 MHz). DAC current outputs are converted to a voltage and then processed by passive low-pass filters (LPF). The low-pass filters reject out of band signal harmonics and their sampling images. The filter outputs feed the baseband inputs of a quadrature modulator. Quadrature modulator baseband inputs CLKP CLKN PLL AND CLOCK DISTRIBUTION OR BYPASS See the ADRF6518 as ADC Driver section for further information about this interface. PASSIVE LPF IOUTA_x DCI_x DCO_x STROBE_x The MxFE receive signal chain consists of a VGA followed by a quadrature demodulator, then by a programmable LPF, and another VGA. The ADRF6518 is an LPF and VGA specifically designed to drive the analog inputs of high speed ADCs like the ones on the MxFE. The LPF is an antialiasing filter. At 250 MSPS, the ADC signal bandwidth is 125 MHz. AD9993 500MSPS DACs DINxA_x, DINxB_x DOUTxA_x/DOUxB_x must fall within an allowable voltage range, which gives rise to a common-mode voltage requirement at the outputs of the DACs. DATA ASSEMBLER A_VINx, B_VINx ADRF6518 QUAD DEMOD VGA RF IN 250MSPS ADCs 12206-037 IBIAS_TEST A_CML, B_CML, C_CML, D_CML REFERENCES AND BIAS VREF_DAC CML_A, CML_B SERIAL PORT LOGIC RF OUT VGA PROGRAMMABLE LPF AND VGA C_VINx, D_VINx RST SPI_SDI, SPI_SDO SPI_SCLK SPI_CS QUAD MODULATOR IOUTB_x Figure 32. Radio Signal Chain Example Rev. B | Page 27 of 56 AD9993 Data Sheet REGISTER MAP Table 10. SPI Accessible Register Summary Address 0x000 0x001 0x002 0x005 0x008 0x00A 0x00C 0x010 0x011 0x012 0x013 0x014 0x016 0x017 0x020 0x021 0x022 0x023 0x02D 0x02E 0x02F 0x030 0x031 0x032 0x033 0x034 0x035 0x036 0x037 0x038 0x039 0x03A 0x03C 0x03D 0x03F 0x040 0x041 0x042 0x043 0x044 0x045 0x046 0x047 0x048 0x049 0x04A 0x04B 0x04C 0x04D 0x04E Name SPI_CONFIG CHIP_ID CHIP_GRADE DEVICE_INDEX POWER_MODES ALIGN Reserved Reserved Reserved STROBE_CTRL FLEX_OUTPUT_MODE FLEX_OUTPUT_ADJUST FLEX_VREF PRBS_GEN_CTRL PRBS0_SEED_MSB PRBS1_SEED_MSB PRBS2_SEED_MSB PRBS3_SEED_MSB SYNTH_STAT LF_CTRL1 LF_CTRL2 LF_CTRL3 SYNTH_INT SYNTH_CTRL CLKGEN_CTRL1 CLKGEN_CTRL2 DAC_LVDS_CTRL DAC_LVDS_BIAS Reserved Reserved DAC_CTRL DAC_DP_FMT DAC_CAL_IQ_CTRL DAC_CAL_IQ_STAT DAC_FIFO_STS1 DAC_PRBS_CTRL DAC_A_PRBS_ERR0 DAC_A_PRBS_ERR1 DAC_A_PRBS_ERR2 DAC_A_PRBS_ERR3 DAC_A_PRBS_ERR4 DAC_A_PRBS_ERR5 DAC_A_PRBS_ERR6 DAC_B_PRBS_ERR0 DAC_B_PRBS_ERR1 DAC_B_PRBS_ERR2 DAC_B_PRBS_ERR3 DAC_B_PRBS_ERR4 DAC_B_PRBS_ERR5 DAC_B_PRBS_ERR6 Description SPI configuration Chip ID CHIP_GRADE Device index Power mode control (indexed) Align ADC LVDS clocks, ADC FIFO, DAC FIFO Reserved Reserved Reserved Strobe lane control (transfer) Output mode (transfer, indexed) LVDS Tx control (transfer) VREF control (transfer) PRBS generator control (transfer, indexed) 8-bit seed MSB of PRBS generator for Lane0 (transfer, indexed) 8-bit seed MSB of PRBS generator for Lane1 (transfer, indexed) 8-bit seed MSB of PRBS generator for Lane2 (transfer, indexed) 8-bit seed MSB of PRBS generator for Lane3 (transfer, indexed) Synthesizer status Loop filter control signals (transfer) Loop filter control signals (transfer) Loop filter control signals (transfer) Integer value of synthesize divider (transfer) Synthesizer control (transfer) Clock generator control (transfer) CLKGEN control (transfer) DAC LVDS Rx control (transfer) DAC LVDS current bias control (transfer) Reserved Reserved DAC cores control (transfer) DAC datapath format control (transfer) DAC IQ calibration control (transfer) DAC IQ calibration status DAC Rx FIFO Status 1 PRBS detector control (transfer) PRBS Detector Error Count 0 for DAC A PRBS Detector Error Count 1 for DAC A PRBS Detector Error Count 2 for DAC A PRBS Detector Error Count 3 for DAC A PRBS Detector Error Count 4 for DAC A PRBS Detector Error Count 5 for DAC A PRBS Detector Error Count 6 for DAC A PRBS Detector Error Count 0 for DAC B PRBS Detector Error Count 1 for DAC B PRBS Detector Error Count 2 for DAC B PRBS Detector Error Count 3 for DAC B PRBS Detector Error Count 4 for DAC B PRBS Detector Error Count 5 for DAC B PRBS Detector Error Count 6 for DAC B Rev. B | Page 28 of 56 Reset Value 0x18 0xB2 0x01 0x0F 0x55 0x80 0x01 0x00 0x00 0x00 0x11 0x00 0x00 0x00 0x01 0x02 0x03 0x04 0x00 0x77 0xF7 0x00 0x40 0x00 0x00 0x04 0x4D 0x00 0x00 0x00 0x02 0x00 0x04 0x00 0x55 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 RW RW R R RW RW RW R R R RW RW RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R RW R R R R R R R R R R R R R R Data Sheet Address 0x050 0x051 0x052 0x053 0x054 0x055 0x060 0x061 0x062 0x063 0x064 0x0F0 0x0F1 0x0F2 0x0FF Name TS_RD_LSB TS_RD_MSB Reserved Reserved TS_CTRL IRQ_CTRL DDS_CTRL DDS_TW1_0 DDS_TW1_1 DDS_TW1_2 DDS_TW1_3 INT INTEN INT_RAW DEVICE_UPDATE AD9993 Description Bits[7:0] of Temperature sensor data readback Bits[15:8] of Temperature sensor data readback Reserved Reserved Temperature sensor control signals Interrupt pin control DDS control DDS tuning word for Tone 1 DDS tuning word for Tone 1 DDS tuning word for Tone 1 DDS tuning word for Tone 1 Interrupt status Interrupt enable (transfer) Interrupt source status Global device update register Rev. B | Page 29 of 56 Reset Value 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x00 0x00 0xA0 0x19 0x00 0x00 0x00 0x00 RW R R R R RW RW RW RW RW RW RW R RW R RW AD9993 Data Sheet REGISTER DESCRIPTIONS SPI CONFIGURATION REGISTER Address: 0x000, Reset: 0x18, Name: SPI_CONFIG Table 11. Bit Descriptions for SPI_CONFIG Bits 6 Bit Name SPI_LSB_FIRST2 5 SPI_SOFT_RESET2 [4:3] 2 SPI_ADDR_MODE SPI_SOFT_RESET1 1 SPI_LSB_FIRST1 Description SPI least significant bit first. 1 = least significant bit shifted first for all SPI operations. On multibyte SPI operations, addressing increments automatically. 0 = most significant bit shifted first for all SPI operations. On multibyte SPI operations, addressing decrements automatically. This bit must be accessed with all devices enabled and is not reset by setting the SPI_SOFT_RESET1 or SPI_SOFT_RESET2 bit. Self Clearing Soft Reset 1. Reset the SPI registers (self clearing). This bit must be accessed with all devices enabled. 13-bit addressing mode always enabled. Self Clearing Soft Reset 1. Reset the SPI registers (self clearing). This bit must be accessed with all devices enabled. SPI least significant bit first. 1 = least significant bit shifted first for all SPI operations. On multibyte SPI operations, addressing increments automatically. 0 = most significant bit shifted first for all SPI operations. On multibyte SPI operations, addressing decrements automatically. This bit must be accessed with all devices enabled and is not reset by setting the SPI_SOFT_RESET1 or SPI_SOFT_RESET2 bit. Reset 0x0 Access RW 0x0 RW 0x3 0x0 R RW 0x0 RW Reset 0xB2 Access R CHIP ID REGISTER Address: 0x001, Reset: 0xB2, Name: CHIP_ID Table 12. Bit Descriptions for CHIP_ID Bits [7:0] Bit Name CHIP_ID Description Chip ID. Rev. B | Page 30 of 56 Data Sheet AD9993 CHIP GRADE REGISTER Address: 0x002, Reset: 0x01, Name: CHIP_GRADE Table 13. Bit Descriptions for CHIP_GRADE Bits [5:4] [2:0] Bit Name CHIP_SPEED_GRADE CHIP_DIE_REV Description Chip ID/speed grade. Chip die revision. Reset 0x0 0x1 Access R R DEVICE INDEX REGISTER Address: 0x005, Reset: 0x0F, Name: DEVICE_INDEX Table 14. Bit Descriptions for DEVICE_INDEX Bits 3 Bit Name SPI_ADC_D_INDEX 2 SPI_ADC_C_INDEX 1 SPI_ADC_B_INDEX 0 SPI_ADC_A_INDEX Description ADC Core D access enable. 1 = ADC Core D receives the next read/write access from the SPI interface. 0 = ADC Core D does not receive the next read/write access from the SPI interface. ADC Core C access enable. 1 = ADC Core C receives the next read/write access from the SPI interface. 0 = ADC Core C does not receive the next read/write access from the SPI interface. ADC Core B access enable. 1 = ADC Core B receives the next read/write access from the SPI interface. 0 = ADC Core B does not receive the next read/write access from the SPI interface. ADC Core A access enable. 1 = ADC Core A receives the next read/write access from the SPI interface. 0 = ADC Core A does not receive the next read/write access from the SPI interface. Rev. B | Page 31 of 56 Reset 0x1 Access RW 0x1 RW 0x1 RW 0x1 RW AD9993 Data Sheet POWER MODE CONTROL REGISTER Address: 0x008, Reset: 0x55, Name: POWER_MODES Table 15. Bit Descriptions for POWER_MODES Bits 7 Bit Name PDWN_PIN_FUNC 6 [5:4] [3:2] [1:0] CLKGEN_PDWN SYNTH_PDWN_MODE DAC_PDWN_MODE ADC_PDWN_MODE Description Power-down pin function. External power-down pin mode. 0 = assertion of external power-down pin (PDWN) causes chip to enter full power-down mode. 1 = assertion of external power-down pin (PDWN) causes chip to enter standby mode. Clock generation power-down mode. Synthesizer power-down mode. DAC power-down mode. ADC power-down mode. (ADC indexed) 00 = normal mode (power up). 01 = power-down mode; digital datapath clocks disabled; digital datapath held in reset; outputs disabled. 10 = standby mode; digital datapath clocks disabled; outputs disabled. 11 = reserved. Reset 0x0 Access RW 0x1 0x1 0x1 0x1 RW RW RW RW Reset 0x4 Access RW 0x0 0x0 0x0 RW RW RW ALIGN ADC LVDS CLOCKS, ADC FIFO, DAC FIFO REGISTER Address: 0x00A, Reset: 0x80, Name: ALIGN Table 16. Bit Descriptions for ALIGN Bits [7:5] Bit Name RXFIFO_WR_OFFSET 4 1 0 RXFIFO_ALIGN_REQ LVDS_DCO_SYNC TXFIFO_ALIGN Description The distance of Rx FIFO write pointer away from read pointer; needs RXFIFO_ALIGN_REQ asserted to apply this value to datapath. Align Rx FIFO read and write pointers. Sync LVDS Tx DCO with data and strobe (self clear with following SPI clock). Align Tx FIFO read and write pointers (self clear with following SPI clock). Rev. B | Page 32 of 56 Data Sheet AD9993 STROBE LANE CONTROL REGISTER Address: 0x012, Reset: 0x00, Name: STROBE_CTRL Table 17. Bit Descriptions for STROBE_CTRL Bits [7:4] Bit Name STROBE_SAMPLE_RATE 0 STROBE_DUTY_CYCLE_EN Description Sample rate of strobe output. 0 = 1/1 of data sample rate. 1 = 1/2 of data sample rate. 2 = 1/4 of data sample rate. 3 = 1/8 of data sample rate. 4 = 1/16 of data sample rate. 5 = 1/32 of data sample rate. 6 = 1/64 of data sample rate. 7 = 1/128 of data sample rate. 8 = 1/256 of data sample rate. Needs at least one ADC channel working. Enable 50% duty cycle of strobe lane. Needs at least one ADC channel working. Reset 0x0 Access RW 0x0 RW OUTPUT MODE REGISTER Address: 0x013, Reset: 0x11, Name: FLEX_OUTPUT_MODE Table 18. Bit Descriptions for FLEX_OUTPUT_MODE Bits 4 Bit Name DP_OUT_DATA_EN_N 2 DP_OUT_DATA_INV [1:0] DP_OUT_DFS Description Digital datapath output enable (active low) (ADC indexed). 0 = digital output from ADC is enabled. 1 = digital output from ADC is disabled. Digital datapath output invert (ADC indexed). 0 = output from ADC is not inverted. 1 = output from ADC is inverted. Digital datapath output data format select (DFS) (ADC indexed). 00 = offset binary. 01 = twos complement. 10 = gray code. 11 = reserved. Rev. B | Page 33 of 56 Reset 0x1 Access RW 0x0 RW 0x1 RW AD9993 Data Sheet LVDS TX CONTROL REGISTER Address: 0x014, Reset: 0x00, Name: FLEX_OUTPUT_ADJUST Table 19. Bit Descriptions for FLEX_OUTPUT_ADJUST Bits [7:5] Bit Name LVDS_BIAS_DAC [4:2] [1:0] LVDS_BG_TRIM LVDS_DRIVE Description Sets LVDS output swing. 000 = 200 mV. 001 = 227 mV. 010 = 257 mV. 011 = 282 mV. 100 = 296 mV. 101 = 330 mV. 110 = 350 mV. 111 = 372 mV. Band gap trim for LVDS Tx DOUTxx_P and DOUTxx_N pins. Output LVDS drive current. 00 = 1 mA output drive current (default). 01 = 2 mA output drive current. 10 = 3 mA output drive current. 11 = 4 mA output drive current. Reset 0x0 Access RW 0x0 0x0 RW RW Reset 0x0 Access RW VREF CONTROL REGISTER Address: 0x016, Reset: 0x00, Name: FLEX_VREF Table 20. Bit Descriptions for FLEX_VREF Bits [4:0] Bit Name VREF_FS_ADJ Description Main reference full-scale VREF adjustment. 01111 = internal 2.087 V p-p. … 00001 = internal 1.772 V p-p. 00000 = internal 1.75 V p-p. 11111 = internal 1.727 V p-p. … 10000 = internal 1.383 V p-p. Rev. B | Page 34 of 56 Data Sheet AD9993 PRBS GENERATOR CONTROL REGISTER Address: 0x017, Reset: 0x00, Name: PRBS_GEN_CTRL Table 21. Bit Descriptions for PRBS_GEN_CTRL Bits 5 Bit Name STROBE_PRBS_RESET 4 STROBE_PRBS_EN 1 DP_PRBS_GEN_RESET 0 DP_PRBS_GEN_EN Description Reset PRBS generator on strobe lane (transfer not needed). 0 = normal working if PRBS enabled. 1 = reset the PRBS on strobe lane. Enable PRBS testing on strobe lane. 0 = normal mode working with STROBE_DUTY_CYCLE_EN and STROBE_SAMPLE_RATE. 1 = test mode only. Note: needs at least one ADC channel working. Pseudorandom binary sequence generator reset (transfer not needed, ADC indexed). 0 = PRBS generator enabled. 1 = PRBS generator held in reset. Enable PRBS generating on ADC data lanes (ADC indexed). Reset 0x0 Access RW 0x0 RW 0x0 RW 0x0 RW Reset 0x1 Access RW 8-BIT SEED MSB OF PRBS GENERATOR FOR LANE 0 REGISTER Address: 0x020, Reset: 0x01, Name: PRBS0_SEED_MSB Table 22. Bit Descriptions for PRBS0_SEED_MSB Bits [7:0] Bit Name DP_PRBS0_SEED_MSB Description 8-bit MSB seed of PRBS generator in Lane 0 (ADC indexed). The 15-bit LSB is always 0x3AFF. Rev. B | Page 35 of 56 AD9993 Data Sheet 8-BIT SEED MSB OF PRBS GENERATOR FOR LANE 1 REGISTER Address: 0x021, Reset: 0x02, Name: PRBS1_SEED_MSB Table 23. Bit Descriptions for PRBS1_SEED_MSB Bits [7:0] Bit Name DP_PRBS1_SEED_MSB Description 8-bit MSB seed of PRBS generator in Lane 1 (ADC indexed.) The 15-bit LSB is always 0x3AFF. Reset 0x2 Access RW Reset 0x3 Access RW Reset 0x4 Access RW 8-BIT SEED MSB OF PRBS GENERATOR FOR LANE 2 REGISTER Address: 0x022, Reset: 0x03, Name: PRBS2_SEED_MSB Table 24. Bit Descriptions for PRBS2_SEED_MSB Bits [7:0] Bit Name DP_PRBS2_SEED_MSB Description 8-bit MSB seed of PRBS generator in Lane 2 (ADC indexed). The 15-bit LSB is always 0x3AFF. 8-BIT SEED MSB OF PRBS GENERATOR FOR LANE 3 REGISTER Address: 0x023, Reset: 0x04, Name: PRBS3_SEED_MSB Table 25. Bit Descriptions for PRBS3_SEED_MSB Bits [7:0] Bit Name DP_PRBS3_SEED_MSB Description 8-bit MSB seed of PRBS generator in Lane 3 (ADC indexed). The 15-bit LSB is always 0x3AFF. Rev. B | Page 36 of 56 Data Sheet AD9993 SYNTHESIZER STATUS REGISTER Address: 0x02D, Reset: 0x00, Name: SYNTH_STAT Table 26. Bit Descriptions for SYNTH_STAT Bits 2 1 0 Bit Name SYNTH_CP_CAL_DONE SYNTH_LOCKDET SYNTH_VCO_CAL_IN_PROGRESS Description Charge pump calibration done. Synthesizer frequency locked. VCO calibration in progress. Reset 0x0 0x0 0x0 Access R R R LOOP FILTER CONTROL SIGNALS REGISTER Address: 0x02E, Reset: 0x77, Name: LF_CTRL1 Table 27. Bit Descriptions for LF_CTRL1 Bits [6:4] Bit Name LF_C2 [2:0] LF_C1 Description Loop filter coefficient. 000 = 3.13 pF. 001 = 2.26 pF. 010 = 9.39 pF. 011 = 12.52 pF. 100 = 15.65 pF. 101 = 18.78 pF. 110 = 21.91 pF. 111 = 25.04 pF. Loop filter coefficient. 000 = 46.584 pF. 001 = 93.168 pF. 010 = 139.752 pF. 011 = 186.336 pF. 100 = 232.920 pF. 101 = 279.504 pF. 110 = 326.088 pF. 111 = 372.672 pF. Rev. B | Page 37 of 56 Reset 0x7 Access RW 0x7 RW AD9993 Data Sheet LOOP FILTER CONTROL SIGNALS REGISTER Address: 0x02F, Reset: 0xF7, Name: LF_CTRL2 Table 28. Bit Descriptions for LF_CTRL2 Bits [7:6] Bit Name LF_R3 [5:4] LF_R1 [2:0] LF_C3 Description Loop filter coefficient. 00 = 4.63 kΩ. 01 = 2.315 kΩ. 10 = 1.543 kΩ. 11 = 1.157 kΩ Loop filter coefficient. 00 = 12.04 kΩ. 01 = 6.02 kΩ. 10 = 4.01 kΩ. 11 = 3.01 kΩ. Loop filter coefficient. 000 = 0.6325 pF. 001 = 1.265 pF. 010 = 1.8975 pF. 011 = 2.530 pF. 100 = 3.1625 pF. 101 = 3.795 pF. 110 = 4.4275 pF. 111 = 5.06 pF. Reset 0x3 Access RW 0x3 RW 0x7 RW Reset 0x0 0x0 Access RW RW LOOP FILTER CONTROL SIGNALS REGISTER Address: 0x030, Reset: 0x00, Name: LF_CTRL3 Table 29. Bit Descriptions for LF_CTRL3 Bits 1 0 Bit Name EXT_CP_SEL BYP_R3 Description Short external CP pin to charge pump output. Bypass R3 in loop filter. Rev. B | Page 38 of 56 Data Sheet AD9993 INTEGER VALUE OF SYNTHESIZER DIVIDER REGISTER Address: 0x031, Reset: 0x40, Name: SYNTH_INT Table 30. Bit Descriptions for SYNTH_INT Bits [7:0] Bit Name SYNTH_INT Description Integer part on the synthesizer divider (N). N = freq (MHz)/31.25. Reset 0x40 Access RW Reset 0x0 0x0 Access RW RW Reset 0x0 Access RW 0x0 0x0 RW RW 0x0 0x0 RW RW SYNTHESIZER CONTROL REGISTER Address: 0x032, Reset: 0x00, Name: SYNTH_CTRL Table 31. Bit Descriptions for SYNTH_CTRL Bits 4 0 Bit Name SYNTH_CAL_START SYNTH_CP_CAL_EN Description Start synthesizer calibration. Enable charge pump calibration. CLOCK GENERATOR CONTROL REGISTER Address: 0x033, Reset: 0x00, Name: CLKGEN_CTRL1 Table 32. Bit Descriptions for CLKGEN_CTRL1 Bits 7 Bit Name CLKGEN_DC_MODE 6 5 CLKGEN_DC_MODE_INV CLKGEN_REFCLK_DIV1 4 [1:0] CLKGEN_REFDIV_EN CLKGEN_REFDIV_SEL Description DAC clock direct connect to ADC. 0 = ADC clock from 1 GHz. 1 = ADC clock from DAC. Not used. 0 = select REFCLK as PLL reference. 1 = select REFCLK/2 as PLL reference. Selects the output of the on-chip reference clock divider to the PLL. Sets the divider ratio for the on-chip reference clock divider. Rev. B | Page 39 of 56 AD9993 Data Sheet CLKGEN CONTROL REGISTER Address: 0x034, Reset: 0x04, Name: CLKGEN_CTRL2 Table 33. Bit Descriptions for CLKGEN_CTRL2 Bits 3 Bit Name CLKGEN_DAC_M0_INV 2 CLKGEN_ADC_M0_INV [1:0] CLKGEN_MODE Description Swaps CMOS and differential clock buffer for DAC only. 0 = normal mode. 1 = inverts CLKGEN_MODE[0] for DAC only. Swaps CMOS and differential clock buffer for ADC only. 0 = normal mode. 1 = inverts CLKGEN_MODE[0] for ADC only. Configures the IC for external or internal clock. 00 = selects on-chip synthesizer to drive LVDS at 1 GHz, ADC at 250 MHz, and DAC at 500 MHz. 01 = same as 00 except uses differential clock buffer for DAC and ADC. 10 = selects external clock source to drive LVDS at clock rate, ADC at clock rate divide by 4, and DAC at clock rate divide by 2. Minimum clock rate = 200 MHz. 11 = same as 10 except uses differential clock buffer for DAC and ADC. DAC LVDS RX CONTROL REGISTER Address: 0x035, Reset: 0x4D, Name: DAC_LVDS_CTRL Rev. B | Page 40 of 56 Reset 0x0 Access RW 0x1 RW 0x0 RW Data Sheet AD9993 Table 34. Bit Descriptions for DAC_LVDS_CTRL Bits [3:0] Bit Name DAC_RES_CAL Description DAC LVDS Rx termination selection. 0001 = 977 Ω. 0010 = 497 Ω. 0011 = 341 Ω. 0100 = 267 Ω. 0101 = 215 Ω. 0110 = 184 Ω. 0111 = 160 Ω. 1000 = 145Ω. 1001 = 131 Ω. 1010 = 121 Ω. 1011 = 112 . 1100 = 105 Ω. 1101 = 99 Ω. 1110 = 93Ω. 1111 = 89 Ω. Reset 0xD Access RW Reset 0x0 Access RW 0x0 RW DAC LVDS CURRENT BIAS CONTROL REGISTER Address: 0x036, Reset: 0x00, Name: DAC_LVDS_BIAS Table 35. Bit Descriptions for DAC_LVDS_BIAS Bits [5:4] Bit Name DAC_IAMP [1:0] DAC_IRCV Description Adjust bias current for LVDS DAC receiver. 00 = nominal. 01 = 25%. 10 = 50%. 11 = 75%. Adjust the bias current to cascade voltage for LVDS DAC receiver. 00 = nominal. 01 = 25%. 10 = 50%. 11 = 75%. Rev. B | Page 41 of 56 AD9993 Data Sheet DAC CORES CONTROL REGISTER Address: 0x039, Reset: 0x02, Name: DAC_CTRL Table 36. Bit Descriptions for DAC_CTRL Bits 7 Bit Name DAC_TRANS [6:4] DAC_VCM_VREF_BIT 1 0 DAC_RSET_EN DAC_REF_EXT Description DAC input latch data transfer method select. 0 = edge triggered. 1 = level triggered. Sets DAC common-mode level. 000 = 0.0 V. 001 = 0.2 V. 010 = 0.3 V. 011 = 0.4 V 100 = 0.5 V 101 = 0.6 V 110 = 0.7 V. 111 = 0.8 V. Selects on-chip RFSADJ_x resistor. Selects external DAC Reference voltage. Set to 1 to use an off-chip DAC reference. Reset 0x0 Access RW 0x0 RW 0x1 0x0 RW RW Reset 0x0 Access RW DAC DATAPATH FORMAT CONTROL REGISTER Address: 0x03A, Reset: 0x00, Name: DAC_DP_FMT Table 37. Bit Descriptions for DAC_DP_FMT Bits 1 Bit Name DAC_BINARY Description Enable binary offset data format (default is twos complement). 0 = twos complement. 1 = binary offset. Rev. B | Page 42 of 56 Data Sheet AD9993 DAC IQ CALIBRATION CONTROL REGISTER Address: 0x03C, Reset: 0x04, Name: DAC_CAL_IQ_CTRL Table 38. Bit Descriptions for DAC_CAL_IQ_CTRL Bits 5 4 2 Bit Name DAC_CAL_IQ_START DAC_CAL_IQ_RESET PD_DAC_CAL_CLK 1 0 DAC_CAL_IQ_SEL DAC_CAL_IQ_EN Description Starts DAC IQ calibration. Resets DAC IQ calibration. 0 = DAC IQ calibration clock enabled. Must be 0 to run IQ calibration. 1 = DAC IQ calibration clock disabled. Selects output of IQ calibration. Must be 1 to run IQ calibration. Enables DAC I to Q calibration. Must stay high until DAC_CAL_IQ_DONE = 1. Reset 0x0 0x0 0x1 Access RW RW RW 0x0 0x0 RW RW DAC IQ CALIBRATION STATUS REGISTER Address: 0x03D, Reset: 0x00, Name: DAC_CAL_IQ_STAT Table 39. Bit Descriptions for DAC_CAL_IQ_STAT Bits [7:1] 0 Bit Name DAC_CAL_IQ_RD DAC_CAL_IQ_DONE Description Value of DAC IQ calibration, valid when DAC_CAL_IQ_DONE = 1. Indicates when DAC IQ calibration is done. Reset 0x0 0x0 Access R R Reset 0x55 Access R DAC RX FIFO STATUS 1 REGISTER Address: 0x03F, Reset: 0x55, Name: DAC_FIFO_STS1 Table 40. Bit Descriptions for DAC_FIFO_STS1 Bits [7:0] Bit Name RXFIFO_THERM Description Thermal value of FIFO usage. Rev. B | Page 43 of 56 AD9993 Data Sheet PRBS DETECTOR CONTROL REGISTER Address: 0x040, Reset: 0x00, Name: DAC_PRBS_CTRL Table 41. Bit Descriptions for DAC_PRBS_CTRL Bits 1 0 Bit Name PRBS_DET_ERRCLR PRBS_DET_EN Description Clear the error count of PRBS detector (transfer not required). Enable the PRBS detector. Reset 0x0 0x0 Access RW RW Reset 0x0 Access R Reset 0x0 Access R PRBS DETECTOR ERROR COUNT 0 FOR DAC A REGISTER Address: 0x041, Reset: 0x00, Name: DAC_A_PRBS_ERR0 Table 42. Bit Descriptions for DAC_A_PRBS_ERR0 Bits [7:0] Bit Name PRBS_DET_ERRCNT_A0 Description Error count of Lane 0 of DAC A. PRBS DETECTOR ERROR COUNT 1 FOR DAC A REGISTER Address: 0x042, Reset: 0x00, Name: DAC_A_PRBS_ERR1 Table 43. Bit Descriptions for DAC_A_PRBS_ERR1 Bits [7:0] Bit Name PRBS_DET_ERRCNT_A1 Description Error count of Lane 1 of DAC A. Rev. B | Page 44 of 56 Data Sheet AD9993 PRBS DETECTOR ERROR COUNT 2 FOR DAC A REGISTER Address: 0x043, Reset: 0x00, Name: DAC_A_PRBS_ERR2 Table 44. Bit Descriptions for DAC_A_PRBS_ERR2 Bits [7:0] Bit Name PRBS_DET_ERRCNT_A2 Description Error count of Lane 2 of DAC A. Reset 0x0 Access R Reset 0x0 Access R Reset 0x0 Access R PRBS DETECTOR ERROR COUNT 3 FOR DAC A REGISTER Address: 0x044, Reset: 0x00, Name: DAC_A_PRBS_ERR3 Table 45. Bit Descriptions for DAC_A_PRBS_ERR3 Bits [7:0] Bit Name PRBS_DET_ERRCNT_A3 Description Error count of Lane 3 of DAC A. PRBS DETECTOR ERROR COUNT 4 FOR DAC A REGISTER Address: 0x045, Reset: 0x00, Name: DAC_A_PRBS_ERR4 Table 46. Bit Descriptions for DAC_A_PRBS_ERR4 Bits [7:0] Bit Name PRBS_DET_ERRCNT_A4 Description Error count of Lane 4 of DAC A. Rev. B | Page 45 of 56 AD9993 Data Sheet PRBS DETECTOR ERROR COUNT 5 FOR DAC A REGISTER Address: 0x046, Reset: 0x00, Name: DAC_A_PRBS_ERR5 Table 47. Bit Descriptions for DAC_A_PRBS_ERR5 Bits [7:0] Bit Name PRBS_DET_ERRCNT_A5 Description Error count of Lane 5 of DAC A. Reset 0x0 Access R Reset 0x0 Access R Reset 0x0 Access R PRBS DETECTOR ERROR COUNT 6 FOR DAC A REGISTER Address: 0x047, Reset: 0x00, Name: DAC_A_PRBS_ERR6 Table 48. Bit Descriptions for DAC_A_PRBS_ERR6 Bits [7:0] Bit Name PRBS_DET_ERRCNT_A6 Description Error count of Lane 6 of DAC A. PRBS DETECTOR ERROR COUNT 0 FOR DAC B REGISTER Address: 0x048, Reset: 0x00, Name: DAC_B_PRBS_ERR0 Table 49. Bit Descriptions for DAC_B_PRBS_ERR0 Bits [7:0] Bit Name PRBS_DET_ERRCNT_B0 Description Error count of Lane 0 of DAC B. Rev. B | Page 46 of 56 Data Sheet AD9993 PRBS DETECTOR ERROR COUNT 1 FOR DAC B REGISTER Address: 0x049, Reset: 0x00, Name: DAC_B_PRBS_ERR1 Table 50. Bit Descriptions for DAC_B_PRBS_ERR1 Bits [7:0] Bit Name PRBS_DET_ERRCNT_B1 Description Error count of Lane 1 of DAC B. Reset 0x0 Access R Reset 0x0 Access R Reset 0x0 Access R PRBS DETECTOR ERROR COUNT 2 FOR DAC B REGISTER Address: 0x04A, Reset: 0x00, Name: DAC_B_PRBS_ERR2 Table 51. Bit Descriptions for DAC_B_PRBS_ERR2 Bits [7:0] Bit Name PRBS_DET_ERRCNT_B2 Description Error count of Lane 2 of DAC B. PRBS DETECTOR ERROR COUNT 3 FOR DAC B REGISTER Address: 0x04B, Reset: 0x00, Name: DAC_B_PRBS_ERR3 Table 52. Bit Descriptions for DAC_B_PRBS_ERR3 Bits [7:0] Bit Name PRBS_DET_ERRCNT_B3 Description Error count of Lane 3 of DAC B. Rev. B | Page 47 of 56 AD9993 Data Sheet PRBS DETECTOR ERROR COUNT 4 FOR DAC B REGISTER Address: 0x04C, Reset: 0x00, Name: DAC_B_PRBS_ERR4 Table 53. Bit Descriptions for DAC_B_PRBS_ERR4 Bits [7:0] Bit Name PRBS_DET_ERRCNT_B4 Description Error count of Lane 4 of DAC B. Reset 0x0 Access R Reset 0x0 Access R Reset 0x0 Access R PRBS DETECTOR ERROR COUNT 5 FOR DAC B REGISTER Address: 0x04D, Reset: 0x00, Name: DAC_B_PRBS_ERR5 Table 54. Bit Descriptions for DAC_B_PRBS_ERR5 Bits [7:0] Bit Name PRBS_DET_ERRCNT_B5 Description Error count of Lane 5 of DAC B. PRBS DETECTOR ERROR COUNT 6 FOR DAC B REGISTER Address: 0x04E, Reset: 0x00, Name: DAC_B_PRBS_ERR6 Table 55. Bit Descriptions for DAC_B_PRBS_ERR6 Bits [7:0] Bit Name PRBS_DET_ERRCNT_B6 Description Error count of Lane 6 of DAC B. Rev. B | Page 48 of 56 Data Sheet AD9993 BITS[7:0] OF TEMPERATURE SENSOR DATA READBACK REGISTER Address: 0x050, Reset: 0x00, Name: TS_RD_LSB Table 56. Bit Descriptions for TS_RD_LSB Bits [7:0] Bit Name TEMP_SENSE_RDBK_LSB Description Temperature sensor measurement MSB. Reset 0x0 Access R Reset 0x0 Access R BITS[15:8] OF TEMPERATURE SENSOR DATA READBACK REGISTER Address: 0x051, Reset: 0x00, Name: TS_RD_MSB Table 57. Bit Descriptions for TS_RD_MSB Bits [7:0] Bit Name TEMP_SENSE_RDBK_MSB Description Temperature sensor neasurement LSB. TEMPERATURE SENSOR CONTROL SIGNALS REGISTER Address: 0x054, Reset: 0x01, Name: TS_CTRL Table 58. Bit Descriptions for TS_CTRL Bits 0 Bit Name TEMP_SENSE_PD Description Turn off temperature sensor. Rev. B | Page 49 of 56 Reset 0x1 Access RW AD9993 Data Sheet INTERRUPT PIN CONTROL REGISTER Address: 0x055, Reset: 0x00, Name: IRQ_CTRL Table 59. Bit Descriptions for IRQ_CTRL Bits 0 Bit Name ALERT_PULLUP_EN Description Interrupt (alarm) pin pull-up enable. Reset 0x0 Access RW Reset 0x0 0x0 Access RW RW 0x0 RW 0x0 RW DDS CONTROL REGISTER Address: 0x060, Reset: 0x00, Name: DDS_CTRL Table 60. Bit Descriptions for DDS_CTRL Bits 6 [3:2] Bit Name DDS_1DB_DIS DDS_ATTEN 1 DDS_CLK_INV 0 DDS_EN Description Disable the −1 db attenuation on both DDS tone outputs. Amplitude attenuation. 00 = ×1/1 amplitude. 01 = ×1/2 amplitude. 10 = ×1/4 amplitude. 11 = ×1/8 amplitude. DDS clock invert bit. 0 = normal. DDS clock not inverted. 1 = DDS clock inverted. Enable DDS Tone 1 output. Rev. B | Page 50 of 56 Data Sheet AD9993 DDS TUNING WORD FOR TONE 1 REGISTER Address: 0x061, Reset: 0x00, Name: DDS_TW1_0 Table 61. Bit Descriptions for DDS_TW1_0 Bits [7:0] Bit Name DDS_TW1_0 Description 32-bit tuning word for Tone 1 combined by DDS_TW1_3, DDS_TW1_2, DDS_TW1_1, and DDS_TW1_0. The default configuration is for 50 MHz when working with 500 MHz DAC clock. Reset 0x0 Access RW Reset 0x0 Access RW DDS TUNING WORD FOR TONE 1 REGISTER Address: 0x062, Reset: 0x00, Name: DDS_TW1_1 Table 62. Bit Descriptions for DDS_TW1_1 Bits [7:0] Bit Name DDS_TW1_1 Description 32-bit tuning word for Tone 1 combined by DDS_TW1_3, DDS_TW1_2, DDS_TW1_1, and DDS_TW1_0. The default configuration is for 50 MHz when working with 500 MHz DAC clock. Rev. B | Page 51 of 56 AD9993 Data Sheet DDS TUNING WORD FOR TONE 1 REGISTER Address: 0x063, Reset: 0xA0, Name: DDS_TW1_2 Table 63. Bit Descriptions for DDS_TW1_2 Bits [7:0] Bit Name DDS_TW1_2 Description 32-bit tuning word for Tone 1 combined by DDS_TW1_3, DDS_TW1_2, DDS_TW1_1, and DDS_TW1_0. The default configuration is for 50 MHz when working with 500 MHz DAC clock. Reset 0xa0 Access RW Reset 0x19 Access RW DDS TUNING WORD FOR TONE 1 REGISTER Address: 0x064, Reset: 0x19, Name: DDS_TW1_3 Table 64. Bit Descriptions for DDS_TW1_3 Bits [7:0] Bit Name DDS_TW1_3 Description 32-bit tuning word for Tone 1 combined by DDS_TW1_3, DDS_TW1_2, DDS_TW1_1, and DDS_TW1_0. The default configuration is for 50 MHz when working with 500 MHz DAC clock. Rev. B | Page 52 of 56 Data Sheet AD9993 INTERRUPT STATUS REGISTER Address: 0x0F0, Reset: 0x00, Name: INT Table 65. Bit Descriptions for INT Bits 7 6 5 4 3 2 1 0 Bit Name ADC_D_OVR_IRQ ADC_C_OVR_IRQ ADC_B_OVR_IRQ ADC_A_OVR_IRQ FIFO_WARN2_IRQ FIFO_WARN1_IRQ PLL_UNLOCK_IRQ PLL_LOCKED_IRQ Description ADC D overrange interrupt (write 1 to clear). ADC C overrange interrupt (write 1 to clear). ADC B overrange interrupt(write 1 to clear). ADC A overrange interrupt (write 1 to clear). FIFO Warning 2 interrupt (write 1 to clear). FIFO Warning 1 interrupt (write 1 to clear). PLL unlock interrupt (write 1 to clear). PLL lock interrupt (write 1 to clear). INTERRUPT ENABLE REGISTER Address: 0x0F1, Reset: 0x00, Name: INTEN Rev. B | Page 53 of 56 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW1C RW1C RW1C RW1C RW1C RW1C RW1C RW1C AD9993 Data Sheet Table 66. Bit Descriptions for INTEN Bits 7 6 5 4 3 2 1 0 Bit Name ADC_D_OVR_IRQ_EN ADC_C_OVR_IRQ_EN ADC_B_OVR_IRQ_EN ADC_A_OVR_IRQ_EN FIFO_WARN2_IRQ_EN FIFO_WARN1_IRQ_EN PLL_UNLOCK_IRQ_EN PLL_LOCKED_IRQ_EN Description Enable ADC D Overrange interrupt. Enable ADC C Overrange interrupt. Enable ADC B Overrange interrupt. Enable ADC A Overrange interrupt. Enable FIFO Warning 2 interrupt. Enable FIFO Warning 1 interrupt. Enable PLL unlock interrupt. Enable PLL lock interrupt. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access RW RW RW RW RW RW RW RW Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R R R R R R R INTERRUPT SOURCE STATUS REGISTER Address: 0x0F2, Reset: 0x00, Name: INT_RAW Table 67. Bit Descriptions for INT_RAW Bits 7 6 5 4 3 2 1 0 Bit Name ADC_D_OVR_RAW ADC_C_OVR_RAW ADC_B_OVR_RAW ADC_A_OVR_RAW FIFO_WARN2_RAW FIFO_WARN1_RAW PLL_UNLOCK_RAW PLL_LOCKED_RAW Description ADC D overrange interrupt source. ADC C overrange interrupt source. ADC B overrange interrupt source. ADC A overrange interrupt source. FIFO Warning 2 interrupt source. FIFO Warning 1 interrupt source. PLL unlock interrupt source. PLL lock interrupt source. Rev. B | Page 54 of 56 Data Sheet AD9993 GLOBAL DEVICE UPDATE REGISTER Address: 0x0FF, Reset: 0x00, Name: DEVICE_UPDATE Table 68. Bit Descriptions for DEVICE_UPDATE Bits 0 Bit Name CHIP_REGMAP_TRANSFER Description Register map master/slave transfer bit. Self clearing bit used to synchronize the transfer of data from the master to the slave registers. 0 = no effect 1 = transfer data from the master registers written by the register maps to the slave registers seen by the datapath. Rev. B | Page 55 of 56 Reset 0x0 Access RW AD9993 Data Sheet OUTLINE DIMENSIONS A B C D E F G H J K L M N P 10.40 BSC SQ 0.80 BSC 0.80 REF TOP VIEW *1.40 1.24 1.15 A1 BALL CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BOTTOM VIEW DETAIL A 0.54 REF DETAIL A 0.36 REF SEATING PLANE 0.97 0.90 0.83 0.39 0.34 0.29 0.50 COPLANARITY 0.45 0.12 0.40 BALL DIAMETER *COMPLIANT TO JEDEC STANDARDS MO-219 WITH EXCEPTION TO PACKAGE HEIGHT. 05-09-2011-A A1 BALL CORNER 12.10 12.00 SQ 11.90 Figure 33. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-196-9) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD9993BBCZ AD9993BBCZRL AD9993-EBZ 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board Z = RoHS Compliant Part. ©2014–2017 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12260-0-12/17(B) Rev. B | Page 56 of 56 Package Option BC-196-9 BC-196-9