OVP and EMI Protected, Precision,
Low Noise and Bias Current Op Amps
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
PIN CONNECTION DIAGRAM
OUT A 1
TOP VIEW
(Not to Scale)
V+
OUT B
6
–IN B
5
+IN B
The ADA4177-1/ADA4177-2/ADA4177-4 operate over the
−40°C to +125°C industrial temperature range. The ADA4177-1/
ADA4177-2 are available in an 8-lead SOIC package and an 8-lead
MSOP package. The ADA4177-4 is available in a 14-lead TSSOP
and a 14-lead SOIC package.
12
10
8
VSY = ±15V
6
4
2
0
–2
–4
–6
–30
–10
10
30
VIN (V)
50
12282-446
–8
–10
–50
GENERAL DESCRIPTION
Rev. E
+IN A 3
8
7
Applications for these amplifiers include sensor signal conditioning
(such as thermocouples, resistor thermal detectors (RTDs), and
strain gages), process control front-end amplifiers, and
precision diode power measurement in optical and wireless
transmission systems.
Wireless base station control circuits
Optical network control circuits
Instrumentation
Sensors and controls
Thermocouples, RTDs, strain gages, shunt current
measurements
The inputs of the ADA4177-1/ADA4177-2/ADA4177-4 feature
outstanding precision amplifier robustness, providing input
protection against signal excursions 32 V beyond either supply,
as well as 70 dB of rejection for electromagnetic interference (EMI)
at 1000 MHz.
ADA4177-2
Figure 1. ADA4177-2, for Additional Packages and Models, See the Pin
Configurations and Function Descriptions Section
APPLICATIONS
The ADA4177-1 single-channel, ADA4177-2 dual-channel, and
ADA4177-4 quad-channel amplifiers feature low offset voltage
(2 µV typical) and drift (1 µV/°C maximum), low input bias
current, low noise, and low current consumption (500 µA
typical). Outputs are stable with capacitive loads of more than
1000 pF with no external compensation.
–IN A 2
V– 4
INPUT BIAS CURRENT (mA)
Low offset voltage: 60 µV maximum at 25°C (8-lead and
14-lead SOIC)
Low offset voltage drift: 1 µV/°C maximum (8-lead and
14-lead SOIC)
Low input bias current: 1 nA maximum at 25°C
Low voltage noise density: 8 nV/√Hz typical at 1 kHz
Large signal voltage gain (AVO): 100 dB minimum over full
supply voltage and operating temperature
Input overvoltage protection to 32 V above and below the
supply voltage rail
Integrated EMI filter
70 dB typical rejection at 1000 MHz
90 dB typical rejection at 2400 MHz
Rail-to-rail output swing
Low supply current: 500 µA typical per amplifier
Wide bandwidth
Gain bandwidth product (AV = 100): 3.5 MHz typical
Unity-gain crossover (AV = 1): 3.5 MHz typical
−3 dB bandwidth (AV = 1): 6 MHz typical
Dual-supply operation
Specified at ±5 V to ±15 V, operates over ±2.5 V to ±18 V
Unity-gain stable
No phase reversal
Long-term offset voltage drift (10,000 hours): 2 µV typical
Temperature hysteresis: 2 µV typical
12282-001
FEATURES
Figure 2. Overvoltage Current Limiting, Voltage Follower Configuration
Table 1. Evolution of Protected Input Op Amps by Generation1
Gen. 1,
OVP (10 V)
OP191
OP291
OP491
1
Gen. 2,
OVP (25 V)
ADA4091-2
ADA4091-4
ADA4092-4
Gen. 3,
OVP (32 V)
ADA4096-2
ADA4096-4
Gen. 4
EMI Filters
AD8657
AD8659
AD8546
AD8548
ADA4661-2
ADA4666-2
Gen. 5, OVP
(32 V) + EMI
ADA4177-1
ADA4177-2
ADA4177-4
Gen. means generation.
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ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 26
Applications ....................................................................................... 1
Active Overvoltage Protection ................................................. 26
General Description ......................................................................... 1
Pin Connection Diagram ................................................................ 1
Limiting Overvoltage Current Out of the Positive Supply Pin
....................................................................................................... 27
Revision History ............................................................................... 3
EMI Protection ........................................................................... 28
Specifications..................................................................................... 4
Self Heating ................................................................................. 28
Electrical Characteristics, ±5 V .................................................. 4
Using the ADA4177-1/ADA4177-2/ADA4177-4 as a
Comparator ................................................................................. 28
Electrical Characteristics, ±15 V ................................................ 6
Absolute Maximum Ratings ....................................................... 8
Maximum Power Dissipation ..................................................... 8
Thermal Resistance ...................................................................... 8
ESD Caution .................................................................................. 8
Pin Configurations and Function Descriptions ........................... 9
Typical Performance Characteristics ........................................... 12
Output Phase Reversal ............................................................... 29
Proper Printed Circuit Board (PCB) Layout .......................... 29
Long-Term Drift ......................................................................... 29
Temperature Hysteresis ............................................................. 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 33
Theory of Operation ...................................................................... 25
Rev. E | Page 2 of 33
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
REVISION HISTORY
8/2018—Rev. D to Rev. E
Change to Input Capacitance (CINCM) Parameter, Table 2............ 4
Change to Input Capacitance (CINCM) Parameter, Table 3............ 6
Changes to Ordering Guide ...........................................................33
5/2017—Rev. C to Rev. D
Changes to Features Section, Applications Section, and General
Description Section ........................................................................... 1
Changes to Figure 9, Figure 10, Figure 11, Figure 12, Figure 13,
and Figure 14 ...................................................................................12
Changes to Figure 15 and Figure 16 .............................................13
Changes to Add an External Series Input Resistor Section and
Figure 85 ...........................................................................................26
Changes to Self Heating Section ...................................................28
Added Long-Term Drift Section ...................................................29
Added Temperature Hysteresis Section, Figure 97, Figure 98, and
Figure 99; Renumbered Sequentially ...............................................30
4/2015—Rev. B to Rev. C
Added ADA4177-1 ............................................................ Universal
Deleted Figure 2; Renumbered Sequentially ................................. 1
Change to Table 1 .............................................................................. 1
Added Figure 5, Figure 6, and Table 7; Renumbered
Sequentially ........................................................................................ 9
Changes to Figure 16, Figure 17, Figure 19, and Figure 20 .......12
Changes to Figure 26 ......................................................................14
Changes to Figure 34, Figure 35, Figure 37, and Figure 39 .......16
Changes to Figure 46, Figure 47, Figure 49, and Figure 50 .......17
Changes to Figure 59 and Figure 62 .............................................19
Changes to Figure 63, Figure 65, Figure 66, and Figure 68 .......20
Changes to Figure 69 and Figure 72 .............................................21
Changes to Figure 75 and Figure 78 .............................................22
Added Figure 77 and Figure 80 .....................................................22
Added Figure 81 to Figure 83 ........................................................23
Changes to Theory of Operation Section ....................................24
Changes to Input Protection Circuit Section and Limiting
Overvoltage Current Out of the Positive Supply Pin Section ... 26
Changes to Using the ADA4177-1/ADA4177-2/ADA4177-4 as
a Comparator Section ..................................................................... 27
Changes to Ordering Guide ........................................................... 31
1/2015—Rev. A to Rev. B
Added ADA4177-4 ............................................................ Universal
Reorganized Layout ........................................................... Universal
Added Figure 2; Renumbered Sequentially ................................... 1
Changes to Features and General Description Section................ 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 5
Changes to Table 5 ............................................................................ 7
Added Figure 6, Figure 7, and Table 7; Renumbered
Sequentially ........................................................................................ 9
Added Figure 10 and Figure 13 ..................................................... 10
Replaced Figure 15 and Figure 18 ................................................. 11
Added Figure 14, Figure 16, Figure 17, and Figure 19 ............... 11
Changes to Figure 20, Figure 21, Figure 23, and Figure 24 ....... 12
Changes to Figure 32 and Figure 33 ............................................. 14
Changes to Figure 38 and Figure 41 ............................................. 15
Changes to Figure 58 and Figure 61 ............................................. 18
Changes to Figure 62, Figure 65, and Figure 66 .......................... 19
Changes to Figure 69 and Figure 72 ............................................. 20
Change to Figure 87 Caption ......................................................... 25
Updated Outline Dimensions........................................................ 27
Added Figure 93 and Figure 94 ..................................................... 28
Changes to Ordering Guide ........................................................... 29
10/2014—Rev. 0 to Rev. A
Changes to Large Signal Voltage Gain Parameter, Test
Conditions/Comments Column, Table 3....................................... 5
10/2014—Revision 0: Initial Version
Rev. E | Page 3 of 33
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS, ±5 V
VSY = ±5.0 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
8-Lead SOIC and 14-Lead SOIC
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
2
60
120
120
200
150
300
µV
µV
µV
µV
µV
µV
40
110
µV
µV
1
1.6
+1
+2
+0.75
+1.5
+3.5
1
8
4
100
µV/°C
µV/°C
nA
nA
nA
nA
V
mA
mA
dB
dB
dB
dB
dB
dB
pF
pF
MΩ
GΩ
25
V
V
V
V
V
V
V
V
mA
36
48
0.11
mA
mA
Ω
VOS
−40°C < TA < +125°C
8-Lead MSOP
3
−40°C < TA < +125°C
14-Lead TSSOP
3
−40°C < TA < +125°C
Offset Voltage Matching
8-Lead SOIC
8-Lead MSOP
Offset Voltage Drift
8-Lead SOIC and 14-Lead SOIC
8-Lead MSOP and 14-Lead TSSOP
Input Bias Current
ΔVOS/ΔT
−40°C < TA < +125°C
IB
−40°C < TA < +125°C
Input Offset Current
IOS
−40°C < TA < +125°C
Input Voltage Range
Overvoltage Current Limit1
IVR
IOVP
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Input Capacitance
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage
High
Low
Output Current
Short-Circuit Current
Sourcing
Sinking
Closed-Loop Output Impedance
CINDM
CINCM
RDIFF
RCM
VOH
VOL
IOUT
ISC
ZOUT
5 V < VCM < 37 V
−37 V < VCM < −5 V
VCM = −3.5 V to +3.5 V
−40°C < TA < +125°C
RL = 2 kΩ, VOUT = −4.5 V to +4.5 V
−40°C < TA < +125°C
RL = 10 kΩ, VOUT = −4.5 V to +4.5 V
−40°C < TA < +125°C
Differential mode
Common mode
Differential mode
Common mode
ILOAD = 1 mA
−40°C < TA < +125°C
ILOAD = 7 mA
−40°C < TA < +125°C
ILOAD = 1 mA
−40°C < TA < +125°C
ILOAD = 7 mA
−40°C < TA < +125°C
VDROPOUT < 1 V
TA = 25°C
f = 1 kHz, AV = 1
Rev. E | Page 4 of 33
−1
−2
−0.75
−1.5
−3.5
122
120
108
100
115
110
−0.4
+0.1
12
10
130
110
120
4.95
4.90
4.80
4.75
−4.95
−4.90
−4.80
−4.75
Data Sheet
Parameter
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
To 0.1%
To 0.01%
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Closed-Loop Bandwidth
Total Harmonic Distortion Plus Noise
EMI Rejection of +INx
f = 1000 MHz
f = 2400 MHz
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
1
ADA4177-1/ADA4177-2/ADA4177-4
Symbol
Test Conditions/Comments
Min
Typ
PSRR
VS = ±2.5 V to ±18 V
−40°C < TA < +125°C
VOUT = 0 V
−40°C < TA < +125°C
125
120
145
ISY
SR
tS
GBP
UGC
f−3 dB
THD + N
EMIRR
en p-p
en
in
500
Max
Unit
560
600
dB
dB
µA
µA
RL = 2 kΩ
1.5
V/µs
VIN = 1 V step, RL = 2 kΩ, AV = −1
VIN = 1 V step, RL = 2 kΩ, AV = −1
VIN = 10 mV p-p, RL = 2 kΩ, AV = 100
VIN = 10 mV p-p, RL = 2 kΩ, AV = 1
VIN = 10 mV p-p, RL = 2 kΩ, AV = 1
VIN = 1 V rms, RL = 2 kΩ, AV = +1, f = 1 kHz
VIN = 200 mV p-p
1.8
3.5
3.5
3.5
6
0.003
µs
µs
MHz
MHz
MHz
%
70
90
dB
dB
175
10
8
0.2
nV p-p
nV/√Hz
nV/√Hz
pA/√Hz
0.1 Hz to 10 Hz
f = 10 Hz
f = 1 kHz
f = 1 kHz
All inputs are stressed to 32 V beyond supplies for 500 ms. See Figure 71 for the typical input bias current vs. the input voltage over the overvoltage protected input range.
Rev. E | Page 5 of 33
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
ELECTRICAL CHARACTERISTICS, ±15 V
VSY = ±15 V, VCM = 0 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
INPUT CHARACTERISTICS
Offset Voltage
8-Lead SOIC and 14-Lead SOIC
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
2
60
120
120
200
150
300
µV
µV
µV
µV
µV
µV
40
110
µV
µV
1
1.6
+1
+2
+0.75
+1.5
+13.5
1
8
4
130
µV/°C
µV/°C
nA
nA
nA
nA
V
mA
mA
dB
dB
dB
dB
dB
dB
pF
pF
MΩ
GΩ
25
V
V
V
V
V
V
V
V
mA
53
65
0.08
mA
mA
Ω
VOS
−40°C < TA < +125°C
8-Lead MSOP
3
−40°C < TA < +125°C
14-Lead TSSOP
3
−40°C < TA < +125°C
Offset Voltage Matching
8-Lead SOIC
8-Lead MSOP
Offset Voltage Drift
8-Lead SOIC and 14-Lead SOIC
8-Lead MSOP and 14-Lead TSSOP
Input Bias Current
ΔVOS/ΔT
−40°C < TA < +125°C
IB
−40°C < TA < +125°C
Input Offset Current
IOS
−40°C < TA < +125°C
Input Voltage Range
Overvoltage Current Limit1
IVR
IOVP
Common-Mode Rejection Ratio
CMRR
Large Signal Voltage Gain
AVO
Input Capacitance
Input Resistance
OUTPUT CHARACTERISTICS
Output Voltage
High
Low
Output Current
Short-Circuit Current
Sourcing
Sinking
Closed-Loop Output Impedance
CINDM
CINCM
RDIFF
RCM
VOH
VOL
IOUT
ISC
ZOUT
15 V < VCM < 47 V
−47 V < VCM < −15 V
VCM = −13.5 V to +13.5 V
−40°C < TA < +125°C
RL = 2 kΩ, VOUT = −14.2 V to +14.2 V
−40°C < TA < +125°C
RL = 10 kΩ, VOUT = −14.5 V to +14.5 V
−40°C < TA < +125°C
Differential mode
Common mode
Differential mode
Common mode
ILOAD = 1 mA
−40°C < TA < +125°C
ILOAD = 7 mA
−40°C < TA < +125°C
ILOAD = 1 mA
−40°C < TA < +125°C
ILOAD = 7 mA
−40°C < TA < +125°C
VDROPOUT < 1 V
TA = 25°C
f = 1 kHz, AV = 1
Rev. E | Page 6 of 33
−1
−2
−0.75
−1.5
−13.5
128
125
110
103
118
110
−0.3
+0.1
12
10
130
114
120
14.95
14.90
14.80
14.75
−14.95
−14.90
−14.80
−14.75
Data Sheet
Parameter
POWER SUPPLY
Power Supply Rejection Ratio
Supply Current per Amplifier
DYNAMIC PERFORMANCE
Slew Rate
Settling Time
To 0.1%
To 0.01%
Gain Bandwidth Product
Unity-Gain Crossover
−3 dB Closed-Loop Bandwidth
Total Harmonic Distortion Plus Noise
EMI Rejection of +INx
f = 1000 MHz
f = 2400 MHz
NOISE PERFORMANCE
Voltage Noise
Voltage Noise Density
Current Noise Density
MULTIPLE AMPLIFIERS CHANNEL SEPARATION
1
ADA4177-1/ADA4177-2/ADA4177-4
Symbol
Test Conditions/Comments
Min
Typ
PSRR
VS = ±2.5 V to ±18 V
−40°C < TA < +125°C
VOUT = 0 V
−40°C < TA < +125°C
125
120
145
ISY
SR
tS
GBP
UGC
f−3 dB
THD + N
EMIRR
en p-p
en
in
CS
500
Max
Unit
580
620
dB
dB
µA
µA
RL = 2 kΩ
1.5
V/µs
VIN = 10 V p-p, RL = 2 kΩ, AV = −1
VIN = 10 V p-p, RL = 2 kΩ, AV = −1
VIN = 10 mV p-p, RL = 2 kΩ, AV = 100
VIN = 10 mV p-p, RL = 2 kΩ, AV = 1
VIN = 10 mV p-p, RL = 2 kΩ, AV = 1
VIN = 1 V rms, AV = +1, RL = 2 kΩ, f = 1 kHz
VIN = 200 mV p-p
5.5
7.5
3.5
3.5
6
0.002
µs
µs
MHz
MHz
MHz
%
70
90
dB
dB
175
10
8
0.2
127
nV p-p
nV/√Hz
nV/√Hz
pA/√Hz
dB
0.1 Hz to 10 Hz
f = 10 Hz
f = 1 kHz
f = 1 kHz
f = 1 kHz
All inputs are stressed to 32 V beyond supplies for 500 ms. See Figure 74 for the typical input bias current vs. the input voltage over the overvoltage protected input range.
Rev. E | Page 7 of 33
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage
Output Short-Circuit Duration to GND
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature, Soldering (10 sec)1
Electrostatic Discharge (ESD)
Human Body Model (HBM)2
Field Induced Charged Device
Model (FICDM)3
Machine Model (MM)
Rating
36 V
VSY ± 32 V
±VSY
See the Maximum Power
Dissipation section
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
4 kV
1250 V
200 V
2
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The ADA4177-1/ADA4177-2/ADA4177-4 can drive a shortcircuit output current of up to 65 mA. However, the usable
output load current drive is limited by the maximum power
dissipation allowed by the device package. The absolute
maximum junction temperature is 150°C (see Table 4). The
junction temperature can be estimated as follows:
PD = (VSY × ISY) + (VSY − VOUT) × ILOAD
where:
VSY is the power supply rail.
ISY is the quiescent current.
VOUT is the output of the amplifier.
ILOAD is the output load.
Do not exceed the 150°C maximum junction temperature for
the device. Exceeding the junction temperature limit can cause
degradation in the parametric performance or even destroy the
device. Refer to Technical Article MS-2251, Data Sheet Intricacies—
Absolute Maximum Ratings and Thermal Resistances, for more
information.
THERMAL RESISTANCE
IPC/JEDEC J-STS-020D applicable standard.
ESDA/JEDEC JS-001-2011 applicable standard.
3
JESD22-C101 (ESD FICDM standard of JEDEC) applicable standard.
1
MAXIMUM POWER DISSIPATION
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated by the
output stage transistor. It is calculated as follows:
Thermal resistance between junction and ambient (θJA) is
specified for the worst case conditions, that is, a device soldered
in a circuit board for surface-mount packages.
Table 5. Thermal Resistance
Package Type
8-Lead MSOP
8-Lead SOIC
14-Lead TSSOP
14-Lead SOIC
ESD CAUTION
TJ = PD × θJA + TA
where:
TJ is the die junction temperature.
PD is the power dissipated in the package.
θJA is the thermal resistance of the package.
TA is the ambient temperature.
Rev. E | Page 8 of 33
θJA
190
158
240
115
θJC
44
43
43
36
Unit
°C/W
°C/W
°C/W
°C/W
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
NIC
NIC 1
8
NIC
ADA4177-1
7
V+
–IN 2
ADA4177-1
7
V+
+IN 3
TOP VIEW
(Not to Scale)
6
OUT
+IN 3
TOP VIEW
(Not to Scale)
6
OUT
5
NIC
V– 4
5
NIC
V– 4
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
12282-205
8
–IN 2
NIC 1
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
Figure 4. ADA4177-1 8-Lead SOIC Pin Configuration
Figure 3. ADA4177-1 8-Lead MSOP Pin Configuration
Table 6. ADA4177-1 Pin Function Descriptions
Pin No.
1, 5, 8
2
3
4
6
7
Mnemonic
NIC
−IN
+IN
V−
OUT
V+
12282-105
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Description
Not Internally Connected.
Inverting Input Channel.
Noninverting Input Channel.
Negative Supply Voltage.
Output Channel.
Positive Supply Voltage.
Rev. E | Page 9 of 33
OUT A 1
Data Sheet
8
V+
–IN A 2
ADA4177-2
7
OUT B
–IN A 2
ADA4177-2
+IN A 3
TOP VIEW
(Not to Scale)
6
–IN B
+IN A 3
5
+IN B
TOP VIEW
(Not to Scale)
12282-004
V– 4
OUT A 1
V– 4
Figure 5. ADA4177-2 8-Lead MSOP Pin Configuration
Mnemonic
OUT A
−IN A
+IN A
V−
+IN B
−IN B
OUT B
V+
V+
7
OUT B
6
–IN B
5
+IN B
Figure 6. ADA4177-2 8-Lead SOIC Pin Configuration
Table 7. ADA4177-2 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
8
12282-005
ADA4177-1/ADA4177-2/ADA4177-4
Description
Output Channel A.
Inverting Input Channel A.
Noninverting Input Channel A.
Negative Supply Voltage.
Noninverting Input Channel B.
Inverting Input Channel B.
Output Channel B.
Positive Supply Voltage.
Rev. E | Page 10 of 33
ADA4177-1/ADA4177-2/ADA4177-4
OUT A
1
14 OUT D
–IN A
2
13 –IN D
3
ADA4177-4
V+
4
TOP VIEW
(Not to Scale)
+IN B
5
10 +IN C
–IN B
6
9
–IN C
OUT B
7
8
OUT C
12 +IN D
11 V–
–IN D
ADA4177-4
12
+IN D
TOP VIEW
(Not to Scale)
11
V–
10
+IN C
–IN B 6
9
–IN C
OUT B 7
8
OUT C
+IN B 5
Figure 8. ADA4177-4 14-Lead SOIC Pin Configuration
Table 8. ADA4177-4 Pin Function Descriptions
Mnemonic
OUT A
−IN A
+IN A
V+
+IN B
−IN B
OUT B
OUT C
−IN C
+IN C
V−
+IN D
−IN D
OUT D
OUT D
13
V+ 4
Figure 7. ADA4177-4 14-Lead TSSOP Pin Configuration
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
14
–IN A 2
+IN A 3
12282-206
+IN A
OUT A 1
12282-207
Data Sheet
Description
Output Channel A.
Inverting Input Channel A.
Noninverting Input Channel A.
Positive Supply Voltage.
Noninverting Input Channel B.
Inverting Input Channel B.
Output Channel B.
Output Channel C.
Inverting Input Channel C.
Noninverting Input Channel C.
Negative Supply Voltage.
Noninverting Input Channel D.
Inverting Input Channel D.
Output Channel D.
Rev. E | Page 11 of 33
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
Ambient temperature (TA) = 25°C unless otherwise noted.
80
80
NUMBER OF AMPLIFIERS
60
50
40
30
20
70
60
50
40
30
0
VOS (µV)
VOS (µV)
Figure 12. Input Offset Voltage (VOS) Distribution, VSY = ±15 V,
8-Lead SOIC
60
60
VSY = ±5V
8-LEAD MSOP
VSY = ±15V
8-LEAD MSOP
50
30
20
40
30
20
0
0
VOS (µV)
12282-400
10
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
10
VOS (µV)
Figure 10. Input Offset Voltage (VOS) Distribution, VSY = ±5 V, 8-Lead MSOP
12282-401
40
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
NUMBER OF AMPLIFIERS
50
Figure 13. Input Offset Voltage (VOS) Distribution, VSY = ±15 V,
8-Lead MSOP
300
300
VSY = ±5V
14-LEAD SOIC
VSY = ±15V
14-LEAD SOIC
250
200
150
100
200
150
100
0
0
VOS (µV)
12282-503
50
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
50
VOS (µV)
Figure 11. Input Offset Voltage (VOS) Distribution, VSY = ±5 V,
14-Lead SOIC
Figure 14. Input Offset Voltage (VOS) Distribution, VSY = ±15 V,
14-Lead SOIC
Rev. E | Page 12 of 33
12282-504
NUMBER OF AMPLIFIERS
250
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
NUMBER OF AMPLIFIERS
12282-403
0
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
10
12282-402
10
Figure 9. Input Offset Voltage (VOS) Distribution, VSY = ±5 V, 8-Lead SOIC
NUMBER OF AMPLIFIERS
VSY = ±15V
8-LEAD SOIC
20
–50
–45
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
15
20
25
30
35
40
45
50
NUMBER OF AMPLIFIERS
70
90
VSY = ±5V
8-LEAD SOIC
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
90
80
60
50
40
30
50
40
30
10
0
0
12282-501
10
VOS (µV)
160
VSY = ±5V
8-LEAD SOIC, 14-LEAD SOIC
120
80
40
40
VOS (µV)
80
0
0
–40
–40
–80
–80
–120
–120
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
–160
–40
12282-508
–160
–40
300
200
100
100
VOS (µV)
200
0
–200
–200
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
12282-512
–100
–10
5
20
35
50
65
80
95
110
125
Figure 17. Input Offset Voltage (VOS) vs. Temperature, VSY = ±5 V,
8-Lead MSOP and 14-Lead TSSOP
VSY = ±15V
8-LEAD MSOP, 14-LEAD TSSOP
0
–100
–25
–10
Figure 19. Input Offset Voltage (VOS) vs. Temperature, VSY = ±15 V,
8-Lead SOIC and 14-Lead SOIC
VSY = ±5V
8-LEAD MSOP, 14-LEAD TSSOP
–300
–40
–25
TEMPERATURE (°C)
Figure 16. Input Offset Voltage (VOS) vs. Temperature, VSY = ±5 V,
8-Lead SOIC and 14-Lead SOIC
300
VSY = ±15V
8-LEAD SOIC, 14-LEAD SOIC
12282-511
120
Figure 18. Input Offset Voltage (VOS) Distribution, VSY = ±15 V,
14-Lead TSSOP
–300
–40
–25
–10
5
20
35
50
65
80
95
110
125
TEMPERATURE (°C)
Figure 20. Input Offset Voltage (VOS) vs. Temperature, VSY = ±15 V,
8-Lead MSOP and 14-Lead TSSOP
Rev. E | Page 13 of 33
12282-515
160
VOS (µV)
60
20
Figure 15. Input Offset Voltage (VOS) Distribution, VSY = ±5 V,
14-Lead TSSOP
VOS (µV)
70
20
VOS (µV)
VSY = ±15V
14-LEAD TSSOP
12282-502
NUMBER OF AMPLIFIERS
70
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
NUMBER OF AMPLIFIERS
80
VSY = ±5V
14-LEAD TSSOP
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
90
100
90
ADA4177-1/ADA4177-2/ADA4177-4
80
VSY = ±5V
8-LEAD SOIC, 14-LEAD SOIC
70
70
60
60
NUMBER OF AMPLIFIERS
50
40
30
20
50
40
30
20
10
0.70
0.45
0.20
–0.05
0.95
TCVOS (µV/°C)
0
–0.55
12282-513
–0.30
Figure 21. Temperature Coefficient of Offset Voltage (TCVOS), VSY = ±5 V,
8-Lead SOIC and 14-Lead SOIC
35
0.45
0.70
0.95
VSY = ±15V
8-LEAD MSOP, 14-LEAD TSSOP
30
NUMBER OF AMPLIFIERS
25
20
15
10
25
20
15
10
5
5
–0.30
–0.05
0.70
0.45
0.20
0.95
TCVOS (µV/°C)
Figure 22. Temperature Coefficient of Offset Voltage (TCVOS), VSY = ±5 V,
8-Lead MSOP and 14-Lead TSSOP
100
0
–0.55
12282-514
0
–0.55
100
80
60
60
AVERAGE + 3σ
VOS (µV)
AVERAGE
0
–20
AVERAGE – 3σ
–20
VCM (V)
1
2
3
4
5
–100
–15
12282-407
0
AVERAGE – 3σ
–40
–80
–1
AVERAGE + 3σ
AVERAGE
–60
–2
0.95
0
–80
–3
0.70
20
–60
–4
0.45
VSY = ±15V
40
20
0.20
Figure 25. Temperature Coefficient of Offset Voltage (TCVOS), VSY = ±15 V,
8-Lead MSOP and 14-Lead TSSOP
VSY = ±5V
–40
–0.05
TCVOS (µV/°C)
80
40
–0.30
12282-517
NUMBER OF AMPLIFIERS
0.20
Figure 24. Temperature Coefficient of Offset Voltage (TCVOS), VSY = ±15 V,
8-Lead SOIC and 14-Lead SOIC
VSY = ±5V
8-LEAD MSOP, 14-LEAD TSSOP
30
VOS (µV)
–0.05
TCVOS (µV/°C)
35
–100
–5
–0.30
12282-516
10
0
–0.55
40
VSY = ±15V
8-LEAD SOIC, 14-LEAD SOIC
Figure 23. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VSY = ±5 V
–10
–5
0
VCM (V)
5
10
15
12282-408
NUMBER OF AMPLIFIERS
80
Data Sheet
Figure 26. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM),
VS = ±15 V
Rev. E | Page 14 of 33
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
5.00
15.00
VOL AT ILOAD = 1mA
VOH AT ILOAD = 1mA
4.96
4.94
VOL AT ILOAD = 7mA
4.92
VOL AT ILOAD = 1mA
14.98
OUTPUT VOLTAGE SWING (V)
4.90
4.88
4.86
VOH AT ILOAD = 7mA
4.84
VOH AT ILOAD = 1mA
14.96
14.94
VOL AT ILOAD = 7mA
14.92
14.90
14.88
14.86
VOH AT ILOAD = 7mA
14.84
14.82
4.82
VSY = ±15V
14.80
–50
–25
4.80
–50
–25
0
25
75
50
100
125
TEMPERATURE (°C)
12282-409
VSY = ±5V
0
25
50
75
100
12282-410
OUTPUT VOLTAGE SWING (V)
4.98
125
TEMPERATURE (°C)
Figure 27. Output Voltage Swing vs. Temperature, VSY = ±5 V
Figure 30. Output Voltage Swing vs. Temperature, VSY = ±15 V
300
450
VSY = ±15V
VSY = ±5V
400
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
250
200
150
100
350
300
250
200
150
100
50
12282-412
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
INPUT BIAS CURRENT (nA)
Figure 28. Input Bias Current Distribution, VSY = ±5 V
Figure 31. Input Bias Current Distribution, VSY = ±15 V
0.2
0.2
VSY = ±5V
VCM = 0V
VSY = ±15V
VCM = 0V
0
IB –
I B+
–0.1
–0.2
–0.3
IB–
0
–0.1
–0.2
–0.3
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 29. Input Bias Current (IB) vs. Temperature, VSY = ±5 V
–0.5
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 32. Input Bias Current (IB) vs. Temperature, VSY = ±15 V
Rev. E | Page 15 of 33
12282-414
–0.4
12282-413
–0.4
–0.5
–50
I B+
0.1
INPUT BIAS CURRENT (nA)
0.1
INPUT BIAS CURRENT (nA)
–0.8
12282-411
INPUT BIAS CURRENT (nA)
–1.0
0
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
0
–1.0
50
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
0.6
10
0.2
–40°C
+25°C
+85°C
+125°C
0
0
5
10
15
20
25
30
34
40
VSY (V)
0
OUTPUT DROPOUT VOLTAGE (mV)
10
1
0.001
–40°C
+25°C
+85°C
+125°C
0.01
0.1
1
10
100
SINK CURRENT (mA)
OUTPUT DROPOUT VOLTAGE (mV)
10
–40°C
+25°C
+85°C
+125°C
1
10
100
SOURCE CURRENT (mA)
12282-423
OUTPUT DROPOUT VOLTAGE (mV)
100
0.1
30
35
1k
100
10
10k
1k
0.01
25
–40°C
+25°C
+85°C
+125°C
0.01
0.1
1
10
100
Figure 37. Output Dropout Voltage vs. Sink Current, VSY = ±15 V
VSY = ±5V
1
0.001
20
SINK CURRENT (mA)
Figure 34. Output Dropout Voltage vs. Sink Current, VSY = ±5 V
10k
15
VSY = ±15V
1
0.001
12282-421
OUTPUT DROPOUT VOLTAGE (mV)
10k
100
10
Figure 36. Offset Voltage (VOS) vs. Power Supply Voltage (VSY)
VSY = ±5V
1k
5
VSY (V)
Figure 33. Supply Current per Amplifier (ISY) vs. Power Supply Voltage (VSY)
10k
–5
–10
12282-406
0.1
0
12282-422
0.3
5
Figure 35. Output Dropout Voltage vs. Source Current, VSY = ±5 V
VSY = ±15V
1k
100
10
1
0.001
–40°C
+25°C
+85°C
+125°C
0.01
0.1
1
10
100
SOURCE CURRENT (mA)
Figure 38. Output Dropout Voltage vs. Source Current, VSY = ±15 V
Rev. E | Page 16 of 33
12282-424
ISY (mA)
0.4
12282-419
OFFSET VOLTAGE (µV)
0.5
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
100
80
80
60
60
40
40
20
20
0
0
PHASE WITH CL = 0pF
PHASE WITH CL = 100pF
PHASE WITH CL = 200pF
–40
GAIN WITH CL = 0pF
GAIN WITH CL = 100pF
GAIN WITH CL = 200pF
–60
–80
1k
10k
1M
40
20
FREQUENCY (Hz)
–80
1k
–60
10k
100k
–40
1M
G = +10
20
G = +1
–20
G = +100
G = +10
20
G = +1
0
–20
100k
10k
1M
–40
1k
12282-427
–40
1k
10M
FREQUENCY (Hz)
10k
100k
1M
Figure 43. Closed-Loop Gain vs. Frequency, VSY = ±15 V
146
146
VSY = ±5V
VSY = ±15V
144
142
142
140
140
CMRR (dB)
144
138
136
138
136
134
134
132
132
–25
0
25
50
TEMPERATURE (°C)
75
100
125
130
–50
12282-429
130
–50
10M
FREQUENCY (Hz)
Figure 40. Closed-Loop Gain vs. Frequency, VSY = ±5 V
CMRR (dB)
–80
100M
10M
VSY = ±15V
40
CLOSED-LOOP GAIN (dB)
CLOSED-LOOP GAIN (dB)
GAIN WITH CL = 0pF
GAIN WITH CL = 100pF
GAIN WITH CL = 200pF
60
G = +100
0
–20
Figure 42. Open-Loop Gain and Phase vs. Frequency, VSY = ±15 V
VSY = ±5V
40
PHASE WITH CL = 0pF
PHASE WITH CL = 100pF
PHASE WITH CL = 200pF
FREQUENCY (Hz)
Figure 39. Open-Loop Gain and Phase vs. Frequency, VSY = ±5 V
60
0
0
–20
–60
–80
100M
10M
40
20
–40
–60
100k
60
12282-428
–40
–20
60
Figure 41. Common-Mode Rejection Ratio (CMRR) vs. Temperature, VSY = ±5 V
–25
0
25
50
TEMPERATURE (°C)
75
100
125
12282-430
–20
120
VSY = ±15V
AV = –10
100
RL = 2kΩ
TA = 25°C
80
PHASE (Degrees)
100
12282-425
OPEN-LOOP GAIN (dB)
80
120
12282-426
100
120
OPEN-LOOP GAIN (dB)
VSY = ±5V
AV = –10
RL = 2kΩ
TA = 25°C
PHASE (Degrees)
120
Figure 44. Common-Mode Rejection Ratio (CMRR) vs. Temperature, VSY = ±15 V
Rev. E | Page 17 of 33
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
1000
1000
VSY = ±15V
VSY = ±5V
100
100
AV = +100
AV = +10
AV = +1
0.1
0.1
0.01
0.01
0.001
0.0001
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
0.001
0.0001
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
Figure 45. Output Impedance (ZOUT) vs. Frequency, VSY = ±5 V
Figure 48. Output Impedance (ZOUT) vs. Frequency, VSY = ±15 V
3
12.5
VSY = ±5V
VIN = 4V p-p
AV = +1
RL = 2kΩ
CL = 300pF
2
VSY = ±15V
VIN = 20V p-p
AV = +1
RL = 2kΩ
CL = 300pF
10.0
7.5
5.0
VOUT (2.5V/DIV)
1
VOUT (1V/DIV)
AV = +1
1
12282-432
ZOUT (Ω)
AV = +10
1
AV = +100
10
12282-431
ZOUT (Ω)
10
0
–1
2.5
0
–2.5
–5.0
–7.5
–2
–3
TIME (100µs/DIV)
–12.5
TIME (100µs/DIV)
Figure 46. Large Signal Transient Response, VSY = ±5 V
Figure 49. Large Signal Transient Response, VSY = ±15 V
0.10
0.10
VSY = ±5V
VIN = 100mV p-p
AV = +1
RL = 2kΩ
CL = 1000pF
VSY = ±15V
VIN = 100mV p-p
AV = +1
RL = 2kΩ
CL = 1000pF
0.05
VOUT (V)
0.05
0
–0.05
0
–0.10
TIME (100µs/DIV)
12282-435
–0.05
Figure 47. Small Signal Transient Response, VSY = ±5 V
–0.10
TIME (100µs/DIV)
Figure 50. Small Signal Transient Response, VSY = ±15 V
Rev. E | Page 18 of 33
12282-436
VOUT (V)
12282-434
12282-433
–10.0
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
0.6
4
3
2
0.05
INPUT
1
0
10
0.2
8
INPUT
0
6
–0.2
4
–0.4
2
–0.6
OUTPUT
–0.05
12
0.4
OUTPUT
0
0
12282-437
–0.8
–1
–0.10
TIME (10µs/DIV)
–1.0
–2
TIME (10µs/DIV)
Figure 51. Positive Overload Recovery, VSY = ±5 V
0.8
2
VSY = ±15V
VIN = 225mV
AV = –100
RL = 10kΩ
CL = 35pF
0.7
0
OUTPUT
0.6
–1
0.10
–2
0.05
–3
INPUT
0
–4
–0.05
–5
INPUT VOLTAGE (V)
0.15
0
OUTPUT
–2
0.5
–4
0.4
–6
0.3
–8
0.2
–10
–12
0.1
0
10
5
15
20
INPUT
–14
0
–6
25
12282-439
–0.10
–5
TIME (5µs/DIV)
–0.1
–5
0
5
10
15
20
–16
25
TIME (5µs/DIV)
Figure 52. Negative Overload Recovery, VSY = ±5 V
Figure 55. Negative Overload Recovery, VSY = ±15 V
145
140
VSY = ±5V TO ±15V
VSY = ±5V
VSY = ±15V
120
140
CMRR (dB)
100
135
80
60
40
130
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (°C)
0
0.1
1
10
100
1k
10k
FREQUENCY (kHz)
Figure 56. Common-Mode Rejection Ratio (CMRR) vs. Frequency,
VSY = ±5 V and VSY = ±15 V
Figure 53. Power Supply Rejection Ratio (PSRR) vs. Temperature,
VSY = ±5 V to ±15 V
Rev. E | Page 19 of 33
12282-455
20
12282-420
PSRR (dB)
INPUT VOLTAGE (V)
0.20
1
VSY = ±5V
VIN = 75mV
AV = –100
RL = 10kΩ
CL = 35pF
OUTPUT VOLTAGE (V)
0.25
Figure 54. Positive Overload Recovery, VSY = ±15 V
OUTPUT VOLTAGE (V)
0.10
14
OUTPUT VOLTAGE (V)
0.8
12282-440
0.15
VSY = ±15V
VIN = 225mV
AV = –100
RL = 10kΩ
CL = 35pF
5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
0.20
16
1.0
OUTPUT VOLTAGE (V)
VSY = ±5V
VIN = 75mV
AV = –100
RL = 10kΩ
CL = 35pF
12282-438
6
0.25
ADA4177-1/ADA4177-2/ADA4177-4
120
Data Sheet
120
VSY = ±5V
100
VSY = ±15V
100
PSRR–
PSRR–
80
PSRR (dB)
PSRR+
40
60
PSRR+
40
20
20
0
0
1
10
100
1k
10k
FREQUENCY (kHz)
–20
0.1
12282-456
–20
0.1
100
50
40
VSY = ±15V
AV = +1
RL = 2kΩ
VIN = 100mV p-p
OS–
OVERSHOOT (%)
OS+
20
30
OS+
20
10
10
0.1
1
10
LOAD CAPACITANCE (nF)
0
0.01
12282-458
0
0.01
Figure 58. Small Signal Overshoot vs. Load Capacitance, VSY = ±5 V
1.0
–1.0
5
0.015
0.003
0
0.010
0.002
–5
0.001
OUTPUT
–1.5
0
–2.0
–0.001
–2.5
0.4
0.8
1.2
1.6
2.0
2.4
2.8
TIME (µs)
INPUT (V)
VSY = ±5V
VIN = 1V p-p
RL = 2kΩ
0
0.020
0.004
OUTPUT (V)
INPUT (V)
10
0.005
OUTPUT
–10
0
–15
–0.005
–20
–0.002
–25
–0.003
3.2
–30
12282-548
0
–0.4
10
INPUT
INPUT
–0.5
1
Figure 61. Small Signal Overshoot vs. Load Capacitance, VSY = ±15 V
0.005
0.5
0.1
LOAD CAPACITANCE (nF)
12282-459
OVERSHOOT (%)
OS–
–3.0
–0.8
10k
Figure 60. Power Supply Rejection Ratio (PSRR) vs. Frequency, VSY = ±15 V
VSY = ±5V
AV = +1
RL = 2kΩ
VIN = 100mV p-p
30
1k
Figure 59. Positive Settling Time to 0.1%, VSY = ±5 V
–0.010
VSY = ±15V
VIN = 10V p-p
RL = 2kΩ
–0.015
–0.020
–2
–1
0
1
2
3
4
5
6
7
TIME (µs)
Figure 62. Positive Settling Time to 0.1%, VSY = ±15 V
Rev. E | Page 20 of 33
OUTPUT (V)
40
10
FREQUENCY (kHz)
Figure 57. Power Supply Rejection Ratio (PSRR) vs. Frequency, VSY = ±5 V
50
1
12282-457
60
8
12282-551
PSRR (dB)
80
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
0.020
INPUT
5
0.015
0
0.003
0
0.010
–0.5
0.002
–5
0.001
OUTPUT
0
–10
0
–15
–0.005
–0.010
–0.001
–20
–2.5
–0.002
–25
–0.003
3.2
–30
–0.4
0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
TIME (µs)
12282-552
–2.0
VSY = ±15V
VIN = 10V p-p
RL = 2kΩ
–0.020
–2
–1
2
3
4
5
6
7
8
20
VSY = ±5V
VSY = ±15V
VSY = ±15V
VSY = ±5V
VOLTAGE NOISE CORNER (nV/√Hz)
AV = +1
100
10
1
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 64. Voltage Noise Density vs. Frequency, VSY = ±5 V and VSY = ±15 V
12
8
4
0
0.5
1.0
1.5
2.0
2.5
3.0
FREQUENCY (Hz)
Figure 67. Voltage Noise Corner vs. Frequency, VSY = ±5 V and VSY = ±15 V
1
VSY = ±5V
RL = 2kΩ
VIN = 1V rms
80kHz
>500kHz
VSY = ±15V
RL = 2kΩ
VIN = 1V rms
80kHz
>500kHz
0.1
THD + N (%)
0.1
0.01
0.001
0.01
0.001
0.0001
0.1
1
10
FREQUENCY (kHz)
100
12282-470
0.0001
0.00001
0.01
16
0
12282-468
VOLTAGE NOISE DENSITY (nV/√Hz)
1
Figure 66. Negative Settling Time 0.1%, VSY = ±15 V
1k
THD + N (%)
0
TIME (µs)
Figure 63. Negative Settling Time to 0.1%, VSY = ±5 V
1
–0.015
12282-483
–3.0
–0.8
0.005
OUTPUT
0.00001
0.01
Figure 65. THD + N vs. Frequency, VSY = ±5 V
0.1
1
10
FREQUENCY (kHz)
Figure 68. THD + N vs. Frequency, VSY = ±15 V
Rev. E | Page 21 of 33
100
12282-471
–1.5
INPUT (V)
–1.0
OUTPUT (V)
0.004
0.5
INPUT (V)
10
0.005
OUTPUT (V)
VSY = ±5V
VIN = 1V p-p
RL = 2kΩ
INPUT
12282-555
1.0
ADA4177-1/ADA4177-2/ADA4177-4
1
Data Sheet
1
VSY = ±5V
RL = 2kΩ
fIN = 1kHz
0.1
THD + N (%)
0.1
0.01
0.01
0.01
0.1
1
10
AMPLITUDE (V rms)
12282-472
0.0001
0.001
0.0001
0.001
0.1
1
10
AMPLITUDE (V rms)
Figure 69. THD + N vs. Amplitude, VSY = ±5 V
Figure 72. THD + N vs. Amplitude, VSY = ±15 V
VSY = ±5V
TIME (1s/DIV)
Figure 70. 0.1 Hz to 10 Hz Noise, VSY = ±5 V
Figure 73. 0.1 Hz to 10 Hz Noise, VSY = ±15 V
15.0
12.5
12282-465
12282-464
INPUT VOLTAGE (50nV/DIV)
INPUT VOLTAGE (50nV/DIV)
VSY = ±15V
TIME (1s/DIV)
12.5
VSY = ±5V
VSY = ±15V
10.0
10.0
INPUT BIAS CURRENT (mA)
7.5
7.5
5.0
2.5
0
–2.5
–5.0
–7.5
5.0
2.5
0
–2.5
–5.0
–7.5
–10.0
–10.0
–12.5
–12.5
–15.0
–40 –35 –30 –25 –20 –15 –10 –5
0
5
10 15 20 25 30 35 40
VIN (V)
12282-466
INPUT BIAS CURRENT (mA)
0.01
12282-473
0.001
0.001
Figure 71. Input Bias Current vs. Input Voltage (VIN) Including
Input Overvoltage Range (Beyond VSY = ±5 V )
–15.0
–50
–40
–30
–20
–10
0
10
20
30
40
50
VIN (V)
Figure 74. Input Bias Current vs. Input Voltage (VIN) Including
Input Overvoltage Range (Beyond VSY = ±15 V)
Rev. E | Page 22 of 33
12282-467
THD + N (%)
VSY = ±15V
RL = 2kΩ
fIN = 1kHz
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
3000
1000
600
+125°C
+85°C
+25°C
–40°C
2000
INPUT BIAS CURRENT (pA)
800
INPUT BIAS CURRENT (pA)
VSY = ±15V
VSY = ±5V
+125°C
+85°C
+25°C
–40°C
400
200
0
–200
–400
–600
1000
0
–1000
–1000
–5
–4
–3
–2
–1
0
1
2
3
4
–2000
–15
12282-480
–1000
5
COMMON-MODE VOLTAGE (V)
–90
5
10
15
VSY = ±15V
VIN = 10V p-p
AV = +1000
RL = 2kΩ
CHANNEL SEPARATION (dB)
–100
1
–110
–120
–130
0.01
0.1
1
10
100
FREQUENCY (kHz)
–150
0.01
0.1
1
10
100
FREQUENCY (kHz)
Figure 76. Current Noise Density vs. Frequency, VSY = ±5 V and VSY = ±15 V
12282-474
–140
12282-475
Figure 79. Channel Separation vs. Frequency, VSY = ±15 V
45
60
VSY = ±5V
VSY = ±15V
55
SOURCING CURRENT (mA)
40
35
30
25
45
40
35
–25
0
25
50
TEMPERATURE (°C)
75
100
125
30
–50
12282-600
20
–50
50
Figure 77. Output Short-Circuit Sourcing Current vs. Temperature, VSY = ±5 V
–25
0
25
50
TEMPERATURE (°C)
75
100
125
12282-601
CURRENT NOISE DENSITY (pA/√Hz)
0
Figure 78. Input Bias Current vs. Common-Mode Voltage (VCM) and
Temperature, VSY = ±15 V
VSY = ±15V
VSY = ±5V
0.1
0.001
SOURCING CURRENT (mA)
–5
COMMON-MODE VOLTAGE (V)
Figure 75. Input Bias Current vs. Common-Mode Voltage (VCM) and
Temperature, VSY = ±5 V
10
–10
12282-481
–800
Figure 80. Output Short-Circuit Sourcing Current vs. Temperature, VSY = ±15 V
Rev. E | Page 23 of 33
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
–20
–30
VSY = ±15V
VSY = ±5V
–40
SINKING CURRENT (mA)
–30
–35
–40
–60
–70
–45
–25
0
25
50
75
100
125
TEMPERATURE (°C)
–80
–50
12282-602
–50
–50
Figure 81. Output Short-Circuit Sinking Current vs. Temperature, VSY = ±5 V
1
0
–1
50
100
150
200
250
300
TIME (Seconds)
350
12282-604
–2
0
0
25
50
75
100
125
Figure 83. Output Short-Circuit Sinking Current vs. Temperature, VSY = ±15 V
2
–3
–25
TEMPERATURE (°C)
3
CHANGE IN VOS (µV)
–50
12282-603
SINKING CURRENT (mA)
–25
Figure 82. Offset Voltage Short-Term Drift
Rev. E | Page 24 of 33
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
Rev. E | Page 25 of 33
OVP
OVP
gm
12282-449
N BIAS
The ADA4177-1/ADA4177-2/ADA4177-4 are precision,
bipolar op amps that integrate both input overvoltage protection
(OVP) and input EMI filtering while maintaining a low 2 nA
maximum bias current and a rail-to-rail output operation.
Figure 84 shows a conceptual schematic of the main amplifier
that uses super beta, bipolar input transistors and bias current
cancellation to minimize the input bias current. The inputs are
cascoded to protect the super beta input devices from damage
during overvoltage conditions. The cascoded inputs feed into an
active load that makes up the primary gain stage. A buffered
transconductance (gm) stage converts a differential voltage to a
differential current to drive the output stage. The rail-to-rail
output can swing to 50 mV maximum (for example, the
guaranteed room temperature limit for VOH is 14.95 V when
the positive supply is 15 V) with a 1 mA load at 25°C.
P BIAS
THEORY OF OPERATION
Figure 84. Conceptual Schematic
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
APPLICATIONS INFORMATION
ACTIVE OVERVOLTAGE PROTECTION
Add External Clamping Diodes
The ADA4177-1/ADA4177-2/ADA4177-4 use active overvoltage
protection to protect the devices from damage when the inputs
are driven to a voltage up to 32 V above the positive supply
voltage or 32 V below the negative supply voltage. The
ADA4177-1/ADA4177-2/ADA4177-4 not only protect the
input from damage, but they also reduce the input noise.
Precision op amps have a low VOS and a high common-mode
rejection ratio (CMRR). Both of these characteristics simplify
system calibration and minimize dynamic error. To maintain
these specifications in the presence of ESD events, bipolar op
amps often have internal clamp diodes and small limiting
resistors in series with their inputs; however, these do not address
fault conditions where the inputs exceed the rails. In these cases,
the system designer commonly adds clamping diodes (D1 and
D2) along with a series resistor (ROVP), shown in Figure 86.
When an op amp does not have input overvoltage protection,
moving the input voltage above or below the supply voltage can
cause excessive input current, which can damage the op amp.
To avoid this, add a series resistor at the input. To protect the op
amp from a 30 V transient beyond either rail, limit the input
current to 5 mA, and add a 6 kΩ series resistor to the input.
However, a trade-off of adding the series resister is its added
thermal noise. The 6 kΩ series resistor exhibits 10 nV/√Hz of
thermal noise, which adds quadrature thermal noise from the
resistor with the op amp noise.
N TOTAL = N OP AMP 2 + N RESISTOR 2
where:
NTOTAL is the total noise.
NOP AMP is the op amp noise.
NRESISTOR is the thermal noise generated by the resistor.
When the additional thermal noise from the series resistor is added
to the thermal noise (8 nV/√Hz) of the ADA4177-1/ADA4177-2/
ADA4177-4, the 6 kΩ series resistor brings the total thermal
noise to 12 nV/√Hz, which is a 70% increase in thermal noise.
Figure 85 shows how noise from the additional source resistance
adds to the total noise at the amplifier input; the higher the source
resistance, the higher the total noise. Because the ADA4177-1/
ADA4177-2/ADA4177-4 have integrated input protection for
overvoltage conditions, the noise trade-off is avoided.
18
RF
VOUT
D1
V–
Figure 86. Common Scheme for Protecting Precision Amplifier Inputs from
Overvoltage Conditions
If the signal source at VIN is driven to one diode voltage beyond
the op amp supplies, the fault current is limited by ROVP. Schottky
diodes have a low forward knee voltage of 200 mV less than a
typical small signal diode. Therefore, all overvoltage currents
are shunted through the external diodes (D1 and D2). The reverse
leakage current for a typical Schottky diode is extremely variable
with the reverse voltage level. Therefore, as the noninverting
input of the op amp swings, the D1 and D2 leakage currents do
not match, and the differences pass through ROVP, creating a
voltage drop. The voltage drop on ROVP appears as a variation in
VOS, which can drastically reduce the CMRR performance.
Because the ADA4177-1/ADA4177-2/ADA4177-4 have integrated
input protection during overvoltage conditions, the degradation
in performance is avoided.
Input Protection Circuit
The ADA4177-1/ADA4177-2/ADA4177-4 inputs provide
overvoltage protection without the trade-offs encountered in
the common design methods. The conceptual schematic of the
input is shown in Figure 87.
TOTAL NOISE
16
14
RESISTOR NOISE
12
D2
ROVP
VIN
V+
10
J1B
J2B
J1A
J2A
8
ADA4177-1/ADA4177-2/ADA4177-4 NOISE
6
VIN2
2
0
0
5000
10000
15000
20000
25000
30000
TOTAL SOURCE RESISTANCE
Figure 85. Equivalent Thermal Noise vs. Total Source Resistance
Rev. E | Page 26 of 33
V–
Figure 87. Conceptual Schematic of the Inputs of the
ADA4177-1/ADA4177-2/ADA4177-4
12282-442
VIN1
4
12282-445
EQUIVALENT THERMAL NOISE (nV/√Hz)
20
V+
12282-441
Common Protection Methods
Add an External Series Input Resistor
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
J1A, J1B, J2A, and J2B are depletion mode junction field effect
transistors (JFETs) that replace the series resistance in the
conventional protection scheme. Under normal operation, the
input bias current of the ADA4177-1/ADA4177-2/ADA4177-4
flows through the J1A and J2A transistors without pinching off
the channel. To achieve excellent noise performance, J1A and
J2A must have a low on resistance (RDSON) of approximately 300 Ω.
When either input exceeds the rail by more than a diode, large
currents flow through either J1A or J2A, which causes the
channels to pinch off and effectively raises their resistance.
Figure 88 shows the positive overvoltage and negative
overvoltage characteristics as the FET channel pinches.
LIMITING OVERVOLTAGE CURRENT OUT OF THE
POSITIVE SUPPLY PIN
Because the positive power supply of the system can be incapable
of sinking the large overvoltage current of 8 mA (see Figure 88),
care was taken to divide down this current into the positive rail
during an overvoltage event. As shown in Figure 90, Q1L is a
lateral PNP transistor that serves two purposes. First, the emitter
base acts as a clamping diode to route the overvoltage current
away from the V+ pin and to the V− pin. Second, it divides
down this current via the beta of Q1L. At an emitter current of
8 mA, the beta of Q1L is approximately 8, which reduces the
current injected into the positive supply by a factor of 8.
12
V+
10
J1B
6
4
+IN
2
0
–4
–30
–10
10
30
50
VIN (V)
12282-500
–8
–10
–50
V–
Figure 91 shows the positive and negative supply currents when
the input voltage exceeds the supply voltages (and overvoltage
condition). The current at the V+ terminal does not reverse
direction during an overvoltage event because the current is
directed to V− via the collector of Q1L.
8
Figure 88. Input Bias Current During Positive and Negative Overvoltage,
VSY = ±15 V, Voltage Follower Configuration
300Ω AT 2V
8
6
4
SUPPLY CURRENT (mA)
Figure 89 shows how the JFET effective resistance increases
exponentially as shown by the measurements at 2 V, 20 V, and
40 V overvoltage. As the overvoltage increases from 2 V to 40 V,
the resistance increases from 300 Ω to 3.5 kΩ (a factor of 11).
10
J1A
Figure 90. Overvoltage Protection Circuitry
–2
–6
POSITIVE SUPPLY CURRENT
2
0
–2
–4
–6
–8
2.2kΩ
AT 20V
NEGATIVE SUPPLY CURRENT
3.5kΩ AT 40V
–10
–12
–40
–20
–10
0
10
20
30
40
Figure 91. Supply Current vs. Input Differential, Circuit Configured at
Unity Gain with V+ = +15 V and V− = −15 V
2
0
–2
2.5
–30
INPUT DIFFERENTIAL (V)
4
12282-452
6
7.5
12.5
17.5
22.5
27.5
32.5
37.5
42.5
VIN (V)
12282-454
OVERVOLTAGE (mV)
Q1L
VSY = ±15V
12282-443
INPUT BIAS CURRENT (mA)
8
If negative overvoltage transients are expected, ensure that the
negative voltage source driving V− can handle sourcing current
without forcing current into the device and causing the supply
voltage to change.
Figure 89. Overvoltage vs. Input Voltage (VIN), Voltage Follower
Configuration
Rev. E | Page 27 of 33
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
100 mV
EMIRR = 20 × log
ΔVOS
where:
100 mV is generally the peak-to-peak input used for the test.
ΔVOS is the change in the op amp offset as a result of the input
signal.
Figure 92 shows the input EMI protection of the ADA4177-1/
ADA4177-2/ADA4177-4.
100
80
60
40
WITH TWO INPUTS IN OVERVOLTAGE
20
0
0
5
10
15
20
25
30
35
40
CONTINUOUS OVERVOLTAGE (V)
Figure 93. Maximum Operating Temperature vs. Continuous Overvoltage for
One Input and Two Inputs (θJA = 150°C/W)
USING THE ADA4177-1/ADA4177-2/ADA4177-4
AS A COMPARATOR
The ADA4177-1/ADA4177-2/ADA4177-4 can be used as a
comparator as long as relatively small input impedance can be
tolerated. That is, the input differential pair is diode clamped
but the overvoltage protection circuitry limits the differential.
Figure 94 shows the input current vs. the input differential voltage
with ±15 V supplies.
80
60
40
20
8
6
100
1000
FREQUENCY (MHz)
4
Figure 92. EMI Rejection Ratio Peak Voltage vs. Frequency
SELF HEATING
During an overvoltage condition, the ADA4177-1/ADA4177-2/
ADA4177-4 dissipate heat according to the thermal resistance
(θJA) of the package it is in, which, in turn, heats up the die. Ensure
that the specified operating junction temperature does not exceed
150°C for device protection. Extended overtemperature exposure
can cause some operating specifications to shift outside of their
guaranteed limits.
INPUT CURRENT (mA)
0
10
WITH ONE INPUT IN OVERVOLTAGE
120
As shown in Figure 88, the ADA4177-1/ADA4177-2/ADA4177-4
inputs sink by approximately 8 mA at 15 V overvoltage. In that
condition, the ADA4177-1/ADA4177-2/ADA4177-4 dissipate
120 mW of power. If the package has a θJA of 100°C/W, the
junction temperature rises by approximately 12°C over the
ambient temperature of the package and junction. In such a case,
derate the ambient operating temperature by 12°C (125°C
minus 12°C) for an absolute maximum operating temperature
of 113°C.
Rev. E | Page 28 of 33
2
0
–2
–4
–6
–8
–20
–15
–10
–5
0
5
10
15
20
INPUT DIFFERENTIAL (V)
Figure 94. Input Current vs. Input Differential with ±15 V Supplies
12282-451
100
INPUT +IN
VSY = ±15V
RF POWER = –16dBm (50mV p-p)
12282-453
EMI REJECTION RATIO PEAK VOLTAGE (dB)
120
140
12282-447
The ADA4177-1/ADA4177-2/ADA4177-4 inputs are also
protected from high frequency EMI. In an op amp with no EMI
protection, signals not within the bandwidth of the op amp
couple into sensitive amplifier inputs and become rectified as
they travel through the amplifier, eventually appearing as ac
feedthrough on top of a dc offset. When an input filter is not
provided, these offsets can be quite large. These offsets are
referred to as the electromagnetic interference rejection ratio
(EMIRR). The amplifier EMIRR is defined as
When the junction temperature exceeds the absolute maximum
junction temperature of 150°C, add an additional series resistance
to the inputs to further decrease the overvoltage current. Figure 93
shows the maximum operating temperature vs. the continuous
overvoltage at θJA = 150°C/W.
MAXIMUM OPERATING TEMPERATURE (°C)
EMI PROTECTION
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
Figure 95 shows the input and output of a comparator circuit
referenced to ground using the ADA4177-1/ADA4177-2/
ADA4177-4. The supply voltages are ±5 V. The −INx input is
grounded and a positive input is stepped to ±1 V. Both the
positive and negative recovery is approximately 4 µs.
PROPER PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADA4177-1/ADA4177-2/ADA4177-4 are high precision
devices. To ensure optimum performance at the PCB level, take
care in the design of the board layout.
To avoid leakage currents, maintain a clean and moisture free
board surface. Coating the surface creates a barrier to moisture
accumulation and reduces parasitic resistance on the board.
Keeping supply traces short and properly bypassing the power
supplies minimizes the power supply disturbances caused by
the output current variation, such as when driving an ac signal
into a heavy load. Connect bypass capacitors as closely as possible
to the device supply pins. Stray capacitances are a concern at the
outputs and the inputs of the amplifier. Keep the signal traces at
least 5 mm from supply lines to minimize coupling.
VOUT
12282-448
VIN
Figure 95. ADA4177-1/ADA4177-2/ADA4177-4 Used as a Comparator with
±5 V Supplies and a ±1 V Input Step, Voltage Follower Configuration
OUTPUT PHASE REVERSAL
Phase reversal is defined as a change in polarity in the amplifier
transfer function. Many op amps exhibit phase reversal when
the voltage applied to the input is greater than the maximum
common-mode voltage. In some instances, this phase reversal
can cause permanent damage to the amplifier. In feedback
loops, it can result in system lockups or equipment damage.
The ADA4177-1/ADA4177-2/ADA4177-4 are immune to phase
reversal problems even at input voltages beyond the power
supply settings.
A variation in temperature across the PCB can cause a mismatch
in the Seebeck voltages at solder joints and other points where
dissimilar metals are in contact, resulting in thermal voltage errors.
To minimize these thermocouple effects, orient resistors so that
heat sources warm both ends equally. Ensure, where possible,
that input signal paths contain matching numbers and types of
components, to match the number and type of thermocouple
junctions. For example, dummy components such as zero value
resistors can be used to match real resistors in the opposite
input path. Place matching components in close proximity to
each other, and orient them in the same manner. Ensure that
leads are of equal length so that thermal conduction is in
equilibrium. Keep heat sources on the PCB as far away from
amplifier input circuitry as is practical.
The use of a ground plane is highly recommended. A ground
plane reduces EMI noise and maintains a constant temperature
across the circuit board.
12282-482
LONG-TERM DRIFT
Figure 96. Output Showing No Phase Reversal in Overvoltage Condition
The stability of a precision signal path over its lifetime or
between calibration procedures is dependent on the long-term
stability of the analog components in the path, such as op amps,
references, and data converters. To help system designers
predict the long-term drift of circuits that use the ADA4177-1/
ADA4177-2/ADA4177-4, Analog Devices measured the offset
voltage of multiple units for 10,000 hours (more than 13 months)
using a high precision measurement system, including an
ultrastable oil bath. To replicate real-world system performance,
the devices under test (DUTs) were soldered onto an FR4 PCB
using a standard reflow profile (as defined in the JEDEC J-STD020D standard), as opposed to testing them in sockets. This
manner of testing is important because expansion and
contraction of the PCB can apply stress to the integrated circuit
(IC) package and contribute to shifts in the offset voltage.
Rev. E | Page 29 of 33
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
The ADA4177-1/ADA4177-2/ADA4177-4 have extremely low
long-term drift, as shown in Figure 97. The red, blue, and green
traces show sample units. Note that the ADA4177-1/ADA4177-2/
ADA4177-4 have a mean drift over 10,000 hours of less than
2 µV, or 2% of their maximum specified offset voltage of 60 µV
at room temperature.
In the three full cycles, the offset hysteresis is typically only 2 µV, or
less than 2% of its 120 µV maximum offset voltage over the full
operating temperature range. The histogram in Figure 99 shows
that the hysteresis is larger when the device is cycled through
only a half cycle, from room temperature to hot 125°C and back
to room temperature.
80
8
MEAN
MEAN PLUS ONE STANDARD DEVIATION
MEAN MINUS ONE STANDARD DEVIATION
4
2
0
–2
–4
VSY = 10V
27 UNITS
TA = 25°C
0
–20
–40
–80
–40
10,000
12282-197
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
20
–60
–8
TIME (Hours)
40
0
20
40
60
TEMPERATURE (°C)
80
100
120
Figure 98. Change in Offset Voltage over Three Full Temperature Cycles
Figure 97. Measured Long-Term Drift of the ADA4177-1/ADA4177-2/
ADA4177-4 Offset Voltage over 10,000 Hours
NUMBER OF DEVICES
TEMPERATURE HYSTERESIS
In addition to stability over time as described in the Long-Term
Drift section, it is useful to know the temperature hysteresis,
that is, the stability vs. cycling of temperature. Hysteresis is an
important parameter because it tells the system designer how
closely the signal returns to its starting amplitude after the
ambient temperature changes and subsequent return to room
temperature. Figure 98 shows the change in input offset voltage
as the temperature cycles three times from room temperature to
+125°C to −40°C and back to room temperature. The dotted
line is an initial preconditioning cycle to eliminate the original
temperature induced offset shift from exposure to production
solder reflow temperatures.
–20
12282-198
–6
60
50
45 VSY = 10V
27 UNITS × 3 CYCLES
40 HALF CYCLE = +26°C, +125°C, +26°C
35 FULL CYCLE = +26°C, +125°C, +26°C, –40°C, +26°C
30
25
20
15
10
5
0
50
45
40
35
30
25
20
15
10
5
0
–18 –15 –12 –9 –6 –3
0
3
6
HALF CYCLE
FULL CYCLE
9
OFFSET VOLTAGE HYSTERESIS (µV)
12
15
18
12282-199
SAMPLE 1
SAMPLE 2
SAMPLE 3
PRECONDITION
CYCLE 1
CYCLE 2
CYCLE 3
VSY = 10V
CHANGE IN OFFSET VOLTAGE (µV)
CHANGE IN OFFSET VOLTAGE (µV)
6
Figure 99. Histogram Showing the Temperature Hysteresis of the Offset
Voltage over Three Full Cycles and over Three Half Cycles
Rev. E | Page 30 of 33
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
OUTLINE DIMENSIONS
3.20
3.00
2.80
8
3.20
3.00
2.80
5.15
4.90
4.65
5
1
4
PIN 1
IDENTIFIER
0.65 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.80
0.55
0.40
0.23
0.09
6°
0°
0.40
0.25
10-07-2009-B
0.15
0.05
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 100. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
5.00 (0.1968)
4.80 (0.1890)
1
5
6.20 (0.2441)
5.80 (0.2284)
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
SEATING
PLANE
0.50 (0.0196)
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 101. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Rev. E | Page 31 of 33
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
ADA4177-1/ADA4177-2/ADA4177-4
Data Sheet
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.20
0.09
0.30
0.19
0.75
0.60
0.45
8°
0°
SEATING
PLANE
061908-A
1.05
1.00
0.80
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 102. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
8.75 (0.3445)
8.55 (0.3366)
8
14
1
7
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0039)
COPLANARITY
0.10
0.51 (0.0201)
0.31 (0.0122)
6.20 (0.2441)
5.80 (0.2283)
0.50 (0.0197)
0.25 (0.0098)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
45°
8°
0°
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012-AB
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 103. 14-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-14)
Dimensions shown in millimeters and (inches)
Rev. E | Page 32 of 33
060606-A
4.00 (0.1575)
3.80 (0.1496)
Data Sheet
ADA4177-1/ADA4177-2/ADA4177-4
ORDERING GUIDE
Model1
ADA4177-1ARMZ
ADA4177-1ARMZ-R7
ADA4177-1ARMZ-RL
ADA4177-1ARZ
ADA4177-1ARZ-R7
ADA4177-1ARZ-RL
ADA4177-2ARMZ
ADA4177-2ARMZ-R7
ADA4177-2ARMZ-RL
ADA4177-2ARZ
ADA4177-2ARZ-R7
ADA4177-2ARZ-RL
ADA4177-4ARUZ
ADA4177-4ARUZ-R7
ADA4177-4ARUZ-RL
ADA4177-4ARZ
ADA4177-4ARZ-R7
ADA4177-4ARZ-RL
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Mini Small Outline Package [MSOP]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
8-Lead Standard Small Outline Package [SOIC_N]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
14-Lead Standard Small Outline Package [SOIC_N]
Z = RoHS Compliant Part.
©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12282-0-8/18(E)
Rev. E | Page 33 of 33
Package Option
RM-8
RM-8
RM-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
R-8
R-8
R-8
RU-14
RU-14
RU-14
R-14
R-14
R-14
Marking Code
A3E
A3E
A3E
A36
A36
A36
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