Integrated Triple Video Filter
for High Definition Video
ADA4417-3
FEATURES
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
Y/G IN
×1
×2
Y/G OUT
×2
Pb/B OUT
×2
Pr/R OUT
36MHz
Pb/B IN
×1
36MHz
Pr/R IN
×1
36MHz
DCO
DISABLE
ADA4417-3
06221-001
Optimized for high definition video
Sixth-order Butterworth filters
−1 dB bandwidth of 38 MHz
44 dB rejection at 75 MHz
5 ns group delay variation
Fixed throughput gain of ×2
0.06% differential gain
0.21° differential phase
Pin selectable output offset (DCO)
Single-supply operation
3.3 V to 5 V range
Rail-to-rail output
Output ESD protection exceeds 8 kV
Small packaging: 10-lead MSOP
Figure 1.
Set-top boxes
HDTVs
Projectors
DVD players/recorders
Personal video recorders
GENERAL DESCRIPTION
The ADA4417-3 is a low cost, fully integrated, video
reconstruction filter specifically designed for consumer high
definition video. With 1 dB frequency flatness out to 38 MHz,
and 44 dB of rejection at 75 MHz, the ADA4417-3 can handle
the most demanding HD video applications.
The ADA4417-3 operates on a single 3.3 V to 5 V supply. It is
well-suited for applications where power consumption is
critical. A disable feature allows for further power conservation
by reducing the supply current to 10 μA (typical) when the
device is not in use. With rail-to-rail output, it can be efficiently
used on a 3.3 V supply, while providing the user with a 2 V p-p
output. The buffers can drive two 75 Ω terminated loads, either
dc- or ac-coupled.
The ADA4417-3 also has an output dc offset function that can
operate in two states. When the DCO pin is tied to VCC, the
video signal at the output is offset by 200 mV. When the DCO
pin is tied to ground, the output dc level follows the input level.
The ADA4417-3 is available in a 10-lead MSOP package and is
rated for operation over the extended industrial temperature
range of −40°C to +85°C.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2009 Analog Devices, Inc. All rights reserved.
ADA4417-3
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 12
Applications ....................................................................................... 1
Applications..................................................................................... 13
Functional Block Diagram .............................................................. 1
Overview ..................................................................................... 13
General Description ......................................................................... 1
Disable ......................................................................................... 13
Revision History ............................................................................... 2
Output DC Offset Control ........................................................ 13
Specifications..................................................................................... 3
Input and Output Coupling ...................................................... 13
Absolute Maximum Ratings............................................................ 5
Printed Circuit Board Layout ................................................... 13
Thermal Resistance ...................................................................... 5
Video Encoder Reconstruction Filter ...................................... 14
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 15
Pin Configuration and Function Descriptions ............................. 6
Ordering Guide .......................................................................... 15
Typical Performance Characteristics ............................................. 7
Test Circuit ...................................................................................... 11
REVISION HISTORY
11/09—Rev. 0 to Rev. A
Changes to Input and Output Coupling ...................................... 13
Changes to Figure 28 ...................................................................... 14
Updated Outline Dimensions ....................................................... 15
7/06—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADA4417-3
SPECIFICATIONS
VS = 5 V (@ TA = 25°C, VIN = 1 V p-p, G = +2, RT = 0 Ω 1 , RL = 150 Ω, DCO = 1, unless otherwise noted).
Table 1.
Parameter
OVERALL PERFORMANCE
DC Offset
Input Voltage Range
Output Voltage Range
Linear Output Current
DC Voltage Gain
Integrated Voltage Noise
Filter Input Bias Current
Slew Rate
Settling Time to 0.5%
Output Overdrive Recovery
Total Harmonic Distortion
Gain Matching
FILTER DYNAMIC PERFORMANCE
−1 dB Bandwidth
−3 dB Bandwidth
Out-of-Band Rejection
Crosstalk
Propagation Delay
Group Delay Variation
Differential Gain
Differential Phase
DISABLE PERFORMANCE
DISABLE Assert Voltage
DISABLE Assert Time
DISABLE Deassert Voltage
DISABLE Deassert Time
DISABLE Input Bias Current
Input-to-Output Isolation—Disabled
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current—Disabled
PSRR
1
2
Test Conditions/Comments
Min
Typ
Max
Unit
DCO = 1, input referred
DCO = 0, input referred
70
100
142
40
mV
mV
4.73
V
mA
dB
mV rms
μA
V/μs
ns
ns
%
dB
See Note 2 2
0.08
Per channel
30
5.88
f = 100 kHz to 30 MHz, input referred
f = 1 MHz, VIN = 0.7 V p-p
f = 75 MHz
f = 5 MHz, input referred, RT = 275 Ω1
f = 5 MHz
f = 1 MHz to 36 MHz
Modulated 10 step ramp, sync tip at 0 V
Modulated 10 step ramp, sync tip at 0 V
6.07
0.4
3.2
150
65
125
0.01
0.01
27
31
38
0.09
38
42
44
−68
26
5
0.06
0.21
MHz
MHz
dB
dB
ns
ns
%
Degrees
0.8
f = 5 MHz, DISABLE = 0
2.0
32
92
V
ns
V
μs
μA
dB
DCO = 0
DCO = 1
DCO = 0, DISABLE = 0
DCO = 0
3.3 to 5.0
19.5
24.0
10
71
V
mA
mA
μA
dB
100
2.0
See Figure 25.
Limited by output range.
Rev. A | Page 3 of 16
55
22.5
29.5
ADA4417-3
VS = 3.3 V (@ TA = 25°C, VIN = 1.0 V p-p, G = +2, RT = 0 Ω 1 , RL = 150 Ω, DCO = 1, unless otherwise noted).
Table 2.
Parameter
OVERALL PERFORMANCE
DC Offset
Input Voltage Range
Output Voltage Range
Linear Output Current
DC Voltage Gain
Integrated Voltage Noise
Filter Input Bias Current
Slew Rate
Settling Time to 0.5%
Output Overdrive Recovery
Total Harmonic Distortion
Gain Matching
FILTER DYNAMIC PERFORMANCE
−1 dB Bandwidth
−3 dB Bandwidth
Out-of-Band Rejection
Crosstalk
Propagation Delay
Group Delay Variation
Differential Gain
Differential Phase
DISABLE PERFORMANCE
DISABLE Assert Voltage
DISABLE Assert Time
DISABLE Deassert Voltage
DISABLE Deassert Time
DISABLE Input Bias Current
Input-to-Output Isolation—Disabled
POWER SUPPLY
Operating Range
Quiescent Current
Quiescent Current—Disabled
PSRR
1
2
Test Conditions/Comments
Min
Typ
Max
Unit
DCO = 1, input referred
DCO = 0, input referred
66
100
145
42
mV
mV
3.05
V
mA
dB
mV rms
μA
V/μs
ns
ns
%
dB
See Note 2 2
0.08
Per channel
20
5.75
f = 100 kHz to 30 MHz, input referred
f = 1 MHz, VIN = 0.7 V p-p
f = 75 MHz
f = 5 MHz, input referred, RT = 275 Ω1
f = 5 MHz
f = 1 MHz to 36 MHz
Modulated 10 step ramp, sync tip at 0 V
Modulated 10 step ramp, sync tip at 0 V
6.16
0.4
3.2
130
70
125
0.08
0.02
27
31
40
0.18
38
42
44
−61
26.5
4
0.07
0.14
MHz
MHz
dB
dB
ns
ns
%
Degrees
0.8
110
2.0
f = 5 MHz, DISABLE = 0
3.0
19
92
DCO = 0
DCO = 1
DCO = 0, DISABLE = 0
DCO = 0
3.3 to 5.0
19.0
22.5
10
71
See Figure 25.
Limited by output range.
Rev. A | Page 4 of 16
52
21.5
29.0
V
ns
V
μs
μA
dB
V
mA
mA
μA
dB
ADA4417-3
ABSOLUTE MAXIMUM RATINGS
Table 3.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the supply voltage (VS) times the quiescent current (IS).
Assuming the load (RL) is midsupply, then the total drive power is
Rating
5.5 V
See Figure 2
−65°C to +125°C
−40°C to +85°C
300°C
150°C
VS/2 × IOUT
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 4.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, more metal directly in contact with the package leads
from metal traces, through holes, ground, and power planes
reduce the θJA.
Unit
°C/W
2.0
Maximum Power Dissipation
The maximum safe power dissipation in the ADA4417-3
package is limited by the associated rise in junction temperature
(TJ) on the die. At approximately 150°C, which is the glass
transition temperature, the plastic changes its properties. Even
temporarily exceeding this temperature limit can change the
stresses that the package exerts on the die, permanently shifting
the parametric performance of the ADA4417-3. Exceeding a
junction temperature of 175°C for an extended period can
result in changes in the silicon devices potentially causing
failure.
1.5
1.0
0.5
0
–40 –30 –20 –10
0
10
20
30
40
50
AMBIENT TEMPERATURE (°C)
60
70
80
06221-002
θJA
130
RMS output voltages should be considered. If RL is referenced to
GND, the total power is VS × IOUT.
Figure 2 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 10-lead MSOP
(130°C/W) on a JEDEC standard 4-layer board. θJA values are
approximate.
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Package Type
10-Lead MSOP
some of which is dissipated in the package and some in the load
(VOUT × IOUT).
MAXIMUM POWER DISSIPATION (W)
Parameter
Supply Voltage
Power Dissipation
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. A | Page 5 of 16
ADA4417-3
Y/G IN
1
DISABLE
2
Pb/B IN
3
DCO
4
Pr/R IN
5
ADA4417-3
TOP VIEW
(Not to Scale)
10
Y/G OUT
9
VCC
8
Pb/B OUT
7
GND
6
Pr/R OUT
06221-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Mnemonic
Y/G IN
DISABLE
Pb/B IN
DCO
Pr/R IN
Pr/R OUT
GND
Pb/B OUT
VCC
Y/G OUT
Description
Y/G HD Video Input
Disable/Power Down (Active Low)
Pb/B HD Video Input
Output DC Offset Enable
Pr/R HD Video Input
Pr/R HD Video Output
Ground
Pb/B HD Video Output
Power Supply
Y/G HD Video Output
Rev. A | Page 6 of 16
ADA4417-3
TYPICAL PERFORMANCE CHARACTERISTICS
7.0
BLACK LINE: VS = 3.3V
GRAY LINE: VS = 5V
6.5
6.0
5.5
GAIN (dB)
5.0
4.5
4.0
100
500
FREQUENCY (MHz)
3.0
1
7.0
BLACK LINE: RL = 75Ω
GRAY LINE: RL = 150Ω
6.5
6.0
GAIN (dB)
5.5
5.0
4.5
4.0
3.5
100
500
FREQUENCY (MHz)
3.0
1
100
Figure 8. Flatness Response vs. Load
7.0
–40°C (5V)
+25°C (5V)
+85°C (5V)
–40°C (5V)
+25°C (5V)
+85°C (5V)
6.5
6.0
GAIN (dB)
5.5
5.0
4.5
4.0
1
10
100
FREQUENCY (MHz)
500
Figure 6. Frequency Response vs. Temperature
3.0
1
10
FREQUENCY (MHz)
Figure 9. Flatness Response vs. Temperature
Rev. A | Page 7 of 16
100
06221-009
3.5
06221-006
GAIN (dB)
10
FREQUENCY (MHz)
Figure 5. Frequency Response vs. Load
9
6
3
0
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
–48
100
Figure 7. Flatness Response vs. Supply
06221-005
GAIN (dB)
Figure 4. Frequency Response vs. Supply
9
6
3
BLACK LINE: R = 75Ω
0 GRAY LINE: R L= 150Ω
L
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
–48
1
10
10
FREQUENCY (MHz)
06221-007
3.5
06221-008
9
6
3
BLACK LINE: V = 3.3V
0 GRAY LINE: V S= 5V
S
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
–48
1
10
06221-004
GAIN (dB)
Default Conditions: VS = 5 V, TA = 25°C, VO = 2 V p-p, G = +2, RT = 0 Ω (see Figure 25), RL = 150 Ω, DCO = 1, unless otherwise noted.
9
6
3
BLACK LINE: V = 0.2V p-p
0 GRAY LINE: V S= 2.0V p-p
S
–3
–6
–9
–12
–15
–18
–21
–24
–27
–30
–33
–36
–39
–42
–45
–48
1
10
36
BLACK LINE: VS = 3.3V
GRAY LINE: VS = 5V
GROUP DELAY (ns)
34
32
30
28
100
500
FREQUENCY (MHz)
24
1
10
100
FREQUENCY (MHz)
Figure 10. Frequency Response vs. Amplitude
06221-013
26
06221-010
GAIN (dB)
ADA4417-3
Figure 13. Group Delay vs. Frequency
10
10k
DISABLE = 0
REFERRED TO INPUT
0
–10
–30
–40
–50
–60
VS = 3.3V, DCO = H
VS = 3.3V, DCO = L
VS = 5V, DCO = H
VS = 5V, DCO = L
–80
0.01
0.1
1
10
100
500
FREQUENCY (MHz)
100
0.1
06221-011
–70
1k
VIN = 1V p-p
–30 DISABLE = 0
10
100
500
FREQUENCY (MHz)
Figure 11. PSRR vs. Frequency
–20
1
06221-014
IMPEDANCE (Ω)
PSRR (dB)
–20
Figure 14. Output Impedance (Disabled) vs. Frequency
–30
BLACK LINE: VS = 3.3V
GRAY LINE: VS = 5V
–40
REFERRED TO INPUT
RT = 275Ω
BLACK LINE: VS = 3.3V
GRAY LINE: VS = 5V
–50
CROSSTALK (dB)
–50
–60
–70
–80
–90
–60
–70
–80
–100
–120
1
10
100
FREQUENCY (MHz)
500
Figure 12. Off Isolation vs. Frequency
–100
0.1
1
10
FREQUENCY (MHz)
Figure 15. Crosstalk vs. Frequency
Rev. A | Page 8 of 16
100
500
06221-015
–90
–110
06221-012
OFF ISOLATION (dB)
–40
ADA4417-3
4.00
2 × INPUT
3.75
3.50
OUTPUT
OUTPUT AMPLITUDE (V)
3.25
1.0%, 61ns
2.50
2.25
2.00
1.75
1.50
1.25
50ns/DIV
1.00
Figure 16. Transient Response
Figure 19. Settling Time
5.5
5.5
5.0
5.0
4.5
4.0
3.5
VOLTAGE (V)
3.5
3.0
2.5
2.0
2.5
2.0
1.5
1.0
1.0
0.5
0.5
0
1µs/DIV
–0.5
OUTPUT
3.0
1.5
06221-017
VOLTAGE (V)
DISABLE INPUT
4.5
OUTPUT
0
1µs/DIV
–0.5
Figure 20. Enable Turn Off Time
Figure 17. Enable Turn On Time
6
300
2 × INPUT
VS = 5V
4
OUTPUT VOLTAGE WRT VS+ (mV)
5
OUTPUT (DCO = 1)
3
OUTPUT (DCO = 0)
2
0
100ns/DIV
–1
06221-018
1
275
250
225
200
175
150
–40
–25
–10
5
20
35
50
65
80
TEMPERATURE (°C)
Figure 18. Output Overdrive Recovery
Figure 21. Output Saturation Voltage vs. Temperature
Rev. A | Page 9 of 16
06221-021
4.0
DISABLE INPUT
06221-019
50ns/DIV
06221-020
BLACK LINE: VS = 3.3V
GRAY LINE: VS = 5V
06221-016
250mV/DIV
VOLTAGE (V)
ERROR
0.5%, 63ns
2.75
0.5%/DIV
VOLTAGE (V)
3.00
ADA4417-3
30
SUPPLY CURRENT (mA)
27
DCO = 1
24
21
DCO = 0
15
–40 –30 –20 –10
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
Figure 22. Supply Current vs. Temperature
3.0
DCO = 0
2.5
2.0
1.5
1.0
0.5
0.75
1.25
1.75
2.25
INPUT VOLTAGE (V)
2.75
06221-023
OUTPUT VOLTAGE (V)
DCO = 1
3.5
0.25
TA = +25°C
TA = –40°C
20
15
10
5
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Figure 24. Supply Current vs. DISABLE/DCO Voltage and Temperature
4.5
0
–0.25
TA = +85°C
DISABLE AND DCO VOLTAGE (V)
5.0
4.0
25
0
06221-022
18
VS = 5V,
DISABLE AND DCO
TIED TOGETHER,
RL = OPEN
06221-024
BLACK LINE: VS = 3.3V
GRAY LINE: VS = 5V
POWER SUPPLY CURRENT (mA)
30
Figure 23. Output Voltage vs. Input Voltage
Rev. A | Page 10 of 16
ADA4417-3
TEST CIRCUIT
50Ω
RL = 150Ω
RT
50Ω
DUT
NETWORK
ANALYZER Rx
118Ω
86.6Ω
50Ω
MINIMUM-LOSS MATCHING NETWORK LOSS CALIBRATED OUT
06221-025
NETWORK
ANALYZER Tx
Figure 25. Basic Test Circuit for Swept Frequency Measurements
Rev. A | Page 11 of 16
ADA4417-3
THEORY OF OPERATION
The ADA4417-3 is a low cost, integrated video filtering and
driving solution that offers a 38 MHz, 1 dB bandwidth to meet
the requirements of high definition video. Each of the three
filters has a sixth-order Butterworth response that includes
group delay equalization. Group delay variation from 1 MHz to
36 MHz is only 5 ns, resulting in greater stop-band attenuation
and minimal phase distortion.
The ADA4417-3 is designed to operate in many video
environments. With a supply range of 3.3 V to 5 V, it requires
a relatively low nominal quiescent current of 10 mA per
channel. This makes the ADA4417-3 well suited for portable
high definition video applications. Additionally, for other low
power applications, the part can be powered down to draw
typically 10 μA by pulling the DISABLE pin to ground. The
ADA4417-3 is also well suited for high encoding frequency
applications because it maintains a stop-band attenuation of over
40 dB out to 500 MHz. Typical power supply rejection ratio
(PSRR) is greater than 70 dB, providing excellent rejection in
systems with supplies that are noisy or underregulated.
The ADA4417-3 is intended to accept dc-coupled inputs
from an encoder or other ground-referenced video signals.
The ADA4417-3 inputs are high impedance. No minimum or
maximum input termination is required; however, terminations
above 1 kΩ may degrade crosstalk performance at high
frequencies.
Each filter input includes level-shifting circuitry. The levelshifting circuitry adds a dc component of 100 mV to groundreferenced input signals so that they reproduce accurately,
without the output buffers hitting the ground rail. For lowest
off state power consumption when using the dc offset function,
it is recommended that the DCO and DISABLE pins be tied
together.
The output drivers on the ADA4417-3 have rail-to-rail output
capabilities with 6 dB gain. Each output is capable of driving
two ac- or dc-coupled, 75 Ω source-terminated loads. If a large
dc output level is required while driving two loads, ac coupling
should be used to limit the power dissipation.
Rev. A | Page 12 of 16
ADA4417-3
APPLICATIONS
There are two ac coupling options when driving two loads from
one output. One simply uses the same value capacitor on the
second load, while the other is to use a common coupling
capacitor that is at least twice the value used for the single load
(see Figure 26 and Figure 27).
When driving two parallel 150 Ω loads (75 Ω effective load), the
3 dB bandwidth of the filters typically varies from that of the
filters with a single 150 Ω load. Typical variation is within ±2.5%.
75Ω
ADA4417-3
75Ω
CABLE
220µF
75Ω
CABLE
75Ω
75Ω
DISABLE
The ADA4417-3 includes a disable feature that can be used to
save power when a particular device is not in use. The disable
feature is asserted by pulling the DISABLE pin to ground.
220µF
75Ω
Figure 26. Driving Two AC-Coupled Loads with Two Coupling Capacitors
Table 6 summarizes the disable feature operation.
ADA4417-3
75Ω
75Ω
CABLE
470µF
Table 6. DISABLE Function
DISABLE Pin Connection
Status
VS
GND
Enabled
Disabled
06221-026
With its high impedance inputs and high output drive, the
ADA4417-3 is ideally suited to video reconstruction and
antialias filtering applications. The high impedance inputs give
designers flexibility with regard to how the input signals are
terminated. Devices with DAC current source outputs that feed
the ADA4417-3 can be loaded in whatever resistance provides
the best performance, and devices with voltage outputs can be
optimally terminated as well. The ADA4417-3 outputs can each
drive up to two source-terminated, 75 Ω loads and can
therefore directly drive the outputs from set-top boxes, DVDs,
and a like without the need for a separate output buffer.
75Ω
75Ω
75Ω
CABLE
75Ω
06221-027
OVERVIEW
OUTPUT DC OFFSET CONTROL
Figure 27. Driving Two AC-Coupled Loads with One Common Coupling Capacitor
The ADA4417-3 has a fixed, pin-selectable, input-referred dc
offset. When the DCO pin is tied to VS, the output is offset by
200 mV, preventing the video sync tips from hitting the ground
rail. When DCO is tied to GND, the dc level of the output
follows that of the input.
PRINTED CIRCUIT BOARD LAYOUT
Table 7 summarizes the dc offset operation.
Table 7. DC Offset Function
DCO Pin Connection
VS
GND
Status
Output offset = 200 mV
No output offset
INPUT AND OUTPUT COUPLING
Inputs to the ADA4417-3 may be ac- or dc-coupled. AC
coupling requires suitable circuitry following the ac coupling
element to provide proper dc level and bias currents at the input
stages. The ADA4417-3 outputs can be either ac- or dc-coupled.
When driving single, ac-coupled loads in standard 75 Ω video
distribution systems, 220 μF coupling capacitors are recommended
for use on all outputs.
As with all high speed applications, attention to printed circuit
board layout is of paramount importance. Standard high speed
layout practices should be adhered to when designing with the
ADA4417-3. A solid ground plane is recommended, and
surface-mount, ceramic power supply decoupling capacitors
should be placed as close as possible to the supply pins. All of
the ADA4417-3 GND pins should be connected to the ground
plane with traces that are as short as possible. Controlled
impedance traces of the shortest length possible should be used
to connect to the signal I/O pins and should not pass over any
voids in the ground plane. A 75 Ω impedance level is typically
used in video applications. All signal outputs of the ADA4417-3
should include series termination resistors when driving
transmission lines.
When the ADA4417-3 receives its inputs from a device with
current outputs, the required load resistor value for the output
current is often different from the characteristic impedance of
the signal traces. In this case, if the interconnections are sufficiently
short (
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