ADATE318

600 MHz Dual Integrated DCL with PPMU, VHH Drive Capability, Level Setting DACs, and On-Chip Calibration Engine ADATE318 FEATURES 600 MHz/1200 Mbps data rate 3-level driver with high-Z and reflection clamps Window and differential comparators ±25 mA active load Per pin PPMU with −2.0 V to +6.5 V range Low leakage mode (typically 4 nA) Integrated 16-bit DACs with offset and gain correction High speed operating voltage range: –1.5 V to +6.5 V Dedicated VHH output pin range: 0.0 V to 13.5 V 1.1 W power dissipation per channel Driver 3-level voltage range: –1.5 V to +6.5 V Precision trimmed output resistance Unterminated swing: 200 mV minimum to 8 V maximum 725 ps minimum pulse width, VIH − VIL = 2.0 V Comparator Differential and single-ended window modes >1.2 GHz input equivalent bandwidth Load ±25 mA current range Per pin PPMU (PPMU) Force voltage/compliance range: –2.0 V to +6.5 V 5 current ranges: 40 mA, 1 mA, 100 μA, 10 μA, 2 μA External sense input for system PMU Go/no-go comparators Levels Fully integrated 16-bit DACs On-chip gain and offset calibration registers and add/multiply engine Package 84-lead 10 mm × 10 mm LFCSP (0.4 mm pitch) GENERAL DESCRIPTION The ADATE318 is a complete, single-chip ATE solution that performs the pin electronics functions of driver, comparator, and active load (DCL), four quadrant, per pin, parametric measurement unit (PPMU). It has VHH drive capability per chip to support flash memory testing applications and integrated 16-bit DACs with an on-chip calibration engine to provide all necessary dc levels for operation of the part. The driver features three active states: data high, data low, and terminate mode, as well as a high impedance inhibit state. The inhibit state, in conjunction with the integrated dynamic clamps, facilitates the implementation of a high speed active termination. The output voltage capability is −1.5 V to +6.5 V to accommodate a wide range of ATE and instrumentation applications. The ADATE318 can be used as a dual, single-ended drive/ receive channel or as a single differential drive/receive channel. Each channel of the ADATE318 features a high speed window comparator as well as a programmable threshold differential comparator for differential ATE applications. A four quadrant PPMU is also provided per channel. All dc levels for DCL and PPMU functions are generated by 24 on-chip 16-bit DACs. To facilitate accurate levels programming, the ADATE318 contains an integrated calibration function to correct gain and offset errors for each functional block. Correction coefficients can be stored on chip, and any values written to the DACs are automatically adjusted using the appropriate correction factors. The ADATE318 uses a serial programmable interface (SPI) bus to program all functional blocks, DACs, and on-chip calibration constants. It also has an on-chip temperature sensor and over/undervoltage fault clamps for monitoring and reporting the device temperature and any output pin or PPMU voltage faults that may occur during operation. APPLICATIONS Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. ADATE318 TABLE OF CONTENTS Features .............................................................................................. 1  Applications....................................................................................... 1  General Description ......................................................................... 1  Revision History ............................................................................... 2  Functional Block Diagram .............................................................. 3  Specifications..................................................................................... 4  SPI Timing Details ..................................................................... 22  Absolute Maximum Ratings.......................................................... 27  Thermal Resistance .................................................................... 27  ESD Caution................................................................................ 27  Pin Configuration and Function Descriptions........................... 28  Typical Performance Characteristics ........................................... 31  SPI Interconnect Details ................................................................ 49  Use of the SPI BUSY Pin................................................................ 50  Reset Sequence and the RST Pin .................................................. 51  SPI Register Definitions and Memory Map................................ 52  Control Register Details................................................................. 55  Level Setting DACs......................................................................... 63  DAC Update Modes ................................................................... 63  DAC Transfer Functions ........................................................... 67  Gain and Offset Correction ...................................................... 68  X2 Registers.................................................................................. 68  Sample Calculations of m and c ............................................... 68  Power Supply, Grounding, and Decoupling Strategy ................ 70  User Information and Truth Tables ............................................. 71  Alarm Functions......................................................................... 72  PPMU External Capacitors....................................................... 72  Temperature Sensor ................................................................... 72  Default Test Conditions............................................................. 73  Detailed Functional Block Diagrams........................................... 74  Outline Dimensions ....................................................................... 80  Ordering Guide .......................................................................... 80  REVISION HISTORY 4/11—Revision 0: Initial Version Rev. 0 | Page 2 of 80 ADATE318 FUNCTIONAL BLOCK DIAGRAM ADATE318 VOH0 PPMU_CMPH0 PPMU_CMPL0 VOL0 PPMU_MEAS0 PPMU_S0 MUX THERM OUT PPMU MUX S F PPMU GO/NO-GO OVDH TO ALARM (PPMU HIGH/LOW CLAMP FAULT) TO ALARM (HIGH/LOW VOLTAGE FAULT) OVDL PPMU_VIN0 VCH0 VCL0 OVERVOLTAGE DAT0 100Ω DAT0 RCV0 100Ω RCV0 VIH0 VIT/VCOM0 VIL0 DRIVER VCH0 VCL0 PMU_S0 50Ω DUT0 IOL0 + VCOM0 ACTIVE LOAD – IOH0 VTTC0 50Ω CMPH0 NWC CMPH0 COMPARATOR CMPL0 CMPL0 CHANNEL 0 VHH VIH0 VIL0 HVOUT ALARM SDI SCLK CS SDO BUSY RST COMMON 09530-001 50Ω VOH0 DIFF CH0 ONLY NWC VOL0 THERM TEMP SENSOR ALARM DAT0 RCV 0 VHH DRIVER VPLUS VDD SPI GAIN/OFFSET CORRECTION MUX VCC 2 × 12 16-BIT DACs PGND DGND VSS CHANNEL 1 (SAME AS CHANNEL 0 EXCEPT WHERE NOTED) Figure 1. Rev. 0 | Page 3 of 80 ADATE318 SPECIFICATIONS VDD = +10.0 V, VCC = +2.5 V, VSS = −6.0 V, VPLUS = +16.75 V, VTTCx = +1.2 V, VREF = 5.000 V, VREFGND = 0.000 V. All test conditions are as defined in Table 32. All specified values are at TJ = 50°C, where TJ corresponds to the internal temperature sensor reading (THERM pin), unless otherwise noted. Temperature coefficients are measured around TJ = 50° ± 20°C, unless otherwise noted. Typical values are based on statistical mean of design, simulation analyses, and/or limited bench evaluation data. Typical values are neither tested nor guaranteed. See Table 16 for an explanation of test levels. Table 1. Detailed Electrical Specifications Parameter TOTAL FUNCTION Output Leakage Current, DCL Disable PPMU Range E PPMU Range A, Range B, Range C, and Range D Output Leakage Current, Driver High-Z Mode DUTx Pin Capacitance DUTx Pin Voltage Range POWER SUPPLIES Total Supply Range, VPLUS to VSS VPLUS Supply, VPLUS Positive Supply, VDD Negative Supply, VSS Logic Supply, VCC Comparator Output Termination, VTTCx VPLUS Supply Current, VPLUS 4.75 Logic Supply Current, VCC −125 15.90 9.5 −6.3 2.3 0.5 22.75 16.75 10.0 −6.0 2.5 1.2 1.1 13.28 1 7.5 Termination Supply Current, VTTCx Positive Supply Current, VDD Negative Supply Current, VSS Total Power Dissipation Positive Supply Current, VDD Negative Supply Current, VSS Total Power Dissipation Positive Supply Current, VDD Negative Supply Current, VSS Total Power Dissipation Positive Supply Current, VDD Negative Supply Current, VSS Total Power Dissipation 30 90 155 1.9 145 210 3.0 45 99 172 2.1 174 246 3.3 167 238 3.2 109 183 2.3 50 115 185 2.3 210 280 3.6 23.55 17.60 10.5 −5.7 3.5 3.3 2.5 16.25 +125 V V V V V V mA mA μA mA mA mA mA W mA mA W mA mA W mA mA W D D D D D D P P P S P P P P P P P CT CT CT CT CT CT Load power-down (IOH = IOL = 0 mA) Load power-down (IOH = IOL = 0 mA) Load power-down (IOH = IOL = 0 mA) Load active off (IOH = IOL = 25 mA) Load active off (IOH = IOL = 25 mA) Load active off (IOH = IOL = 25 mA) Load active off (IOH = IOL = 25 mA), calibrated Load active off (IOH = IOL = 25 mA), calibrated Load active off (IOH = IOL = 25 mA), calibrated Load power-down, PPMU standby Load power-down, PPMU standby Load power-down, PPMU standby VHH pin disabled VHH pin enabled, RCVx active, no load, VHH programmed level = 13.0 V Quiescent (SPI is static); VCC = 2.5 V Current drawn during clocked portion of device reset sequence Defines dc PSR conditions Defines dc PSR conditions Defines dc PSR conditions Defines dc PSR conditions −2.0 −2 1.2 +7.0 −10.0 ±4.0 ±4.0 +10.0 nA nA P CT −2.0 V < VDUTx < +6.5 V, PPMU and DCL disabled, PPMU Range E, VCL = −2.5 V, VCH = +7.5 V −2.0 V < VDUTx < +6.5 V, PPMU and DCL disabled, PPMU Range A, Range B, Range C, Range D, VCL = −2.5 V, VCH = +7.5 V −2.0 V < VDUTx < +7.0 V, PPMU disabled and DCL enabled, RCVx active, VCL = −2.5 V, VCH = +7.5 V Drive VIT = 0.0 V Min Typ Max Unit Test Level Conditions +2 μA pF V P S D Rev. 0 | Page 4 of 80 ADATE318 Parameter TEMPERATURE MONITOR Temperature Sensor Gain Temperature Sensor Accuracy over Temperature Range VREF INPUT REFERENCE DAC Reference Input Voltage Range (VREF Pin) Input Bias Current DUTGND INPUT Input Voltage Range, Referenced to AGND Input Bias Current −0.1 −100 +0.1 +100 V μA D P Tested at −100 mV and +100 mV 4.950 5.000 5.050 V D Provided externally: VREF pin = +5.000 V VREFGND pin = 0.000 V (not referenced to VDUTGND) Tested with 5.000 V applied 10 ±6 mV/K K D CT Min Typ Max Unit Test Level Conditions 100 μA P Table 2. Driver (VIH − VIL ≥ 100 mV to Meet DC and AC Performance Specifications) Parameter DC SPECIFICATIONS High-Speed Differential Input Characteristics High Speed Input Termination Resistance: DATx, RCVx Input Voltage Differential: DATx, RCVx Input Voltage Range: DATx, RCVx Output Characteristics Output High Range, VIH Output Low Range, VIL Output Term Range, VIT Functional Amplitude (VIH – VIL) DC Output Current Limit Source DC Output Current Limit Sink Output Resistance, ±40 mA DC ACCURACY −1.4 −1.5 −1.5 0.0 75 −130 46 48.6 8.0 130 −75 51 +6.5 +6.4 +6.5 V V V V mA mA Ω D D D D P P P Drive high, VIH = +6.5 V, short DUTx pin to −1.5 V, measure current Drive low, VIL = −1.5 V, short DUTx pin to +6.5 V, measure current ΔVDUT/ΔIDUT; source: VIH = 3.0 V, IDUT = +1 mA, +40 mA; sink: VIL = 0.0 V, IDUT = −1 mA, −40 mA VIH tests with VIL = −2.5 V, VIT = −2.5 V VIL tests with VIH = +7.5 V, VIT = +7.5 V VIT tests with VIL = −2.5 V, VIH = +7.5 V, unless otherwise specified −500 ±625 1.0 1.1 +500 mV μV/°C V/V P CT P Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V); based on ideal DAC transfer functions (see Table 21) Measured at DAC Code 0x4000 (0 V), uncalibrated 92 100 108 Ω P Impedance between each pair of DATx and RCVx pins; push 4 mA into positive pin, force 0.8 V on negative pin, measure voltage between pins; calculate resistance (ΔV/ΔI) 0.2 V < VDM < 1.0 V 0.0 V < (VCM ± VDM/2) < 3.3 V Min Typ Max Unit Test Level Conditions 0.2 0.0 0.4 1.0 3.3 V V D D VIH, VIL, VIT Offset Error VIH, VIL, VIT Offset Tempco VIH, VIL, VIT Gain VIH, VIL, VIT Gain Tempco VIH, VIL, VIT DNL ±40 ±1 ppm/°C mV CT CT After two point gain/offset calibration; calibration points at 0x4000 (0 V) output; 0xC000 (+5 V) output; measured over full specified output range After two point gain/offset calibration; applies to nominal VDD = +10.0 V supply case only VIH, VIL, VIT INL −7 +7 mV P Rev. 0 | Page 5 of 80 ADATE318 Parameter VIH, VIL, VIT Resolution DUTGND Voltage Accuracy DC Levels Interaction VIH vs. VIL VIH vs. VIT VIL vs. VIH VIL vs. VIT VIT vs. VIH VIT vs. VIL Overall Voltage Accuracy VIH, VIL, VIT DC PSRR AC SPECIFICATIONS Rise/Fall Times 0.2 V Programmed Swing, TRISE 0.2 V Programmed Swing, TFALL 0.5 V Programmed Swing, TRISE 0.5 V Programmed Swing, TFALL 1.0 V Programmed Swing, TRISE 1.0 V Programmed Swing, TFALL 2.0 V Programmed Swing, TRISE 2.0 V Programmed Swing, TFALL 3.0 V Programmed Swing, TRISE 3.0 V Programmed Swing, TFALL 5.0 V Programmed Swing, TRISE 5.0 V Programmed Swing, TFALL Rise to Fall Matching 150 150 215 277 218 274 222 283 297 322 447 397 1117 798 −25 −61 Minimum Pulse Width 0.5 V Programmed Swing 725 725 Maximum Toggle Rate 1.0 V Programmed Swing 2040 725 725 ps ps Mbps ps ps CB CB CB CB CB 320 320 ps ps ps ps ps ps ps ps ps ps ps ps ps ps CB CB CB CB P P CB CB CB CB CB CB CB CB ±0.2 ±1 ±0.2 ±1 ±1 ±1 ±8 ±10 mV mV mV mV mV mV mV mV/V CT CT CT CT CT CT CT CT −7 Min Typ 153 ±2 +7 Max Unit μV mV Test Level D P Over ±0.1 V range; measured at end points of VIH, VIL, and VIT functional range DC interaction on VIL, VIH, and VIT output level while other driver DAC levels are varied Monitor interaction on VIH = +6.5 V; sweep VIL = −1.5 V to +6.4 V, VIT = +1.0 V Monitor interaction on VIH = +6.5 V; sweep VIT = −1.5 V to +6.5 V, VIL = 0.0 V Monitor interaction on VIL = −1.5 V; sweep VIH = −1.4 V to +6.5 V, VIT = +1.0 V Monitor interaction on VIL = −1.5 V; sweep VIT = −1.5 V to +6.5 V, VIH = +2.0 V Monitor interaction on VIT = +1.0 V; sweep VIH = −1.4 V to +6.5 V, VIL = −1.5 V Monitor interaction on VIT = +1.0 V; sweep VIL = −1.5 V to +6.4 V, VIH = +6.5 V VIH − VIL ≥ 100 mV; sum of INL, dc interaction, DUTGND, and tempco errors over ±5ºC, after calibration Measured at calibration points All ac specifications performed after calibration Toggle DATx 20% to 80%, VIH = 0.2 V, VIL = 0.0 V, terminated 20% to 80%, VIH = 0.2 V, VIL = 0.0 V, terminated 20% to 80%, VIH = 0.5 V, VIL = 0.0 V, terminated 20% to 80%, VIH = 0.5 V, VIL = 0.0 V, terminated 20% to 80%, VIH = 1.0 V, VIL = 0.0 V, terminated 20% to 80%, VIH = 1.0 V, VIL = 0.0 V, terminated 20% to 80%, VIH = 2.0 V, VIL = 0.0 V, terminated 20% to 80%, VIH = 2.0 V, VIL = 0.0 V, terminated 20% to 80%, VIH = 3.0 V, VIL = 0.0 V, terminated 20% to 80%, VIH = 3.0 V, VIL = 0.0 V, terminated 10% to 90%, VIH = 5.0 V, VIL = 0.0 V, unterminated 10% to 90%, VIH = 5.0 V, VIL = 0.0 V, unterminated Rise to fall within one channel, VIH = 2.0 V, VIL = 0.0 V, terminated Rise to fall within one channel; VIH = 1.0 V, VIL = 0.0 V, terminated Toggle DATx VIH = 0.5 V, VIL = 0.0 V, terminated, timing error less than +69/−33 ps VIH = 0.5 V, VIL = 0.0 V, terminated, less than 10% amplitude loss VIH = 0.5 V, VIL = 0.0 V, terminated, less than 10% loss at 50% duty VIH = 1.0 V, VIL = 0.0 V, terminated, timing error less than +58/−35 ps VIH = 1.0 V, VIL = 0.0 V, terminated, less than 10% amplitude loss Conditions Rev. 0 | Page 6 of 80 ADATE318 Parameter Maximum Toggle Rate 2.0 V Programmed Swing Min Typ 2040 725 725 Maximum Toggle Rate 3.0 V Programmed Swing 1400 900 900 Maximum Toggle Rate Dynamic Performance, Drive (VIH to VIL) Propagation Delay Time Propagation Delay Tempco Delay Matching, Edge to Edge Delay Matching, Channel to Channel Delay Change vs. Duty Cycle Overshoot and Undershoot Settling Time (VIH to VIL) To Within 3% of Final Value To Within 1% of Final Value Dynamic Performance, VTerm (VIH or VIL to/from VIT) Propagation Delay Time Propagation Delay Tempco Transition Time, Active to VIT Transition Time, VIT to Active Dynamic Performance, Inhibit (VIH or VIL to/from Inhibit) Transition Time, Inhibit to Active Transition Time, Active to Inhibit Prop Delay, Inhibit to VIH Prop Delay, Inhibit to VIL Prop Delay Matching, Inhibit to VIL vs. Inhibit to VIH Prop Delay, VIH to Inhibit Prop Delay, VIL to Inhibit I/O Spike Driver Pre-Emphasis (CLC) Pre-Emphasis Amplitude Rising 35 14 Pre-Emphasis Amplitude Falling 24 16 % % % % CB CB CB CB VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 7 VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 0 VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 7 VIH = 2.0 V, VIL = 0.0 V, terminated, DRV_CLC_x[15:13] = 0 357 1.34 2.6 2.8 52 2.29 2.02 24 ps ns ns ns ps ns ns mV pkpk CB CB CB CB CB CB CB CB 1.39 2.3 310 329 ns ps/ºC ps ps CB CB CB CB 1.7 45 ns ns CB CB 1.26 1.4 43 32 −28 −116 ns ps/ºC ps ps ps mV CB CB CB CB CB CB 1100 Max Unit Mbps ps ps Mbps ps ps Mbps Test Level CB CB CB CB CB CB CB Conditions VIH = 1.0 V, VIL = 0.0 V, terminated, less than 10% loss at 50% duty VIH = 2.0 V, VIL = 0.0 V, terminated, timing error less than +80/−48 ps VIH = 2.0 V, VIL = 0.0 V, terminated, less than 10% amplitude loss VIH = 2.0 V, VIL = 0.0 V, terminated, less than 10% loss at 50% duty VIH = 3.0 V, VIL = 0.0 V, terminated, timing error less than +50/−83 ps VIH = 3.0 V, VIL = 0.0 V, terminated, less than 10% amplitude loss VIH = 3.0 V, VIL = 0.0 V, terminated, less than 10% amplitude loss at 50% duty cycle Toggle DATx VIH = 2.0 V, VIL = 0.0 V, terminated VIH = 2.0 V, VIL = 0.0 V, terminated VIH = 2.0 V, VIL = 0.0 V, terminated, rising vs. falling VIH = 2.0 V, VIL = 0.0 V, terminated, rising vs. rising, falling vs. falling VIH = 2.0 V, VIL = 0.0 V, terminated, 5% to 95% duty cycle VIH = 2.0 V, VIL = 0.0 V, terminated, driver CLC set to 0 Toggle DATx VIH = 2.0 V, VIL= 0.0 V, terminated VIH = 2.0 V, VIL= 0.0 V, terminated Toggle RCVx VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated 20% to 80%, VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated 20% to 80%, VIH = 2.0 V, VIT = 1.0 V, VIL = 0.0 V, terminated Toggle RCVx 20% to 80%, VIH = +1.0 V, VIL = −1.0 V, terminated 20% to 80%, VIH = +1.0 V, VIL = −1.0 V, terminated VIH = +1.0 V, VIL = −1.0 V, terminated; measured from RCVx input crossing to DUTx pin output 50% VIH = +1.0 V, VIL = −1.0 V, terminated VIH = +1.0 V, VIL = −1.0 V, terminated VIH = +1.0 V, VIL = −1.0 V, terminated, measured from RCVx input crossing to DUTx pin output 50% VIH = +1.0 V, VIL = −1.0 V, terminated VIH = 0.0 V, VIL = 0.0 V, terminated Rev. 0 | Page 7 of 80 ADATE318 Parameter Pre-Emphasis Resolution Pre-Emphasis Time Constant Min Typ 2 0.8 Max Unit % ns Test Level D CB VIH = 2.0 V, VIL = 0.0 V, terminated Conditions Table 3. Reflection Clamp (Clamp Accuracy Specifications Apply Only When VCH − VCL > 0.8 V) Parameter VCH/VCL PROGRAMMABLE RANGE VCH VCH Functional Range VCH Offset Error VCH Offset Tempco VCH Gain 1.0 −1.2 −300 ±0.5 1.1 +7.0 +300 V mV mV/ºC V/V D P CT P Driver high-Z, sinking 1 mA, gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V), based on ideal DAC transfer function (see Table 21). Driver high-Z, sinking 1 mA, measured at DAC Code 0x4000, uncalibrated. Min −2.5 Typ Max +7.5 Unit V Test Level D Conditions DC specifications apply over full functional range unless noted. VCH Gain Tempco VCH Resolution VCH DNL ±30 153 ±1 ppm/°C μV mV CT D CT Driver high-Z, sinking 1 mA, after two point gain/offset calibration; calibration points at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V), measured over functional clamp range. Driver high-Z, sinking 1 mA, after two point gain/offset calibration; calibration points at 0x4000 (0 V) and 0xC000 (5 V), measured over functional clamp range. VCH INL −20 +20 mV P VCL VCL Functional Range VCL Offset Error VCL Offset Tempco VCL Gain 1.0 −2 −300 ±0.5 1.1 +6.2 +300 V mV mV/°C V/V D P CT P Drive high-Z, sourcing 1 mA, gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V), based on ideal DAC transfer function (see Table 21). Driver high-Z, sourcing 1 mA, measured at DAC Code 0x4000, uncalibrated. VCL Gain Tempco VCL Resolution VCL DNL ±30 153 ±1 ppm/°C μV mV CT D CT Driver high-Z, sourcing 1 mA, after two point gain/offset calibration; calibration points at 0x4000 (0 V) and 0xC000 (+5 V), measured over functional clamp range. Driver high-Z, sourcing 1 mA, after two point gain/offset calibration; calibration points at 0x4000 (0 V) and 0xC000 (+5 V), measured over functional clamp range. Driver high-Z, VCH = 0 V, VCL = −2.0 V, VDUTx = +5.0 V. Driver high-Z, VCH = +6.0 V, VCL = +5.0 V, VDUTx = 0.0 V. Over ±0.1 V range, measured at end points of VCH and VCL functional range. VCL INL −20 +20 mV P DC Clamp Current Limit, VCH DC Clamp Current Limit, VCL DUTGND Voltage Accuracy −120 +75 −7 ±2 −75 +120 +7 mA mA mV P P P Rev. 0 | Page 8 of 80 ADATE318 Table 4. Normal Window Comparator (NWC) (Unless Otherwise Specified: VOH Tests at VOL = −1.5 V, VOL Tests at VOH = +6.5 V, Specifications Apply to Both Comparators) Parameter DC SPECIFICATIONS Input Voltage Range Differential Voltage Range Comparator Input Offset Voltage Input Offset Voltage Tempco Gain 1.0 −1.5 ±0.1 −250 ±100 1.1 +6.5 ±8.0 +250 V V mV μV/ºC V/V D D P CT P Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V); based on ideal DAC transfer function (see Table 21) Measured at DAC Code 0x4000 (0V), uncalibrated Min Typ Max Unit Test Level Conditions Gain Tempco Threshold Resolution Threshold DNL ±25 153 ±1 ppm/°C μV mV CT D CT Measured over −1.5 V to +6.5 V functional range after two point gain/offset calibration; calibration points at 0x4000 (0 V) and 0xC000 (5 V) Measured over −1.5 V to +6.5 V functional range after two point gain/offset calibration; calibration points at 0x4000 (0 V) and 0xC000 (5 V) Over ±0.1 V range; measured at end points of VOH and VOL functional range VDUTx = 0 V, sweep comparator threshold to determine the uncertainty band Threshold INL −7 +7 mV P DUTGND Voltage Accuracy Uncertainty Band Maximum Programmable Hysteresis Hysteresis Resolution DC PSRR Digital Output Characteristics Internal Pull-Up Resistance to Comparator, VTTC Comparator Termination Voltage, VTTC Common Mode Voltage −7 ±2 5 96 5 ±5 +7 mV mV mV mV mV/V P CB CB D CT Calculated over hystersis control Code 10 to Code 31 Measured at calibration points 46 50 54 Ω P Pull 1 mA and 10 mA from Logic 1 leg and measure ∆V to calculate resistance; measured ∆V/9 mA; done for both comparator logic states 0.5 1.2 VTTC − 0.3 3.3 V V D CT P CT P CB Measured with 100 Ω differential termination Measured with no external termination Measured with 100 Ω differential termination Measured with no external termination Measured with 50 Ω to external termination voltage (VTTC) All ac specifications performed after dc level calibration, input transition time of ~200 ps, 20% to 80%, measured with 50 Ω to external termination voltage (VTTC); peaking set to CLC = 2, unless otherwise specified VTTC − 0.5 Differential Voltage 450 Rise/Fall Times, 20% to 80% AC SPECIFICATIONS 250 500 166 VTTC V mV 550 mV ps Propagation Delay, Input to Output Propagation Delay Tempco Propagation Delay Matching High Transition to Low Transition Propagation Delay Matching High to Low Comparator 0.93 1.6 7 7 ns ps/ºC ps ps CB CB CB CB VDUTx: 0 V to 1.0 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.5 V VDUTx: 0 V to 1.0 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.5 V VDUTx: 0 V to 1.0 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.5 V VDUTx: 0 V to 1.0 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.5 V Rev. 0 | Page 9 of 80 ADATE318 Parameter Propagation Delay Dispersion Slew Rate 400 ps vs. 1 ns (20% to 80%) Overdrive 250 mV vs. 1.0 V 1 V Pulse Width 0.7 ns, 1 ns, 5 ns, 10 ns 0.5 V Pulse Width 0.6 ns, 1 ns, 5 ns, 10 ns Duty Cycle 5% to 95% Minimum Detectable Pulse Width 19 40 ps ps CB CB VDUTx: 0 V to 0.5 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.25 V For 250 mV, VDUTx: 0 V to 0.5 V swing; for 1.0 V, VDUTx: 0 V to 1.25 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.25 V VDUTx: 0 V to 1.0 V swing at~32.0 MHz; driver term mode, VIT = 0.0 V, comparator threshold = 0.5 V VDUTx: 0 V to 0.5 V swing at~32.0 MHz, driver term mode, VIT = 0.0 V; comparator threshold = 0.25 V VDUTx: 0 V to 1.0 V swing at~32.0 MHz; driver term mode, VIT =0.0 V, comparator threshold = 0.5 V VDUTx: 0 V to 1.0 V swing at 32.0 MHz, driver term mode, VIT = 0.0 V; greater than 50% output differential amplitude VDUTx: 0 V to 1.0 V swing; driver term mode, VIT = 0.0 V, CLC = 2; as measured by shmoo plot; fEQUIV = 0.22/√(tMEAS2 − tDUT2) VDUTx: 0 V to 3.0 V swing, driver high-Z as measured by shmoo plot; fEQUIV = 0.22/√(tMEAS2 – tDUT2) Min Typ Max Unit Test Level Conditions +2/− 17 +3/− 24 21 0.5 ps ps ps ns CB CB CB CB Input Equivalent Bandwidth, Terminated ERT High-Z Mode, 3 V, 20% to 80% Comparator Pre-Emphasis (CLC) CLC Amplitude Range 1520 MHz CB 721 ps CB 16 % CB VDUTx: 0 V to 1.0 V swing, driver term mode, VIT = 0.0 V, comparator pre-emphasis set to maximum 3-bit amplitude control VDUTx: 0 V to 1.0 V swing, driver term mode, VIT = 0.0 V, comparator pre-emphasis set to maximum CLC Resolution Pre-Emphasis Time Constant 2.3 4.3 % per bit ns CB CB Table 5. Differential Mode Comparator (DMC) (Unless Otherwise Specified: VOH Tests at VOL = −1.1 V, VOL Tests at VOH = +1.1 V) Parameter DC SPECIFICATIONS Input Voltage Range Functional Differential Range Maximum Differential Input Input Offset Voltage Offset Voltage Tempco Gain 1.0 −250 ±150 1.1 −1.5 ±0.05 +6.5 ±1.1 ±8 +250 V V V mV μV/ºC V/V D D D P CT P Gain derived from measurements at DAC Code 0x2666 (−1 V) and DAC Code 0x599A (+1 V), based on ideal DAC transfer function (see Table 21) Offset extrapolated from measurements at DAC Code 0x2666 (−1 V) and DAC Code 0x599A (+1 V), with VCM = 0 V Min Typ Max Unit Test Level Conditions Gain Tempco VOH, VOL Resolution VOH, VOL DNL VOH, VOL INL −7 ±25 153 ±1 +7 ppm/°C μV mV mV CT D CT P After two point gain/offset calibration, VCM = 0.0 V, calibration points at 0x2666 (−1 V) and 0x599A (+1 V) After two point gain/offset calibration, measured over VOH/VOL range of −1.1 V to +1.1 V, VCM = 0.0 V; calibration points at 0x2666 (−1 V) and 0x599A (+1 V) VDUTx = 0 V; sweep comparator threshold to determine the uncertainty band Uncertainty Band 7 mV CB Rev. 0 | Page 10 of 80 ADATE318 Parameter Maximum Programmable Hysteresis Hysteresis Resolution CMRR DC PSRR AC SPECIFICATIONS −1 ±5 Min Typ 117 5.6 +1 Max Unit mV mV mV/V mV/V Test Level CB D P CT Calculated over hystersis control Code 10 to Code 31 Offset measured at VCM = −1.5 V and +6.5 V with VDM = 0.0 V, offset error change Measured at calibration points All ac specifications performed after dc level calibration, unless noted; input transition time ~200 ps, 20% to 80%, measured with 50 Ω to external termination voltage (VTTC), peaking set to CLC = 2, unless otherwise specified 0.83 ns CB VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for other channel VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for other channel VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for other channel VDUT0 = 0 V, VDUT1: −0.5 V to +0.5 V swing, driver term mode, VIT = 0.0 V, comparator threshold = 0.0 V, repeat for other channel Conditions Propagation Delay, Input to Output Propagation Delay Tempco 2.6 ps/ºC CB Propagation Delay Matching, High Transition to Low Transition Propagation Delay Matching, High to Low Comparator Propagation Delay Change (Dispersion) With Respect To Slew Rate: 400 ps and 1 ns (20% to 80%) Overdrive: 250 mV and 750 mV 15 ps CB 17 ps CB 31 ps CB VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V, repeat for other channel VDUT0 = 0.0 V; for 250 mV: VDUT1: 0 V to 0.5 V swing; for 750 mV: VDUT1: 0 V to 1.0 V swing; driver term mode, VIT = 0.0 V; comparator threshold = −0.25 V; repeat for other channel with comparator threshold = +0.25 V VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; repeat for other channel VDUT0 = 0.0 V; VDUT1: −0.25 V to +0.25 V swing at 32 MHz; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; repeat for other channel VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; repeat for other channel VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing at 32 MHz; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; greater than 50% output differential amplitude; repeat for other channel VDUT0 = 0.0 V; VDUT1: −0.5 V to +0.5 V swing; driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V, CLC = 2 as measured by shmoo; repeat for other channel VDUT0 = 0.0 V; VDUT1: −0.8 V to +0.8 V swing, driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; comparator CLC set to maximum; repeat for other channel 3-bit amplitude control VDUT0 = 0.0 V; VDUT1: −0.8 V to +0.8 V swing, driver term mode, VIT = 0.0 V; comparator threshold = 0.0 V; comparator CLC set to maximum; repeat for other channel 32 ps CB 1 V Pulse Width: 0.7 ns, 1 ns, 5 ns, 10 ns 0.5 V Pulse Width: 0.6 ns, 1 ns, 5 ns, 10 ns Duty Cycle: 5% to 95% Minimum Detectable Pulse Width +1/− 21 +1/− 31 18 ps CB ps CB ps CB 0.5 ns CB Input Equivalent Bandwidth, Terminated Comparator Pre-Emphasis (CLC) CLC Amplitude Range 1038 MHz CB 11 % CB CLC Resolution Pre-Emphasis Time Constant 1.6 4.8 % per bit ns CB CB Rev. 0 | Page 11 of 80 ADATE318 Table 6. Active Load Parameter DC SPECIFICATIONS Input Characteristics VCOM Voltage Range −1.5 −1.0 VCOM Offset VCOM Offset Tempco VCOM Gain 1.0 −200 ±25 1.1 +6.5 +5.5 +200 V V mV μV/°C V/V D D P CT P Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (+5 V), based on ideal DAC transfer function (see Table 21) | IOL and IOH | ≤ 1 mA | IOL and IOH | ≤ 25 mA Measured at DAC Code 0x4000, uncalibrated Min Typ Max Unit Test Level Conditions Load active on, RCVx active, unless otherwise noted VCOM Gain Tempco VCOM Resolution VCOM DNL ±25 153 ±1 ppm/°C μV mV CT D CT IOH = IOL = 12.5 mA; after two point gain/offset calibration; measured over VCOM range of −1.5 V to +6.5 V; calibration points at 0x4000 (0 V) and 0xC000 (+5 V) IOH = IOL = 12.5 mA; after two point gain/offset calibration; measured at end points of VCOM functional range Over ±0.1 V range VCOM INL DUTGND Voltage Accuracy Output Characteristics Maximum Source Current IOL Offset −7 −7 ±2 +7 +7 mV mV P P 25 −600 +600 mA μA D P −1.5 V to +5.5 V DUT range IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; offset extrapolated from measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20 mA) IOL Offset Tempco IOL Gain Error 0 ±1 25 μA/°C % CT P IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; gain derived from measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20 mA); based on ideal DAC transfer function (see Table 21 and Table 22) IOL Gain Tempco IOL Resolution IOL DNL ±25 763 ±4 ppm/°C nA μA CT D CT IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; after two point gain/offset calibration; measured over IOL range, 0 mA to 25 mA; calibrated at Code 0x451F (1 mA) and Code 0xA666 (20 mA) IOH = −2.5 mA, VCOM = 1.5 V, VDUTx = 0.0 V; after two point gain/offset calibration IOH = IOL = 25 mA, VCOM = 2.0 V; measure IOL reference at VDUTx = −1.0 V; measure IOL current at VDUTx = 1.6 V; check >90% of reference current IOH = IOL = 1 mA, VCOM = 2.0 V; measure IOL reference at VDUTx = −1.0 V; measure IOL current at VDUTx = 1.9 V; check >90% of reference current −1.0 V to +6.5 V output range IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; offset extrapolated from measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20 mA) IOL INL IOL 90% Commutation Voltage IOL 90% Commutation Voltage Maximum Sink Current IOH Offset −100 ±20 0.25 +100 0.4 μA V P P 0.1 V CT 25 −600 +600 mA μA D P IOH Offset Tempco IOH Gain Error 0 ±1 25 μA/°C % CT P IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; gain derived from measurements at DAC Code 0x451F (1 mA) and DAC Code 0xA666 (20 mA); based on ideal DAC transfer function (see Table 21 and Table 22) Rev. 0 | Page 12 of 80 ADATE318 Parameter IOH Gain Tempco IOH Resolution IOH DNL Min Typ ±25 763 ±4 Max Unit ppm/°C nA μA Test Level CT D CT IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; after two point gain/offset calibration; measured over IOH range, 0 mA to 25 mA; calibrated at Code 0x451F (1 mA) and Code 0xA666 (20 mA) IOL = −2.5 mA, VCOM = 1.5 V, VDUTx = 3.0 V; after two point gain/offset calibration IOH = IOL = 25 mA, VCOM = 2.0 V; measure IOH reference at VDUTx = 5.0 V; measure IOH current at VDUTx = 2.4 V; ensure >90% of reference current IOH = IOL = 1 mA, VCOM = 2.0 V; measure IOH reference at VDUTx = 5.0 V; measure IOH current at VDUTx = 2.1 V; ensure >90% of reference current All ac specifications performed after dc level calibration unless noted; load active on Conditions IOH INL IOH 90% Commutation Voltage −100 ±25 0.25 +100 0.4 μA V P P 0.1 V CT AC SPECIFICATIONS Dynamic Performance Propagation Delay, Load Active On to Load Active Off; 50%, 90% Propagation Delay, Load Active Off to Load Active On; 50%, 90% Propagation Delay Matching Load Spike 3.1 ns CB Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA, VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH; measured from 50% point of RCVx − RCVx to 90% point of final output; repeat for drive low and drive high Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA, VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH; measured from 50% point of RCVx − RCVx to 90% point of final output; repeat for drive low and drive high Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA, VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH; active on vs. active off; repeat for drive low and drive high Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 0 mA, VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH; repeat for drive low and drive high Toggle RCVx; DUTx terminated 50 Ω to GND; IOL = IOH = 20 mA, VIH = VIL = 0 V; VCOM = +1.5 V for IOL and −1.5 V for IOH; measured at 90% of final value 4.1 ns CB 1.0 ns CB 106 mV pkpk ns CB Settling Time to 90% 1.6 CB Table 7. PPMU (PPMU Enabled in FV, DCL Disabled) Parameter FORCE VOLTAGE Current Range A Current Range B Current Range C Current Range D Current Range E Voltage Range at Output Range A −2.0 −2.0 Range B, Range C, Range D, and Range E Offset Range C All Ranges Offset Tempco, All Ranges −100 ±10 ±25 +100 mV mV μV/°C Rev. 0 | Page 13 of 80 Min Typ Max +40 +1 +100 +10 +2 +5.75 +6 +6.5 Unit Test Level Conditions −40 −1 −100 −10 −2 mA mA μA μA μA D D D D D V V V D D D Output range for full-scale source and sink. Output range for ±25 mA. Output range for full-scale source and sink. −2.0 P CT CT Measured at DAC Code 0x4000 (0 V). Measured at DAC Code 0x4000 (0 V). ADATE318 Parameter Gain Range C 1.0 1.1 V/V P Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V); based on ideal DAC transfer function (see Table 21 and Table 23). Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (5 V); based on ideal DAC transfer function (see Table 21 and Table 23). Gain derived from measurements at DAC Code 0x4000 (0V) and DAC Code 0xC000 (5 V); calibration point 0x4000 (0 V) and 0xC000 (+5 V) output. Min Typ Max Unit Test Level Conditions All Ranges 1.05 V/V CT Gain Tempco, All Ranges ±25 ppm/°C CT INL Range A ±1 mV CT After two point gain/offset calibration, output range of −2.0 V to +5.75 V, PPMU Current Range A only. After two point gain/offset calibration; output range of −2.0 V to +6.5 V. After two point gain/offset calibration, output range of −2.0 V to +6.5 V. Force −2.0 V; measure voltage while sinking zero and full-scale current; measure ΔV; force +5.75 V; measure voltage while sourcing zero and full-scale current; measure ΔV. Force −2.0 V; measure voltage while sinking zero and 25 mA current; measure ΔV; force +6 V; measure voltage while sourcing zero and 25 mA current; measure ΔV. Force −2.0 V; measure voltage while sinking zero and full-scale current; measure ΔV; force +6.5 V; measure voltage while sourcing zero and full-scale current; measure ΔV. Sink: force −2.0 V, short DUTx to +6.5 V; source: force +6.5 V, short DUTx to −2.0 V; repeat for each current range; example: Range A FS = 40 mA, 120% FS = 48 mA 180% FS = 72 mA Over ±0.1 V range; measured at endpoints of PPMU_VINFV functional range (see Figure 136). PPMU enabled in FIMI, DCL disabled. Range C Range B, Range D, and Range E Compliance vs. Current Load Range A −1.7 ±1 +1.7 mV mV P CT ±40 mV CT ±25 mV CT Range B, Range C, Range D, and Range E ±1 mV CT Current Limit, Source and Sink All Ranges 120 140 180 %FS P DUTGND Voltage Accuracy −7 ±2 +7 mV P MEASURE CURRENT DUTx Pin Voltage Range at Full Current Range A Range B, Range C, Range D, and Range E Zero-Current Offset, Range B −2.0 −2.0 −2 +5.75 +6.5 2 V V %FSR D D P Interpolated from measurements sourcing and sinking 80% FSR current each range; FSR = 80 mA for Range A, 2 mA for Range B, 200 μA for Range C, 20 μA for Range D, 4 μA for Range E (see Table 21and Table 23). See Table 21and Table 23. See Table 21 and Table 23. All Ranges Zero-Current Offset Tempco, Range A ±0.5 ±0.001 %FSR %FSR/°C Rev. 0 | Page 14 of 80 CT CT ADATE318 Parameter Range B, Range C, and Range D Range E Gain Error Range B All Ranges Gain Tempco Range A Range B, Range C, Range D, and Range E INL Range A ±0.0125 %FSR CT Range A, after two point gain/offset calibration at ±80% FSR current; measured over FSR output of −40 mA to +40 mA. After two point gain/offset calibration at ±80% FSR current; measured over FSR output of −1 mA to +1 mA. After two point gain/offset calibration at ±80% FSR current; measured over each FSR output for Range C, Range D, and Range E. Range B, FVMI, force −1 V and 5 V into load of 0.5 mA, measure ΔI reported at PPMU_MEASx pin. Over ±0.1 V range (see Figure 136). PPMU enabled in FIMI, DCL disabled. −2.0 −2.0 DUTx Pin Voltage Range at Full Current, Range B, Range C, Range D, and Range E Zero-Current Offset, All Ranges −2.0 +5.75 +6 +6.5 V V V D D D At full-scale source and sink current. At 25 mA source and sink current. ±50 ±25 ppm/°C ppm/°C CT CT −30 −10 +5 % % P CT Based on measurements sourcing and sinking, 80% FSR current. Based on measurements sourcing and sinking, 80% FSR current. Min Typ ±0.001 ±0.002 Max Unit %FSR/°C %FSR/°C Test Level CT CT Conditions Range B −0.03 +0.03 %FSR P Range C, Range D, and Range E ±0.01 %FSR CT DUTx Pin Voltage Rejection −1.2 +1.2 μA P DUTGND Voltage Accuracy FORCE CURRENT DUTx Pin Voltage Range in Range A −7 ±2 +7 mV P −14.5 +14.5 %FSR P Extrapolated from measurements at Code 0x4CCC and Code 0xB333 for each range (see Table 21and Table 23). Zero-Current Offset Tempco Gain Error, All Ranges −5 ±0.002 +25 %FSR/°C % CT P Derived from measurements at Code 0x4CCC and Code 0xB333 for each range (see Table 21 and Table 23). Gain Tempco Range A ±50 ppm/°C CT Significant PPMU self-heating effects in Range A can influence gain drift/tempco measurements. Range B, Range C, Range D, and Range E INL Range A −0.12 ±25 ppm/°C CT ±0.02 +0.12 %FSR P After two point gain/offset calibration; measured over FSR output of −40 mA to +40 mA. After two point gain/offset calibration; measured over FSR output; repeat for Range B, Range C, and Range D. Range B, Range C, and Range D −0.03 +0.03 %FSR P Rev. 0 | Page 15 of 80 ADATE318 Parameter Range E Force Current Compliance vs. Voltage Load Range A −0.3 +0.3 %FSR P Force positive full-scale current driving −2.0 V and +5.75 V; measure ΔI at DUTx pin; force negative full-scale current driving −2.0 V and +5.75 V; measure ΔI at DUTx pin. Force +25 mA driving −2.0 V and +6.0 V; measure ΔI at DUTx pin; force −25 mA driving −2.0 V and +6.0 V; measure ΔI at DUTx pin. Force positive full-scale current driving 0.0 V and +4.0 V; measure ΔI at DUTx pin; force negative full-scale current driving 0.0 V and +4.0 V; measure ΔI at DUTx pin. Force positive full-scale current driving −2.0 V and +6.5 V; measure ΔI at DUTx pin; force negative full-scale current driving −2.0 V and +6.5 V; measure ΔI at DUTx pin. Force positive full-scale current driving 0.0 V and +4.0 V; measure ΔI at DUTx pin; force negative full-scale current driving 0.0 V and +4.0 V; measure ΔI at DUTx pin. Force positive full-scale current driving −2.0 V and +6.5 V; measure ΔI at DUTx pin; force negative full-scale current driving −2.0 V and +6.5 V; measure ΔI at DUTx pin; allows for 10 nA of DUTx pin leakage. Force positive full-scale current driving −2.0 V and +6.5 V; measure ΔI at DUTx pin; force negative full-scale current driving −2.0 V and +6.5 V; measure ΔI at DUTx pin; allows for 10 nA of DUTx pin leakage. PPMU enabled, FVMV, DCL disabled. −2.0 −25 ±10 0.98 ±1 −1.7 +1.7 +6.5 4 200 1.02 +6.5 +25 V mV μV/°C V/V ppm/°C mV D P CT P CT P Range B, measured over −2.0 V to +6.5 V. Range B, gain derived from measurements at VDUTx = 0.0 V and +5.0 V. Range B, VDUTx = 0 V; offset = (PPMU_MEAS − VDUTx). Min −0.045 Typ Max +0.045 Unit %FSR Test Level P Conditions After two point gain/offset calibration; measured over FSR output. −0.3 +0.3 %FSR P −0.06 +0.06 %FSR P Range B and Range C −0.3 +0.3 %FSR P −0.06 +0.06 %FSR P Range D −0.3 +0.3 %FSR P Range E −0.85 +0.85 %FSR P MEASURE VOLTAGE Voltage Range Offset Offset Tempco Gain Gain Tempco INL Measure Pin DC Characteristics Output Range DC Output Current Output Impedance −2.0 V mA Ω D D P PPMU enabled in FVMV, DCL disabled; Source resistance: PPMU force +6.5 V with 0 mA, +4 mA load Sink resistance: PPMU force −2.0 V with 0 mA, −4 mA load Resistance = ΔV/ΔI at PPMU_MEAS pin. Tested at −2.0 V and +6.5 V. Output Leakage Current When Tristated −1 +1 μA P Rev. 0 | Page 16 of 80 ADATE318 Parameter Output Short-Circuit Current Min −25 Typ Max +25 Unit mA Test Level P Conditions PPMU enabled in FVMV, DCL disabled; Source: PPMU force +6.5 V, PPMU_MEAS to −2.0 V Sink: PPMU force −2.0 V, PPMU_MEAS to +6.5 V PPMU_MEASx Pin, Output Capacitance PPMU_MEASx Pin, Load Capacitance VOLTAGE CLAMPS 2 100 pF pF S S Maximum load capacitance. PPMU enabled in FIMI, DCL disabled, PPMU clamps enabled; clamp accuracy specifications apply only when VCH > VCL. Low Clamp Range (VCL) High Clamp Range (VCH) Positive Clamp Voltage Droop −2.0 0.0 −300 ±1 +4.0 +6.5 +300 V V mV D D P ΔV seen at DUTx pin, Range A, VCH = +5.0 V, VCL = −1 V; PPMU force 5 mA and 40 mA into open. ΔV seen at DUTx pin, Range A, VCH = +5.0 V, VCL = −1 V, PPMU force −5 mA and 40 mA into open. Range B, PPMU force ±0.5 mA into open; VCH measured at DAC Code 0x4000 (0 V) with VCL at Code 0x0000 (−2.5 V); VCL measured at DAC Code 0x4000 (0 V) with VCH at 0xFFFF (+7.5 V). Negative Clamp Voltage Droop −300 ±1 +300 mV P Offset, PPMU Clamp VCH/VCL −300 +300 mV P Offset Tempco, PPMU Clamp VCH/VCL Gain, PPMU Clamp VCH/VCL 1.0 ±0.5 1.2 mV/°C V/V CT P Range B, PPMU force ±0.5 mA into open; VCH gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (+5.0 V) with VCL at Code 0x0000 (−2.5 V); VCL gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xA666 (+4.0 V) with VCH at 0xFFFF (+7.5 V). Gain Tempco, PPMU Clamp VCH/VCL INL, PPMU Clamp VCH/VCL −20 ±25 +20 ppm/°C mV CT P Range B, PPMU force ±0.5 mA into open, after two point gain/offset calibration; measured over PPMU clamp functional range. Over ±0.1 V range; measured at end points of clamp functional range. DUTGND Voltage Accuracy SETTLING/SWITCHING TIMES Force Voltage Settling Time to 0.1% of Final Value Range A, 200 pF and 2000 pF Load Range B, 200 pF and 2000 pF Load Range C, 200 pF and 2000 pF Load Force Voltage Settling Time to 1.0% of Final Value Range A, 200 pF & 2000 pf Load Range B, 200 pF and 2000 pf Load Range C, 200 pF and 2000 pf Load −7 ±2 +7 mV P 10 12 32 μs μs μs S S S PPMU enabled in FV, Range A, DCL disabled; program VIN steps from 0 V to 0.5 V and 5.0 V. PPMU enabled in FV, Range B, DCL disabled; program VIN steps from 0 V to 0.5 V and 5.0 V. PPMU enabled in FV, Range C, DCL disabled; program VIN steps from 0 V to 0.5 V and 5.0 V. 8.1 8.1 8.1 μs μs μs CB CB CB PPMU enabled in FV, Range A, DCL disabled; program VIN steps from 0 V to 5.0 V. PPMU enabled in FV, Range B, DCL disabled; program VIN steps from 0 V to 5.0 V. PPMU enabled in FV, Range C, DCL disabled; program VIN steps from 0 V to 5.0 V. Rev. 0 | Page 17 of 80 ADATE318 Parameter Range A, 200 pF and 2000 pf Load Range B, 200 pF and 2000 pf Load Range C, 200 pF and 2000 pf Load Force Current Settling Time to 0.1% of Final Value Range A, 200 pF in Parallel with 120 Ω Range B, 200 pF in Parallel with 1.5 KΩ Range C, 200 pF in Parallel with 15.0 KΩ Force Current Settling Time to 1.0% of Final Value Range A, 200 pF in Parallel with 120 Ω Range B, 200 pF in Parallel with 1.5 KΩ Range C, 200 pF in Parallel with 15.0 KΩ INTERACTION and CROSSTALK Measure Voltage Channel-to-Channel Crosstalk ±0.01 %FSR CT 0.01% × 8.5 V = 0.85 mV, PPMU enabled in FIMV, DCL disabled; CHx under test: Range B, forcing 0 mA into 0 V load; other channel: Range A, sweep 0 mA to 40 mA into 0 V load; report ΔV of PPMU_MEASx pin under test. 0.01% × 5.0 V = 0.5 mV, PPMU enabled in FVMI, DCL disabled; CHx under test: Range E, forcing 0 V into 0 mA current load; other channel: Range E, sweep −2.0 V to +6.5 V into 0 mA current load; report ΔV of PPMU_MEASx pin under test. 8.1 7.5 8.1 μs μs μs CB CB CB PPMU enabled in FI, Range A, DCL disabled; program VIN step of 0 mA to 40 mA. PPMU enabled in FI, Range B, DCL disabled; program VIN step of 0 mA to 1 mA. PPMU enabled in FI, Range C, DCL disabled; program VIN step of 0 mA to 100 μA. 16 10 40 μs μs μs S S S PPMU enabled in FI, Range A, DCL disabled; program VIN step of 0 mA to 40 mA. PPMU enabled in FI, Range B, DCL disabled; program VIN step of 0 mA to 1 mA. PPMU enabled in FI, Range C, DCL disabled; program VIN step of 0 mA to 100 μA. Min Typ 2.5 6.3 8.1 Max Unit μs μs μs Test Level CB CB CB Conditions PPMU enabled in FV, Range A, DCL disabled; program VIN steps from 0 V to 0.5 V. PPMU enabled in FV, Range B, DCL disabled; program VIN steps from 0 V to 0.5 V. PPMU enabled in FV, Range C, DCL disabled; program VIN steps from 0 V to 0.5 V. Measure Current Channel-to-Channel Crosstalk ±0.01 %FSR CT Table 8. PPMU_Go/No-Go Comparators Parameter Compare Voltage Range Input Offset Voltage Input Offset Voltage Tempco Gain 1.0 Min −2.0 −250 ±50 1.1 Typ Max +6.5 +250 Unit V mV μV/ºC V/V Test Level D P CT P Gain derived from measurements at DAC Code 0x4000 (0 V) and DAC Code 0xC000 (+5.0 V) Applies at m = 1.0 and c = 0.0 Measured at DAC Code 0x4000 (0 V) Conditions Gain Tempco Comparator Threshold Resolution Comparator Threshold DNL ±25 153 ±1 ppm/ºC μV mV CT D CT After two point gain/offset calibration; measured over VOH/VOL range − 2.0 V to +6.5 V; calibration points at 0x4000 (0 V) and 0xC000 (+5 V) After two point gain/offset calibration; measured at end points of VOH and VOL functional range Over ±0.1 V range Comparator Threshold INL −7 +7 mV P DUTGND Voltage Accuracy −7 ±2 +7 mV P Rev. 0 | Page 18 of 80 ADATE318 Parameter Comparator Uncertainty Band DC Hysteresis COMPARATOR OUTPUTS Output Logic High Output Logic Low VDD/4 − 0.5 0 VDD/4 + 0.5 0.5 V V PF PF Min Typ 1.6 500 Ω, toggle DATx 20% to 80%, VHH mode enabled, RCVx inactive, VIL = 0.0 V, VIH = 3.0 V, RLOAD > 500 Ω, toggle DATx VHH mode enabled, RCVx inactive, VIL = 0.0 V, VIH = 3.0 V, RLOAD > 500 Ω, toggle DATx DC Output Current Limit Source 60 100 mA P DC Output Current Limit Sink −100 −60 mA P Rise Time, VIL to VIH 6.4 ns CB Fall Time, VIH to VIL 7.3 ns CB Preshoot, Overshoot, and Undershoot ±30 mV CB Table 12. Alarm Functions Parameter DC CHARACTERISTICS Overvoltage Detect (OVD) Programmable Voltage Range Uncalibrated Error at −2.0 V Min Typ Max Unit Test Level Condition See Figure 137 −2.5 −200 +7.5 +200 V mV D P Measured at DAC Code 0x0CCC (−2.0 V); OVD comparators not guaranteed to function as specified if VDUTx is outside absolute maximum voltage range Measured at DAC Code 0xF333 (+7.0 V) Gain derived from measurements at DAC Code 0x4000 and DAC Code 0xC000 Uncalibrated Error at +7.0 V Offset Voltage Tempco Gain Hysteresis Thermal Alarm Setpoint Error Thermal Hysteresis PPMU Clamp Alarm ALARM Output Characteristics Off State Leakage Max On Voltage at100 μA Propagation Delay −450 ±0.5 1.045 125 ±10 −15 +450 mV mV/°C V/V mV °C °C P CT CT CT CT CT See Figure 137 Relative to default value, 100°C See Figure 137 and Table 29 for electrical characteristics 10 0.1 1.5 500 0.7 nA V μs P P CB Disable alarm, apply 2.5 V to ALARM pin, measure leakage current Activate alarm, force 100 μA into ALARM pin, measure active alarm voltage For OVD_HI: VDUTx: 0 V to 6 V swing, OVDH = +3.0 V, OVDL = −1.0 V For OVD_LO: VDUTx: 0 V to 6 V swing, OVDH = +7.0 V, OVDL= +3.0 V Rev. 0 | Page 21 of 80 ADATE318 SPI TIMING DETAILS tCH SCLK 0 1 2 3 4 5 6 7 8 9 10 11 24 25 tCSAM 0 1 2 3 4 5 6 7 tCSAS CS tCL tCSRS tCSAH SDI C1 C0 tDS A6 A5 A4 A3 A2 A1 A0 R/W D15 D14 tCSRH D1 D0 C1 C0 A6 A5 A4 A3 A2 A1 tCSO SDO NOTE 1 C1 C0 tDH A6 A5 A4 tDO A3 A2 A1 A0 R/W D15 D14 D1 tCSZ D0 NOTE 1 C1 C0 A6 A4 A3 A2 A1 A0 tBUSA BUSY NOTES 1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS. tBUSR SEE TABLE 18 tBUSW Figure 2. SPI Detailed Read/Write Timing Diagram SCLK CS SDI CH[1:0] ADDR[6:0] W DATA[15:0] SDO NOTE 1 ACTIVE – OUTPUT IS THE PREVIOUS SPI WORD SHIFTED INTO SDI NOTE 1 BUSY FROM PREVIOUS SPI INSTRUCTIONS (SEE TABLE 18) NOTES 1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS. SEE TABLE 18 Figure 3. SPI Write Instruction Rev. 0 | Page 22 of 80 09530-005 09530-004 ADATE318 tCH SCLK tCL tRMIN RST ASYNCHRONOUS ASSERT tRS tBUSA BUSY tBUSR SEE TABLE 18 tBUSW 3µs (DAC DEGLITCH) DAC0 PREVIOUS CODE VDUTGND DEFAULT DAC0 CODE DAC1 PREVIOUS CODE VDUTGND DEFAULT DAC1 CODE DAC23 RESET CONDITION INITIALIZED CONDITION Figure 4. SPI Detailed Hardware Reset Timing Diagram Rev. 0 | Page 23 of 80 09530-006 ........ PREVIOUS CODE ........ VDUTGND ........ DEFAULT DAC23 CODE ........ ADATE318 tCH SCLK tCL CS SDI SPI RESET tBUSA BUSY tBUSR SEE TABLE 18 tBUSW 3µs (DAC DEGLITCH) DAC0 PREVIOUS CODE VDUTGND DEFAULT DAC0 CODE DAC1 PREVIOUS CODE VDUTGND DEFAULT DAC1 CODE DAC23 RESET CONDITION INITIALIZED CONDITION Figure 5. SPI Detailed Software Reset Timing Diagram SCLK CS SDI CH[1:0] ADDR[6:0] R DATA[15:0] = DON’T CARE SDO NOTE 1 ACTIVE – OUTPUT IS THE PREVIOUS SPI WORD SHIFTED INTO SDI NOTE 1 BUSY FROM PREVIOUS SPI INSTRUCTIONS (SEE TABLE 18) NOTES 1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTRO BIT IS LOW, THE SDO PIN ALWAYS L REMAINS ACTIVE INDEPENDENT OF CS. Figure 6. SPI Read Request Instruction (Prior to Readout) Rev. 0 | Page 24 of 80 09530-008 09530-007 ........ PREVIOUS CODE ........ VDUTGND ........ DEFAULT DAC23 CODE ........ ADATE318 SCLK CS SDI CH[1:0] ADDR[6:0] (COULD BE NOP) R/W DATA[15:0] = (IF NOP, THEN DON’T CARE) NOTE 2 SDO NOTE 1 CH[1:0] ADDR[6:0] READ OUT DATA[15:0] 0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NOTE 1 BUSY NOTES 1. IF THE SPI_SDO_HIZ CONTROL BIT (ADDR 0x12 [1]) IS HIGH, THE SDO PIN BECOMES ACTIVE FOLLOWING THE ASSERTION OF CS. IT BECOMES HIGH-Z FOLLOWING RELEASE OF CS. IF THE SPI_SDO_HIZ CONTROL BIT IS LOW, THE SDO PIN REMAINS ACTIVE INDEPENDENT OF CS. 2. THE FIRST 10 BITS OF SDO FOLLOWING A READ REQUEST ECHO ADDRESS AND CHANNEL BITS OF THE PRECEDING REQUEST. THE R/W BIT POSITION IS SET LOW. THE FOLLOWING 16 BITS CONTAIN DATA FROM THE REQUESTED ADDRESS AND CHANNEL. SEE TABLE 18 Figure 7. SPI Readout Instruction (Subsequent to Read Request) Rev. 0 | Page 25 of 80 09530-009 ADATE318 Table 13. SPI Detailed Timing Requirements Parameter fCLK tCH tCL tCSAS tCSAH tCSRS tCSRH Min 0.5 9 9 3 3 3 3 4 Max 50 Unit MHz ns ns ns ns ns ns ns Test Level CT CT CT CT CT CT CT CT Description SCLK operating frequency. SCLK high time. SCLK low time. Setup of CS to rising SCLK at assert. Hold of CS to rising SCLK at assert. Setup of CS to rising SCLK at release. Hold of CS to rising SCLK at release. Hold of CS release prior to rising SCLK. This parameter is critical only if the number of SCLK cycles from the previous release of CS is the minimum specified by the tCSAM parameter. Delay from CS assert to SDO active. Delay from CS release to SDO high-Z, depends greatly on external pin loading. Width of CS release between consecutive assertions of CS. This parameter is specified in units of SCLK cycles, more specifically in terms of rising edges of the SCLK input. Setup of SDI data prior to rising SCLK. Hold of SDI data following rising SCLK. Delay of SDO data from rising SCLK. Delay of BUSY assert from first rising SCLK following a valid CS release or an asynchronous RSTb release. Width of BUSY assert. To ensure proper SPI operation, the SCLK must be provided for as long as BUSY remains asserted. Note that the number of SCLK cycles within any BUSY period is variable but deterministic and is based on the previous SPI write instruction type. See the Use of the SPI BUSY Pin section and Figure 3, Figure 6, Figure 8, and Table 18 for more information. Delay of BUSY release from first rising SCLK, satisfying the requirements detailed in the Use of the SPI BUSY Pin section. Width of asynchronous RST assert. Setup of RST to rising SCLK at release. Number of SCLK rising edge cycles per SPI word write plus the additional tCSAM requirement. Settling time of analog DAC levels to ±0.5 LSB relative to the beginning of the DAC deglitch period, which begins x SCLK cycles following the release of CS and four SCLK cycles prior to the release of the BUSY pin. The number of SCLK cycles, x, is defined by Table 18. Also see Figure 124 for more information. tCSO tCSZ tCSAM 6 10 3 ns ns Cycles CT CT CT tDS tDH tDO tBUSA tBUSW 3 4 12 12 3 26 ns ns ns ns Cycles CT CT CT CT CT tBUSR tRMIN tRS tSPI tDAC 10 3 29 5 12 ns ns ns Cycles CT CT CT CT S 10 μs Rev. 0 | Page 26 of 80 ADATE318 ABSOLUTE MAXIMUM RATINGS Table 14. Absolute Maximum Ratings Parameter Supply Voltages Positive Supply Voltage (VDD to PGND) Positive VCC Supply Voltage (VCC to DGND) Negative Supply Voltage (VSS to PGND) Supply Voltage Difference (VDD to VSS) Reference Ground (DUTGND to AGND) VPLUS Supply Voltage (VPLUS to PGND) Supply Sequence or Dropout Condition1 Input/Output Voltages Analog Input Common-Mode Voltage DUTx Output Short Circuit Voltage2 High Speed Input Voltage Absolute Range3 High Speed Differential Input Voltage3 DUTx I/O Pin Current DCL Maximum Short-Circuit Current4 Temperature Operating Temperature, Junction Storage Temperature Range 1 2 Rating −0.5 V to +11.0 V −0.5 V to +4.0 V −6.5 V to +0.5 V −1.0 V to +17.0 V −0.5 V to +0.5 V −0.5 V to +19.0 V rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 15. Thermal Resistance Package Type Airflow LFCSP 0 45 θJA 1 40 θJC 2 37 1 Unit m/s °C/W VSS to VDD −3.0 V to +8.0 V −0.5 V to VTTC + 0.5 V −1.0 V to +1.0 V Table 16. Explanation of Test Levels Test Level D S P PF CT CB Description Definition Design verification simulation 100% production tested Functionally checked during production test Characterized on tester Characterized on bench ±140 mA 125°C −65°C to +150°C ESD CAUTION No supply should exceed the given ratings. RLOAD = 0 Ω, VDUTx continuous short-circuit condition (VIH, VIL, VIT), high-Z, VCOM, and clamp modes). 3 DAT, DAT, RCV, RCV, RSOURCE = 0 Ω. 4 RLOAD = 0 Ω, VDUTx = −3 V to +8 V; DCL current limit. Continuous short-circuit condition. ADATE318 current limits and survives a continuous short-circuit fault. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress Rev. 0 | Page 27 of 80 ADATE318 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 VSS PMU_S1 VDD VDDO1 DUT1 VSSO1 VSS PGND VDD VSS AGND VSS VDD PGND VSS VSSO0 DUT0 VDDO0 VDD PMU_S0 VSS VDD_THERM PPMU_S1 THERM DAT1 DAT1 NC RCV1 RCV1 SCAP1 FFCAPB1 FFCAPA1 CMPL1 CMPL1 VTTC1 CMPH1 CMPH1 PGND VDD VSS PPMU_CMPH1 AGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 PIN 1 IDENTIFIER ADATE318 TOP VIEW (Not to Scale) 84-LEAD 10mm × 10mm LFCSP (HEATSINK FACE UP, DIE FACE DOWN) VPLUS PPMU_S0 HVOUT DAT0 DAT0 NC RCV0 RCV0 SCAP0 FFCAPB0 FFCAPA0 CMPL0 CMPL0 VTTC0 CMPH0 CMPH0 PGND VDD VSS PPMU_CMPH0 AGND NOTES 1. EXPOSED PADDLE IS INTERNALLY CONNECTED VIA HIGH IMPEDANCE TO VSS (SUBSTRATE). 2. NC = THIS PIN IS OPEN. NO INTERNAL CONNECTION. AGND PPMU_CMPL1 PPMU_MEAS1 DGND DUTGND ALARM VSS DGND CS BUSY SDO SCLK SDI VCC VDD RST VREF VREFGND PPMU_MEAS0 PPMU_CMPL0 AGND 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Figure 8. LFCSP Pin Configuration Table 17. Pin Function Descriptions Pin EP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Mnemonic Exposed Paddle VDD_THERM PPMU_S1 THERM DAT1 DAT1 NC RCV1 RCV SCAP1 FFCAPB1 FFCAPA1 CMPL1 CMPL1 VTTC1 CMPH1 CMPH1 PGND VDD VSS PPMU_CMPH1 AGND AGND PPMU_CMPL1 Description Exposed paddle is internally connected via high impedance to VSS (substrate). Temperature Sensor VDD Supply. PPMU External Sense Connect, Channel 1. Temperature Sensor Analog Output. High Speed Data Input, Channel 1. High Speed Data Input Complement, Channel 1. This pin is open. No internal connection. High Speed Receive Input, Channel 1. High Speed Receive Input Complement, Channel 1. PPMU External Compensation Capacitor, Channel 1. PPMU External Feed Forward Capacitor Pin B, Channel 1. PPMU External Feed Forward Capacitor Pin A, Channel 1. High Speed Comparator Low Output, Channel 1. High Speed Comparator Low Output Complement, Channel 1. Comparator Supply Termination, Channel 1. High Speed Comparator High Output Complement, Channel 1. High Speed Comparator High Output, Channel 1. Power Ground. VDD Supply. VSS Supply. PPMU Go/No-Go Comparator High Output, Channel 1. Analog Ground. Analog Ground. PPMU Go/No-Go Comparator Low Output, Channel 1. Rev. 0 | Page 28 of 80 09530-002 ADATE318 Pin 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Mnemonic PPMU_MEAS1 DGND DUTGND ALARM VSS DGND CS BUSY SDO SCLK SDI VCC VDD RST VREF VREFGND PPMU_MEAS0 PPMU_CMPL0 AGND AGND PPMU_CMPH0 VSS VDD PGND CMPH0 CMPH0 VTTC0 CMPL0 CMPL0 FFCAPA0 FFCAPB0 SCAP0 RCV0 RCV0 NC DAT0 DAT0 HVOUT PPMU_S0 VPLUS VSS PMU_S0 VDD VDDO0 DUT0 VSSO0 VSS PGND VDD VSS AGND Description PPMU Analog Measure Output, Channel 1. Digital Logic Ground. DUT Ground Sense Input. Fault Alarm Open Drain Output. VSS Supply. Digital Logic Ground. Serial Programmable Interface (SPI) Chip Select Input (Active Low). Serial Programmable Interface (SPI) Busy Output (Active Low). Serial Programmable Interface (SPI) Serial Data Output. Serial Programmable Interface (SPI) Clock Input. Serial Programmable Interface (SPI) Serial Data Input. VCC Supply. VDD Supply. Reset Input (Active Low). DAC Precision +5.0 V Reference Input. DAC Precision +0.0 V Reference Input. PPMU Analog Measure Output, Channel 0. PPMU Go/No-Go Comparator Low Output, Channel 0. Analog Ground. Analog Ground. PPMU Go/No-go Comparator High Output, Channel 0. VSS Supply. VDD Supply. Power Ground. High Speed Comparator High Output, Channel 0. High Speed Comparator High Output Complement, Channel 0. Comparator Supply Termination, Channel 0. High Speed Comparator Low Output Complement, Channel 0. High Speed Comparator Low Output, Channel 0. PPMU External Feed Forward Capacitor Pin A, Channel 0. PPMU External Feed Forward Capacitor Pin B, Channel 0. PPMU External Compensation Capacitor, Channel 0. High Speed Receive Input Complement, Channel 0. High Speed Receive Input, Channel 0. This pin is open. No internal connection. High Speed Data Input Complement, Channel 0. High Speed Data Input, Channel 0. VHH Output Pin. PPMU External Sense Connect, Channel 0. VPLUS Supply. VSS Supply. System PMU Sense Input, Channel 0. VDD Supply. VDD Supply, Driver Output Stage, Channel 0. DUT Pin, Channel 0. VSS Supply, Driver Output Stage, Channel 0. VSS Supply. Power Ground. VDD Supply. VSS Supply. Analog Ground. Rev. 0 | Page 29 of 80 ADATE318 Pin 75 76 77 78 79 80 81 82 83 84 Mnemonic VSS VDD PGND VSS VSSO1 DUT1 VDDO1 VDD PMU_S1 VSS Description VSS Supply. VDD Supply. Power Ground. VSS Supply. VSS Supply, Driver Output Stage, Channel 1. DUT Pin, Channel 1. VDD Supply, Driver Output Stage, Channel 1. VDD Supply. System PMU Sense Input, Channel 1. VSS Supply. Rev. 0 | Page 30 of 80 ADATE318 TYPICAL PERFORMANCE CHARACTERISTICS 0.35 0.30 0.25 0.20 VOLTAGE (V) 1.8 1.6 500mV 1.4 1.2 1V 2V 3V 0.15 0.10 0.05 0 –0.05 09530-101 VOLTAGE (V) 1.0 0.8 0.6 0.4 0.2 0 –0.2 200mV 0 2 4 6 8 10 12 TIME (ns) 14 16 18 20 0 2 4 6 8 10 TIME (ns) 12 14 16 18 20 Figure 9. Driver Small Signal Response, VIH = 0.2 V, 0.5 V, VIL = 0.0 V, 50 Ω Termination 1.8 1.6 1.4 1.2 VOLTAGE (V) Figure 12. 100 MHz Driver Response, VIH = 1. 0 V, 2.0 V, 3.0 V; VIL = 0.0 V, 50 Ω Termination 1.8 1V 2V 3V 3V 1.6 1.4 VOLTAGE (V) 1.0 0.8 0.6 0.4 0.2 0 –0.2 2V 1.2 1.0 0.8 0.6 0.4 0.2 0 09530-102 1V 0 2 4 6 8 10 12 14 16 18 20 0 2 4 TIME (ns) 6 8 10 TIME (ns) Figure 10. Driver Large Signal Response, VIH = 1.0 V, 2.0 V, 3.0 V; VIL = 0.0 V, 50 Ω Termination 6 5 4 5V Figure 13. 300 MHz Driver Response, VIH = 1.0 V, 2.0 V, 3.0 V; VIL = 0.0 V, 50 Ω Termination 1.8 1.6 1.4 1.2 0.5V 1V 2V 3V VOLTAGE (V) 3 2 1 0 –1 3V VOLTAGE (V) 1.0 0.8 0.6 0.4 0.2 0 1V 09530-103 0 2 4 6 8 10 TIME (ns) 12 14 16 18 20 0 2 4 TIME (ns) 6 8 10 Figure 11. Driver Large Signal Response, VIH = 1.0 V, 3.0 V, 5.0 V; VIL = 0.0 V, 50 Ω Unterminated Figure 14. 400 MHz Driver Response, VIH = 0.5 V, 1.0 V, 2.0 V, 3.0 V; VIL = 0.0 V, 50 Ω Termination Rev. 0 | Page 31 of 80 09530-106 –0.2 09530-105 –0.4 –0.2 09530-104 –0.10 –0.4 ADATE318 1.2 1.0 0.8 0.5V 1V 2V 1.6 1.4 1.2 1.0 VOLTAGE (V) VIH TO/FROM VIT VOLTAGE (V) 0.6 0.4 0.2 0.8 0.6 0.4 0.2 VIL TO/FROM VIT 0 09530-108 0 0 5 10 TIME (ns) 15 20 09530-111 –0.2 –0.2 0 1 2 TIME (ns) 3 4 5 Figure 15. 600 MHz Driver Response, VIH = 0.5 V, 1.0 V, 2.0 V; VIL = 0.0 V, 50 Ω Termination 0.6 Figure 18. Driver Active (VIH/VIL) to/from VTERM Transition; VIH =3.0 V, VIT = 1.5 V; VIL = 0.0 V, 50 Ω Termination 90 POSITIVE PULSE NEGATIVE PULSE 0.5 VIH TO/FROM VIT 0.4 TRAILING EDGE ERROR (ps) 70 50 30 10 –10 –30 –50 VOLTAGE (V) 0.3 0.2 0.1 VIL TO/FROM VIT 0 –0.1 09530-109 0 5 10 TIME (ns) 15 20 0 2 4 6 8 10 PULSE WIDTH (ns) Figure 16. Driver Active (VIH/VIL) to/from VTERM Transition; VIH = 1.0 V, VIT = 0.5 V; VIL = 0.0 V, 50 Ω Termination 1.2 1.0 0.8 VOLTAGE (V) Figure 19. Driver Trailing Edge Timing Error Pulse Width, VIH = 0.2 V; VIL = 0.0 V, 50 Ω Termination 90 70 50 30 10 –10 –30 –50 POSITIVE PULSE NEGATIVE PULSE 0.6 0.4 0.2 VIL TO/FROM VIT 0 –0.2 TRAILING EDGE ERROR (ps) VIH TO/FROM VIT 09530-110 0 5 10 TIME (ns) 15 20 0 2 4 6 8 10 PULSE WIDTH (ns) Figure 17. Driver Active (VIH/VIL) to/from VTERM Transition; VIH = 2.0 V, VIT = 1.0 V; VIL = 0.0 V, 50 Ω Termination Figure 20. Driver Trailing Edge Timing Error vs. Pulse Width, VIH = 0.5 V; VIL = 0.0 V, 50 Ω Termination Rev. 0 | Page 32 of 80 09530-113 09530-112 ADATE318 70 POSITIVE PULSE NEGATIVE PULSE 50 1.5 TRAILING EDGE ERROR (ps) 1.0 LINEARITY ERROR (mV) 30 0.5 10 0 –10 0 –30 –0.5 09530-114 0 2 4 6 8 10 –1 0 PULSE WIDTH (ns) 1 2 3 4 5 DRIVER OUTPUT VOLTAGE (V) 6 7 Figure 21. Driver Trailing Edge Timing Error vs. Pulse Width, VIH = 1.0 V; VIL = 0.0 V, 50 Ω Termination 90 70 50 30 10 –10 –30 –50 POSITIVE PULSE NEGATIVE PULSE Figure 24. Driver VIH Linearity Error 1.5 TRAILING EDGE ERROR (ps) 1.0 LINEARITY ERROR (mV) 0.5 0 –0.5 09530-115 0 2 4 6 8 10 –1 0 PULSE WIDTH (ns) 5 1 2 3 4 DRIVER OUTPUT VOLTAGE (V) 6 7 Figure 22. Driver Trailing Edge Timing Error vs. Pulse Width, VIH = 2.0 V; VIL = 0.0 V, 50 Ω Termination 100 80 POSITIVE PULSE NEGATIVE PULSE Figure 25. Driver VIL Linearity Error 1.5 TRAILING EDGE ERROR (ps) 60 40 20 0 –20 –40 –60 –80 09530-116 1.0 LINEARITY ERROR (mV) 0.5 0 –0.5 0 2 4 6 8 10 –1 0 PULSE WIDTH (ns) 1 2 3 4 5 DRIVER OUTPUT VOLTAGE (V) 6 7 Figure 23. Driver Trailing Edge Timing Error vs. Pulse Width, VIH = 3.0 V; VIL = 0.0 V, 50 Ω Termination Figure 26. Driver VIT Linearity Error Rev. 0 | Page 33 of 80 09530-119 –100 –1.0 –2 09530-118 –1.0 –2 09530-117 –50 –1.0 –2 ADATE318 0.25 0.20 INTERACTION ERROR (mV) 50.0 DRIVER OUTPUT RESISTANCE (Ω) 09530-120 49.5 0.15 0.10 0.05 0 –0.05 –0.10 –2 49.0 48.5 48.0 –1 0 1 2 3 4 5 6 7 –40 –20 0 20 40 60 VIL PROGRAMMED DAC VOLTAGE (V) DRIVER OUTPUT CURRENT (mA) Figure 27. Driver Interaction Error VIH vs. VIL, VIH = +6.5 V, VIL Swept from −1.5 V to +6.5 V 0.08 0.06 0.04 0.02 0 –0.02 –0.04 –0.06 –2 DRIVER OUTPUT CURRENT (mA) INTERACTION ERROR (mV) Figure 30. Driver Output Resistance vs. Output Current 120 100 80 60 40 20 09530-121 –1 0 1 2 3 4 5 6 7 –1 0 1 2 3 4 5 6 7 VIH PROGRAMMED DAC VOLTAGE (V) VDUT (V) Figure 28. Driver Interaction Error VIL vs. VIH; VIL = −1.5 V, VIH Swept from −1.5 V to +6.5 V 0.8 0.7 INTERACTION ERROR (mV) Figure 31. Driver Output Current Limit; Driver Programmed to −1.5 V, VDUT Swept −1.5 V to +6.5 V 0 0.6 0.5 0.4 0.3 0.2 0.1 0 09530-122 DRIVER OUTPUT CURRENT (mA) –20 –40 –60 –80 –100 –1 0 1 2 3 4 5 6 7 –1 0 1 2 3 4 5 6 7 VIH PROGRAMMED DAC VOLTAGE (V) VDUT (V) Figure 29. Driver Interaction Error VIT vs. VIH, VIT = +1.0 V, VIH Swept from −1.5 V to +6.5 V Figure 32. Driver Output Current Limit. Driver Programmed to 6.5 V, VDUT Swept −1.5 V to +6.5 V Rev. 0 | Page 34 of 80 09530-125 –0.1 –2 –120 –2 09530-124 0 –2 09530-123 47.5 –60 ADATE318 16 14 12 VHH OUTPUT 10 5 LINEARITY ERROR (mV) VOLTAGE (V) 10 8 6 4 2 0 –5 –10 09530-126 0 0.5 1.0 TIME (µs) 1.5 2.0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HVOUT OUTPUT VOLTAGE (V) Figure 33. HVOUT Transient Response, VHH = 13.5 V 3 2 Figure 36. HVOUT VHH Linearity Error 100 90 0 –1 –2 –3 –4 –5 –6 09530-127 HVOUT DRIVER CURRENT (mA) 1 80 70 60 50 40 30 20 10 LINEARITY ERROR (mV) 0 2 4 5 1 3 HVOUT OUTPUT VOLTAGE (V) 6 7 5 6 7 8 9 10 11 VHVOUT (V) 12 13 14 15 Figure 34. HVOUT VIH Linearity Error 3 2 Figure 37. HVOUT VHH Output Current Limit; VHH = 5.9 V, HVOUT Swept 5.9 V to 13.5 V 20 10 HVOUT DRIVER CURRENT (mA) 1 0 –10 –20 –30 –40 –50 –60 –70 –80 LINEARITY ERROR (mV) 0 –1 –2 –3 –4 –5 –6 09530-128 0 2 4 5 1 3 HVOUT OUTPUT VOLTAGE (V) 6 7 5 6 7 8 9 10 11 VHVOUT (V) 12 13 14 15 Figure 35. HVOUT VIL Linearity Error Figure 38. HVOUT VHH Output Current Limit; VHH = 13.5 V, HVOUT Swept 5.9 V to 13.5 V Rev. 0 | Page 35 of 80 09530-131 –7 –1 –90 09530-130 –7 –1 0 09530-129 0 –15 ADATE318 80 70 HVOUT DRIVER CURRENT (mA) 1.2 1.0 0.8 60 50 VOLTAGE (V) 40 30 20 10 0 09530-132 0.6 0.4 0.2 0 –0.2 INPUT EDGE SHMOO 0 1 2 3 VHVOUT (V) 4 5 6 7 0 2 4 TIME (ns) 6 8 10 Figure 39. HVOUT VIL Output Current Limit; VIL = −0.1 V, HVOUT Swept −0.1 V to 6.0 V 10 0 Figure 42. Normal Window Comparator Shmoo; 1.0 V Swing, 50 Ω Termination, 200 ps (20% to 80%) 5 0 –5 –10 –15 –20 –25 09530-133 HVOUT DRIVER CURRENT (mA) –10 –30 –40 –50 –60 –70 –80 –90 –1 0 1 2 3 VHVOUT (V) 4 5 6 7 TRAILING EDGE (ps) –20 POSITIVE PULSE NEGATIVE PULSE 0 2 6 4 PULSE WIDTH (ns) 8 10 Figure 40. HVOUT VIH Output Current Limit; VIH = 6.0 V, HVOUT Swept −0.1 V to 6.0 V 1.2 1.0 0.8 Figure 43. Normal Window Comparator Trailing Edge Timing Error vs. Input Pulse Width; 50 Ω Termination, 1.0 V Swing, 200 ps (20% to 80%) 0 INPUT VOLTAGE SWING = 1V COMPARATOR THRESHOLD = 0.5V PROPAGATION DELAY VARIATION (ps) –2 –4 –6 –8 –10 –12 –14 –16 VOLTAGE (V) 0.6 0.4 0.2 0 –0.2 INPUT EDGE SHMOO INPUT RISING EDGE INPUT FALLING EDGE 09530-134 0 2 4 TIME (ns) 6 8 10 0.5 0.6 0.7 0.8 0.9 INPUT TRANSITION TIME (20%/80%) (ns) 1.0 Figure 41. Normal Window Comparator Shmoo 1.0 V Swing; 50 Ω Termination, 200 ps (20% to 80%) Figure 44. Normal Window Comparator Input Transition Time (20%/80%), 50 Ω Termination Rev. 0 | Page 36 of 80 09530-192 –18 0.4 09530-191 –30 09530-190 –10 –1 ADATE318 0.8 0.7 0.6 0.20 0.15 0.10 LINEARITY ERROR (mV) 09530-138 VOLTAGE (V) 0.5 0.4 0.3 0.2 0.1 0 0.05 0 –0.05 –0.10 –0.15 –0.20 0 5 10 TIME (ns) 15 20 –2 –1 0 1 2 3 4 THRESHOLD VOLTAGE (V) 5 6 7 Figure 45. Comparator Output Waveform 0 –0.2 –0.4 LINEARITY ERROR (mV) –0.6 –0.8 –1.0 –1.2 –1.4 –1.6 –1.8 –2.0 –2 09530-139 Figure 48. PPMU Go/No-Go Comparator Linearity Error 2.5 DIFFERENTIAL COMPARATOR OFFSET (mV) 2.0 1.5 1.0 0.5 –1 0 1 2 3 4 THRESHOLD VOLTAGE (V) 5 6 7 0 –2 –1 1 2 3 4 5 0 INPUT COMMON-MODE VOLTAGE (V) 6 7 Figure 46. Normal Window Comparator Threshold Linearity Error 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 09530-140 Figure 49. Differential Comparator CMR Error 30 25 20 15 10 5 0 –5 CURRENT VIL TO LOAD CURRENT LOAD TO VIL LINEARITY ERROR (mV) –1.0 –0.5 0 0.5 1.0 1.5 0 5 10 TIME (ns) 15 15 20 THRESHOLD VOLTAGE (V) Figure 47. Differential Comparator Threshold Linearity Error Figure 50. Active Load Response to/from Drive VIL = 0 V, 50 Ω Termination, IOL = 25 mA, VCOM = 2 V Rev. 0 | Page 37 of 80 09530-143 –2.0 –1.5 LOAD CURRENT (mA) 09530-142 09530-141 –0.25 –3 ADATE318 30 10 8 6 4 2 0 –2 –4 09530-144 20 LINEARITY ERROR (µA) LOAD CURRENT (mA) 10 0 –10 –20 –30 –3 –2 –1 0 1 2 VDUT (V) 3 4 5 6 7 –6 0 5 10 15 ACTIVE LOAD CURRENT (mA) 20 25 Figure 51. Active Load Commutation Response, VCOM = 2.0 V, IOH = IOL = 25 mA 20 15 LINEARITY ERROR (µA) 0 –0.5 –1.0 Figure 54. Active Load IOL Linearity Error 10 5 0 –5 –10 –15 LEAKAGE (nA) –1.5 –2.0 –2.5 –3.0 –3.5 –4.0 09530-145 0 5 10 15 20 25 –2 –1 0 1 ACTIVE LOAD CURRENT (mA) 2 3 VDUT (V) 4 5 6 7 Figure 52. Active Load IOH Linearity Error 0 250 Figure 55. DUTx Pin Leakage in Low Leakage Mode –0.2 200 LINEARITY ERROR (mV) –0.6 LEAKAGE (nA) –0.4 150 100 –0.8 50 –1.0 0 09530-146 –1 0 1 2 3 4 VCOM VOLTAGE (V) 5 6 7 –2 –1 0 1 2 3 VDUT (V) 4 5 6 7 8 Figure 53. Active Load VCOM Linearity Error Figure 56. DUTx Pin Leakage in High-Z Mode Rev. 0 | Page 38 of 80 09530-149 –1.2 –2 –50 –3 09530-148 –4.5 –3 09530-147 ADATE318 3.0 0.15 2.5 0.10 2.0 LINEARITY ERROR (µA) 0.05 ERROR (mV) 1.5 0 1.0 –0.05 0.5 –0.10 –0.10 –0.05 0 0.05 DUTGND VOLTAGE (V) 0.10 0.15 09530-150 –0.5 0 0.5 1.0 PMU OUTPUT CURRENT (mA) Figure 57. Typical DUTGND Transfer Function Voltage Error, Drive Low VIL = 0 V 0.2 0.1 LINEARITY ERROR (mV) 0 –0.1 –0.2 –0.3 –0.4 09530-151 Figure 60. PPMU Range B Force Current Linearity Error 0.018 0.016 0.014 LINEARITY ERROR (µA) 0.012 0.010 0.008 0.006 0.004 0.002 0 0.05 –0.05 PMU OUTPUT CURRENT (mA) 0.10 09530-154 09530-155 –0.5 –2 –1 0 1 2 3 4 5 6 7 0 –0.10 PMU OUTPUT VOLTAGE (V) Figure 58. PPMU Force Voltage Linearity Error, All Ranges 15 Figure 61. PPMU Range C Force Current Linearity Error 0.0015 10 0.0010 LINEARITY ERROR (µA) 5 LINEARITY ERROR (µA) 0.0005 0 0 –5 –0.0005 09530-152 –10 –40 –30 0 10 20 –20 –10 PMU OUTPUT CURRENT (mA) 30 40 –0.0010 –0.010 0 0.005 –0.005 PMU OUTPUT CURRENT (mA) 0.010 Figure 59. PPMU Range A Force Current Linearity Error Figure 62. PPMU Range D Force Current Linearity Error Rev. 0 | Page 39 of 80 09530-153 0 –0.15 –0.15 –1.0 ADATE318 0.0004 0.0003 0.0002 0.5 0.4 0.3 0.2 LINEARITY ERROR (µA) 0.0001 0 –0.0001 –0.0002 –0.0003 –0.0004 –0.0005 09530-156 ERROR (mV) 0.1 0 –0.1 –0.2 –0.3 –0.4 0 0.0005 0.0010 0.0015 0.0020 –0.5 –1.0 –0.5 PMU OUTPUT CURRENT (mA) 0 IDUT (mA) 0.5 1.0 Figure 63. PPMU Range E Force Current Linearity Error 25 20 Figure 66. PPMU Force Voltage Range B Compliance Error at −2.0 V vs. Output Current, Internal Sense 0.3 0.2 15 10 0.1 ERROR (mV) 5 0 –5 –10 –15 –20 09530-157 ERROR (mV) 0 –0.1 –0.2 –0.3 09530-160 –25 –40 –30 –20 –10 0 10 IDUT (mA) 20 30 40 –0.4 –1.0 –0.5 0 IDUT (mA) 0.5 1.0 Figure 64. PPMU Force Voltage Range A Compliance Error at −2.0 V vs. Output Current, Internal Sense 25 20 15 10 Figure 67. PPMU Force Voltage Range B Compliance Error at +6.5 V vs. Output Current, Internal Sense 20 15 ERROR (mV) ERROR (µA) 5 0 –5 –10 –15 –20 09530-158 10 5 0 –30 –20 –10 0 10 IDUT (mA) 20 30 40 –1 0 1 2 VDUT (V) 3 4 5 6 Figure 65. PPMU Force Voltage Range A Compliance Error at +5.75 V vs. Output Current, Internal Sense Figure 68. PPMU Force Current Range A Compliance Error at −40 mA vs. Output Voltage Rev. 0 | Page 40 of 80 09530-161 –25 –40 –5 –2 09530-159 –0.0006 –0.0020 –0.0015 –0.0010 –0.0005 ADATE318 35 30 25 0.0020 0.0015 ERROR (µA) 15 10 5 0 09530-162 ERROR (µA) 20 0.0010 0.0005 0 –0.0005 –1 0 1 2 VDUT (V) 3 4 5 6 –0.0010 –2 –1 0 1 3 2 VDUT (V) 4 5 6 7 Figure 69. PPMU Force Current Range A Compliance Error at +40 mA vs. Output Voltage 0.30 0.25 Figure 72. PPMU Force Current Range E Compliance Error at −2 μA vs. Output Voltage 0.0020 0.0015 0.20 ERROR (µA) ERROR (µA) 0.15 0.10 0.05 0.0010 0.0005 0 0 –0.05 –2 09530-163 –1 0 1 3 2 VDUT (V) 4 5 6 7 –0.0005 –2 –1 0 1 2 3 VDUT (V) 4 5 6 7 Figure 70. PPMU Force Current Range B Compliance Error at −1 mA vs. Output Voltage 0.5 Figure 73. PPMU Force Current Range E Compliance Error at +2 μA vs. Output Voltage 60 PPMU OUTPUT CURRENT (mA) 0.4 50 0.3 ERROR (µA) 40 0.2 30 0.1 20 0 10 –0.1 –2 09530-164 –1 0 1 2 3 VDUT (V) 4 5 6 7 0 –3 –2 –1 0 1 3 2 VDUT (V) 4 5 6 7 Figure 71. PPMU Force Current Range B Compliance Error at +1 mA vs. Output Voltage Figure 74. PPMU Force Voltage Output Current Limit Range A, FV = −2.0 V, VDUT Swept −2.0 V to +6.5 V Rev. 0 | Page 41 of 80 09530-167 09530-166 09530-165 –5 –2 ADATE318 10 0 0.04 0.03 0.02 –10 –20 –30 –40 –50 09530-168 PPMU OUTPUT CURRENT (mA) LINEARITY ERROR (mV) 0.01 0 –0.01 –0.02 –0.03 –0.04 –0.05 –60 –3 –2 –1 0 1 2 VDUT (V) 3 4 5 6 7 –0.06 –2 –1 0 1 2 3 VDUT (V) 4 5 6 7 Figure 75. PPMU Force Voltage Output Current Limit Range A, FV = +6.5 V, VDUT Swept −2.0 V to +6.5 V 2.90 Figure 78. PPMU Range B Measure Voltage Linearity Error 0.12 0.10 0.08 2.85 PPMU OUTPUT CURRENT (µA) 2.80 LINEARITY ERROR (µA) 0.06 0.04 0.02 0 –0.02 –0.04 2.75 2.70 2.65 –3 –2 –1 0 1 3 2 VDUT (V) 4 5 6 7 –0.06 –1.0 –0.5 0 IDUT (mA) 0.5 1.0 Figure 76. PPMU Force Voltage Output Current Limit Range E, FV = −2.0 V, VDUT Swept −2.0 V to +6.5 V 3 2 Figure 79. PPMU Range B Measure Current Linearity Error 0.10 0.05 PPMU_MEAS0 PIN ERROR (mV) 1mV = ~400nA PPMU OUTPUT CURRENT (µA) 0 –0.05 –0.10 –0.15 –0.20 –0.25 –0.30 –0.35 –0.40 1 0 –1 –2 –3 09530-170 –4 –3 –2 –1 0 1 2 VDUT (V) 3 4 5 6 7 –1 0 1 2 VDUT (V) 3 4 5 6 Figure 77. PPMU Force Voltage Output Current Limit Range E, FV = 6.5 V, VDUT Swept −2.0 V to +6.5 V Figure 80. PPMU Measure Current CMR Error, (FVMI), Sourcing 0.5 mA Rev. 0 | Page 42 of 80 09530-173 –0.45 –2 09530-172 2.60 09530-169 09530-171 ADATE318 1.2 1.0 0.8 LINEARITY ERROR (mV) 2.0 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 09530-174 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –3 –2 –1 0 1 2 3 4 OUTPUT VOLTAGE (V) 5 6 7 LINEARITY ERROR (mV) 0 1 2 3 4 5 OUTPUT VOLTAGE (V) 6 7 Figure 81. Reflection Clamp VCL Linearity Error 0.5 0.4 0.3 LINEARITY ERROR (mV) 0 –10 –20 Figure 84. PPMU Voltage Clamp VCH Linearity Error OUTPUT CURRENT (mA) 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 09530-175 –30 –40 –50 –60 –70 –80 –90 –1 0 1 2 3 4 5 OUTPUT VOLTAGE (V) 6 7 8 –2 –1 0 1 2 VDUT (V) 3 4 5 6 Figure 82. Reflection Clamp VCH Linearity Error 2 1 Figure 85. VCL Reflection Clamp Current Limit; VCH = 6 V, VCL = 5 V, VDUT Swept −2.0 V to +5.0 V 90 80 70 LINEARITY ERROR (mV) OUTPUT CURRENT (mA) 0 –1 –2 –3 –4 –5 –3 60 50 40 30 20 10 09530-176 –2 –1 0 1 2 OUTPUT VOLTAGE (V) 3 4 5 0 1 2 3 4 VDUT (V) 5 6 7 8 Figure 83. PPMU Voltage Clamp VCL Linearity Error Figure 86. VCH Reflection Clamp Current Limit; VCH = 0 V, VCL = −2 V, VDUT Swept −2.0 V to +5.0 V Rev. 0 | Page 43 of 80 09530-179 0 09530-178 –0.5 –2 –100 –3 09530-177 –2.0 ADATE318 0 –20 –40 –60 100 90 RESOLUTION (0 TO 31) = ~ 3.0mV/BIT RESOLUTION (10 TO 31) = ~ 4.6mV/BIT MEASURED HYSTERESIS (mV) 80 70 60 50 40 30 20 10 VOL_HYSTERESIS VOH_HYSTERESIS 0 5 10 15 20 HYSTERESIS CODE 25 30 35 09530-208 09530-209 OFFSET (mV) –80 –100 –120 –140 –160 0 1 2 3 4 5 DRIVER CLC SETTING 3-BIT VALUE 6 7 09530-180 –180 0 Figure 87. Driver Offset Error vs. Driver CLC Setting 20 15 10 Figure 90. Normal Window Comparator Hysteresis Transfer Function 140 120 RESOLUTION (0 TO 31) = ~ 3.6mV/BIT RESOLUTION (10 TO 31) = ~ 5.6mV/BIT MEASURED HYSTERESIS (mV) 100 80 60 40 20 0 OFFSET (mV) 5 0 –5 –10 –15 09530-181 VOL_HYSTERESIS VOH_HYSTERESIS 0 5 10 15 20 HYSTERESIS CODE 25 30 35 –20 0 1 3 4 5 6 2 COMPARATOR CLC SETTING 3-BIT VALUE 7 Figure 88. Normal Window Comparator Offset Error vs. CLC Setting 20 15 10 Figure 91. Differential Comparator Hysteresis Transfer Function OFFSET (mV) 0 –5 –10 –15 09530-182 100mV/DIV 5 C1 –20 0 3 4 5 6 7 1 2 DIFFERENTIAL COMPARATOR CLC SETTING 3-BIT VALUE 1ns/DIV Figure 89. Differential Comparator Offset error vs. CLC Setting Figure 92. Driver Eye Diagram, 400 Mbps, PRBS31; VIH = 1 V, VIL = 0 V Rev. 0 | Page 44 of 80 09530-183 ADATE318 C1 100mV/DIV 200mV/DIV 09530-184 C1 500ps/DIV 200ps/DIV Figure 93. Driver Eye Diagram, 800 Mbps, PRBS31; VIH = 1 V, VIL = 0 V Figure 96. Driver Eye Diagram, 1600 Mbps, PRBS31; VIH = 2 V, VIL = 0 V 200mV/DIV 100mV/DIV C1 C1 09530-185 500ps/DIV 200ps/DIV Figure 94. Driver Eye Diagram, 800 Mbps, PRBS31; VIH = 2 V, VIL = 0 V Figure 97. Driver Eye Diagram, 2000 Mbps, PRBS31; VIH = 1 V, VIL = 0 V 100mV/DIV 200mV/DIV C1 C1 09530-186 200ps/DIV 200ps/DIV Figure 95. Driver Eye Diagram, 1600 Mbps, PRBS31; VIH = 1 V, VIL = 0 V Figure 98. Driver Eye Diagram, 2000 Mbps, PRBS31; VIH = 2 V, VIL = 0 V Rev. 0 | Page 45 of 80 09530-189 09530-188 09530-187 ADATE318 0.8 0.6 0.4 0.10 VOLTAGE (V) VOLTAGE (V) 0.16 0.14 0.12 CLC0 CLC3 CLC7 0.2 0 –0.2 –0.4 –0.6 –0.8 0.08 0.06 0.04 0.02 VIH TO HIGH-Z VIL TO HIGH-Z 0 –0.02 09530-195 0 5 10 TIME (µs) 15 20 0 2 4 6 8 10 12 TIME (ns) 14 16 18 20 Figure 99. Drive to/from High-Z Transition, VIH = 1 V, VIL = −1 V, 50 Ω Termination 100 80 60 40 VOLTAGE (mV) Figure 102. Driver 0.2 V Response vs. CLC Settings 0.8 20 0 –20 –40 –60 –80 VOLTAGE (V) VIL TO IOL VIL TO IOH VIH TO IOL VIH TO IOH IOL TO VIL IOL TO VIH IOH TO VIL IOH TO VIH 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 09530-210 CLC0 CLC3 CLC7 0 5 10 TIME (ns) 15 20 0 2 4 6 8 10 12 TIME (µs) 14 16 18 20 Figure 100. Drive to/from Active Load Transient, VIL = VIH = 0 V, IOH = IOL = 0 V 50 40 30 20 VOLTAGE (mV) VOLTAGE (V) Figure 103. Driver 1 V Response vs. CLC Settings 2.0 VIL TO HIZ VIH TO HIZ HIZ TO VIL HIZ TO VIH CLC0 CLC3 CLC7 1.5 10 0 –10 –20 –30 –40 09530-211 1.0 0.5 0 0 5 10 15 20 25 30 TIME (ns) 35 40 45 50 0 2 4 6 8 10 12 TIME (ns) 14 16 18 20 Figure 101. Drive to/from High-Z Transient, VIL = VIH = 0 V, 50 Ω Termination Figure 104. Driver 3 V Response vs. CLC Settings Rev. 0 | Page 46 of 80 09530-199 –50 –0.5 09530-198 –100 –0.2 09530-197 –0.04 ADATE318 6 5 4 4 6 5 VOLTAGE (V) 3 2 1 0 –1 RISE FALL VOLTAGE (V) 3 RISE FALL 2 1 09530-200 0 10 20 30 TIME (µs) 40 50 60 0 10 20 30 TIME (µs) 40 50 60 Figure 105. PPMU Transient Response, FI Range A, Full -Scale Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 120 Ω 2.0 Figure 108. PPMU Transient Response, FV Range A, 0 V to 5 V, Uncalibrated, CLOAD = 200 pF 0.6 1.5 0.5 0.4 VOLTAGE (V) 1.0 RISE FALL 0.5 VOLTAGE (V) 0.3 RISE FALL 0.2 0 0.1 09530-201 0 5 10 15 TIME (µs) 20 25 30 0 2 4 TIME (µs) 6 8 10 Figure 106. PPMU Transient Response, FI Range B, Full-Scale Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 1.5 kΩ 2.0 Figure 109. PPMU Transient Response, FV Range A, 0 V to 0.5 V, Uncalibrated, CLOAD = 200 pF 0.7 0.6 1.5 0.5 VOLTAGE (V) 1.0 RISE FALL 0.5 VOLTAGE (V) 0.4 0.3 0.2 0.1 0 RISE FALL 0 09530-202 0 10 20 30 TIME (µs) 40 50 60 0 5 10 TIME (µs) 15 20 Figure 107. PPMU Transient Response, FI Range C, Full-Scale Transition, Uncalibrated, CLOAD = 200 pF, RLOAD = 15 kΩ Figure 110. PPMU Transient Response, FV Range C, 0 V to 0.5 V, Uncalibrated, CLOAD = 200 pF Rev. 0 | Page 47 of 80 09530-205 –0.5 –0.1 09530-204 –0.5 0 09530-203 0 ADATE318 0.6 0.7 0.6 0.5 0.5 VOLTAGE (V) VOLTAGE (V) 0.4 0.4 0.3 0.2 0.1 0.3 RISE FALL 0.2 RISE FALL 0.1 0 09530-206 09530-207 0 0 2 4 TIME (µs) 6 8 10 –0.1 0 10 20 TIME (µs) 30 40 Figure 111. PPMU Transient Response, FV Range A, 0 V to 0.5 V, Uncalibrated, CLOAD = 2000 pF Figure 112. PPMU Transient Response, FV Range C, 0 V to 0.5 V, Uncalibrated, CLOAD = 2000 pF Rev. 0 | Page 48 of 80 ADATE318 SPI INTERCONNECT DETAILS ADATE318 (CHIP 0) ADATE318 (CHIP 1) ............ ADATE318 (CHIP x) SCLK SDI SDO BUSY CS SCLK SDI SDO BUSY CS SCLK SDI SDO BUSY CS SCLK SDI SDO BUSY CS[3:0] x NOTES 1. x ≤ 4. CSn CS0 CS1 Figure 113. Multiple SPI with Shared SDO Line Rev. 0 | Page 49 of 80 09530-003 ADATE318 USE OF THE SPI BUSY PIN After any valid SPI instruction is written to the ADATE318, the BUSY pin becomes asserted to indicate a busy status of the DAC update and calibration engines. The BUSY pin is an open drain type output capable of sinking a minimum of 5 mA from the VCC supply. Because it is an open drain type output, it can be wire-or’ed in common with many other similar open drain devices. In such cases, it is the user’s responsibility either to determine which device is indicating the busy state or, alternatively, to wait until all devices on the shared line become not busy. It is recommended that the BUSY pin be tied to VCC with an external 1 kΩ pull-up. It is not a requirement to wait for release of BUSY prior to a subsequent assertion of the CS pin. This is not the purpose of the BUSY pin. As long as the minimum number of SCLK cycles following the previous release of CS is met according to the tCSAM parameter, the CS pin can be asserted again for a subsequent SPI operation. With the one exception of recovery from a reset request (either by hardware assertion of the RST pin or a sofware setting of the internal SPI_RESET control bit), there is no scenario in normal operation of the ADATE318 in which the user must wait for release of BUSY prior to asserting the CS for another SPI operation. The only requirement on the assertion of CS is that the tCSAM parameter be defined as in Figure 4 and Table 13. It is very important, however, that the SCLK continue to operate for as long as the BUSY pin state remains active. This minimum period of time is defined by the tBUSW parameter (see Figure 4, Figure 6, Figure 7, and Table 18). If the SCLK does not remain active for at least the time specified by the tBUSW parameter, operations pending to the internal processor may not fully complete or, worse, they may complete in an incorrect fashion. In either case, a temporary malfunction of the ADATE318 may occur. After the ADATE318 releases the BUSY pin, the SCLK may again be stopped to prevent unwanted digital noise from coupling into the analog levels during normal operation of the Table 18. BUSY Minimum SCLK Cycle Requirements SPI Instruction Type Following the Release of the Asynchronous Reset Pin (Hardware Reset) Following Assertion of the SPI_RESET Control Bit (Software Reset) No Operation (NOP) Instruction Read Request to Any Valid ADATE318 Address and/or Channel (0x00 – 0x7F) Single/Double Channel Write Request to Any Valid ADATE318 Address ≥ 0x10 Single Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E) Double Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E) Single Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E) Double Channel Write Request to Any DAC (ADDR 0x01 – ADDR 0x0E) 1 pin electronics functions. In every case (with no exception for reset recovery), it is the purpose of the BUSY pin to notify the external test processor that it is again safe to stop the SCLK signal to the ADATE318. Running the SCLK for extra periods when BUSY is not active is never a problem except for the possibility of adding unwanted digital switching noise to the analog pin electronics circuitry as already noted. While the length of the BUSY period (tBUSW) is variable depending on the particular preceding SPI instruction, it is nevertheless deterministic. The parameter tBUSW depends only on factors such as whether the previous instruction involved a write to one or more DAC addresses and, if so, then how many channels were involved and whether or not the calibration function was enabled. Table 18 describes the precise length of the tBUSW period in units of rising edge SCLK cycles for each possible SPI instruction scenario as well as recovery from a hard RST reset. Because tBUSW is deterministic, it is therefore possible to predict in advance the minimum number of rising edge SCLK cycles required to complete any given SPI instruction. This makes it possible to operate the ADATE318 without a need to monitor the state of the BUSY pin. For applications in which it is neither possible nor desireable to monitor the pin, it is acceptable to use the information in Table 18 to guarantee that the minimum number of cycles is provided in lieu of monitoring BUSY following release of CS or reset. All DAC addresses have been assigned to the contiguous address block from 0x00 through 0x0F; therefore, it is possible to decode this information within the external test processor to provide a software indication that extra SCLK cycles may be required according to the scenarios listed in Table 18. All other operations not involving these addresses require only the standard number of clock cycles determined by tCSAM. As stated above, however, it is extremely important to honor the minimum number of required rising edge SCLK cycles as defined by tBUSW following the release of CS for each of the SPI instruction scenarios listed in Table 18 to ensure proper operation of the ADATE318. Calibration Engine 1 X X X X X Disabled Disabled Enabled Enabled Maximum tBUSW (SCLK Cycles) 64 64 3 3 3 10 16 20 26 X = don’t care. Rev. 0 | Page 50 of 80 ADATE318 RESET SEQUENCE AND THE RST PIN The internal state of the ADATE318 is indeterminate following power-up. For this reason, it is necessary to perform a complete reset sequence once the power supplies have stabilized. Further, the RST pin must be held in the asserted state before and during the power-up sequence and released only after all power supplies are known to be stable. The ADATE318 has an active low pin (RST) that asynchronously starts a reset sequence. A soft reset sequence can also be initiated under SPI software control by writing to the SPI_RESET bit in the SPI Control Register (SPI 0x12[0] (see Figure 13)). In the case of a soft reset, the sequence begins on the first rising edge of SCLK following the release of CS, subject to the normal setup and hold times. Certain actions take place immediately upon initiation of the reset request, whereas other actions require SCLK. The following asynchronous actions take place as soon as a reset request is detected, whether or not SCLK is active: • • • • • • Assert BUSY pin Force all control registers to the default reset state as defined by control register definitions Clear all calibration registers to the default reset state as defined by calibration register definitions Override all DAC output voltages and force analog levels to VDUTGND Disable DCLs and PPMUs; open system PMU switches Soft connect the DUT0 and DUT1 pins to VDUTGND (see Figure 114) CLAMPS DRIVER TO PPMU The part remains in this static reset state indefinitely until the clocked portion of the sequence begins with either the first rising edge of SCLK following the release of RST (asynchronous reset) or the second rising edge of SCLK following the release of CS (soft reset). No matter how the reset sequence is initiated, the clocked portion of the reset sequence requires 64 SCLK cycles to run to completion, and the BUSY pin remains asserted until these clock cycles have been received. The following actions take place during the clocked portion of the reset sequence: • • • Complete internal SPI controller initialization Write the appropriate values to specific DAC X2 registers (see Table 19) Enable the thermal alarm with a 100C threshold; disable PPMU and the overvoltage detect (OVD) alarms The 64th rising edge of SCLK releases BUSY and starts a selftimed DAC deglitch period of approximately 3 μs. DAC voltages begin to change once the deglitch circuits have timed out, and they then require an additional 10 μs to settle to their final values. Thus, a full reset sequence requires approximately 15 μs, comprising 1.28 μs (64 cycles × 20 ns) for the reset state machine, 3 μs for DAC deglitch, and another 10 μs for settling. 50Ω 10kΩ DUTx LOAD DUT PULLDOWNx ADDR 0x19[7] DUTGND DUT PULL-DOWN SWITCH DEFAULTS TO A CLOSED STATE IMMEDIATELY FOLLOWING AN ASSERT OF RST (FOR HARD RESET) OR AT THE FIRST RISING EDGE OF SCLK FOLLOWING THE SPI CS (FOR SOFT RESET). SEE DCL CONTROL REGISTER 0x19[7]. Figure 114. DUTx to VDUTGND Soft Connect Detail Rev. 0 | Page 51 of 80 09530-010 COMPARATORS ADATE318 SPI REGISTER DEFINITIONS AND MEMORY MAP SPI CLOCK INDEX SPI WORD INDEX 0 C1 1 C0 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 10 11 12 13 14 15 16 D9 17 D8 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 A0 R/W D15 D14 D13 D12 D11 D10 CH[1:0] CHANNEL SELECT 00 = NOP 01 = READ/WRITE CHANNEL 0 10 = READ/WRITE CHANNEL 1 11 = READ NOP 11 = WRITE CHANNEL 0 AND 1 ADDR[6:0] ADDRESS FIELD R/W READ/WRITE SELECT 0 = READ: THE CONTENTS OF REGISTER SPECIFIED BY ADDR[6:0] AND CH[1:0] ARE SHIFTED OUT ON THE SDO PIN DURING THE NEXT SPI INSTRUCTION CYCLE. 1 = WRITE: DATA[15:0] IS WRITTEN TO THE REGISTER SPECIFIED BY ADDR[6:0] AND CH[1:0]. 09530-011 DATA[15:0] DATA FIELD Figure 115. SPI Word Definition Table 19. SPI Register Memory Map CH[1:0]1, 2 XX CC CC CC CC CC CC CC CC CC CC 01 01 01 01 XX XX CC 01 XX 01 CC CC CC CC CC CC CC XX CC CC CC CC ADDR[6:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 to 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 R/W1 X R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W X X R/W R/W X R/W R/W R/W R/W R/W R/W R R/W X R/W R/W R/W R/W DATA[15:0]1, 3 XXXX DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD XXXX XXXX DDDD DDDD XXXX DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD XXXX DDDD DDDD DDDD DDDD Register Description No operation (NOP) VIH DAC level (reset value = 0.0 V) VIT/VCOM DAC level (reset value = 0.0 V) VIL DAC level (reset value = 0.0 V) VOH DAC level (reset value = +0.5 V)) VOL DAC level (reset value = −0.5 V) VCH DAC level (reset value = +7.5 V) VCL DAC level (reset value = −2.5 V) VIOH DAC level (reset value = 50 μA) VIOL DAC level (reset value = 50 μA) PPMU DAC level (reset value = 0.0 V) VHH DAC level (reset value = 0.0 V) OVDH DAC level (reset value = +7.5 V) OVDL DAC level (reset value = −2.5 V) Spare DAC level (reset value = 0.0 V) Reserved No operation (NOP) DAC control register SPI control register Reserved VHH control register DCL control register PPMU control register PPMU MEAS control register CMP control register ALARM mask register ALARM state register CLC control register No operation (NOP) VIH (driver) m-coefficient VIT (driver) m-coefficient VIL (driver) m-coefficient VOH (normal window comparator) m-coefficient Reset Value1 XXXX 0x4000 0x4000 0x4000 0x4CCC 0x3333 0xFFFF 0x0000 0x4040 0x4040 0x4000 0x2666 0xFFFF 0x0000 0x4000 XXXX XXXX 0x0000 0x0000 XXXX 0x0000 0x0080 0x0000 0x0000 0x07FE 0x0045 0x0000 0x0000 XXXX 0xFFFF 0xFFFF 0xFFFF 0xFFFF Rev. 0 | Page 52 of 80 ADATE318 CH[1:0] 1 , 2 CC CC CC CC CC CC 01 01 01 01 XX XX CC CC CC CC CC CC CC CC CC CC 01 01 01 01 XX XX 01 CC 01 01 CC CC CC CC CC CC 01 CC CC CC CC CC CC CC CC CC CC CC CC CC 01 CC 01 01 CC ADDR[6:0] 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D R/W1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W X X R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W X X R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DATA[15:0]1, 3 DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD XXXX XXXX DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD XXXX XXXX DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD DDDD Register Description VOL (normal window comparator) m-coefficient VCH (reflection clamp) m-coefficient VCL (reflection clamp) m-coefficient VIOH (active load) m-coefficient VIOL (active load) m-coefficient PPMU (PPMU force-voltage) m-coefficient VHH (HVOUT) m-coefficient OVDH (overvoltage) m-coefficient OVDL (overvoltage) m-coefficient Spare DAC m-coefficient Reserved No operation (NOP) VIH (driver) c-coefficient VIT (driver) c-coefficient VIL (driver) c-coefficient VOH (normal window comparator) c-coefficient VOL (normal window comparator) c-coefficient VCH (reflection clamp) c-coefficient VCL (reflection clamp) c-coefficient VIOH (active load) c-coefficient VIOL (active load) c-coefficient PPMU (PPMU force voltage) c-coefficient VHH (HVOUT) c-coefficient OVDH (overvoltage) c-coefficient OVDL (overvoltage) c-coefficient Spare DAC c-coefficient Reserved No operation (NOP) VIH (HVOUT) m-coefficient VCOM (active load) m-coefficient VIL (HVOUT) m-coefficient VOH (differential comparator) m-coefficient VOH (PPMU measure voltage) m-coefficient VOH (PPMU measure current, Range A) m-coefficient VOH (PPMU measure current Range B) m-coefficient VOH (PPMU measure current, Range C) m-coefficient VOH (PPMU measure current, Range D) m-coefficient VOH (PPMU measure current, Range E) m-coefficient VOL (differential comparator) m-coefficient VOL (PPMU measure voltage) m-coefficient VOL (PPMU measure current, Range A) m-coefficient VOL (PPMU measure current, Range B) m-coefficient VOL (PPMU measure current, Range C) m-coefficient VOL (PPMU measure current, Range D) m-coefficient VOL (PPMU measure current, Range E) m-coefficient VCH (PPMU) m-coefficient VCL (PPMU) m-coefficient PPMU force current, Range A m-coefficient PPMU force current, Range B m-coefficient PPMU force current, Range C m-coefficient PPMU force current Range D m-coefficient PPMU force current, Range E m-coefficient VIH (HVOUT) c-coefficient VCOM (active load) c-coefficient VIL (HVOUT) c-coefficient VOH (differential comparator) c-coefficient VOH (PPMU measure voltage) c-coefficient Reset Value1 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF XXXX XXXX 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 0x8000 XXXX XXXX 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0x8000 0x8000 0x8000 0x8000 0x8000 Rev. 0 | Page 53 of 80 ADATE318 CH[1:0] 1 , 2 CC XX 01 CC CC XX CC CC CC XX 1 2 ADDR[6:0] 0x5E 0x5F to 0x62 0x63 0x64 0x65 0x66 to 0x69 0x6A 0x6B 0x6C 0x6D to 0x70 R/W1 R/W X R/W R/W R/W X R/W R/W R/W X DATA[15:0]1, 3 DDDD XXXX DDDD DDDD DDDD XXXX DDDD DDDD DDDD XXXX Register Description VOH (PPMU measure current) c-coefficient Reserved VOL (differential comparator) c-coefficient VOL (PPMU measure voltage) c-coefficient VOL (PPMU measure current) c-coefficient Reserved VCH (PPMU) c-coefficient VCL (PPMU) c-coefficient PPMU force current c-coefficient Reserved Reset Value1 0x8000 XXXX 0x8000 0x8000 0x8000 XXXX 0x8000 0x8000 0x8000 XXXX X = don’t care. CC corresponds to the channel address bits and indicates that there is dedicated register space for each channel. 3 DDDD stands for data. Rev. 0 | Page 54 of 80 ADATE318 CONTROL REGISTER DETAILS Reserved bits in any register are undefined. In some cases, a physical (but unused) memory bit may be present, in other cases not. Write operations have no effect. Read operations result in meaningless but deterministic data. Any SPI read operation from any reserved bit or register results in an unknown but deterministic readback value. Any SPI write operation to a control bit or control register defined only on Channel 0 must be addressed to at least Channel 0. Any such write that is addressed only to Channel 1 is ignored. Further, any such write that is addressed to both Channel 0 and Channel 1 (as a multichannel write) proceeds as if the write were addressed only to Channel 0. The data addressed to the undefined Channel 1 control bit or control register is ignored. 14 15 16 D9 17 D8 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 SPI CLOCK INDEX DATA-WORD INDEX 10 11 12 13 D15 D14 D13 D12 D11 D10 RESERVED[15:3] RESERVED DAC_LOAD[2] DAC LOAD SOFT PIN, SELF-RESETTING, CHANNEL 0/CHANNEL 1 [0] = DEFAULT STATE OF THE DAC_LOAD SOFT PIN 1 = BEGIN DAC LOAD OPERATION (PULSE, SELF-CLEAR TO ZERO) A WRITE TO THIS BIT PARALLEL UPDATES ALL DACs OF CHANNEL x WITH PREVIOUSLY BUFFERED DATA ASSUMING THAT THE DAC_LOAD_MODE CONTROL BIT OF CHANNEL x IS NOT SET TO WRITE DAC IMMEDIATE MODE. THIS BIT AUTOMATICALLY SELF-CLEARS. DAC_LOAD_MODE[1] DAC LOAD MODE, CHANNEL 0/CHANNEL 1 [0] = WRITE DAC IMMEDIATE MODE. 1 = WRITE DAC DEFERRED MODE. IN WRITE DAC IMMEDIATE MODE, EACH RESPECTIVE DAC IS UPDATED IMMEDIATELY SUBSEQUENT TO A VALID SPI WRITE INSTRUCTION TO THAT DAC ADDRESS. IN WRITE DAC DEFERRED MODE, EACH VALID SPI WRITE TO A DAC ADDRESS IS BUFFERED, AND DACs ARE ONLY UPDATED FOLLOWING ASSERTION OF THE DAC_LOAD SOFT PIN. IN THIS MODE, ALL ANALOG DAC DATA FOR EITHER OR BOTH CHANNELS CAN BE UPDATED IN PARALLEL. DAC_CAL_ENABLE[0] DAC CALIBRATION ENGINE ENABLE, CHANNEL 0 ONLY [0] = CALIBRATION ENGINE IS DISABLED 1 = CALIBRATION ENGINE IS ENABLED WHEN DAC CALIBRATION IS ENABLED, EACH WRITE TO A VALID DAC ADDRESS RESULTS IN A SUBSEQUENT MULTIPLY AND ACCUMULATE (MAC) OPERATION TO THE DATA FOR THE RESPECTIVE DAC USING CALIBRATION DATA CONTAINED IN THE APPROPRIATE m- AND cCOEFFICIENT REGISTERS. WHEN THE CALIBRATION ENGINE IS DISABLED, DATA WRITTEN TO A VALID DAC ADDRESS IS NOT MODIFIED BY THE ON-CHIP CALIBRATION COEFFICIENTS. Figure 116. DAC Control Register (ADDR = 0x11) Rev. 0 | Page 55 of 80 09530-012 ADATE318 SPI CLOCK INDEX DATA-WORD INDEX 10 11 12 13 14 15 16 D9 17 D8 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 D15 D14 D13 D12 D11 D10 RESERVED[15:2] RESERVED SPI_SDO_HIZ[1] SPI SERIAL DATA OUTPUT PIN, HIGH-Z CONTROL, CHANNEL 0 ONLY [0] = SDO PIN IS ALWAYS ACTIVE, INDEPENDENT OF THE CS INPUT. 1 = SDO PIN IS ACTIVE ONLY WHEN CS IS ACTIVE, OTHERWISE HIGH-Z. SPI_RESET[0] SPI SOFTWARE RESET, CHANNEL 0 ONLY [0] = DEFAULT SETTING, NO ACTION IS TAKEN UNTIL A 1 IS WRITTEN. 1 = RESET (PULSE, SELF-CLEAR TO ZERO). FOLLOWING A WRITE TO SET THIS BIT, THE ADATE318 BEGINS A FULL RESET SEQUENCE JUST AS IF THE RST PIN HAD BEEN ASSERTED ASYNCHRONOUSLY. FOLLOWING RESET THIS BIT SELF-CLEARS TO THE DEFAULT 0 CONDITION. Figure 117. SPI Control Register (ADDR = 0x12) SPI CLOCK INDEX DATA-WORD INDEX 10 11 12 13 14 15 16 D9 17 D8 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 D15 D14 D13 D12 D11 D10 RESERVED[15:1] RESERVED VHH_ENABLE[0] VHH (HVOUT) ENABLE, CHANNEL 0 ONLY [0] = HVOUT PIN IS DISABLED. 1 = HVOUT PIN IS ENABLED. WHEN VHH MODE IS ENABLED, THE HVOUT PIN IS SET TO THE LEVELS ACCORDING TO THE VHH AND VIH/VIL DRIVER TRUTH TABLE (TABLE 25). WHEN VHH MODE IS DISABLED, THE IMPEDANCE OF THE HVOUT PIN IS APPROXIMATELY 50Ω TO VDUTGND. Figure 118. VHH Control Register (ADDR = 0x18) Active Truth Table Rev. 0 | Page 56 of 80 09530-014 09530-013 ADATE318 SPI CLOCK INDEX DATA-WORD INDEX 10 11 12 13 14 15 16 D9 17 D8 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 D15 D14 D13 D12 D11 D10 RESERVED[15:8] RESERVED DUT_PULLDOWN_x[7] DUTx PIN 10K SOFT PULL-DOWN, CHANNEL 0/CHANNEL 1 0 = HVOUT PIN IS DISABLED. [1] = DUTx PIN HAS 10kΩ PULL-DOWN TO DUTGND. WHEN DUT_PULLDOWN IS ASSERTED, THE DUTx PIN ON CHANNEL x HAS A 10kΩ PULL-DOWN TO DUTGND. THIS CONTROL BIT IS ASYNCHRONOUSLY SET AT THE BEGINNING OF ANY RESET OPERATION, AND IT REMAINS SET UNTIL CLEARED BY THE USER. THIS CONTROL BIT DOES NOT DEPEND ON OTHER CONTROL BITS IN THIS REGISTER. DRIVE_VT_HIZ_x[6] DRIVER VT/HiZ MODE SELECT, CHANNEL 0/CHANNEL 1 [0] = DRIVER GOES TO HIGH-Z STATE WHEN RCVx = 1. 1 = DRIVER GOES TO VIT STATE WHEN RCVx = 1. WHEN DRV_VT_HIZ IS ASSERTED, THE DRIVER ON CHANNEL x ASSUMES THE VIT LEVEL ON ASSERTION OF THE RCVx HIGH SPEED INPUT IN ACCORDANCE WITH THE DRIVER TRUTH TABLE. THIS CONTROL BIT IS SUBORDINATE TO THE DCL_ENABLE AND FORCE_DRIVE CONTROL BITS. LOAD_ENABLE_x[5] ACTIVE LOAD ENABLE, CHANNEL 0/CHANNEL 1 [0] = ACTIVE LOAD IS DISABLED AND POWERED DOWN. 1 = ACTIVE LOAD IS ENABLED. WHEN LOAD_ENABLE IS ASSERTED, THE ACTIVE LOAD ON CHANNEL x IS ENABLED AND CONNECTS TO THE DUTx PIN ON ASSERTION OF THE RCVn HIGH SPEED INPUT IN ACCORDANCE WITH THE ACTIVE LOAD TRUTH TABLE. THIS CONTROL BIT IS SUBORDINATE TO THE DCL_ENABLE AND FORCE_LOAD CONTROL BITS BUT TAKES PRECEDENCE OVER THE RCVn HIGH SPEED INPUTS. FORCE_DRIVE_STATE_x[4:3] DRIVER STATE WHEN FORCE_DRIVE, CHANNEL 0/CHANNEL 1 [00] = FORCE DRIVE VIL STATE. 01 = FORCE DRIVE VIH STATE. 10 = FORCE DRIVE HIGH-Z STATE. 11 = FORCE DRIVE VIT STATE. WHEN THE FORCE_DRIVE CONTROL BIT IS ACTIVE, THE DRIVER ON CHANNEL x ASSUMES THE INDICATED STATE IN ACCORDANCE WITH THE DRIVER TRUTH TABLE. FORCE_LOAD_x[2] FORCE ACTIVE LOAD TO ACTIVE ON STATE, CHANNEL 0/CHANNEL 1 [0] = ACTIVE LOAD RESPONDS TO RCVx. 1 = FORCE ACTIVE ON STATE. WHEN FORCE_LOAD IS ASSERTED, THE ACTIVE LOAD ON CHANNEL x ASSUMES THE ACTIVE ON STATE AND IS CONNECTED TO THE DUTx PIN IN ACCORDANCE WITH THE ACTIVE LOAD TRUTH TABLE. THIS CONTROL BIT IS SUBORDINATE TO THE DCL_ENABLE CONTROL BIT BUT TAKES PRECEDENCE OVER BOTH THE LOAD_ENABLE AND DRV_VT_HIZ CONTROL BITS, AS WELL AS THE RCVx INPUTS. THIS BIT DOES NOT FORCE SELECTION OF VCOM CALIBRATION CONSTANTS. FORCE_DRIVE_x[1] FORCE DRIVER TO FORCE_STATE, CHANNEL 0/CHANNEL 1 [0] = DRIVER RESPONDS TO DATx AND RCVx. 1 = FORCE DRIVER STATE TO FORCE_STATE. WHEN FORCE_DRIVE IS ASSERTED, THE DRIVER ON CHANNEL x ASSUMES THE STATE INDICATED BY FORCE_STATE IN ACCORDANCE WITH THE DRIVER TRUTH TABLE. THIS CONTROL BIT IS SUBORDINATE TO THE DCL_ENABLE CONTROL BIT BUT TAKES PRECEDENCE OVER DRV_VT_HIZ, AS WELL AS THE DATx AND RCVx INPUTS. THIS BIT DOES NOT FORCE SELECTION OF VCH AND VCL CALIBRATION CONSTANTS NOR DOES IT FORCE SELECTION OF VIT CALIBRATION CONSTANTS. DCL_ENABLE_x[0] ENABLE DCL ON CHANNEL 0/CHANNEL 1 [0] = DCL IS DISABLED (LOW LEAKAGE MODE). 1 = DCL IS ENABLED. WHEN DCL_ENABLE IS NOT ASSERTED, THE DRIVER, COMPARATOR, AND ACTIVE LOAD ON CHANNEL x ASSUME THE LOW LEAKAGE STATE IN ACCORDANCE WITH DRIVER AND ACTIVE LOAD TRUTH TABLES. THIS CONTROL BIT TAKES PRECEDENCE OVER ALL OTHER CONTROL BITS IN THE DCL CONTROL REGISTER EXCEPT FOR DUT_PULLDOWN. Figure 119. DCL Control Register (ADDR = 0x19) Rev. 0 | Page 57 of 80 09530-015 ADATE318 SPI CLOCK INDEX DATA-WORD INDEX 10 11 12 13 14 15 16 D9 17 D8 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 D15 D14 D13 D12 D11 D10 PPMU_POWER_x[15] PPMU POWER, CHANNEL 0/CHANNEL 1 [0] = PPMU POWER OFF. 1 = PPMU POWER ON. WHEN PPMU_POWER_x[15] = 1, THE NWC AND DMC HYSTERESIS IS FORCED TO A MAXIMUM, BUT THE HYSTERESIS REGISTER VALUES ARE LEFT UNCHANGED. RESERVED[14:12] RESERVED PMU_S_ENABLE_x[11] PMU SENSE INPUT ENABLE, CHANNEL 0/CHANNEL 1 [0] = PMU SENSE INPUT SWITCH OPEN. 1 = PMU SENSE INPUT SWITCH CLOSED. RESERVED PPMU_CLAMP_ENABLE_x[9] PPMU CLAMP ENABLE, CHANNEL 0/CHANNEL 1 [0] = PPMU CLAMPS DISABLED. 1 = PPMU CLAMPS ENABLED. PPMU_SENSE_PATH_x[8] PPMU SENSE PATH, CHANNEL 0/CHANNEL 1 [0] = PPMU INTERNAL SENSE PATH. 1 = PPMU EXTERNAL SENSE PATH. PPMU_INPUT_SEL_x[7:6] PPMU INPUT SELECT, CHANNEL 0/CHANNEL 1 [00] = PPMU INPUT FROM DUTGND. 01 = PPMU INPUT FROM DUTGND + 2.5V. 1X = PPMU INPUT FROM DACPPMU LEVEL. PPMU_MEAS_VI_x[5] PPMU MEASURE V OR MEASURE I, CHANNEL 0/CHANNEL 1 [0] = PPMU MEASURE V MODE. 1 = PPMU MEASURE I MODE. PPMU_FORCE_VI_x[4] PPMU FORCE V OR FORCE I, CHANNEL 0/CHANNEL 1 [0] = PPMU FORCE V MODE. 1 = PPMU FORCE I MODE. PPMU_RANGE_x[3:1] PPMU RANGE, CHANNEL 0/CHANNEL 1 [0XX] = PPMU RANGE E (2µA). 100 = PPMU RANGE D (10µA). 101 = PPMU RANGE C (100µA). 110 = PPMU RANGE B (1mA). 111 = PPMU RANGE A (40mA). PPMU_ENABLE_x[0] PPMU ENABLE, CHANNEL 0/CHANNEL 1 [0] = PPMU FULL POWER STANDBY. 1 = PPMU ACTIVE. Figure 120. PPMU Control Register (ADDR = 0x1A) Rev. 0 | Page 58 of 80 09530-016 ADATE318 SPI CLOCK INDEX DATA-WORD INDEX 10 11 12 13 14 15 16 D9 17 D8 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 D15 D14 D13 D12 D11 D10 RESERVED[15:3] RESERVED PPMU_MEAS_SEL_x[2:1] PPMU ANALOG MEASURE OUT PIN SELECT, CHANNEL 0/CHANNEL 1 [X0] = PPMU CHANNEL x TO PPMU_MEASx OUTPUT PIN. X1 = CHANNEL 0: TEMPERATURE SENSOR OUTPUT (THERM). CHANNEL 1: TEMPERATURE SENSOR GND REFERENCE. PPMU_MEAS_ENABLE_x[0] PPMU ANALOG MEASURE OUT PIN ENABLE, CHANNEL 0/CHANNEL 1 [0] = PPMU MEASURE OUT PIN ON CHANNEL x IS DISABLED, HIGH-Z. 1 = PPMU MEASURE OUT PIN ON CHANNEL x IS ENABLED. Figure 121. PPMU MEAS Control Register (ADDR = 0x1B) SPI CLOCK INDEX DATA-WORD INDEX 10 11 12 13 14 15 16 D9 17 D8 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 D15 D14 D13 D12 D11 D10 RESERVED[15:11] RESERVED NWC_HYST_x[10:6] NORMAL WINDOW COMPARATOR HYSTERESIS VALUE, CHANNEL 0/CHANNEL 1 0x00 = DISABLE HYSTERESIS. 0x01 = ENABLE MINIMUM HYSTERESIS. [0x1F] = ENABLE MAXIMUM HYSTERESIS. WHEN SET TO 0x00, THE NORMAL WINDOW COMPARATOR ON CHANNEL x HAS NO HYSTERESIS ADDED TO THE INPUT STAGE. WHEN SET TO A VALUE OTHER THAN 0x00, HYSTERESIS IS ADDED AND THE AMOUNT IS CONTROLLED BY THE VALUE IN THIS REGISTER. WHEN ADDR 0x1A PPMU _POWER_x[15] = 1, THE NWC HYSTERESIS IS FORCED TO A MAXIMUM, BUT THE HYSTERESIS REGISTER VALUE IS LEFT UNCHANGED. DMC_HYST[5:1] DIFFERENTIAL COMPARATOR HYSTERESIS VALUE, CHANNEL 0 ONLY 0x00 = DISABLE HYSTERESIS. 0x01 = ENABLE MINIMUM HYSTERESIS. [0x1F] = ENABLE MAXIMUM HYSTERESIS. WHEN SET TO 0x00, THE DIFFERENTIAL COMPARATOR ON CHANNEL 0 HAS NO HYSTERESIS ADDED TO THE INPUT STAGE. WHEN SET TO A VALUE OTHER THAN 0x00, HYSTERESIS IS ADDED AND THE AMOUNT IS CONTROLLED BY THE VALUE IN THIS REGISTER. WHEN ADDR 0x1A PPMU _POWER_x[15] = 1, THE DMC HYSTERESIS IS FORCED TO A MAXIMUM, BUT THE HYSTERESIS REGISTER VALUE IS LEFT UNCHANGED. DMC_ENABLE[0] DIFFERENTIAL MODE COMPARATOR ENABLE, CHANNEL 0 ONLY [0] = DISABLE DIFFERENTIAL MODE COMPARATOR. 1 = ENABLE DIFFERENTIAL MODE COMPARATOR. WHEN DMC_ENABLE IS ASSERTED, THE NORMAL WINDOW COMPARATOR ON CHANNEL 0 IS DISABLED, THE DIFFERENTIAL MODE COMPARATOR ON CHANNEL 0 IS ENABLED, AND ITS OUTPUTS GOES TO THE CMPH0 AND CMPL0 HIGH SPEED OUTPUT PINS. THE OPERATION OF THE NORMAL WINDOW COMPARATOR ON CHANNEL 1 IS NOT AFFECTED. THIS CONTROL BIT EXISTS AT ADDR 0x1C CHANNEL 0 ONLY. Figure 122. CMP Control Register (ADDR = 0x1C) Rev. 0 | Page 59 of 80 09530-018 09530-017 ADATE318 SPI CLOCK INDEX DATA-WORD INDEX 10 11 12 13 14 15 16 D9 17 D8 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 D15 D14 D13 D12 D11 D10 RESERVED[15:7] RESERVED THERM_ALARM_THRESH[6:4] THERMAL ALARM THRESHOLD, CHANNEL 0 ONLY 000 = 0°C (FOR TEST USE ONLY) 001 = 25°C 010 = 50°C 011 = 75°C [100] = 100°C 101 = 125°C 110 = 150°C 111 = 175°C THERM_ALARM_MASK[3] THERMAL ALARM MASK BIT, CHANNEL 0 ONLY [0] = THERMAL ALARM ENABLED. 1 = THERMAL ALARM DISABLED. WHEN THE THERMAL ALARM IS ENABLED, A TEMPERATURE SENSOR READING ABOVE THE THRESHOLD SPECIFIED BY THERM_ALARM_THRESH ASSERTS AND LATCHES THE ALARM OPEN DRAIN OUTPUT PIN. PPMU_ALARM_MASK_x[2] PPMU CLAMP ALARM MASK, CHANNEL 0/CHANNEL 1 0 = PPMU CLAMP ALARM ENABLED. [1] = PPMU CLAMP ALARM DISABLED. WHEN THE PPMU CLAMP IS ENABLED, A CLAMP CONDITION ON CHANNEL x PPMU CLAMPS ASSERTS AND LATCHES THE ALARM OPEN DRAIN OUTPUT PIN. THE PPMU CLAMP LEVELS ARE DEFINED BY THE VCL AND VCH DAC REGISTERS. RESERVED[1] RESERVED OVD_ALARM_MASK_n[0] OVERVOLTAGE DETECTOR ALARM MASK, CHANNEL 0/CHANNEL 1 0 = OVERVOLTAGE ALARM ENABLED. [1] = OVERVOLTAGE ALARM DISABLED. WHEN THE OVD ALARM IS ENABLED, AN OVERVOLTAGE FAULT CONDITION ON DUTx ASSERTS AND LATCHES THE ALARM OPEN DRAIN OUTPUT PIN. THE OVERVOLTAGE THRESHOLDS ARE DEFINED BY THE OVDH AND OVDL DAC REGISITERS. Figure 123. Alarm Mask Register (ADDR = 0x1D) Rev. 0 | Page 60 of 80 09530-019 ADATE318 SPI CLOCK INDEX DATA-WORD INDEX 10 11 12 13 14 15 16 D9 17 D8 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 D15 D14 D13 D12 D11 D10 RESERVED[15:4] RESERVED THERM_ALARM_FLAG[3] THERMAL ALARM FLAG, CHANNEL 0 ONLY [0] = THERMAL FAULT NOT DETECTED. 1 = THERMAL FAULT DETECTED. WHEN THE THERM_ALARM_FLAG BIT IS SET, A FAULT WAS DETECTED ON THE DIE ACCORDING TO THE THERMAL THRESHOLD SET IN THE THERM_ALARM_THRESH REGISTER. THIS FLAG IS SUBORDINATE TO THE THERM_ALARM_MASK CONTROL BIT, AND IT IS AUTOMATICALLY RESET AFTER ANY READ FROM THE ALARM STATE REGISTER. PPMU_ALARM_FLAG_x[2] PPMU CLAMP ALARM FLAG, CHANNEL 0/CHANNEL 1 [0] = PPMU CLAMP CONDITION NOT DETECTED. 1 = PPMU CLAMP CONDITION DETECTED. WHEN THE PPMU_ALARM_FLAG BIT IS SET, A PPMU CLAMP CONDITION WAS DETECTED ON CHANNEL x ACCORDING TO THE THRESHOLDS SET IN THE VCH AND VCL CLAMP REGISTERS. THIS FLAG IS SUBORDINATE TO THE PPMU_ALARM_MASK_x CONTROL BIT, AND IT AUTOMATICALLY RESETS AFTER ANY READ FROM THE ALARM STATE REGISTER. OVDH_ALARM_FLAG_x[1] OVER VOLTAGE ALARM FLAG, CHANNEL 0/CHANNEL 1 [0] = OVER VOLTAGE FAULT NOT DETECTED. 1 = OVER VOLTAGE FAULT DETECTED. WHEN OVDH_ALARM_FLAG IS SET, AN OVER VOLTAGE FAULT CONDITION WAS DETECTED ON CHANNEL x DUTx PIN ACCORDING TO THE THRESHOLD SET IN THE OVDH DAC REGISTER. THIS FLAG IS SUBORDINATE TO THE OVD_ALARM_MASK_x CONTROL BIT, AND IT IS AUTOMATICALLY RESET AFTER ANY READ FROM THE ALARM STATE REGISTER. OVDL_ALARM_FLAG_x[0] UNDER VOLTAGE ALARM FLAG, CHANNEL 0/CHANNEL 1 [0] = UNDER VOLTAGE FAULT NOT DETECTED. 1 = UNDER VOLTAGE FAULT DETECTED. WHEN OVDL_ALARM_FLAG IS SET, AN UNDER VOLTAGE FAULT CONDITION WAS DETECTED ON CHANNEL x DUTx PIN ACCORDING TO THE THRESHOLD SET IN THE OVDL DAC REGISTER. THIS FLAG IS SUBORDINATE TO THE OVD_ALARM_MASK_x CONTROL BIT, AND IT IS AUTOMATICALLY RESET AFTER ANY READ FROM THE ALARM STATE REGISTER. Figure 124. Alarm State Register (ADDR = 0x1E) (Read Only) Rev. 0 | Page 61 of 80 09530-020 ADATE318 SPI CLOCK INDEX DATA-WORD INDEX 10 11 12 13 14 15 16 D9 17 D8 18 D7 19 D6 20 D5 21 D4 22 D3 23 D2 24 D1 25 D0 D15 D14 D13 D12 D11 D10 DRV_CLC_x[15:13] DRIVER CABLE LOSS COMPENSATION, CHANNEL 0/CHANNEL 1 [000] = DISABLE DRIVER CLC. 001 = ENABLE DRIVER MINIMUM CLC. 111 = ENABLE DRIVER MAXIMUM CLC. WHEN SET TO 0x00, THE DRIVER ON CHANNEL x HAS ZERO CABLE LOSS COMPENSATION (CLC) ADDED TO ITS OUTPUT CHARACTERISTIC. WHEN SET TO A VALUE OTHER THAN 0x00, CABLE LOSS COMPENSATION PRE-EMPHASIS IS ADDED AND THE PERCENTAGE IS CONTROLLED BY THE REGISTER VALUE. RESERVED[12:11] RESERVED NWC_CLC_x[10:8] NORMAL WINDOW COMPARATOR CABLE LOSS COMPENSATION, CHANNEL 0/CHANNEL 1 [000] = DISABLE NWC CLC. 001 = ENABLE NWC MINIMUM CLC. 111 = ENABLE NWC MAXIMUM CLC. WHEN SET TO 0x00, THE NORMAL WINDOW COMPARATOR (NWC) ON CHANNEL x HAS NO CABLE LOSS COMPENSATION (CLC) ADDED TO THE INPUT ADDED TO THE INPUT WAVEFORM CHARACTERISTIC. WHEN SET TO A VALUE OTHER THAN 0x00, PRE-EMPHASIS IS ADDED AND THE PERCENTAGE IS CONTROLLED BY THE VALUE IN THIS REGISTER. RESERVED[7:6] RESERVED DMC_CLC[5:3] DIFFERENTIAL MODE COMPARATOR CABLE LOSS COMPENSATION, CHANNEL 0 ONLY [000] = DISABLE DMC CLC. 001 = ENABLE DMC MINIMUM CLC. 111 = ENABLE DMC MAXIMUM CLC. WHEN SET TO 0x00, THE DIFFERENTIAL MODE COMPARATOR (ON CHANNEL 0 ONLY) HAS NO CABLE LOSS COMPENSATION (CLC) ADDED TO THE INPUT WAVEFORM CHARACTERISTIC. WHEN SET TO A VALUE OTHER THAN 0x00, PRE-EMPHASIS IS ADDED AND THE PERCENTAGE IS CONTROLLED BY THE VALUE IN THIS REGISTER. RESERVED[2:0] RESERVED 09530-021 Figure 125. CLC Control Register (ADDR = 0x1F) Rev. 0 | Page 62 of 80 ADATE318 LEVEL SETTING DACS DAC UPDATE MODES The ADATE318 provides 24- × 16-bit integrated level setting DACs organized as two channel banks of 12 DACs each. The detailed mapping of the DAC register to pin electronics function is shown in Table 19. Each DAC can be programmed by writing data to the respective SPI register address and channel. The ADATE318 provides two methods for updating analog DAC levels: DAC immediate update mode and DAC deferred update mode. At release of the CS pin associated with any valid SPI write to a DAC address, the update of analog levels may start immediately 1 , or it can be deferred, depending on the state of the DAC_LOAD_MODE control bits in the DAC control register (SPI ADDR 0x11[1] (see Figure 116)). The DAC update mode can be selected independently for each channel bank. If the DAC_LOAD_MODE control bit for a given channel bank is cleared, the DACs assigned to that channel are then in the DAC immediate update mode. Writing to any DAC of that channel causes the corresponding analog level to be updated immediately following the associated release of CS. Because all analog levels are updated on a per-channel basis, any previously pending DAC writes queued to the channel (while in deferred update mode) are also updated at this time. This situation can arise if DAC writes are queued to the channel while in deferred update mode, and the DAC_LOAD_MODE bit is subsequently changed to immediate update mode before the analog levels are updated by writing to the respective DAC_LOAD soft pin. The queued data is not lost. Note that writing to the DAC_LOAD soft pin has no effect in immediate update mode. If the DAC_LOAD_MODE control bit for a given channel is set, the DACs assigned to that channel are in the deferred update mode. Writing to any DAC of that channel only queues the DAC data into that channel. The analog update of queued DAC levels is deferred until the respective DAC_LOAD soft pin is set (SPI ADDR 0x11[2] (see Figure 116)). The DAC deferred update mode, in conjunction with the respective DAC_LOAD soft pin, provides the means to queue all DAC level writes to a given channel bank before synchronously updating the analog levels with a single SPI command. Certain pin electronics functions, such as VHH, OVDH, OVDL, and the spare DAC, do not fit neatly within a particular channel bank. However, they must be updated as a part of the channel bank to which they are assigned as shown in Table 19. The ADATE318 provides a feature in which a single SPI write operation can address two channels at one time (see Figure 115). This feature makes possible a scenario in which a SPI write 1 operation can address corresponding DACs on both channels at the same time even though the channels may be configured with different DAC update modes. In such a case, the part behaves as expected. For example, if both channels are in immediate update mode, the update of analog levels of both channel banks begins after the associated release of the CS pin. If both channels are in deferred update mode, the update of analog levels is deferred for both channels until the corresponding DAC_LOAD bits are set. If one channel is in deferred update mode and the other channel is in immediate update mode, the former channel defers analog updates until the corresponding DAC_LOAD bit is written, and the latter channel begins analog updates immediately after the associated release of the CS pin. An on-chip deglitch circuit with a period of approximately 3 μs is provided to prevent DAC-to-DAC crosstalk whenever an analog update is processed. Only one deglitch circuit is provided per chip, and it must operate over all physical DACs (both channels) at the same time. The deglitch circuit can be retriggered when an analog levels update is initiated before a previous update operation has completed. In the case of a dualchannel immediate mode DAC write using a single SPI command, the deglitch circuit is triggered once after data is loaded into both DAC channels. Analog transitions at the DAC outputs do not begin until the deglitch circuit has timed out, and final settling to full precision requires an additional 7 μs beyond the end of the 3 μs deglitch interval. Total settling time following release of the associated CS is approximately 10 μs. Note that prolonged and consecutive retriggering of the deglitch circuit by one channel may cause the apparent settling time of analog levels on the other channel to be much longer than the specified 10 μs. A typical DAC update sequence is illustrated in Figure 126 in which two immediate mode DAC update commands are written in direct succession. This example illustrates what happens when a DAC update command is written subsequent to a previous update command that has not yet finished its deglitch and settling sequence. Recommended Sequence for OVDH DAC Level Addressing For correct OVDH addressing, first write data to the OVDH DAC level at SPI 0x0C at CH0. If in DAC immediate mode, the OVDH data write must be followed by either a DAC_LOAD command to SPI 0x11[2] at CH1 or a subsequent write to any other CH1 DAC data address before the OVDH value will be updated. If in DAC deferred mode, the OVDH DAC level write must be followed by a DAC_LOAD command to SPI 0x11[2] at CH1 (not CH0) before the analog OVDH value will be updated. Initiation of the analog level update sequence (and triggering of the on-chip deglitch circuit) actually begins four SCLK cycles following the associated release of the CS pin. For the purpose of this discussion, it is assumed to start coincident with the release of CS. Rev. 0 | Page 63 of 80 ADATE318 tSPI SCLK CS SDI WRITE DAC0 WRITE DAC1 BUSY SEE TABLE 18 NOTE 1 SEE TABLE 18 NOTE 1 ±0.5 LSB DAC0 DAC1 DAC2 DAC23 09530-022 Addressing M and C Registers Some DACs have pairs of m/c-coefficients that are controlled depending on other register status. Table 20 details the specific register settings and register addresses for the different pairs (X = don’t care). Table 20. M- and C-Register Mapping SPI Address (Channel) 0x0D[0] 0x04[0] DAC Name OVDL VOH0 Functional (DAC Usage) Description Overvoltage detect low NWC high level, Channel 0 DMC high level PPMU go/no-go MV high level, Channel 0 PPMU go/no-go MI Range A high level, Channel 0 PPMU go/no-go MI Range B high level, Channel 0 PPMU go/no-go MI Range C high level, Channel 0 PPMU go/no-go MI Range D high level, Channel 0 PPMU go/no-go MI Range E high level, Channel 0 mregister 0x2D[0] 0x24[0] 0x44[0] 0x45[0] 0x46[0] cregister 0x3D[0] 0x34[0] 0x5C[0] 0x5D[0] 0x5E[0] VHH_ ENABLE 0x18[0] X X X X X DMC_ ENABLE 0x1C[0] X 0 1 X X LOAD_ ENABLEx 0x19[5] X X X X X PPMU_ POWERx 0x1A[15] X 0 0 1 1 PPMU_ MEAS_ VIx 0x1A[5] X X X 0 1 PPMU_FORCE _VIx 0x1A[4] X X X X X PPMU_ RANGEx (0x1A[3:1]) XXX XXX XXX XXX 111 ........ BEGINNING OF 3µs DEGLITCH PERIOD RETRIGGER OF 3µs DEGLITCH PERIOD COMPLETION OF 3µs DEGLITCH PERIOD NOTES 1. DAC DEGLITCH PERIOD ALWAYS BEGINS FOUR SCLK CYCLES BEFORE RELEASE OF BUSY. 3µs tDAC Figure 126. SPI DAC Write and Settling Time 0x47[0] 0x5E[0] X X X 1 1 X 110 0x48[0] 0x5E[0] X X X 1 1 X 101 0x49[0] 0x5E[0] X X X 1 1 X 100 0x4A[0] 0x5E[0] X X X 1 1 X 0XX Rev. 0 | Page 64 of 80 ADATE318 SPI Address (Channel) 0x05[0] DAC Name VOL0 Functional (DAC Usage) Description NWC low level, Channel 0 DMC low level PPMU go/no-go MV low level, Channel 0 PPMU go/no-go MI Range A low level, Channel 0 PPMU go/no-go MI Range B low level, Channel 0 PPMU go/no-go MI Range C low level, Channel 0 PPMU go/no-go MI Range D low level, Channel 0 PPMU go/no-go MI Range E low level, Channel 0 Load IOH level, Channel 0 Load IOL level, Channel 0 Drive term level, Channel 0 Load commutation voltage, Channel 0 Drive high level, Channel 0 HVOUT drive high level, Channel 0 Drive low level, Channel 0 HVOUT drive low level, Channel 0 Ref clamp high level, Channel 0 PPMU clamp high level, Channel 0 Ref clamp low level, Channel 0 PPMU clamp low level, Channel 0 PPMU VIN FV level, Channel 0 PPMU VIN FI Range A level, Channel 0 PPMU VIN FI Range B level, Channel 0 PPMU VIN FI Range C level, Channel 0 PPMU VIN FI Range D Level, Channel 0 PPMU VIN FI Range E level, Channel 0 VHH level Overvoltage detect high mregister 0x25[0] 0x4B[0] 0x4C[0] 0x4D[0] cregister 0x35[0] 0x63[0] 0x64[0] 0x65[0] VHH_ ENABLE 0x18[0] X X X X DMC_ ENABLE 0x1C[0] 0 1 X X LOAD_ ENABLEx 0x19[5] X X X X PPMU_ POWERx 0x1A[15] 0 0 1 1 PPMU_ MEAS_ VIx 0x1A[5] X X 0 1 PPMU_FORCE _VIx 0x1A[4] X X X X PPMU_ RANGEx (0x1A[3:1]) XXX XXX XXX 111 0x4E[0] 0x65[0] X X X 1 1 X 110 0x4F[0] 0x65[0] X X X 1 1 X 101 0x50[0] 0x65[0] X X X 1 1 X 100 0x51[0] 0x65[0] X X X 1 1 X 0XX 0x08[0] 0x09[0] 0x02[0] VIOH0 VIOL0 VIT0/ VCOM0 0x28[0] 0x29[0] 0x22[0] 0x42[0] 0x21[0] 0x41[0] 0x23[0] 0x43[0] 0x26[0] 0x52[0] 0x27[0] 0x53[0] 0x2A[0] 0x54[0] 0x55[0] 0x56[0] 0x57[0] 0x58[0] 0x2B[0] 0x2C[0] 0x38[0] 0x39[0] 0x32[0] 0x5A[0] 0x31[0] 0x59[0] 0x33[0] 0x5B[0] 0x36[0] 0x6A[0] 0x37[0] 0x6B[0] 0x3A[0] 0x6C[0] 0x6C[0] 0x6C[0] 0x6C[0] 0x6C[0] 0x3B[0] 0x3C[0] X X X X 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X X X X X X X X X 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 1 1 1 X X XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX 111 110 101 100 0XX XXX XXX 0x01[0] VIH0 0x03[0] VIL0 0x06[0] VCH0 0x07[0] VCL0 0x0A[0] PPMU0 0x0B[0] 0x0C[0] VHH OVDH Rev. 0 | Page 65 of 80 ADATE318 SPI Address (Channel) 0x04[1] DAC Name VOH1 Functional (DAC Usage) Description NWC high level, Channel 1 PPMU go/no-go MV high level, Channel 1 PPMU go/no-go MI Range A high level, Channel 1 PPMU go/no-go MI Range B high level, Channel 1 PPMU go/no-go MI Range C high level, Channel 1 PPMU go/no-go MI Range D high level, Channel 1 PPMU go/no-go MI Range E high level, Channel 1 NWC low level, Channel 1 PPMU go/no-go MV low level, Channel 1 PPMU go/no-go MI Range A low level, Channel 1 PPMU go/no-go MI Range B low level, Channel 1 PPMU go/no-go MI Range C low level, Channel 1 PPMU go/no-go MI Range D low level, Channel 1 PPMU go/no-go MI Range E low level, Channel 1 Load IOH level, Channel 1 Load IOL level, Channel 1 Drive term level, Channel 0 Load commutation voltage, Channel 1 Drive high level, Channel 1 Drive low level, Channel 1 Ref clamp high level, Channel 1 PPMU clamp high level, Channel 1 Ref clamp low level, Channel 1 PPMU clamp low level, Channel 1 PPMU VIN FV level, Channel 1 PPMU VIN FI Range A level, Channel 1 PPMU VIN FI Range B level, Channel 1 PPMU VIN FI Range C level, Channel 1 PPMU VIN FI Range D level, Channel 1 PPMU VIN FI Range E level, Channel 1 mregister 0x24[1] 0x45[1] 0x46[1] cregister 0x34[1] 0x5D[1] 0x5E[1] VHH_ ENABLE 0x18[0] X X X DMC_ ENABLE 0x1C[0] X X X LOAD_ ENABLEx 0x19[5] X X X PPMU_ POWERx 0x1A[15] 0 1 1 PPMU_ MEAS_ VIx 0x1A[5] X 0 1 PPMU_FORCE _VIx 0x1A[4] X X X PPMU_ RANGEx (0x1A[3:1]) XXX XXX 111 0x47[1] 0x5E[1] X X X 1 1 X 110 0x48[1] 0x5E[1] X X X 1 1 X 101 0x49[1] 0x5E[1] X X X 1 1 X 100 0x4A[1] 0x5E[1] X X X 1 1 X 0XX 0x05[1] VOL1 0x25[1] 0x4C[1] 0x4D[1] 0x35[1] 0x64[1] 0x65[1] X X X X X X X X X 0 1 1 X 0 1 X X X XXX XXX 111 0x4E[1] 0x65[1] X X X 1 1 X 110 0x4F[1] 0x65[1] X X X 1 1 X 101 0x50[1] 0x65[1] X X X 1 1 X 100 0x51[1] 0x65[1] X X X 1 1 X 0XX 0x08[1] 0x09[1] 0x02[1] VIOH1 VIOL1 VIT1/ VCOM1 0x28[1] 0x29[1] 0x22[1] 0x42[1] 0x21[1] 0x23[1] 0x26[1] 0x52[1] 0x27[1] 0x53[1] 0x2A[1] 0x54[1] 0x55[1] 0x56[1] 0x57[1] 0x58[1] 0x38[1] 0x39[1] 0x32[1] 0x5A[1] 0x31[1] 0x33[1] 0x36[1] 0x6A[1] 0x37[1] 0x6B[1] 0x3A[1] 0x6C[1] 0x6C[1] 0x6C[1] 0x6C[1] 0x6C[1] X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X X X 0 1 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 1 1 1 XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX XXX 111 110 101 100 0XX 0x01[1] 0x03[1] 0x06[1] VIH1 VIL1 VCH1 0x07[1] VCL1 0x0A[1] PPMU1 Rev. 0 | Page 66 of 80 ADATE318 SPI Address (Channel) 0x0E[0] DAC Name Spare Functional (DAC Usage) Description Spare level mregister 0x2E[0] cregister 0x3E[1] VHH_ ENABLE 0x18[0] X DMC_ ENABLE 0x1C[0] X LOAD_ ENABLEx 0x19[5] X PPMU_ POWERx 0x1A[15] X PPMU_ MEAS_ VIx 0x1A[5] X PPMU_FORCE _VIx 0x1A[4] X PPMU_ RANGEx (0x1A[3:1]) XXX DAC TRANSFER FUNCTIONS Table 21. Detailed DAC Code to Voltage Level Transfer Functions Levels VIHx, VILx, VITx/VCOMx, VOLx, VOHx, VCHx, VCLx, OVDHx, OVDLx VHH IOHx, IOLx PPMU_VINx (FV) PPMU_VINx (FI, Range A) PPMU_VINx (FI, Range B) PPMU_VINx (FI, Range C) PPMU_VINx (FI, Range D) PPMU_VINx (FI, Range E) Programmable DAC Range1, 0x0000 to 0xFFFF −2.5 V to +7.5 V DAC-to-Level and Level-to-DAC Transfer Functions VOUT = 2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) + VDUTGND DAC = [VOUT − VDUTGND + 0.5 × (VREF − VREFGND)] × [(216)/(2 × (VREF − VREFGND))] VOUT = 4 × (VREF − VREFGND) × (DAC/216 ) − 0.6 × (VREF − VREFGND) + VDUTGND DAC = [VOUT − VDUTGND + 0.6 × (VREF − VREFGND)] × [216/(4 × (VREF − VREFGND))] IOUT = [2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND)] × (25 mA/5) DAC = [(IOUT × (5/25 mA)) + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))] VOUT = 2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) + VDUTGND DAC = [VOUT − VDUTGND + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))] IOUT = [2 × (VREF − VREFGND) × (DAC/216) − 0.5 × (VREF − VREFGND) − 2.5] × (80 mA/5) DAC = [(IOUT × (5/80 mA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))] IOUT = [2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) − 2.5] × (2 mA/5) DAC = [(IOUT × (5/2 mA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))] IOUT = [2 × (VREF − VREFGND) × (DAC/216 ) − 0.5 × (VREF − VREFGND) − 2.5] × (200 μA/5) DAC = [(IOUT × (5/200 μA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))] IOUT = [2 × (VREF − VREFGND) × (DAC/216) − 0.5 × (VREF − VREFGND) − 2.5] × (20 μA/5) DAC = [(IOUT × (5/20 μA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))] IOUT = [2 × (VREF − VREFGND) × (DAC/216) − 0.5 × (VREF − VREFGND) − 2.5] × (4 μA/5) DAC = [(IOUT × (5/4 μA)) + 2.5 + 0.5 × (VREF − VREFGND)] × [216/(2 × (VREF − VREFGND))] −3.0 V to +17.0 V −12.5 mA to +37.5 mA −2.5 V to +7.5 V −80 mA to +80 mA −2 mA to +2 mA −200 μA to +200 μA −20 μA to +20 μA −4 μA to +4 μA 1 Programmable ranges include the margin outside the specified performance range, allowing for offset and gain calibration. Table 22. Load Transfer Functions Load Level IOLx IOHx Transfer Functions VIOLx/( VREF − VREFGND) × 25 mA VIOHx/( VREF − VREFGND) × 25 mA Notes VIOLx and VIOHx DAC levels are not referenced to VDUTGND. Table 23. PPMU Transfer Functions PPMU Mode FV MV MV FI MI 1 Transfer Functions1 VOUT = PPMU_VINx VPPMU_MEASx = VDUTx (internal sense path) VPPMU_MEASx = VPPMU_Sx (external sense path) IOUT = [PPMU_VINx − (VREF − VREFGND)/2]/(5 × RPPMU) VPPMU_MEASx = [VREF − VREFGND)/2] + (5 × IOUT × RPPMU) + VDUTGND Uncalibrated PPMU_VIN DAC Settings to Achieve Specified PPMU Range −2.0 V < PPMU_VINx < +6.5 V N/A N/A 0.0 V < PPMU_VINx < 5.0 V N/A RPPMU = 12.5 Ω for Range A, 500 Ω for Range B, 5.0 kΩ for Range C, 50 kΩ for Range D, and 250 kΩ for Range E. Table 24. VHH Transfer Functions VHH Mode VHH VIL VIH Transfer Functions HVOUT = 2 × [VHH + (VREF − VREFGND)/5] + VDUTGND HVOUT = VIL0 + VDUTGND HVOUT = VIH0 + VDUTGND Rev. 0 | Page 67 of 80 ADATE318 GAIN AND OFFSET CORRECTION Each DAC within the ADATE318 has independent gain (m) and offset (c) correction registers that allow digital trim of gain and offset errors. DACs that are shared between functions or levels are provided with per-level or per-function gain and offset correction registers, as appropriate. These registers provide the ability to calibrate out errors in the complete signal chain, which includes error in pin electronics function as well as the DACs. All m- and c-registers are volatile and must be loaded after power-on as part of a calibration cycle if values other than the defaults are required. The gain and offset correction function can be bypassed by clearing the DAC_CAL_ENABLE bit in the SPI DAC contol register (SPI ADDR 0x11[0]; see Figure 116). This bypass mode is available on a per-chip basis only; that is, it is not possible to bypass calibration for a subset of the DACs. The calibration function, when enabled, adjusts the numerical data sent to each DAC according to the following equation: that the new X2 value is calculated correctly following the new data write, provided the desired m and c values are stored in advance. The sequence of operations is critical in that the mode or range change must be performed prior to writing the new DAC data, and both m and c values must be present before the new DAC data is written. The m and/or c value can be written either before or after a mode or range change but must be written prior to the DAC data to have the intended effect. SAMPLE CALCULATIONS OF M AND C Because the ADATE318’s on-chip DACs have a theoretical output range that exceeds the operating capabilities of the remainder of its signal channels, calibration points must be chosen to be within the normal operating span. Subject to this constraint, calibration is straightforward. One of the keys to understanding the calibration method is to recognize that the intrinsic DAC offset is defined by its output when the input code is 0x0000. This is quite different from the case of the analog signal paths, where a 0 V level occurs when the DAC code is programmed to near quarter-scale. As a first example, consider the calibration of a drive high level with a theoretical output span of −2.5 V to 7.5 V, a convenient 10.0 V span in which DAC quarter-scale corresponds to precisely 0.0 V out. The ADATE318 drivers do not of course support this full span, but it is a useful choice for illustration of the calibration methodology. 1. Set the channel to drive high and program the VIL and VIT DACs for roughly −1.0 V outputs (Code 0x2700, not critical). Program the VIH DAC to quarter-scale (0x4000) and measure Output Voltage V1; then program the DAC to three-quarter-scale (0xC000) and measure Output Voltage V2. Note that V1 and V2 should be measured with respect to DUTGND. Calculate  m  1   X 2   n   X1   c  2n 1 2      where: X2 = the data-word loaded into the DAC and returned by an SPI read operation. X1 = the 16-bit data-word written to the DAC SPI input register. m = the code in the respective DAC gain register (default code = 0xFFFF = 2n − 1). c = the code in the respective DAC offset register (default code = 0x8000 = 2n−1). n = the DAC resolution (n = 16). From this equation, it can be seen that the gain applied to the X1 value is always less than or equal to 1.0, with the effect that a DAC’s output voltage can only be made smaller. To compensate for this numerically imposed limitation, the ADATE318’s signal paths are designed to have gain guaranteed to be greater than 1.0 when the default m values (0xFFFF) are applied. This guarantees that proper gain calibration is always possible. Note also that the value of c is expressed in raw DAC LSBs; that is, it is calculated without considering the effect of the m-register. When enabled, the calibration function applies the above operation to the X2 register(s) only after a SPI write to the respective X1 register(s). The X2 registers are not updated after writes to either the m- or c-register. In the case of a dual channel write to the DAC, two respective X2 registers are sequentially updated using the appropriate m and c values. 2. Actual _ DAC _ FSR  2  V2  V1  3. where (V2 − V1) represents half the full-scale span. Calculate the extrapolated DAC voltage at Code 0x0000.  Actual _ DAC _ FSR  V0  V1    4   4. Calculate Actual _ DAC _ LSB  5. Calculate V2  V1  32,768 X2 REGISTERS Each DAC has associated with it a single X2 register. There is no provision for storing separate X2 values for DACs shared between functions or ranges. Thus, new data must be written to any shared DAC after a mode or range change is performed, even if the old and new DAC data is identical. The ADATE318 provides separate m- and c-registers for all ranges and modes so 6. 5  m  65,536  1 V2  V1    Calculate the offset from the ideal −2.5 V. Offset   2.5  V0 Rev. 0 | Page 68 of 80 ADATE318 7. Calculate 3. 4. Calculate the offset from the desired −1.5 V. Offset   c  32,768    Actual _ DAC _ LSB     8. Calculate volts 5 Post _ Calibration _ DAC _ LSB  Actual _ DAC _ LSB   V  V   1 2 Offset   1.5  V0 Calculate DAC Offset   c  32,768    Actual _ DAC _ LSB     5. Calculate The above procedure places the DAC’s theoretical 0x0000 output at −2.5 V and its theoretical 0xFFFF output at 7.49985 V (1 LSB below +7.5 V). The useful range extends from below 0x199A (−1.5 V) to above 0xE666 (+6.5 V), a span of at least 52,428 actual DAC codes. An alternative calibration approach can be used to map all 216 DAC codes onto the part’s specified output range by mapping the zero-code to −1.5 V and the full-scale code to +6.5 V. 1. 2. Repeat Step 1 to Step 4 above. Calculate Post _ Calibration _ DAC _ LSB  8 Volts 65,536 m V2  V1  4  65,535 Although this second approach gives an apparent 16 bits of resolution covering the full signal range, it must be kept in mind that this is achieved purely by mathematical alteration of the DAC data. The DAC’s internal LSB step size is not changed. In this example, the number of internal DAC codes used to cover the signal span remains roughly 52,428 even though the number of user codes has increased to 65,536. A consequence of this is that apparent DNL errors are increased as more input codes are mapped onto the same number of DAC codes. While the second calibration method is included here as an example of what is possible, its use can provide a false sense of improved accuracy and it is therefore not recommended. Rev. 0 | Page 69 of 80 ADATE318 POWER SUPPLY, GROUNDING, AND DECOUPLING STRATEGY The ADATE318 product is internally divided into a digital core and an analog core. The VCC and DGND pins provide power and ground, respectively, for the digital core, which includes the SPI and all digital calibration functions. DGND is the logic ground reference for the VCC supply, and VCC should be adequately bypassed to DGND with low ESR bypass capacitors. To reduce transient digital switching noise coupling from the VCC and DGND pins to the analog core, DGND should be connected to a dedicated ground domain that is separate from the analog ground domains. If the application permits, the DGND should share digital ground domain with the system FPGA or ASIC that interfaces with the ADATE318 SPI. All CMOS inputs and outputs are referenced between VCC and DGND, and their valid levels should be guaranteed relative to these. The analog core of the product includes all analog ATE functional blocks such as DACs, driver, comparator, load, PPMU, VHH driver, and so on. The VPLUS, VDD, and VSS supplies provide power for the analog core. The AGND and PGND are analog ground and analog power ground references, respectively. PGND is generally more noisy with analog switching transients, and it may also have large static dc currents. The AGND is generally more quiet and has relatively small static dc currents. Ideally, these ground domains should be separated, but it is not necessary. They can be connected together outside the chip to a shared analog ground plane. VDD and VSS should be adequately bypassed to the PGND ground domain. Both PGND and AGND (whether separated or shared) should be kept separate from the DGND ground plane as discussed above. The VPLUS supply pin has the sole purpose to provide high voltage power for the VHH drive capability (HVOUT pin). If the VHH drive capability is used, the VPLUS supply must be provided as specified. If the VHH drive capability is not used, the VPLUS supply can be connected directly to the VDD supply domain to save power. The ADATE318 also has a DUTGND input pin that can be used to sense the remote DUT ground potential. All DAC functions (with the exception of VIOH and VIOL active load currents and VPMU when in PPMU FI mode) are adjusted relative to this DUTGND input. Further, the PPMU measure out pins (PPMU_MEASx) are referenced to DUTGND not AGND. This, therefore, requires the system ADC to reference its inputs relative to DUTGND as well. Referencing the system ADC to AGND results in errors, except in the case that DUTGND is tied to AGND. For applications that do not distinguish between DUT ground reference and system analog ground reference, the DUTGND pin can be connected to the same ground plane as AGND. The ADATE318 should have ample supply decoupling of 0.1 μF on each supply pin located as close to the device as possible, ideally right up against the device. In addition, there should be one 10 μF tantalum capacitor shared across each power domain. The 0.1 μF capacitor should have low effective series resistance (ESR) and effective series inductance (ESL), such as the common ceramic capacitors that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching. Digital lines running under the device should be avoided because these couple noise onto the device. The analog ground plane should be allowed to run under the device to avoid noise coupling. The power supply lines should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching digital signals should be shielded with digital ground to avoid radiating noise to other parts of the board and should never be run near the reference inputs. It is essential to minimize noise on all VREF lines. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough throughout the board. As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of this package during the assembly process. Rev. 0 | Page 70 of 80 ADATE318 USER INFORMATION AND TRUTH TABLES Table 25. Driver Truth Table 1 DCL Enable ADDR 0x19[0] 0 1 1 1 1 1 1 1 1 1 Force Load ADDR 0x19[2] X X X X X X X X X DCL Control Register Bits (0x19) Force Drive Force State Load Enable ADDR ADDR ADDR 0x19[1] 0x19[4:3] 0x19[5] X XX X 1 00 X 1 01 X 1 10 X 1 11 X 0 XX X 0 XX X 0 XX X 0 XX X High Speed Inputs DRV_VT_HIZ ADDR 0x19 [6] X X X X X X X 0 1 RCVx X X X X X 0 0 1 1 DATx X X X X X 0 1 X X Driver Low leakage VIL VIH High-Z VIT VIL VIH High-Z VIT X = don’t care. Table 26. Active Load Truth Table 1 DCL Enable ADDR 0x19[0] 0 1 1 1 1 1 1 Force Load ADDR 0x19[2] X 1 0 0 0 0 DCL Control Register Bits (0x19) Force Drive Force State Load Enable ADDR ADDR ADDR 0x19[1] 0x19[4:3] 0x19[5] X XX X X XX X X XX 0 X XX 1 X XX 1 X XX 1 High Speed Inputs DRV_VT_HIZ ADDR 0x19 [6] X X X X 0 1 RCVx X X X 0 1 1 DATx X X X X X X Load Low leakage Active on Low leakage Active off Active on Active off X = don’t care. Table 27. VHH and VIH/VIL Driver Truth Table 1 VHH_ENABLE ADDR 0x18[0] 1 1 1 0 1 CH0 RCV (RCV0) 0 0 1 X CH0 DAT (DAT0) 0 1 X X Output of VHH Driver VIL (Channel 0, VIL DAC) VIH (Channel 0, VIH DAC) VHH Disabled (HVOUT pin set to 0.0 V, approximately 50 Ω impedance) X = don’t care. Table 28. Comparator Truth Table DMC ENABLE ADDR 0x1C[0] 0 CMPH0 Normal window compare mode Logic high: VOH0 < VDUT0 Logic low: VOH0 > VDUT0 Differential compare mode Logic high: VOH0 < VDUT0 – VDUT1 Logic low: VOH0 > VDUT0 – VDUT1 CMPL0 Normal window compare mode Logic high: VOL0 < VDUT0 Logic low: VOL0 > VDUT0 Differential compare mode Logic high: VOL0 < VDUT0 − VDUT1 Logic low: VOL0 > VDUT0 − VDUT1 CMPH1 Normal window compare mode Logic high: VOH1 < VDUT1 Logic low: VOH1 > VDUT1 Normal window compare mode Logic high: VOH1 < VDUT1 Logic low: VOH1 > VDUT1 CMPL1 Normal window compare mode Logic high: VOL1 < VDUT1 Logic low: VOL1 > VDUT1 Normal window compare mode Logic high: VOL1 < VDUT1 Logic low: VOL1 > VDUT1 1 Rev. 0 | Page 71 of 80 ADATE318 ALARM FUNCTIONS The ADATE318 contains per-channel overvoltage detectors (OVD), PPMU voltage/current clamps, and a per-chip thermal alarm to detect and signal fault conditions. The status of these circuits may be interrogated via the SPI by reading the alarm state register (SPI ADDR 0x1E; see Figure 124). This read-only register is cleared by a read operation. In addition, the fault conditions are combined in the fault alarm logic (see Figure 137) and drive the open drain ALARM pin to signal that a fault has occurred. The various alarm circuits are controlled through the alarm mask register (ADDR 0x1D; see Figure 123). In the default state, the thermal alarm is enabled, and both the overvoltage alarm and the PPMU clamp alarms are masked off. The only function of the alarm circuits is to detect and signal the presence of a fault. The only actions taken upon detection of a fault are setting of the appropriate register bit and activating the ALARM pin. PPMU EXTERNAL CAPACITORS Table 29. PPMU External Compensation and Feedforward Capacitors External Components 220 pF 220 pF 1000 pF 1000 pF Location Between FFCAPB0 and FFCAPA0 Between FFCAPB1 and FFCAPA1 Between AGND and SCAP0 Between AGND and SCAP1 Table 30. Other External Components External Components 10 kΩ 1 kΩ Location ALARM pull-up to VCC BUSY pull-up to VCC TEMPERATURE SENSOR Table 31. Temperature 0K 300 K TKELVIN Output 0.00 V 3.00 V 0.00 V + (TKELVIN ) × 10 mV/K Rev. 0 | Page 72 of 80 ADATE318 DEFAULT TEST CONDITIONS Table 32. Name VIHx DAC Levels VITx/VCOMx DAC Levels VILx DAC Levels VOHx DAC Levels VOLx DAC Levels VCHx DAC Levels VCLxDAC Levels VIOHxDAC Levels VIOLx DAC Levels PPMU_VINx DAC Levels VHH DAC Level OVDH DAC Levels OVDL DAC Levels DAC_CONTROL VHH_CONTROL DCL_CONTROL PPMU_CONTROL PPMU_MEAS_CONTROL COMPARATOR_CONTROL ALARM_MASK PRE_EMPHASIS_CONTROL Calibration m-Coefficients Calibration c-Coefficients DATx, RCVx Inputs DUTx Pins CMPHx, CMPLx Outputs VDUTGND 1 2 Default Test Condition 2.0 V 1.0 V 0.0 V 6.5 V −1.5 V 7.5 V −2.5 V 0.0 mA 0.0 mA 0.0 V 13.0 V 7.0 V −2.0 V 0x0000: DAC calibration disabled, DAC load mode is immediate 0x0000: HVOUT (VHH) disabled 0x0001: DCL enabled, load disabled, high-Z for RCVx = 1, force drive = 0 (to VIL state) 0x0000: PPMU disabled, PPMU Range E, Force-V 1 /Measure-V 2 , input to VDUTGND, internal sense path, clamps disabled, external PPMU_S open, PPMU_POWER_x off 0x0000: PPMU_MEASx high-Z 0x0000: normal window comparator mode, comparator hysteresis disabled 0x0045: disable alarm functions 0x0000: disable driver CLC, differential comparator CLC, and normal window comparator CLC 1.0 (0xFFFF) 0.0 (0x8000) Logic low Unterminated Unterminated 0.0 V Force-V indicates force voltage. Measure-V indicates measure voltage. Rev. 0 | Page 73 of 80 ADATE318 DETAILED FUNCTIONAL BLOCK DIAGRAMS PMU CLAMP LEVELS SHARED WITH HIGH SPEED DCL CLAMPS DACVCHx ADDR 0x06, CHx DACVCLx ADDR 0x07, CHx (IDEAL CLAMP DIODES) 0 DACVIT/VCCMx ADDR 0x02, CHx TERM 1 DRV_RCV_MODE (SEE THE DRIVER LOGIC DIAGRAM) HIGH-Z DACVIHx ADDR 0x01, CHx DACVILx ADDR 0x03, CHx DATx DRV_RCV_SW (SEE THE DRIVER LOGIC DIAGRAM) DRV_LOW_LEAK (SEE THE DRIVER LOGIC DIAGRAM) DRV 1 0 0 50Ω DUTx Figure 127. Driver Block Diagram DCL_ENABLE ADDR 0x19[0] FORCE_DRV ADDR 0x19[1] FORCE_STATE[1] ADDR 0x19[4] FORCE_STATE[0] ADDR 0x19[3] DRV_VT_HIZ ADDR 0x19[6] RCVx DRV_LOW_LEAK DRV_LOW_LEAK = DCL_ENABLE DRV_RCV_MODE = DRIVE_VT_HIZ + FORCE_DRV × FORCE_STATE[0] DRV_RCV_SW = FORCE_DRV × FORCE_STATE[1] + FORCE_DRV × RCVx DRV_RCV_MODE (SEE THE DRIVER BLOCK DIAGRAM) Figure 128. Driver Logic Diagram Rev. 0 | Page 74 of 80 09530-024 DRV_RCV_SW (SEE THE DRIVER BLOCK DIAGRAM) 09530-023 ADATE318 ADATE318 DAT 100Ω DAT RCV 100Ω RCV 0.0V ≤ VCM ≤ 3.3V 200mV ≤ V DM ≤ 1.0V TO DRIVER, LOAD, AND VHH TYPICAL INPUT WAVEFORMS DAT VDM DAT VCM RCV VDM RCV VCM 0.95V 1.25V VCM = 1.10V VDM = 300mV 1.10V 1.30V VCM = 1.20V VDM = 200mV Figure 129. Driver Input Stage Diagram 50Ω FROM DRIVER 09530-025 DUTx LOAD_CONNECT (SEE THE ACTIVE LOAD LOGIC DIAGRAM) DACVIOL ADDR 0x09 DACVIT/VCOM ADDR 0x2 DACVIOH ADDR 0x08 ACTIVE LOAD LOAD_PWR_DOWN (SEE THE ACTIVE LOAD LOGIC DIAGRAM) 09530-026 Figure 130. Active Load Block Diagram DCL_ENABLE ADDR 0x19[0] FORCE_LOAD ADDR 0x19[2] LOAD_ENABLE ADDR 0x19[5] DRV_VT_HIZ ADDR 0x19[6] RCVn LOAD_PWR_DOWN (SEE THE ACTIVE LOAD BLOCK DIAGRAM) LOAD_CONNECT (SEE THE ACTIVE LOAD BLOCK DIAGRAM) LOAD_CONNECT = DCL_ENABLE × (FORCE_LOAD + RCVn × DRV_VT_HIZ × LOAD_ENABLE) LOAD_PWR_DOWN = DCL_ENABLE + FORCE_LOAD × LOAD_ENABLE Figure 131. Active Load Logic Diagram Rev. 0 | Page 75 of 80 09530-027 ADATE318 DACVHH VDUTGND VHH (NOTE 1) VHH DRIVER