ADCLK948

Two Selectable Inputs, 8 LVPECL Outputs, SiGe Clock Fanout Buffer ADCLK948 FEATURES 2 selectable differential inputs selectable 4.8 GHz operating frequency 75 fs rms broadband random jitter On-chip input terminations 3.3 V power supply FUNCTIONAL FUNCTIONAL BLOCK DIAGRAM LVPECL ADCLK948 Q0 Q0 Q1 Q1 Q2 Q2 Q3 APPLICATIONS APPLICATIONS Low Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation VREF 0 REFERENCE Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 V T0 CLK0 GENERAL GENERAL DESCRIPTION The The ADCLK948 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter. The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs. The ADCLK948 features eight full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differential output swing of 1.6 V. The ADCLK948 is available in a 32-lead LFCSP and specified for operation over the standard industrial temperature range of −40°C to +85°C. CLK0 V T1 CLK1 CLK1 IN_SEL Q7 REFERENCE Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved. 08280-001 VREF 1 ADCLK948 TABLE OF CONTENTS Features .............................................................................................. 1  Applications ....................................................................................... 1  General Description ......................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 2  Specifications..................................................................................... 3  Electrical Characteristics ............................................................. 3  Absolute Maximum Ratings............................................................ 5  Determining Junction Temperature .......................................... 5  ESD Caution .................................................................................. 5  Thermal Performance .................................................................. 5  Pin Configuration and Function Descriptions..............................6  Typical Performance Characteristics ..............................................7  Functional Description .....................................................................9  Clock Inputs ...................................................................................9  Clock Outputs ................................................................................9  Clock Input Select (IN_SEL) Settings...................................... 10  PCB Layout Considerations ...................................................... 10  Input Termination Options ....................................................... 11  Outline Dimensions ....................................................................... 12  Ordering Guide .......................................................................... 12  REVISION HISTORY 7/09—Revision 0: Initial Version Rev. 0 | Page 2 of 12 ADCLK948 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Typical (Typ column) values are given for VCC − VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min column) and maximum (Max column) values are given over the full VCC − VEE = 3.3 V ± 10% and TA = −40°C to +85°C variation, unless otherwise noted. Table 1. Clock Inputs and Outputs Parameter DC INPUT CHARACTERISTICS Input Common Mode Voltage Input Differential Range Input Capacitance Input Resistance Single-Ended Mode Differential Mode Common Mode Input Bias Current Hysteresis DC OUTPUT CHARACTERISTICS Output Voltage High Level Output Voltage Low Level Output Voltage Differential Reference Voltage Output Voltage Output Resistance Symbol VICM VID CIN Min VEE + 1.5 0.4 0.4 50 100 50 20 10 VOH VOL VOD VREF VCC − 1.26 VCC − 1.99 610 (VCC + 1)/2 235 VCC − 0.76 VCC − 1.54 960 Typ Max VCC − 0.1 3.4 Unit V V p-p pF Ω Ω kΩ μA mV V V mV V Ω Test Conditions/Comments ±1.7 V between input pins Open VTx 50 Ω to (VCC − 2.0 V) 50 Ω to (VCC − 2.0 V) 50 Ω to (VCC − 2.0 V) −500 μA to +500 μA Table 2. Timing Characteristics Parameter AC PERFORMANCE Maximum Output Frequency Symbol Min 4.5 Typ 4.8 Max Unit GHz Test Conditions/Comments See Figure 4 for differential output voltage vs. frequency, >0.8 V differential output swing 20% to 80% measured differentially VICM = 2 V, VID = 1.6 V p-p Output Rise Time Output Fall Time Propagation Delay Temperature Coefficient Output-to-Output Skew 1 Part-to-Part Skew Additive Time Jitter Integrated Random Jitter Broadband Random Jitter 2 Crosstalk-Induced Jitter 3 CLOCK OUTPUT PHASE NOISE Absolute Phase Noise fIN = 1 GHz tR tF tPD 40 40 175 75 75 210 50 9 90 90 245 25 45 ps ps ps fs/°C ps ps fs rms fs rms fs rms VID = 1.6 V p-p BW = 12 kHz − 20 MHz, CLK = 1 GHz VID = 1.6 V p-p, 8 V/ns, VICM = 2 V 28 75 90 −119 −134 −145 −150 −150 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Input slew rate > 1 V/ns (see Figure 11, the phase noise plot, for more details) @100 Hz offset @1 kHz offset @10 kHz offset @100 kHz offset >1 MHz offset 1 2 The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method. 3 This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs. Rev. 0 | Page 3 of 12 ADCLK948 Table 3. Input Select Control Pin Parameter Logic 1 Voltage Logic 0 Voltage Logic 1 Current Logic 0 Current Capacitance Symbol VIH VIL IIH IIL Min VCC − 0.4 VEE Typ Max VCC 1 100 0.6 Unit V V μA mA pF 2 Table 4. Power Parameter POWER SUPPLY Supply Voltage Requirement Power Supply Current Negative Supply Current Positive Supply Current Power Supply Rejection 1 Output Swing Supply Rejection 2 1 2 Symbol VCC − VEE IVEE IVCC PSRVCC PSRVCC Min 2.97 Typ Max 3.63 Unit V mA mA ps/V dB Test Conditions/Comments 3.3 V + 10% Static VCC − VEE = 3.3 V ± 10% VCC − VEE = 3.3 V ± 10% VCC − VEE = 3.3 V ± 10% VCC − VEE = 3.3 V ± 10% 96 288 1.1 V p-p 225 220 PROPAGATION DELAY (ps) Figure 7. Propagation Delay vs. Temperature, VID = 1.6 V p-p 230 PROPAGATION DELAY (ps) 215 210 205 200 195 190 185 08280-005 220 +85°C 210 +25°C 200 –40°C 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 DIFFERENTIAL INPUT VOLTAGE SWING (V) DC COMMON-MODE VOLTAGE (V) Figure 5. Propagation Delay vs. Differential Input Voltage Figure 8. Propagation Delay vs. DC Common-Mode Voltage vs. Temperature, Input Slew Rate > 25 V/ns Rev. 0 | Page 7 of 12 08280-008 180 190 0.9 08280-007 0.4 08280-006 C3 ADCLK948 1.56 DIFFERENTIAL OUTPUT VOLTAGE SWING (V) –90 –100 –40°C PHASE NOISE (dBc/Hz) 1.54 1.52 1.50 1.48 1.46 1.44 1.42 2.75 ABSOLUTE PHASE NOISE MEASURED @ 1GHz WITH AGILENT E5052 USING WENZEL CLOCK SOURCE CONSISTING OF A WENZEL 100MHz CRYSTAL OSCILLATOR (P/N 500-06672), WENZEL 5× MULTIPLIER (P/N LNOM-100-5-13-14-F-A), AND A WENZEL 2× MULTIPLIER (P/N LNDD-500-14-14-1-D). –110 –120 –130 –140 –150 –160 –170 10 ADCLK948 +25°C +85°C CLOCK SOURCE 100 1k 10k 100k 1M 10M 100M 08280-011 08280-012 2.85 2.95 3.05 3.15 3.25 3.35 3.45 3.55 3.65 3.75 POWER SUPPLY (V) 08280-009 FREQUENCY OFFSET (Hz) Figure 9. Differential Output Voltage Swing vs. Power Supply Voltage vs. Temperature, VID = 1.6 V p-p 350 ICC 300 250 200 150 100 IEE 50 0 2.75 RANDOM JITTER (fS rms) SUPPLY CURRENT (mA) Figure 11. Absolute Phase Noise Measured @1 GHz 300 250 200 +85°C +25°C –40°C 150 100 50 08280-010 0 0 5 10 15 20 25 INPUT SLEW RATE (V/ns) 3.00 3.25 SUPPLY VOLTAGE (V) 3.50 3.75 Figure 10. Power Supply Current vs. Power Supply Voltage vs. Temperature, All Outputs Loaded (50 Ω to VCC − 2 V). Figure 12. RMS Random Jitter vs. Input Slew Rate, VID Method Rev. 0 | Page 8 of 12 ADCLK948 FUNCTIONAL DESCRIPTION CLOCK INPUTS The ADCLK948 accepts a differential clock input from one of two inputs and distributes the selected clock to all eight LVPECL outputs. The maximum specified frequency is the point at which the output voltage swing is 50% of the standard LVPECL swing (see Figure 4). See the functional block diagram (Figure 1) and the General Description section for more clock input details. See Figure 19 through Figure 23 for various clock input termination schemes. Output jitter performance is degraded by an input slew rate below 4 V/ns, as shown in Figure 12. The ADCLK948 is specifically designed to minimize added random jitter over a wide input slew rate range. Whenever possible, clamp excessively large input signals with fast Schottky diodes because attenuators reduce the slew rate. Input signal runs of more than a few centimeters should be over low loss dielectrics or cables with good high frequency characteristics. Thevenin-equivalent termination uses a resistor network to provide 50 Ω termination to a dc voltage that is below VOL of the LVPECL driver. In this case, VS_DRV on the ADCLK948 should equal VS of the receiving buffer. Although the resistor combination shown (in Figure 15) results in a dc bias point of VS_DRV − 2 V, the actual common-mode voltage is VS_DRV − 1.3 V because there is additional current flowing from the ADCLK948 LVPECL driver through the pull-down resistor. LVPECL Y-termination is an elegant termination scheme that uses the fewest components and offers both odd- and even-mode impedance matching. Even-mode impedance matching is an important consideration for closely coupled transmission lines at high frequencies. Its main drawback is that it offers limited flexibility for varying the drive strength of the emitter follower LVPECL driver. This can be an important consideration when driving long trace lengths but is usually not an issue. VS_DRV ADCLK948 Z0 = 50Ω VCC – 2V Z0 = 50Ω VS = VS_DRV CLOCK OUTPUTS The specified performance necessitates using proper transmission line terminations. The LVPECL outputs of the ADCLK948 are designed to directly drive 800 mV into a 50 Ω cable or into microstrip/stripline transmission lines terminated with 50 Ω referenced to VCC − 2 V, as shown in Figure 14. The LVPECL output stage is shown in Figure 13. The outputs are designed for best transmission line matching. If high speed signals must be routed more than a centimeter, either the microstrip or the stripline technique is required to ensure proper transition times and to prevent excessive output ringing and pulse width dependent propagation delay dispersion. VCC 50Ω 08280-014 50Ω LVPECL Figure 14. DC-Coupled, 3.3 V LVPECL VS_DRV VS_DRV ADCLK948 50Ω SINGLE-ENDED (NOT COUPLED) 50Ω 127Ω 127Ω VS LVPECL Figure 15. DC-Coupled, 3.3 V LVPECL Far-End Thevenin Termination VS_DRV ADCLK948 Z0 = 50Ω 50Ω Z0 = 50Ω VS = VS_DRV 50Ω 08280-016 Qx Qx 50Ω LVPECL Figure 16. DC-Coupled, 3.3 V LVPECL Y-Termination 08280-013 VEE VS_DRV ADCLK948 0.1nF 100Ω DIFFERENTIAL 100Ω (COUPLED) 0.1nF TRANSMISSION LINE VS Figure 13. Simplified Schematic Diagram of the LVPECL Output Stage Figure 17. AC-Coupled, LVPECL with Parallel Transmission Line Rev. 0 | Page 9 of 12 08280-017 Figure 14 through Figure 17 depict various LVPECL output termination schemes. When dc-coupled, VS of the receiving buffer should match VS_DRV. LVPECL 200Ω 200Ω 08280-015 83Ω 83Ω ADCLK948 CLOCK INPUT SELECT (IN_SEL) SETTINGS A Logic 0 on the IN_SEL pin selects the Input CLK0 and Input CLK0. A Logic 1 on the IN_SEL pin selects Input CLK1 and Input CLK1. return path. If the inputs are dc-coupled to a source, take care to ensure that the pins are within the rated input differential and common-mode ranges. If the return is floated, the device exhibits a 100 Ω cross termination, but the source must then control the common-mode voltage and supply the input bias currents. There are ESD/clamp diodes between the input pins to prevent the application from developing excessive offsets to the input transistors. ESD diodes are not optimized for best ac performance. When a clamp is required, it is recommended that appropriate external diodes be used. PCB LAYOUT CONSIDERATIONS The ADCLK948 buffer is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes for both the negative supply (VEE) and the positive supply (VCC) planes as part of a multilayer board. Providing the lowest inductance return path for switching currents ensures the best possible performance in the target application. The following references to the GND plane assume that the VEE power plane is grounded for LVPECL operation. Note that, for ECL operation, the VCC power plane becomes the ground plane. It is also important to adequately bypass the input and output supplies. Place a 1 μF electrolytic bypass capacitor within several inches of each VCC power supply pin to the GND plane. In addition, place multiple high quality 0.001 μF bypass capacitors as close as possible to each of the VCC supply pins, and connect the capacitors to the GND plane with redundant vias. Carefully select high frequency bypass capacitors for minimum inductance and ESR. To improve the effectiveness of the bypass at high frequencies, minimize parasitic layout inductance. Also, avoid discontinuities along input and output transmission lines that can affect jitter performance. In a 50 Ω environment, input and output matching have a significant impact on performance. The buffer provides internal 50 Ω termination resistors for both CLKx and CLKx inputs. Normally, the return side is connected to the reference pin that is provided. Carefully bypass the termination potential using ceramic capacitors to prevent undesired aberrations on the input signal due to parasitic inductance in the termination Exposed Metal Paddle The exposed metal paddle on the ADCLK948 package is both an electrical connection and a thermal enhancement. For the device to function properly, the paddle must be properly attached to the VEE power plane. When properly mounted, the ADCLK948 also dissipates heat through its exposed paddle. The PCB acts as a heat sink for the ADCLK948. The PCB attachment must provide a good thermal path to a larger heat dissipation area. This requires a grid of vias from the top layer down to the VEE power plane (see Figure 18). The ADCLK948 evaluation board (ADCLK948/PCBZ) provides an example of how to attach the part to the PCB. VIAS TO VEE POWER PLANE Figure 18. PCB Land for Attaching Exposed Paddle Rev. 0 | Page 10 of 12 08280-018 ADCLK948 INPUT TERMINATION OPTIONS VCC VTx 50Ω CLKx CLKx VREF x VTx VREF x 50Ω 50Ω CLKx CLKx 50Ω 08280-019 CONNECT VTx TO VCC. CONNECT VTx TO VREF x. Figure 19. DC-Coupled CML Input Termination Figure 21. AC-Coupled Input Termination, Such as LVDS and LEVPECL VREF x VCC V Tx 50Ω CLKx CLKx 50Ω 50Ω 0.01µF (OPTIONAL) VREF x VTx 50Ω CLKx CLKx 08280-020 50Ω ADCLK948 CONNECT VTx, VREF x, AND CLKx. PLACE A BYPASS CAPACITOR FROM VTx TO GROUND. ALTERNATIVELY, VTx, VREF x, AND CLKx CAN BE CONNECTED, GIVING A CLEANER LAYOUT AND A 180º PHASE SHIFT. 08280-021 ADCLK948 ADCLK948 ADCLK948 Figure 20. DC-Coupled LVPECL Input Termination Figure 22. AC-Coupled Single-Ended Input Termination VREF x V Tx 50Ω CLKx CLKx 50Ω ADCLK948 Figure 23. DC-Coupled 3.3 V CMOS Input Termination Rev. 0 | Page 11 of 12 08280-023 08280-022 ADCLK948 OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR 2.85 2.70 SQ 2.55 PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC 0.50 0.40 0.30 EXPOSED PAD (BOTTOM VIEW) 17 16 98 0.20 MIN 3.50 REF 1.00 0.85 0.80 SEATING PLANE 12° MAX 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.25 0.18 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 032807-A COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 24. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-8) Dimensions shown in millimeters ORDERING GUIDE Model ADCLK948BCPZ 1 ADCLK948BCPZ-REEL71 ADCLK948/PCBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ Evaluation Board Package Option CP-32-8 CP-32-8 Z = RoHS Compliant Part. ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08280-0-7/09(0) Rev. 0 | Page 12 of 12