ADCMP580BCPZ-RL7

Ultrafast SiGe Voltage Comparators ADCMP580/ADCMP581/ADCMP582 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM VCCI VTP TERMINATION VP NONINVERTING INPUT VN INVERTING INPUT VCCO ADCMP580/ ADCMP581/ ADCMP582 Q OUTPUT CML/ECL/ PECL Q OUTPUT VEE VTN TERMINATION LE INPUT HYS LE INPUT VEE APPLICATIONS 04672-001 180 ps propagation delay 25 ps overdrive and slew rate dispersion 8 GHz equivalent input rise time bandwidth 100 ps minimum pulse width 37 ps typical output rise/fall 10 ps deterministic jitter (DJ) 200 fs random jitter (RJ) −2 V to +3 V input range with +5 V/−5 V supplies On-chip terminations at both input pins Resistor-programmable hysteresis Differential latch control Power supply rejection > 70 dB Figure 1. Automatic test equipment (ATE) High speed instrumentation Pulse spectroscopy Medical imaging and diagnostics High speed line receivers Threshold detection Peak and zero-crossing detectors High speed trigger circuitry Clock and data signal restoration GENERAL DESCRIPTION The ADCMP580/ADCMP581/ADCMP582 are ultrafast voltage comparators fabricated on the Analog Devices, Inc. proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP580 features CML output drivers, the ADCMP581 features reduced swing ECL (negative ECL) output drivers, and the ADCMP582 features reduced swing PECL (positive ECL) output drivers. All three comparators offer 180 ps propagation delay and 100 ps minimum pulse width for 10 Gbps operation with 200 fs random jitter (RJ). Overdrive and slew rate dispersion are typically less than 15 ps. The CML output stage is designed to directly drive 400 mV into 50 Ω transmission lines terminated to ground. The NECL output stages are designed to directly drive 400 mV into 50 Ω terminated to −2 V. The PECL output stages are designed to directly drive 400 mV into 50 Ω terminated to VCCO − 2 V. High speed latch and programmable hysteresis are also provided. The differential latch input controls are also 50 Ω terminated to an independent VTT pin to interface to either CML or ECL or to PECL logic. The ADCMP580/ADCMP581/ADCMP582 are available in a 16-lead LFCSP. The ±5 V power supplies enable a wide −2 V to +3 V input range with logic levels referenced to the CML/NECL/PECL outputs. The inputs have 50 Ω on-chip termination resistors with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance input. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADCMP580/ADCMP581/ADCMP582 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 12 Applications ....................................................................................... 1 Power/Ground Layout and Bypassing ..................................... 12 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 ADCMP580/ADCMP581/ADCMP582 Family of Output Stages ............................................................................................ 12 Revision History ............................................................................... 2 Using/Disabling the Latch Feature........................................... 12 Specifications..................................................................................... 3 Optimizing High Speed Performance ..................................... 13 Timing Information ......................................................................... 5 Comparator Propagation Delay Dispersion ............................... 13 Absolute Maximum Ratings ............................................................ 6 Comparator Hysteresis .............................................................. 14 Thermal Considerations .............................................................. 6 Minimum Input Slew Rate Requirement ................................ 14 ESD Caution .................................................................................. 6 Outline Dimensions ....................................................................... 15 Pin Configurations and Function Descriptions ........................... 7 Ordering Guide .......................................................................... 15 Typical Performance Characteristics ............................................. 9 Typical Application Circuits.......................................................... 11 REVISION HISTORY 4/16—Rev. A to Rev. B Deleted Figure 4; Renumbered Sequentially................................. 7 Changes to Figure 3 and Table 4 ..................................................... 7 Changes to Figure 4 .......................................................................... 8 Added Table 5; Renumbered Sequentially .................................... 8 Updated Outline Dimensions ....................................................... 14 Changes to Ordering Guide .......................................................... 14 8/07—Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Table 4 ............................................................................ 7 Changes to Figure 9 .......................................................................... 8 Changes to Figure 21, Figure 22, and Figure 23 ......................... 10 Changes to Using/Disabling the Latch Feature .......................... 11 Changes to Comparator Hysteresis Section and Figure 29 ....... 13 Changes to Ordering Guide .......................................................... 14 7/05—Revision 0: Initial Version Rev. B | Page 2 of 16 Data Sheet ADCMP580/ADCMP581/ADCMP582 SPECIFICATIONS VCCI = 5.0 V; VEE = −5.0 V; VCCO = 3.3 V; TA = 25°C, unless otherwise noted. Table 1. Parameter DC INPUT CHARACTERISTICS Input Voltage Range Input Differential Range Input Offset Voltage Offset Voltage Temperature Coefficient Input Bias Current Input Bias Current Temperature Coefficient Input Offset Current Input Resistance Input Resistance, Differential Mode Input Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE CHARACTERISTICS Latch Enable Input Impedance Latch-to-Output Delay Latch Minimum Pulse Width ADCMP580 (CML) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP581 (NECL) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time ADCMP582 (PECL) Latch Enable Input Range Latch Enable Input Differential Latch Setup Time Latch Hold Time DC OUTPUT CHARACTERISTICS ADCMP580 (CML) Output Impedance Output Voltage High Level Output Voltage Low Level Output Voltage Differential ADCMP581 (NECL) Output Voltage High Level Output Voltage High Level Output Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Low Level Output Voltage Differential Symbol Test Conditions/Comments VP, VN VOS ΔVOS/dT IP, IN ΔIB/dT Min −2.0 −2.0 −10.0 VCM = −2.0 V to +3.0 V RHYS = ∞ ±4 10 15 50 +2 47 to 53 50 500 48 60 1 Each pin, VTT at ac ground VOD = 200 mV VOD = 200 mV 47 to 53 175 100 Open termination Open termination Open termination AV CMRR ZIN tPLOH, tPLOL tPL −0.8 0.2 tS tH VOD = 200 mV VOD = 200 mV −1.8 0.2 tS tH VOD = 200 mV VOD = 200 mV VCCO − 1.8 0.2 tS tH ZOUT VOH VOL VOH VOH VOH VOL VOL VOL Typ VOD = 200 mV VOD = 200 mV 0.4 95 −90 0.4 70 −65 0.4 30 −25 Max Unit +3.0 +2.0 +10.0 V V mV µV/°C µA nA/°C µA Ω kΩ kΩ dB dB mV 30.0 ±5.0 Ω ps ps 0 0.5 V V ps ps +0.8 0.5 V V ps ps VCCO − 0.8 0.5 V V ps ps 50 Ω to GND 50 Ω to GND 50 Ω to GND −0.10 −0.50 340 50 0 −0.40 395 +0.03 −0.35 450 Ω V V mV 50 Ω to −2 V, TA = 125°C 50 Ω to −2 V, TA = 25°C 50 Ω to −2 V, TA = −55°C 50 Ω to −2 V, TA = 125°C 50 Ω to −2 V, TA = 25°C 50 Ω to −2 V, TA = −55°C 50 Ω to −2.0 V −0.99 −1.06 −1.11 −1.43 −1.50 −1.55 340 −0.87 −0.94 −0.99 −1.26 −1.33 −1.38 395 −0.75 −0.82 −0.87 −1.13 −1.20 −1.25 450 V V V V V V mV Rev. B | Page 3 of 16 ADCMP580/ADCMP581/ADCMP582 Parameter ADCMP582 (PECL) Output Voltage High Level Output Voltage High Level Output Voltage High Level Output Voltage Low Level Output Voltage Low Level Output Voltage Low Level Output Voltage Differential AC PERFORMANCE Propagation Delay Propagation Delay Temperature Coefficient Propagation Delay Skew—Rising Transition to Falling Transition Overdrive Dispersion VOH VOH VOH VOL VOL VOL tPD ΔtPD/dT Test Conditions/Comments VCCO = 3.3 V 50 Ω to VCCO − 2 V, TA = 125°C 50 Ω to VCCO − 2 V, TA = 25°C 50 Ω to VCCO − 2 V, TA = −55°C 50 Ω to VCCO − 2 V, TA = 125°C 50 Ω to VCCO − 2 V, TA = 25°C 50 Ω to VCCO − 2 V, TA = −55°C 50 Ω to VCCO − 2.0 V Min Typ Max Unit VCCO − 0.99 VCCO − 1.06 VCCO − 1.11 VCCO − 1.43 VCCO − 1.50 VCCO − 1.55 340 VCCO − 0.87 VCCO − 0.94 VCCO − 0.99 VCCO − 1.26 VCCO − 1.33 VCCO − 1.35 395 VCCO − 0.75 VCCO − 0.82 VCCO − 0.87 VCCO − 1.13 VCCO − 1.20 VCCO − 1.25 450 V V V V V V mV VOD = 500 mV VOD = 500 mV, 5 V/ns Slew Rate Dispersion Pulse Width Dispersion Duty Cycle Dispersion 5% to 95% Common-Mode Dispersion Equivalent Input Bandwidth1 BWEQ Toggle Rate Deterministic Jitter DJ Deterministic Jitter DJ RMS Random Jitter Minimum Pulse Width Minimum Pulse Width Rise/Fall Time POWER SUPPLY Positive Supply Voltage Negative Supply Voltage ADCMP580 (CML) Positive Supply Current Negative Supply Current Power Dissipation ADCMP581 (NECL) Positive Supply Current Negative Supply Current Power Dissipation ADCMP582 (PECL) Logic Supply Voltage Input Supply Current Output Supply Current Negative Supply Current Power Dissipation Power Supply Rejection (VCCI) Power Supply Rejection (VEE) Power Supply Rejection (VCCO) 1 Symbol Data Sheet RJ PWMIN PWMIN tR, tF 50 mV < VOD < 1.0 V 10 mV < VOD < 200 mV 2 V/ns to 10 V/ns 100 ps to 5 ns 1.0 V/ns, 15 MHz, VCM = 0.0 V VOD = 0.2 V, −2 V < VCM < 3 V 0.0 V to 400 mV input, tR = tF = 25 ps, 20/80 >50% output swing VOD = 500 mV, 5 V/ns, PRBS31 − 1 NRZ, 5 Gbps VOD = 200 mV, 5 V/ns, PRBS31 − 1 NRZ, 10 Gbps VOD = 200 mV, 5 V/ns, 1.25 GHz ΔtPD < 5 ps ΔtPD < 10 ps 20/80 VCCI VEE 180 0.25 10 ps ps/°C ps 10 15 15 15 10 5 8 ps ps ps ps ps ps/V GHz 12.5 15 Gbps ps 25 ps 0.2 100 80 37 ps ps ps ps +4.5 −5.5 +5.0 −5.0 +5.5 −4.5 V V IVCCI IVEE PD VCCI = 5.0 V, 50 Ω to GND VEE = −5.0 V, 50 Ω to GND 50 Ω to GND −50 6 −40 230 8 −34 260 mA mA mW IVCCI IVEE PD VCCI = 5.0 V, 50 Ω to −2 V VEE = −5.0 V, 50 Ω to −2 V 50 Ω to −2 V −35 6 −25 155 8 −19 200 mA mA mW VCCO IVCCI IVCCO IVEE PD PSRVCCI PSRVEE PSRVCCO VCCI = 5.0 V, 50 Ω to VCCO − 2 V VCCO = 5.0 V, 50 Ω to VCCO − 2 V VEE = −5.0 V, 50 Ω to VCCO − 2 V 50 Ω to VCCO − 2 V VCCI = 5.0 V + 5% VEE = −5.0 V + 5% VCCO = 3.3 V + 5% (ADCMP582) +3.3 6 44 −25 310 −75 −60 −75 +5.0 8 55 −19 350 V mA mA mA mW dB dB dB +2.5 −35 Equivalent input bandwidth assumes a simple first-order input response and is calculated with the following formula: BWEQ = 0.22/(trCOMP2 – trIN2), where trIN is the 20/80 transition time of a quasi-Gaussian input edge applied to the comparator input and trCOMP is the effective transition time digitized by the comparator. Rev. B | Page 4 of 16 Data Sheet ADCMP580/ADCMP581/ADCMP582 TIMING INFORMATION Figure 2 shows the ADCMP580/ADCMP581/ADCMP582 compare and latch timing relationships. Table 2 provides the definitions of the terms shown in Figure 2. LATCH ENABLE 50% LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VN VN ± VOS VOD tPLOH tPDL Q OUTPUT 50% tF tPDH tPLOL tR 04672-002 50% Q OUTPUT Figure 2. Comparator Timing Diagram Table 2. Timing Descriptions Symbol tPDH Symbol Description Input-to-Output High Delay tPDL Input-to-Output Low Delay tPLOH Latch Enable-to-Output High Delay tPLOL Latch Enable-to-Output Low Delay tH Minimum Hold Time tPL tS Minimum Latch Enable Pulse Width Minimum Setup Time tR Output Rise Time tF Output Fall Time VN VOD Normal Input Voltage Voltage Overdrive Timing Description Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time that the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the input voltages VP and VN for output true. Difference between the input voltages VP and VN for output false. Rev. B | Page 5 of 16 ADCMP580/ADCMP581/ADCMP582 Data Sheet ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS Table 3. Parameter SUPPLY VOLTAGES Positive Supply Voltage (VCCI to GND) Negative Supply Voltage (VEE to GND) Logic Supply Voltage (VCCO to GND) INPUT VOLTAGES Input Voltage Differential Input Voltage Input Voltage, Latch Enable HYSTERESIS CONTROL PIN Applied Voltage (HYS to VEE) Maximum Input/Output Current OUTPUT CURRENT ADCMP580 (CML) ADCMP581 (NECL) ADCMP582 (PECL) TEMPERATURE Operating Temperature Range, Ambient Operating Temperature, Junction Storage Temperature Range Rating −0.5 V to +6.0 V –6.0 V to +0.5 V −0.5 V to +6.0 V The ADCMP580/ADCMP581/ADCMP582 16-lead LFCSP option has a junction-to-ambient thermal resistance (θJA) of 70°C/W in still air. ESD CAUTION −3.0 V to +4.0 V −2 V to +2 V −2.5 V to +5.5 V −5.5 V to +0.5 V 1 mA −25 mA −40 mA −40 mA −40°C to +125°C 125°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 6 of 16 Data Sheet ADCMP580/ADCMP581/ADCMP582 13 VEE 14 HYS 16 VCCI 15 GND PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VTP 1 VN 3 12 GND ADCMP580/ ADCMP581 TOP VIEW 11 Q 10 Q 9 LE 7 GND VTT 8 LE 6 VCCI 5 VTN 4 NOTES 1. THE METALLIC BACK SURFACE OF THE PACKAGE IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT. IT CAN BE LEFT FLOATING FOR OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE AND THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE APPLICATION BOARD IF IMPROVED THERMAL AND/OR MECHANICAL STABILITY IS DESIRED. 04672-003 VP 2 Figure 3. ADCMP580/ADCMP581 Pin Configuration Table 4. ADCMP580/ADCMP581 Pin Function Descriptions Pin No. 1 2 3 4 5, 16 6 Mnemonic VTP VP VN VTN VCCI LE 7 LE 8 VTT 9, 12 10 GND Q 11 Q 13 14 VEE HYS 15 GND EPAD Description Termination Resistor Return Pin for VP Input. Noninverting Analog Input. Inverting Analog Input. Termination Resistor Return Pin for VN Input. Positive Supply Voltage. Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator being placed into latch mode. LE must be driven in complement with LE. Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator being placed into latch mode. LE must be driven in complement with LE. Termination Return Pin for the LE/LE Input Pins. For the ADCMP580 (CML output stage), this pin must be connected to ground. For the ADCMP581 (ECL output stage), connect this pin to the –2 V termination potential. Digital Ground Pin/Positive Logic Power Supply Terminal. This pin must be connected to the GND pin. Inverting Output. Q is logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions (Pin 6 to Pin 7) for more information. Noninverting Output. Q is logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions (Pin 6 to Pin 7) for more information. Negative Power Supply. Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the VEE supply with a suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 8 for proper sizing of the HYS hysteresis control resistor. Analog Ground. Exposed Pad. The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. B | Page 7 of 16 13 VEE 14 HYS 16 VCCI Data Sheet 15 GND ADCMP580/ADCMP581/ADCMP582 VTP 1 12 VCCO ADCMP582 VN 3 11 Q 10 Q TOP VIEW 9 LE 7 VCCO VTT 8 LE 6 VCCI 5 VTN 4 NOTES 1. THE METALLIC BACK SURFACE OF THE PACKAGE IS NOT ELECTRICALLY CONNECTED TO ANY PART OF THE CIRCUIT. IT CAN BE LEFT FLOATING FOR OPTIMAL ELECTRICAL ISOLATION BETWEEN THE PACKAGE HANDLE AND THE SUBSTRATE OF THE DIE. IT CAN ALSO BE SOLDERED TO THE APPLICATION BOARD IF IMPROVED THERMAL AND/OR MECHANICAL STABILITY IS DESIRED. 04672-004 VP 2 Figure 4. ADCMP582 Pin Configuration Table 5. ADCMP582 Pin Function Descriptions Pin No. 1 2 3 4 5, 16 6 Mnemonic VTP VP VN VTN VCCI LE 7 LE 8 VTT 9, 12 VCCO 10 Q 11 Q 13 14 VEE HYS 15 GND EPAD Description Termination Resistor Return Pin for VP Input. Noninverting Analog Input. Inverting Analog Input. Termination Resistor Return Pin for VN Input. Positive Supply Voltage. Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator being placed into latch mode. LE must be driven in complement with LE. Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator being placed into latch mode. LE must be driven in complement with LE. Termination Return Pin for the LE/LE Input Pins. For the ADCMP582 (PECL output stage), connect this pin to the VCCO –2 V termination potential. Digital Ground Pin/Positive Logic Power Supply Terminal. This pin must be connected to the positive logic power VCCO supply. Inverting Output. Q is logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions (Pin 6 to Pin 7) for more information. Noninverting Output. Q is logic high if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided that the comparator is in compare mode. See the LE/LE descriptions (Pin 6 to Pin 7) for more information. Negative Power Supply. Hysteresis Control. Leave this pin disconnected for zero hysteresis. Connect this pin to the VEE supply with a suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 8 for proper sizing of the HYS hysteresis control resistor. Analog Ground. Exposed Pad. The metallic back surface of the package is not electrically connected to any part of the circuit. It can be left floating for optimal electrical isolation between the package handle and the substrate of the die. It can also be soldered to the application board if improved thermal and/or mechanical stability is desired. Rev. B | Page 8 of 16 Data Sheet ADCMP580/ADCMP581/ADCMP582 TYPICAL PERFORMANCE CHARACTERISTICS VCCI = 5.0 V, VEE = −5.0 V, VCCO = 3.3 V, TA = 25°C, unless otherwise noted. 12 80 70 10 BIAS CURRENT (µA) VIN COMMON-MODE BIAS SWEEP 60 HYSTERESIS (mV) 8 6 4 50 40 30 20 2 0 2 4 COMMON-MODE (V) 0 1 10 100 10k RHYS CONTROL RESISTOR (Ω) Figure 8. Hysteresis vs. RHYS Control Resistor Figure 5. Bias Current vs. Common-Mode Voltage –0.8 2.5 VOH vs. TEMPERATURE OUTPUT (NECL) –0.9 2.4 VOH vs. TEMPERATURE OUTPUT (PECL) –1.0 OUTPUT (V) 2.3 –1.1 –1.2 2.1 VOL vs. TEMPERATURE OUTPUT (NECL) –1.3 2.2 2.0 –1.4 VOL vs. TEMPERATURE OUTPUT (PECL) –5 45 95 145 TEMPERATURE (°C) 1.9 –55 04672-007 –1.5 –55 –5 45 95 04672-010 OUTPUT (V) 1k 04672-009 –2 04672-006 10 0 –4 145 TEMPERATURE (°C) Figure 6. ADCMP581 Output Voltage vs. Temperature Figure 9. ADCMP582 Output Voltage vs. Temperature 80 8 70 7 60 6 50 5 OFFSET (mV) 40 30 4 3 +25°C COMMON-MODE OFFSET SWEEP 20 2 10 1 0 0 100 200 300 400 –IHYST (µA) 500 600 Figure 7. Hysteresis vs. −IHYST 0 –2 0 2 COMMON-MODE (V) Figure 10. A Typical VOS vs. Common-Mode Voltage Rev. B | Page 9 of 16 4 04672-011 –55°C COMMON-MODE OFFSET SWEEP 04672-008 HYSTERESIS (mV) +125°C COMMON-MODE OFFSET SWEEP Data Sheet 5 45 4 43 3 41 2 39 1 37 tR/tF (ps) 0 –1 35 33 31 –2 29 LOT2 CHAR1 RISE LOT2 CHAR1 FALL LOT3 CHAR1 RISE LOT3 CHAR1 FALL –4 –5 –2 –1 QRISE QRISE QFALL QFALL 27 0 1 2 3 VCM (V) 25 –55 04672-012 –3 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 14. ADCMP581 tR/tF vs. Temperature Figure 11. ADCMP580 Propagation Delay Error vs. Common-Mode Voltage 500mV M1 M1 M1 500mV Figure 12. ADCMP580 Eye Diagram at 7.5 Gbps Figure 15. ADCMP582 Eye Diagram at 2.5 Gbps 18 16 12 10 8 6 OD DISPERSION FALL 2 OD DISPERSION RISE 0 0 50 100 150 OVERDRIVE (mV) 200 250 04672-014 DISPERSION (ps) 14 4 20ps/DIV Figure 13. Dispersion vs. Overdrive Rev. B | Page 10 of 16 04672-016 04672-013 M1 04672-015 PROPAGATION DELAY ERROR (ps) ADCMP580/ADCMP581/ADCMP582 Data Sheet ADCMP580/ADCMP581/ADCMP582 TYPICAL APPLICATION CIRCUITS GND VTP VIN 50Ω 50Ω VP VN VP VN Q ADCMP580 CML ADCMP580 Q VTN 50Ω VEE 04672-017 LATCH INPUTS 50Ω 04672-021 1kΩ Figure 16. Zero-Crossing Detector with CML Outputs on the ADCMP580 Figure 20. Disabling the Latch Feature on the ADCMP580 VTP VN Q VP ADCMP581 VN Q ADCMP581 VTN 50Ω 50Ω 750Ω VTT = –2V 04672-018 VTT LATCH INPUTS Figure 17. LVDS to a 50 Ω Back-Terminated (RS) ECL Receiver on the ADCMP581 VN HYS 50Ω 50Ω VEE VCCO Figure 18. Adding Hysteresis Using the HYS Control on the ADCMP580 GND 50Ω VIN + VTH – 50Ω Q ADCMP580 LATCH INPUTS 04672-020 Q Figure 19. Comparator with −2 to +3 V Input Range on the ADCMP580 Rev. B | Page 11 of 16 50Ω VTT VEE ADCMP582 750Ω 04672-019 0Ω TO 5kΩ 50Ω Figure 21. Disabling the Latch Feature on the ADCMP581 VP ADCMP580 RSECL 04672-022 VN RSPECL 50Ω 50Ω VTT = VCCO – 2V 04672-023 VP VP Figure 22. Disabling the Latch Feature on the ADCMP582 ADCMP580/ADCMP581/ADCMP582 Data Sheet APPLICATIONS INFORMATION GND POWER/GROUND LAYOUT AND BYPASSING The ADCMP580/ADCMP581/ADCMP582 family of comparators is designed for very high speed applications. Consequently, high speed design techniques must be used to achieve the specified performance. It is critically important to use low impedance supply planes, particularly for the negative supply (VEE), the output supply plane (VCCO), and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for the switching currents ensures the best possible performance in the target application. Q Q 16mA VEE Figure 23. Simplified Schematic Diagram of the ADCMP580 CML Output Stage GND/VCCO Q ADCMP580/ADCMP581/ADCMP582 FAMILY OF OUTPUT STAGES Q VEE 04672-025 Specified propagation delay dispersion performance is achieved by using proper transmission line terminations. The outputs of the ADCMP580 family comparators are designed to directly drive 400 mV into 50 Ω cable or microstrip/stripline transmission lines terminated with 50 Ω referenced to the proper return. The CML output stage for the ADCMP580 is shown in the simplified schematic diagram in Figure 23. Each output is backterminated with 50 Ω for best transmission line matching. The outputs of the ADCMP581/ADCMP582 are illustrated in Figure 24; they must be terminated to −2 V for ECL outputs of ADCMP581 and VCCO − 2 V for PECL outputs of ADCMP582. As an alternative, Thevenin equivalent termination networks can also be used. If these high speed signals must be routed more than a centimeter, either microstrip or stripline techniques are required to ensure proper transition times and to prevent excessive output ringing and pulse width-dependent propagation delay dispersion. 50Ω 04672-024 It is also important to adequately bypass the input and output supplies. A 1 µF electrolytic bypass capacitor must be placed within several inches of each power supply pin to ground. In addition, multiple high quality 0.1 µF bypass capacitors must be placed as close as possible to each of the VEE, VCCI, and VCCO supply pins and must be connected to the GND plane with redundant vias. High frequency bypass capacitors must be carefully selected for minimum inductance and ESR. Parasitic layout inductance must be strictly avoided to maximize the effectiveness of the bypass at high frequencies. 50Ω Figure 24. Simplified Schematic Diagram of the ADCMP581/ADCMP582 ECL/PECL Output Stage USING/DISABLING THE LATCH FEATURE The latch inputs (LE/LE) are active low for latch mode and are internally terminated with 50 Ω resistors to the VTT pin. When using the ADCMP580, VTT must be connected to ground. When using the ADCMP581, VTT must be connected to −2 V. When using the ADCMP582, VTT must be connected externally to VCCO − 2 V, preferably with its own low inductance plane. When using the ADCMP580, the latch function can be disabled by connecting the LE pin to VEE with an external pull-down resistor and by leaving the LE pin to ground. To prevent excessive power dissipation, the resistor must be 1 kΩ for the ADCMP580. When using the ADCMP581 comparators, the latch can be disabled by connecting the LE pin to VEE with an external 750 Ω resistor and leaving the LE pin connected to −2 V. The idea is to create an approximate 0.5 V offset using the internal resistor as half of the voltage divider. Connect the VTT pin as recommended. Rev. B | Page 12 of 16 Data Sheet ADCMP580/ADCMP581/ADCMP582 OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION As with any high speed comparator, proper design and layout techniques are essential to obtaining the specified performance. Stray capacitance, inductance, inductive power, and ground impedances or other layout issues can severely limit performance and can cause oscillation. Discontinuities along input and output transmission lines can also severely limit the specified pulse width dispersion performance. The ADCMP580/ADCMP581/ADCMP582 family of comparators has been specifically designed to reduce propagation delay dispersion over a wide input overdrive range of 5 mV to 500 mV. Propagation delay dispersion is a change in propagation delays that results from a change in the degree of overdrive or slew rate (how far or how fast the input signal exceeds the switching threshold). The overall result is a higher degree of timing accuracy. For applications in a 50 Ω environment, input and output matching have a significant impact on data-dependent (or deterministic) jitter (DJ) and pulse width dispersion performance. The ADCMP580/ADCMP581/ADCMP582 family of comparators provides internal 50 Ω termination resistors for both VP and VN inputs. The return side for each termination is pinned out separately with the VTP and VTN pins, respectively. If a 50 Ω termination is desired at one or both of the VP/VN inputs, the VTP and VTN pins can be connected (or disconnected) to (from) the desired termination potential as appropriate. The termination potential must be carefully bypassed using ceramic capacitors as discussed previously to prevent undesired aberrations on the input signal due to parasitic inductance in the termination return path. If a 50 Ω termination is not desired, either one or both of the VTP/VTN termination pins can be left disconnected. In this case, the open pins must be left floating with no external pull downs or bypassing capacitors. Propagation delay dispersion is a specification that becomes important in critical timing applications, such as data communications, automatic test and measurement, instrumentation, and event-driven applications, such as pulse spectroscopy, nuclear instrumentation, and medical imaging. Dispersion is defined as the variation in the overall propagation delay as the input overdrive conditions are changed (see Figure 25 and Figure 26). For the ADCMP580/ADCMP581/ADCMP582 family of comparators, dispersion is typically