ADE7763ARSZ

Single-Phase Active and Apparent Energy Metering IC ADE7763 Data Sheet FEATURES perform active and apparent energy measurements, line-voltage period measurements, and rms calculation on the voltage and current channels. The selectable on-chip digital integrator provides direct interface to di/dt current sensors such as Rogowski coils, eliminating the need for an external analog integrator and resulting in excellent long-term stability and precise phase matching between the current and the voltage channels. High accuracy; supports IEC 61036/60687, IEC62053-21, and IEC62053-22 On-chip digital integrator enables direct interface-to-current sensors with di/dt output A PGA in the current channel allows direct interface to shunts and current transformers Active and apparent energy, sampled waveform, and current and voltage rms Less than 0.1% error in active energy measurement over a dynamic range of 1000 to 1 at 25°C Positive-only energy accumulation mode available On-chip user programmable threshold for line voltage surge and SAG and PSU supervisory Digital calibration for power, phase, and input offset On-chip temperature sensor (±3°C typical) SPI®-compatible serial interface Pulse output with programmable frequency Interrupt request pin (IRQ) and status register Reference 2.4 V with external overdrive capability Single 5 V supply, low power (25 mW typical) The ADE7763 provides a serial interface to read data and a pulse output frequency (CF) that is proportional to the active power. Various system calibration features such as channel offset correction, phase calibration, and power calibration ensure high accuracy. The part also detects short duration, low or high voltage variations. The positive-only accumulation mode gives the option to accumulate energy only when positive power is detected. An internal no-load threshold ensures that the part does not exhibit any creep when there is no load. The zero-crossing output (ZX) produces a pulse that is synchronized to the zero-crossing point of the line voltage. This signal is used internally in the line cycle active and apparent energy accumulation modes, which enables faster calibration. GENERAL DESCRIPTION The interrupt status register indicates the nature of the interrupt, and the interrupt enable register controls which event produces an output on the IRQ pin, an open-drain, active low logic output. The ADE77631 features proprietary ADCs and fixed function DSP for high accuracy over large variations in environmental conditions and time. The ADE7763 incorporates two second-order, 16-bit Σ-∆ ADCs, a digital integrator (on Ch1), reference circuitry, a temperature sensor, and all the signal processing required to The ADE7763 is available in a 20-lead SSOP package. FUNCTIONAL BLOCK DIAGRAM AVDD DVDD RESET INTEGRATOR PGA WGAIN[11:0] MULTIPLIER V1P DGND ADE7763 LPF2 dt ADC V1N HPF1 TEMP SENSOR APOS[15:0] CFNUM[11:0] IRMSOS[11:0] LPF3 PGA VRMSOS[11:0] Φ ADC V2N PHCAL[5:0] AGND CFDEN[11:0] |x| LPF1 LPF3 4kΩ REFIN/OUT CF VADIV[7:0] % % WDIV[7:0] ZX SAG REGISTERS AND SERIAL INTERFACE CLKIN CLKOUT U.S. Patents 5,745,323; 5,760,617; 5,862,069; 5,872,469. Rev. C Document Feedback DIN DOUT SCLK CS IRQ 04481-A-001 V2P 2.4V REFERENCE DFC VAGAIN[11:0] x2 Figure 1. 1 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADE7763 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Active Power Calculation .......................................................... 25 General Description ......................................................................... 1 Energy Calculation ..................................................................... 27 Functional Block Diagram .............................................................. 1 Power Offset Calibration ........................................................... 29 Revision History ............................................................................... 3 Energy-to-Frequency Conversion............................................ 29 Specifications..................................................................................... 4 Line Cycle Energy Accumulation Mode ................................. 31 Timing Characteristics ................................................................ 6 Positive-Only Accumulation Mode ......................................... 31 Absolute Maximum Ratings ............................................................ 7 No-Load Threshold.................................................................... 31 ESD Caution .................................................................................. 7 Apparent Power Calculation ..................................................... 32 Terminology ...................................................................................... 8 Apparent Energy Calculation ................................................... 33 Pin Configuration and Function Descriptions ............................. 9 Line Apparent Energy Accumulation ...................................... 34 Typical Performance Characteristics ........................................... 11 Energies Scaling .......................................................................... 35 Theory of Operation ...................................................................... 14 Calibrating an Energy Meter .................................................... 35 Analog Inputs .............................................................................. 14 CLKIN Frequency ...................................................................... 44 di/dt Current Sensor and Digital Integrator ........................... 15 Suspending Functionality.......................................................... 45 Zero-Crossing Detection ........................................................... 16 Checksum Register..................................................................... 45 Period Measurement .................................................................. 17 Serial Interface ............................................................................ 45 Power Supply Monitor ............................................................... 17 Registers ........................................................................................... 48 Line Voltage Sag Detection ....................................................... 18 Register Descriptions ..................................................................... 51 Peak Detection ............................................................................ 18 Communication Register .......................................................... 51 Interrupts ..................................................................................... 19 Mode Register (0x09)................................................................. 51 Temperature Measurement ....................................................... 20 Analog-to-Digital Conversion .................................................. 20 Interrupt Status Register (0x0B), Reset Interrupt Status Register (0x0C), Interrupt Enable Register (0x0A) ............... 53 Channel 1 ADC .......................................................................... 21 CH1OS Register (0x0D) ............................................................ 54 Channel 2 ADC .......................................................................... 23 Outline Dimensions ....................................................................... 55 Phase Compensation.................................................................. 24 Ordering Guide .......................................................................... 55 Rev. C | Page 2 of 56 Data Sheet ADE7763 REVISION HISTORY 1/13—Rev. B to Rev. C Changes to Figure 1........................................................................... 1 Moved Revision History Section ..................................................... 3 Changes to Table 2 ............................................................................ 6 Changes to Table 4 ............................................................................ 9 Changes to Figure 24 ......................................................................14 Changes to Zero-Crossing Detection Section .............................16 Changes to Period Measurement Section ....................................17 Changes to Peak Level Record Section .........................................18 Change to Figure 37 ........................................................................19 Changes to Figure 43, Channel 1 Sampling Section, and Channel 1 RMS Calculation Section ...........................................22 Changes to Channel 1 RMS Offset Compensation Section and Channel 2 Sampling Section ..........................................................23 Changes to Channel 2 RMS Calculation Section and Channel 2 RMS Offset Compensation Section ..............................................24 Changes to Energy Calculation Section .......................................27 Changes to Power Offset Calibration Section .............................29 Changes to Positive-Only Accumulation Mode Section............31 Changes to Serial Interface Section ..............................................45 Changes to Table 9 ..........................................................................48 Change to Table 12, Bit 1 Description ..........................................53 Changes to Ordering Guide ...........................................................55 7/09—Rev. A to Rev. B Changes to Zero Crossing Detection Section ............................. 15 Changes to Period Measurement Section .................................... 16 Changes to Channel 1 RMS Offset Calculation Section ............ 22 Changes to Channel 1 RMS Offset Compensation Section ...... 22 Changes to Figure 48 ...................................................................... 23 Changes to Channel 2 RMS Calculation Section........................ 23 Changes to Table 11, Bit 15 Description ...................................... 51 Changes to Table 12, Bit 4 Description ........................................ 52 10/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Period Measurement Section .................................. 16 Changes to Temperature Measurement Section ....................... 19 Change to Energy-to-Frequency Conversion Section ............. 28 Update to Figure 61....................................................................... 29 Change to Apparent Energy Calculation Section ..................... 32 Change to Description of AEHF and VAEHF Bits ................... 52 Changes to Ordering Guide ......................................................... 54 4/04—Revision 0: Initial Version Rev. C | Page 3 of 56 ADE7763 Data Sheet SPECIFICATIONS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = –40°C to +85°C. Table 1. Specifications 1, 2 Parameter ENERGY MEASUREMENT ACCURACY Active Power Measurement Error Channel 1 Range = 0.5 V Full Scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel 1 Range = 0.25 V Full Scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Channel 1 Range = 0.125 V Full Scale Gain = 1 Gain = 2 Gain = 4 Gain = 8 Active Power Measurement Bandwidth Phase Error 1 between Channels AC Power Supply Rejection1 Output Frequency Variation (CF) DC Power Supply Rejection1 Output Frequency Variation (CF) IRMS Measurement Error IRMS Measurement Bandwidth VRMS Measurement Error VRMS Measurement Bandwidth ANALOG INPUTS 3 Maximum Signal Levels Input Impedance (dc) Bandwidth Gain Error1, 3 Channel 1 Range = 0.5 V Full Scale Range = 0.25 V Full Scale Range = 0.125 V Full Scale Channel 2 Offset Error 1 Channel 1 Channel 2 WAVEFORM SAMPLING Channel 1 Signal-to-Noise Plus Distortion Bandwidth (–3 dB) Channel 2 Signal-to-Noise Plus Distortion Bandwidth (–3 dB) Spec Unit Test Conditions/Comments 0.1 0.1 0.1 0.1 % typ % typ % typ % typ CLKIN = 3.579545 MHz Channel 2 = 300 mV rms/60 Hz, gain = 2 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 0.1 0.1 0.1 0.2 % typ % typ % typ % typ Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 0.1 0.1 0.2 0.2 14 ±0.05 % typ % typ % typ % typ kHz max Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 Over a dynamic range 1000 to 1 0.2 % typ ±0.3 % typ 0.5 14 0.5 140 % typ kHz % typ Hz ±0.5 390 14 V max k min kHz ±4 ±4 ±4 ±4 ±32 ±13 ±32 ±13 % typ % typ % typ % typ mV max mV max mV max mV max 62 14 dB typ kHz 60 140 dB typ Hz Line frequency = 45 Hz to 65 Hz, HPF on AVDD = DVDD = 5 V + 175 mV rms/120 Hz Channel 1 = 20 mV rms, gain = 16, range = 0.5 V Channel 2 = 300 mV rms/60 Hz, gain = 1 AVDD = DVDD = 5 V ± 250 mV dc Channel 1 = 20 mV rms/60 Hz, gain = 16, range = 0.5 V Channel 2 = 300 mV rms/60 Hz, gain = 1 Over a dynamic range 100 to 1 Over a dynamic range 20 to 1 See the Analog Inputs section V1P, V1N, V2N, and V2P to AGND CLKIN/256, CLKIN = 3.579545 MHz External 2.5 V reference, gain = 1 on Channels 1 and 2 V1 = 0.5 V dc V1 = 0.25 V dc V1 = 0.125 V dc V2 = 0.5 V dc Gain 1 Gain 16 Gain 1 Gain 16 Sampling CLKIN/128, 3.579545 MHz/128 = 27.9 kSPS See the Channel 1 Sampling section 150 mV rms/60 Hz, range = 0.5 V, gain = 2 CLKIN = 3.579545 MHz See the Channel 2 Sampling section 150 mV rms/60 Hz, gain = 2 CLKIN = 3.579545 MHz Rev. C | Page 4 of 56 Data Sheet Parameter REFERENCE INPUT REFIN/OUT Input Voltage Range Input Capacitance ON-CHIP REFERENCE Reference Error Current Source Output Impedance Temperature Coefficient CLKIN Input Clock Frequency LOGIC INPUTS RESET, DIN, SCLK, CLKIN, and CS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN LOGIC OUTPUTS SAG and IRQ Output High Voltage, VOH Output Low Voltage, VOL ZX and DOUT Output High Voltage, VOH Output Low Voltage, VOL CF Output High Voltage, VOH Output Low Voltage, VOL POWER SUPPLY AVDD DVDD AIDD DIDD ADE7763 Spec Unit Test Conditions/Comments 2.6 2.2 10 V max V min pF max 2.4 V + 8% 2.4 V – 8% ±200 10 3.4 30 mV max µA max kΩ min ppm/°C typ 4 1 MHz max MHz min 2.4 0.8 ±3 10 V min V max µA max pF max Nominal 2.4 V at REFIN/OUT pin All specifications CLKIN of 3.579545 MHz DVDD = 5 V ± 10% DVDD = 5 V ± 10% Typically 10 nA, VIN = 0 V to DVDD 4 0.4 V min V max Open-drain outputs, 10 kΩ pull-up resistor ISOURCE = 5 mA ISINK = 0.8 mA 4 0.4 V min V max ISOURCE = 5 mA ISINK = 0.8 mA 4 1 V min V max 4.75 5.25 4.75 5.25 3 4 V min V max V min V max mA max mA max ISOURCE = 5 mA ISINK = 7 mA For specified performance 5 V – 5% 5 V + 5% 5 V – 5% 5 V + 5% Typically 2.0 mA Typically 3.0 mA See the Terminology section for explanation of specifications. See the plots in the Typical Performance Characteristics section. 3 See the Analog Inputs section. 1 2 200 µA +2.1V CL 50pF 1.6mA IOH 04481-A-002 TO OUTPUT PIN IOl Figure 2. Load Circuit for Timing Specifications Rev. C | Page 5 of 56 ADE7763 Data Sheet TIMING CHARACTERISTICS AVDD = DVDD = 5 V ± 5%, AGND = DGND = 0 V, on-chip reference, CLKIN = 3.579545 MHz XTAL, TMIN to TMAX = −40°C to +85°C. Table 2. Timing Characteristics1, 2 Parameter Write Timing t1 t2 t3 t4 t5 t6 t7 t8 Spec Unit Test Conditions/Comments 50 50 50 10 5 4 3200 100 ns min ns min ns min ns min ns min μs min ns min ns min) CS falling edge to first SCLK falling edge. SCLK logic high pulse width. SCLK logic low pulse width. Valid data setup time before falling edge of SCLK. Data hold time after SCLK falling edge. Minimum time between the end of data byte transfers. Minimum time between byte transfers during a serial write. CS hold time after SCLK falling edge. Read Timing t93 4 μs min t10 t11 50 30 ns min ns min t124 100 10 100 10 ns max ns min ns max ns min Minimum time between read command (i.e., a write to communication register) and data read. Minimum time between data byte transfers during a multibyte read. Data access time after SCLK rising edge following a write to the communication register. Bus relinquish time after falling edge of SCLK. t135 Bus relinquish time after rising edge of CS. 1 Sample tested during initial release and after any redesign or process change that could affect this parameter. All input signals are specified with tr = tf = 5 ns (10% to 90%) and timed from a voltage level of 1.6 V. 2 See Figure 3, Figure 4, and the Serial Interface section. 3 Minimum time between read command and data read for all registers except waveform register, which is t9 = 500 ns min. 4 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V. 5 Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. t8 CS t6 t3 SCLK t4 t2 0 1 DIN A5 t7 t7 A4 t5 A3 A2 A1 DB7 A0 MOST SIGNIFICANT BYTE COMMAND BYTE DB0 DB7 DB0 LEAST SIGNIFICANT BYTE 04481-A-003 t1 Figure 3. Serial Write Timing CS t1 t13 t9 SCLK 0 0 A5 A4 A3 A2 A1 A0 DOUT DB7 COMMAND BYTE t12 t11 t11 DB0 MOST SIGNIFICANT BYTE Figure 4. Serial Read Timing Rev. C | Page 6 of 56 DB7 DB0 LEAST SIGNIFICANT BYTE 04481-A-004 DIN t10 Data Sheet ADE7763 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 3. Parameter AVDD to AGND DVDD to DGND DVDD to AVDD Analog Input Voltage to AGND V1P, V1N, V2P, and V2N Reference Input Voltage to AGND Digital Input Voltage to DGND Digital Output Voltage to DGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature 20-Lead SSOP, Power Dissipation θJA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 s) Infrared (15 s) Rating –0.3 V to +7 V –0.3 V to +7 V –0.3 V to +0.3 V –6 V to +6 V –0.3 V to AVDD + 0.3 V –0.3 V to DVDD + 0.3 V –0.3 V to DVDD + 0.3 V –40°C to +85°C –65°C to +150°C 150°C 450 mW 112°C/W 215°C 220°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. C | Page 7 of 56 ADE7763 Data Sheet TERMINOLOGY Measurement Error The error associated with the energy measurement made by the ADE7763 is defined by the following formula: Percent Error =  Energy Register ADE7763 − True Energy    × 100%   True Energy   Phase Error between Channels The digital integrator and the high-pass filter (HPF) in Channel 1 have a nonideal phase response. To offset this phase response and equalize the phase response between channels, two phasecorrection networks are placed in Channel 1: one for the digital integrator and the other for the HPF. The phase correction networks correct the phase response of the corresponding component and ensure a phase match between Channel 1 (current) and Channel 2 (voltage) to within ±0.1° over a range of 45 Hz to 65 Hz with the digital integrator off. With the digital integrator on, the phase is corrected to within ±0.4° over a range of 45 Hz to 65 Hz. Power Supply Rejection This quantifies the ADE7763 measurement error as a percentage of the reading when the power supplies are varied. For the ac PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when an ac (175 mV rms/120 Hz) signal is introduced to the supplies. Any error introduced by this ac signal is expressed as a percentage of the reading—see the Measurement Error definition. For the dc PSR measurement, a reading at nominal supplies (5 V) is taken. A second reading is obtained with the same input signal levels when the supplies are varied ±5%. Any error introduced is again expressed as a percentage of the reading. ADC Offset Error The dc offset associated with the analog inputs to the ADCs. It means that with the analog inputs connected to AGND, the ADCs still see a dc analog input signal. The magnitude of the offset depends on the gain and input range selection—see the Typical Performance Characteristics section. However, when HPF1 is switched on, the offset is removed from Channel 1 (current) and the power calculation is not affected by this offset. The offsets can be removed by performing an offset calibration— see the Analog Inputs section. Gain Error The difference between the measured ADC output code (minus the offset) and the ideal output code—see the Channel 1 ADC and Channel 2 ADC sections. It is measured for each of the input ranges on Channel 1 (0.5 V, 0.25 V, and 0.125 V). The difference is expressed as a percentage of the ideal code. Rev. C | Page 8 of 56 Data Sheet ADE7763 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET 1 20 DIN DVDD 2 19 DOUT AVDD 3 18 SCLK V1P 4 17 CS V1N 5 ADE7763 V2P 7 14 IRQ AGND 8 13 SAG REFIN/OUT 9 12 ZX DGND 10 11 CF 04481-A-005 16 CLKOUT TOP VIEW V2N 6 (Not to Scale) 15 CLKIN Figure 5. Pin Configuration (SSOP Package) Table 4. Pin Function Descriptions Pin No. 1 Mnemonic RESET 2 DVDD 3 AVDD 4, 5 V1P, V1N 6, 7 V2N, V2P 8 AGND 9 REFIN/OUT 10 DGND 11 CF 12 ZX 13 SAG Description Reset Pin 1. A logic low on this pin holds the ADCs and digital circuitry (including the serial interface) in a reset condition. Digital Power Supply. This pin provides the supply voltage for the digital circuitry. The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be decoupled to DGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor. Analog Power Supply. This pin provides the supply voltage for the analog circuitry. The supply should be maintained at 5 V ± 5% for specified operation. Minimize power supply ripple and noise at this pin by using proper decoupling. The typical performance graphs show the power supply rejection performance. This pin should be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor. Analog Inputs for Channel 1. This channel is intended for use with a di/dt current transducer, i.e., a Rogowski coil or another current sensor such as a shunt or current transformer (CT). These inputs are fully differential voltage inputs with maximum differential input signal levels of ±0.5 V, ±0.25 V, and ±0.125 V, depending on the full-scale selection—see the Analog Inputs section. Channel 1 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry and can sustain an overvoltage of ±6 V without risk of permanent damage. Analog Inputs for Channel 2. This channel is intended for use with the voltage transducer. These inputs are fully differential voltage inputs with a maximum differential signal level of ±0.5 V. Channel 2 also has a PGA with gain selections of 1, 2, 4, 8, or 16. The maximum signal level at these pins with respect to AGND is ±0.5 V. Both inputs have internal ESD protection circuitry and can sustain an overvoltage of ±6 V without risk of permanent damage. Analog Ground Reference. This pin provides the ground reference for the analog circuitry, i.e., ADCs and reference. This pin should be tied to the analog ground plane or to the quietest ground reference in the system. Use this quiet ground reference for all analog circuitry, such as antialiasing filters and current and voltage transducers. To minimize ground noise around the ADE7763, connect the quiet ground plane to the digital ground plane at only one point. It is acceptable to place the entire device on the analog ground plane. Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of 2.4 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source can also be connected at this pin. In either case, this pin should be decoupled to AGND with a 10 µF capacitor in parallel with a 100nF ceramic capacitor. Digital Ground Reference. This pin provides the ground reference for the digital circuitry, i.e., multiplier, filters, and digital-to-frequency converter. Because the digital return currents in the ADE7763 are small, it is acceptable to connect this pin to the analog ground plane of the system. However, high bus capacitance on the DOUT pin could result in noisy digital current, which could affect performance. Calibration Frequency Logic Output. The CF logic output gives active power information. This output is intended to be used for operational and calibration purposes. The full-scale output frequency can be adjusted by writing to the CFDEN and CFNUM registers—see the Energy-to-Frequency Conversion section. Voltage Waveform (Channel 2) Zero-Crossing Output. This output toggles logic high and logic low at the zero crossing of the differential signal on Channel 2—see the Zero-Crossing Detection section. This open-drain logic output goes active low when either no zero crossings are detected or a low voltage threshold (Channel 2) is crossed for a specified duration—see the Line Voltage Sag Detection section. Rev. C | Page 9 of 56 ADE7763 Data Sheet Pin No. 14 Mnemonic IRQ 15 CLKIN 16 CLKOUT 17 CS 18 SCLK 19 DOUT 20 DIN 1 Description Interrupt Request Output. This is an active low, open-drain logic output. Maskable interrupts include active energy register rollover, active energy register at half level, and arrivals of new waveform samples—see the Interrupts section. Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock source for the ADE7763. The clock frequency for specified operation is 3.579545 MHz. Ceramic load capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal manufacturer’s data sheet for load capacitance requirements. A crystal can be connected across this pin and CLKIN, as described for Pin 15, to provide a clock source for the ADE7763. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN or a crystal is being used. Chip Select1. Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7763 to share the serial bus with several other devices—see the Serial Interface section. Serial Clock Input for the Synchronous Serial Interface1. All serial data transfers are synchronized to this clock—see the Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source that has a slow edge transition time, such as an opto-isolator output. Data Output for the Serial Interface. Data is shifted out at this pin upon the rising edge of SCLK. This logic output is normally in a high impedance state, unless it is driving data onto the serial data bus—see the Serial Interface section. Data Input for the Serial Interface. Data is shifted in at this pin upon the falling edge of SCLK—see the Serial Interface section. It is recommended to drive the RESET, SCLK, and CS pins with either a push-pull without an external series resistor or with an open-collector with a 10 kΩ pull-up Pulldown resistors are not recommended because under some conditions, they may interact with internal circuitry. Rev. C | Page 10 of 56 Data Sheet ADE7763 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.4 GAIN = 1 INTEGRATOR OFF INTERNAL REFERENCE 0.3 0.2 0.6 +25°C, PF = 1 0.1 0 –40°C, PF = 0.5 –0.1 –0.2 +25°C, PF = 0.5 –0.3 100 –1.0 0.1 100 1.0 GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE 0.8 0.6 0.4 0 +25°C, PF = 1 –0.2 GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE 0.4 +85°C, PF = 1 0.2 ERROR (%) –0.4 0.2 –40°C, PF = 1 +25°C, PF = 1 0 –0.2 –0.4 –0.6 +25°C, PF = 0.5 +85°C, PF = 0.5 –40°C, PF = 0.5 –0.6 –0.8 10 100 FULL-SCALE CURRENT (%) –1.0 0.1 04481-A-007 1 1 10 100 FULL-SCALE CURRENT (%) Figure 7. Active Energy as a Percentage of Reading (Gain = 8) over Temperature with Internal Reference and Integrator Off 04481-A-010 –0.8 –1.0 0.1 Figure 10. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with External Reference and Integrator Off 1.0 0.5 GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE 0.3 0.4 0.2 ERROR (%) +85°C, PF = 0.5 0.2 0 –0.2 +25°C, PF = 1 +25°C, PF = 0.5 –0.4 5.25V 0.1 0 5.00V –0.1 –0.2 –0.6 –40°C, PF = 0.5 –0.3 –0.8 4.75V –0.4 1 10 100 FULL-SCALE CURRENT (%) 04481-A-008 –1.0 0.1 GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE 0.4 Figure 8. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator Off –0.5 0.1 1 10 100 FULL-SCALE CURRENT (%) Figure 11. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Supply with Internal Reference and Integrator Off Rev. C | Page 11 of 56 04481-A-080 ERROR (%) 10 Figure 9. Active Energy Error as a Percentage of Reading (Gain = 8) over Temperature with External Reference and Integrator Off 1.0 ERROR (%) 1 FULL-SCALE CURRENT (%) Figure 6. Active Energy Error as a Percentage of Reading (Gain = 1) over Power Factor with Internal Reference and Integrator Off 0.6 +85°C, PF = 1 04481-A-009 10 04481-A-006 1 FULL-SCALE CURRENT (%) 0.8 0 –0.2 –0.8 –0.6 0.1 0.6 –40°C, PF = 1 –0.6 –0.5 0.8 +25°C, PF = 1 0.2 –0.4 +85°C, PF = 0.5 –0.4 GAIN = 8 INTEGRATOR OFF EXTERNAL REFERENCE 0.4 ERROR (%) ERROR (%) 0.8 ADE7763 Data Sheet 1.2 1.0 GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE 1.0 0.8 0.6 0.8 0.4 PF = 0.5 ERROR (%) 0.4 0.2 PF = 1 0 +25°C, PF = 0.5 +25°C, PF = 1 –0.2 –40°C, PF = 0.5 –0.6 –0.4 47 49 51 53 55 57 59 61 63 65 –1.0 0.1 04481-A-012 45 1 10 100 FULL-SCALE CURRENT (%) Figure 12. Active Energy Error as a Percentage of Reading (Gain = 8) over Frequency with Internal Reference and Integrator Off 04481-A-016 –0.8 FREQUENCY (Hz) Figure 15. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Factor with Internal Reference and Integrator On 1.0 1.0 GAIN = 8 INTEGRATOR OFF INTERNAL REFERENCE 0.8 0.6 0.8 GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE 0.6 0.4 PF = 1 0 PF = 0.5 –0.2 0 –0.4 –0.6 –0.6 –0.8 –0.8 1 10 100 FULL-SCALE CURRENT (%) +25°C, PF = 1 –0.2 –0.4 –1.0 0.1 +85°C, PF = 1 0.2 –40°C, PF = 1 –1.0 0.1 1 10 100 FULL-SCALE CURRENT (%) Figure 13. IRMS Error as a Percentage of Reading (Gain = 8) with Internal Reference and Integrator Off 04481-A-015 ERROR (%) 0.4 0.2 04481-A-013 ERROR (%) 0 –0.4 –0.2 Figure 16. Active Energy Error as a Percentage of Reading (Gain = 8) over Temperature with External Reference and Integrator On 0.5 3.0 GAIN = 1 EXTERNAL REFERENCE 0.4 GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE 2.5 0.3 2.0 0.2 1.5 0.1 1.0 ERROR (%) PF = 0.5 0 –0.1 0.5 –0.5 –0.3 –1.0 –0.4 –1.5 –0.5 1 10 100 FULL-SCALE VOLTAGE (%) Figure 14. VRMS Error as a Percentage of Reading (Gain = 1) with External Reference PF = 1 0 –0.2 04481-A-020 ERROR (%) +85°C, PF = 0.5 0.2 –2.0 45 47 49 51 53 55 57 59 61 63 65 FREQUENCY (Hz) Figure 17. Active Energy Error as a Percentage of Reading (Gain = 8) over Frequency with Internal Reference and Integrator On Rev. C | Page 12 of 56 04481-A-017 ERROR (%) 0.6 –0.6 GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE Data Sheet ADE7763 0.5 16 GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE 0.4 0.3 14 5.25V 12 10 0.1 5.00V 0 HITS ERROR (%) 0.2 8 –0.1 6 –0.2 4.75V 4 –0.3 1 10 0 –15 04481-A-081 –0.5 0.1 100 FULL-SCALE CURRENT (%) –10 –5 0 5 10 15 04481-A-021 2 –0.4 20 CH1 OFFSET (0p5V_1X) (mV) Figure 18. Active Energy Error as a Percentage of Reading (Gain = 8) over Power Supply with Internal Reference and Integrator On Figure 20. Channel 1 Offset (Gain = 1) 0.5 GAIN = 8 INTEGRATOR ON INTERNAL REFERENCE 0.4 0.3 ERROR (%) 0.2 0.1 PF = 0.5 0 –0.1 PF = 1 –0.2 –0.3 –0.5 0.1 1 10 04481-A-019 –0.4 100 FULL-SCALE CURRENT (%) Figure 19. IRMS Error as a Percentage of Reading (Gain = 8) with Internal Reference and Integrator On VDD 33nF 33nF 100 1k 33nF 33nF 100nF AVDD DVDD RESET DIN V1P DOUT V1N U1 SCLK ADE7763 V2N 33nF 600k 110V 1k 10F CLKIN V2P 100nF CURRENT TRANSFORMER 1k TO SPI BUS (USED ONLY FOR CALIBRATION) SAG REFIN/OUT 33nF RB 1k 33nF Y1 3.58MHz 22pF 1k AVDD DVDD RESET DIN V1P DOUT V1N U1 22pF 1k CLKIN V2P 10F TO FREQUENCY COUNTER CHANNEL 1 GAIN = 8 CHANNEL 2 GAIN = 1 PS2501-1 100nF TO SPI BUS (USED ONLY FOR CALIBRATION) Y1 3.58MHz 22pF 22pF IRQ 33nF SAG NOT CONNECTED U3 10F CS V2N 600k 110V AGND DGND SCLK ADE7763 33nF ZX CF 100nF CLKOUT IRQ 33nF 100nF 10F I CS CLKOUT 1k 10F REFIN/OUT NOT CONNECTED ZX CF U3 AGND DGND CT TURN RATIO = 1800:1 CHANNEL 2 GAIN = 1 GAIN 1 (CH1) RB 10 1 1.21 8 TO FREQUENCY COUNTER PS2501-1 Figure 22. Test Circuit for Performance Curves with Integrator Off Figure 21. Test Circuit for Performance Curves with Integrator On Rev. C | Page 13 of 56 04481-A-023 100nF di/dt CURRENT SENSOR 100 1k 04481-A-022 10F I VDD ADE7763 Data Sheet THEORY OF OPERATION ANALOG INPUTS Table 5. Maximum Input Signal Levels for Channel 1 The ADE7763 has two fully differential voltage input channels. The maximum differential input voltage for input pairs V1P/V1N and V2P/V2N is ±0.5 V. In addition, the maximum signal level on analog inputs for V1P/V1N and V2P/V2N is ±0.5 V with respect to AGND. Max Signal Channel 1 0.5 V 0.25 V 0.125 V 0.0625 V 0.0313 V 0.0156 V 0.00781 V 0 7 6 5 GAIN[7:0] 4 3 2 1 0 0 0 0 0 0 0 0 GAIN REGISTER* CHANNEL 1 AND CHANNEL 2 PGA CONTROL 7 6 5 4 3 2 1 0 0 0 0 0 0 0 PGA 2 GAIN SELECT 000 = × 1 001 = × 2 010 = × 4 011 = × 8 100 = × 16 GAIN (K) SELECTION V1P * REGISTER CONTENTS SHOW POWER-ON DEFAULTS VIN 0 0 ADDR: 0x0F PGA 1 GAIN SELECT 000 = × 1 001 = × 2 010 = × 4 011 = × 8 100 = × 16 CHANNEL 1 FULL-SCALE SELECT 00 = 0.5V 01 = 0.25V 10 = 0.125V Figure 24. Analog Gain Register K × VIN V1N + 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 OFFSET ADJUST (±50mV) CH1OS[7:0] BITS 0 to 5: SIGN MAGNITUDE CODED OFFSET CORRECTION BIT 6: NOT USED BIT 7: DIGITAL INTEGRATOR (ON = 1, OFF = 0; DEFAULT OFF) 04481-A-024 7 Figure 23. PGA in Channel 1 In addition to the PGA, Channel 1 also has a full-scale input range selection for the ADC. The ADC analog input range selection is also made using the gain register—see Figure 24. As previously mentioned, the maximum differential input voltage is 0.5 V. However, by using Bits 3 and 4 in the gain register, the maximum ADC input voltage can be set to 0.5 V, 0.25 V, or 0.125 V. This is achieved by adjusting the ADC reference—see the Reference Circuit section. Table 5 summarizes the maximum differential input signal level on Channel 1 for the various ADC range and gain selections. It is also possible to adjust offset errors on Channel 1 and Channel 2 by writing to the offset correction registers (CH1OS and CH2OS, respectively). These registers allow channel offsets in the range ±20 mV to ±50 mV (depending on the gain setting) to be removed. Note that it is not necessary to perform an offset correction in an energy measurement application if HPF in Channel 1 is switched on. Figure 25 shows the effect of offsets on the real power calculation. As seen from Figure 25, an offset on Channel 1 and Channel 2 contributes a dc component after multiplication. Because this dc component is extracted by LPF2 to generate the active (real) power information, the offsets contribute an error to the active power calculation. This problem is easily avoided by enabling HPF in Channel 1. By removing the offset from at least one channel, no error component is generated at dc by the multiplication. Error terms at cos(ωt) are removed by LPF2 and by integration of the active power signal in the active energy register (AENERGY[23:0])—see the Energy Calculation section. Rev. C | Page 14 of 56 04481-A-025 Each analog input channel has a programmable gain amplifier (PGA) with possible gain selections of 1, 2, 4, 8, and 16. The gain selections are made by writing to the gain register—see Figure 24. Bits 0 to 2 select the gain for the PGA in Channel 1; the gain selection for the PGA in Channel 2 is made via Bits 5 to 7. Figure 23 shows how a gain selection for Channel 1 is made using the gain register. ADC Input Range Selection 0.5 V 0.25 V 0.125 V Gain = 1 − − Gain = 2 Gain = 1 − Gain = 4 Gain = 2 Gain = 1 Gain = 8 Gain = 4 Gain = 2 Gain = 16 Gain = 8 Gain = 4 − Gain = 16 Gain = 8 − − Gain = 16 Data Sheet ADE7763 The current and voltage rms offsets can be adjusted with the IRMSOS and VRMSOS registers—see the Channel 1 RMS Offset Compensation and Channel 2 RMS Offset Compensation sections. DC COMPONENT (INCLUDING ERROR TERM) IS EXTRACTED BY THE LPF FOR REAL POWER CALCULATION VOS  IOS VI 2 di/dt CURRENT SENSOR AND DIGITAL INTEGRATOR IOS  V A di/dt sensor detects changes in magnetic field caused by ac current. Figure 27 shows the principle of a di/dt current sensor. 04481-A-026 VOS  I  0 2 FREQUENCY (RAD/S) Figure 25. Effect of Channel Offsets on the Real Power Calculation Table 6. Offset Correction Range—Channels 1 and 2 Correctable Span ±50 mV ±37 mV ±30 mV ±26 mV ±24 mV LSB Size 1.61 mV/LSB 1.19 mV/LSB 0.97 mV/LSB 0.84 mV/LSB 0.77 mV/LSB + EMF (ELECTROMOTIVE FORCE) – INDUCED BY CHANGES IN MAGNETIC FLUX DENSITY (di/dt) Figure 27. Principle of a di/dt Current Sensor The flux density of a magnetic field induced by a current is directly proportional to the magnitude of the current. Changes in the magnetic flux density passing through a conductor loop generate an electromotive force (EMF) between the two ends of the loop. The EMF is a voltage signal that is proportional to the di/dt of the current. The voltage output from the di/dt current sensor is determined by the mutual inductance between the current-carrying conductor and the di/dt sensor. The current signal must be recovered from the di/dt signal before it can be used. An integrator is therefore necessary to restore the signal to its original form. The ADE7763 has a built-in digital integrator to recover the current signal from the di/dt sensor. The digital integrator on Channel 1 is switched off by default when the ADE7763 is powered up. Setting the MSB of CH1OS register turns on the integrator. Figure 28, Figure 29, Figure 30, and Figure 31 show the magnitude and phase response of the digital integrator. 10 CH1OS[5:0] 0 0x1F 01,1111b SIGN + 5 BITS GAIN (dB) –10 0x00 +50mV OFFSET ADJUST 0x3F 11,1111b SIGN + 5 BITS –20 –30 –40 Figure 26. Channel 1 Offset Correction Range (Gain = 1) –50 102 103 FREQUENCY (Hz) Figure 28. Combined Gain Response of the Digital Integrator and Phase Compensator Rev. C | Page 15 of 56 04481-A-029 0mV –50mV 04481-A-027 Gain 1 2 4 8 16 MAGNETIC FIELD CREATED BY CURRENT (DIRECTLY PROPORTIONAL TO CURRENT) 04481-A-028 The contents of the offset correction registers are 6-bit, sign and magnitude coded. The weight of the LSB depends on the gain setting, i.e., 1, 2, 4, 8, or 16. Table 6 shows the correctable offset span for each of the gain settings and the LSB weight (mV) for the offset correction registers. The maximum value that can be written to the offset correction registers is ±31d—see Figure 26. Figure 26 shows the relationship between the offset correction register contents and the offset (mV) on the analog inputs for a gain of 1. To perform an offset adjustment, connect the analog inputs to AGND; there should be no signal on either Channel 1 or Channel 2. A read from Channel 1 or Channel 2 using the waveform register indicates the offset in the channel. This offset can be canceled by writing an equal and opposite offset value to the Channel 1 offset register, or an equal value to the Channel 2 offset register. The offset correction can be confirmed by performing another read. Note that when adjusting the offset of Channel 1, the digital integrator and the HPF should be disabled. PHASE (Degrees) ADE7763 Data Sheet –88.0 frequency noise, necessitating a more effective antialiasing filter to avoid noise due to aliasing—see the Antialias Filter section. –88.5 When the digital integrator is switched off, the ADE7763 can be used directly with a conventional current sensor such as a current transformer (CT) or with a low resistance current shunt. –89.0 ZERO-CROSSING DETECTION –89.5 –90.0 102 04481-A-030 –90.5 103 FREQUENCY (Hz) Figure 29. Combined Phase Response of the Digital Integrator and Phase Compensator The ADE7763 has a zero-crossing detection circuit on Channel 2. This zero crossing is used to produce an external zero-crossing signal (ZX), which is used in the calibration mode (see the Calibrating an Energy Meter section). This signal is also used to initiate a temperature measurement (see the Temperature Measurement section). Figure 32 shows how the zero-crossing signal is generated from the output of LPF1. 1, 2, 1, 8, 16 –1.0 V2P –1.5 PGA2 V2 –2.0 REFERENCE {GAIN[7:5]} ADC 2 1 –63% TO +63% FS TO MULTIPLIER V2N GAIN (dB) –2.5 ZERO CROSSING –3.0 ZX LPF1 f–3dB = 140Hz –3.5 –4.0 2.32° @ 60Hz 1.0 0.93 –4.5 ZX –5.0 45 50 55 60 65 70 FREQUENCY (Hz) Figure 30. Combined Gain Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz) –89.75 PHASE (Degrees) –89.80 –89.85 –89.90 –89.95 –90.00 50 55 60 65 70 FREQUENCY (Hz) 04481-A-032 –90.05 45 LPF1 Figure 32. Zero-Crossing Detection on Channel 2 The ZX signal goes logic high upon a positive-going zero crossing and logic low upon a negative-going zero crossing on Channel 2. The ZX signal is generated from the output of LPF1. LPF1 has a single pole at 140 Hz (@ CLKIN = 3.579545 MHz). As a result, there is a phase lag between the analog input signal V2 and the output of LPF1. The phase response of this filter is shown in the Channel 2 Sampling section. The phase lag response of LPF1 results in a time delay of approximately 1.14 ms (@ 60 Hz) between the zero crossing on the analog inputs of Channel 2 and the rising or falling edge of ZX. –89.70 –90.10 40 V2 04481-A-033 –6.0 40 04481-A-031 –5.5 Figure 31. Combined Phase Response of the Digital Integrator and Phase Compensator (40 Hz to 70 Hz) Note that the integrator has a –20 dB/dec attenuation and approximately a –90° phase shift. When combined with a di/dt sensor, the resulting magnitude and phase response should be a flat gain over the frequency band of interest. The di/dt sensor has a 20 dB/dec gain. It also generates significant high Zero-crossing detection also drives the ZX flag in the interrupt status register. The ZX flag is set to Logic 1 on the rising and falling edge of the voltage waveform. It remains high until the status register is read with reset. An active low in the IRQ output appears if the corresponding bit in the interrupt enable register is set to Logic 1. The flag in the interrupt status register and the IRQ output are set to their default values when reset (RSTSTATUS) is read in the interrupt status register. Zero-Crossing Timeout Zero-crossing detection has an associated timeout register, ZXTOUT. This unsigned, 12-bit register is decremented (1 LSB) Rev. C | Page 16 of 56 Data Sheet ADE7763 every 128/CLKIN seconds. The register is reset to its userprogrammed, full-scale value when a zero crossing on Channel 2 is detected. The default power-on value in this register is 0xFFF. If the internal register decrements to 0 before a zero crossing is detected and the DISSAG bit in the mode register is Logic 0, the SAG pin goes active low. The absence of a zero crossing is also indicated on the IRQ pin if the ZXTO enable bit in the interrupt enable register is set to Logic 1. Irrespective of the enable bit setting, the ZXTO flag in the interrupt status register is always set when the internal ZXTOUT register is decremented to 0— see the Interrupts section. Where CLKIN is the crystal frequency (3.579545 MHz recommended), and f is the line frequency. The ZXOUT register, Address 0x1D, can be written to and read from by the user—see the Serial Interface section. The resolution of the register is 128/CLKIN seconds per LSB; therefore, the maximum delay for an interrupt is 0.15 seconds (128/CLKIN × 212). When CLKIN = 3.579545 MHz, the resolution of this register is 2.2 μs/LSB, which represents 0.013% when the line frequency is 60 Hz. When the line frequency is 60 Hz, the value of the period register is approximately 7457d. The length of the register enables the measurement of line frequencies as low as 13.9 Hz. Figure 33 shows the zero-crossing timeout detection when the line voltage stays at a fixed dc level for more than CLKIN/128 × ZXTOUT seconds. The period register is stable at ±1 LSB when the line is established and the measurement does not change. This filter is associated with a settling time of 1.8 seconds before the measurement is stable. See the Calibrating an Energy Meter section for more on the period register. 12-BIT INTERNAL REGISTER VALUE ZXTOUT The ADE7763 provides the period measurement of the line. The PERIOD register is an unsigned, 16-bit register that is updated every period and always has an MSB of zero. The formula for the period register is shown below: PERIOD  CLKIN  16 4  32  f POWER SUPPLY MONITOR 04481-A-034 CHANNEL 2 The ADE7763 contains an on-chip power supply monitor. The analog supply (AVDD) is continuously monitored. If the supply is less than 4 V ± 5%, the ADE7763 will go into an inactive state and no energy will accumulate. This is useful to ensure correct device operation during power-up and power-down stages. In addition, built-in hysteresis and filtering help prevent false triggering due to noisy supplies. AVDD 5V Figure 33. Zero-Crossing Timeout Detection 4V 0V TIME ADE7763 POWER-ON INACTIVE INACTIVE STATE ACTIVE INACTIVE 04481-A-035 ZXTO DETECTION BIT PERIOD MEASUREMENT SAG Figure 34. On-Chip Power Supply Monitor As seen in Figure 34, the trigger level is nominally set at 4 V. The tolerance on this trigger level is about ±5%. The SAG pin can also be used as a power supply monitor input to the MCU. The SAG pin goes logic low when the ADE7763 is in its inactive state. The power supply and decoupling for the part should be such that the ripple at AVDD does not exceed 5 V ± 5%, as specified for normal operation. Rev. C | Page 17 of 56 ADE7763 Data Sheet LINE VOLTAGE SAG DETECTION PEAK DETECTION In addition to detecting the loss of the line voltage when there are no zero crossings on the voltage channel, the ADE7763 can also be programmed to detect when the absolute value of the line voltage drops below a peak value for a specified number of line cycles. This condition is illustrated in Figure 35. The ADE7763 can also be programmed to detect when the absolute value of the voltage or current channel exceeds a specified peak value. Figure 36 illustrates the behavior of the peak detection for the voltage channel. FULL SCALE Both Channel 1 and Channel 2 are monitored at the same time. V2 CHANNEL 2 VPKLVL[7:0] SAGLVL[7:0] PKV RESET LOW WHEN RSTSTATUS REGISTER IS READ SAG RESET HIGH WHEN CHANNEL 2 EXCEEDS SAGLVL[7:0] 04481-A-036 Figure 35. Sag Detection In Figure 35 the line voltage falls below a threshold that has been set in the sag level register (SAGLVL[7:0]) for three line cycles. The quantities 0 and 1 are not valid for the SAGCYC register, and the contents represent one more than the desired number of full line cycles. For example, if the DISSAG bit in the mode register is Logic 0 and the sag cycle register (SAGCYC[7:0]) contains 0x04, the SAG pin goes active low at the end of the third line cycle for which the line voltage (Channel 2 signal) falls below the threshold. As is the case when zero crossings are no longer detected, the sag event is also recorded by setting the SAG flag in the interrupt status register. If the SAG enable bit is set to Logic 1, the IRQ logic output will go active low—see the Interrupts section. The SAG pin goes logic high again when the absolute value of the signal on Channel 2 exceeds the level set in the sag level register. This is shown in Figure 35 when the SAG pin goes high again during the fifth line cycle from the time when the signal on Channel 2 first dropped below the threshold level. Sag Level Set The contents of the sag level register (1 byte) are compared to the absolute value of the most significant byte output from LPF1 after it is shifted left by one bit. For example, the nominal maximum code from LPF1 with a full-scale signal on Channel 2 is 0x2518—see the Channel 2 Sampling section. Shifting one bit left gives 0x4A30. Therefore, writing 0x4A to the SAG level register puts the sag detection level at full scale. Writing 0x00 or 0x01 puts the sag detection level at 0. The SAG level register is compared to the most significant byte of a waveform sample after the shift left, and detection occurs when the contents of the sag level register are greater. PKV INTERRUPT FLAG (BIT 8 OF STATUS REGISTER) 04481-A-037 SAGCYC[7:0] = 0x04 3 LINE CYCLES SAG READ RSTSTATUS REGISTER Figure 36. Peak Level Detection Figure 36 shows a line voltage exceeding a threshold that has been set in the voltage peak register (VPKLVL[7:0]). The voltage peak event is recorded by setting the PKV flag in the interrupt status register. If the PKV enable bit is set to Logic 1 in the interrupt mask register, the IRQ logic output will go active low. Similarly, the current peak event is recorded by setting the PKI flag in the interrupt status register—see the Interrupts section. Peak Level Set The contents of the VPKLVL and IPKLVL registers are compared to the absolute value of Channel 1 and Channel 2, respectively, after they are multiplied by 2. For example, the nominal maximum code from the Channel 1 ADC with a fullscale signal is 0x2851EC—see the Channel 1 Sampling section. Multiplying by 2 gives 0x50A3D8. Therefore, writing 0x50 to the IPKLVL register, for example, puts the Channel 1 peak detection level at full scale and sets the current peak detection to its least sensitive value. Writing 0x00 puts the Channel 1 detection level at 0. Peak level detection is done by comparing the contents of the IPKLVL register to the incoming Channel 1 sample. The IRQ pin indicates that the peak level is exceeded if the PKI or PKV bits are set in the interrupt enable register (IRQEN [15:0]) at Address 0x0A. Peak Level Record The ADE7763 records the maximum absolute value reached by Channel 1 and Channel 2 in two different registers—IPEAK and VPEAK, respectively. VPEAK and IPEAK are 24-bit, unsigned registers. These registers are updated at a rate of CLKIN/4 regardless of the waveform sampling rate. The contents of the VPEAK register correspond to two times the maximum absolute value observed on the Channel 2 input. The contents of IPEAK represent the maximum absolute value observed on the Channel 1 Rev. C | Page 18 of 56 Data Sheet ADE7763 Using Interrupts with an MCU input. Reading the RSTVPEAK and RSTIPEAK registers clears their respective contents after the read operation. Figure 38 shows a timing diagram with a suggested implementation of ADE7763 interrupt management using an MCU. At time t1, the IRQ line goes active low, indicating that one or more interrupt events have occurred. Tie the IRQ logic output to a negative edge-triggered external interrupt on the MCU. Configure the MCU to start executing its interrupt service routine (ISR) when a negative edge is detected on the IRQ line. After entering the ISR, disable all interrupts by using the global interrupt enable bit. At this point, the MCU IRQ external interrupt flag can be cleared to capture interrupt events that occur during the current ISR. When the MCU interrupt flag is cleared, a read from the status register with reset is carried out. This causes the IRQ line to reset to logic high (t2)—see the Interrupt Timing section. The status register contents are used to determine the source of the interrupt(s) and, therefore, the appropriate action to be taken. If a subsequent interrupt event occurs during the ISR, that event will be recorded by the MCU external interrupt flag being set again (t3). Upon the completion of the ISR, the global interrupt mask is cleared (same instruction cycle) and the external interrupt flag causes the MCU to jump to its ISR again. This ensures that the MCU does not miss any external interrupts. INTERRUPTS Interrupts are managed through the interrupt status register (STATUS[15:0]) and the interrupt enable register (IRQEN[15:0]). When an interrupt event occurs, the corresponding flag in the status register is set to Logic 1—see the Interrupt Status Register section. If the enable bit for this interrupt in the interrupt enable register is Logic 1, the IRQ logic output will go active low. The flag bits in the status register are set irrespective of the state of the enable bits. To determine the source of the interrupt, the system master (MCU) should perform a read from the status register with reset (RSTSTATUS[15:0]). This is achieved by carrying out a read from Address 0Ch. The IRQ output goes logic high after the completion of the interrupt status register read command— see the Interrupt Timing section. When carrying out a read with reset, the ADE7763 is designed to ensure that no interrupt events are missed. If an interrupt event occurs as the status register is being read, the event will not be lost and the IRQ logic output will be guaranteed to go high for the duration of the interrupt status register data transfer before going logic low again to indicate the pending interrupt. See the next section for a more detailed description. t1 t2 MCU INTERRUPT FLAG SET t3 MCU PROGRAM SEQUENCE JUMP TO ISR GLOBAL INTERRUPT MASK SET CLEAR MCU INTERRUPT FLAG READ STATUS WITH RESET (0x0C) ISR RETURN GLOBAL INTERRUPT MASK RESET ISR ACTION (BASED ON STATUS CONTENTS) 04481-A-038 IRQ JUMP TO ISR Figure 37. Interrupt Management CS t1 t9 SCLK DIN 0 0 0 0 0 1 0 1 t11 t11 DB7 DOUT DB0 DB7 DB0 STATUS REGISTER CONTENTS IRQ Figure 38. Interrupt Timing Rev. C | Page 19 of 56 04481-A-039 READ STATUS REGISTER COMMAND ADE7763 Data Sheet Interrupt Timing Review the Serial Interface section before reading this section. As previously described, when the IRQ output goes low, the MCU ISR will read the interrupt status register to determine the source of the interrupt. When reading the status register contents, the IRQ output is set high upon the last falling edge of SCLK of the first byte transfer (read interrupt status register command). The IRQ output is held high until the last bit of the next 15-bit transfer is shifted out (interrupt status register contents)—see Figure 37. If an interrupt is pending at this time, the IRQ output will go low again. If no interrupt is pending, the IRQ output will stay high. TEMPERATURE MEASUREMENT There is an on-chip temperature sensor. A temperature measurement can be made by setting Bit 5 in the mode register. When Bit 5 is set logic high in the mode register, the ADE7763 initiates a temperature measurement of the next zero crossing. When the zero crossing on Channel 2 is detected, the voltage output from the temperature sensing circuit is connected to ADC1 (Channel 1) for digitizing. The resulting code is processed and placed in the temperature register (TEMP[7:0]) approximately 26 µs later (24 CLKIN/4 cycles). If enabled in the interrupt enable register (Bit 5), the IRQ output will go active low when the temperature conversion is finished. The contents of the temperature register are signed (twos complement) with a resolution of approximately 1.5 LSB/°C. The temperature register produces a code of 0x00 when the ambient temperature is approximately −25°C. The temperature measurement is uncalibrated in the ADE7763 and might have an offset tolerance as high as ±25°C. ANALOG-TO-DIGITAL CONVERSION output (and therefore the bit stream) will approach that of the input signal level. For any given input value in a single sampling interval, the data from the 1-bit ADC is virtually meaningless. Only when a large number of samples are averaged can a meaningful result be obtained. This averaging is carried out in the second part of the ADC, the digital low-pass filter. By averaging a large number of bits from the modulator, the lowpass filter can produce 24-bit data-words that are proportional to the input signal level. The Σ-∆ converter uses two techniques to achieve high resolution from what is essentially a 1-bit conversion technique. The first is oversampling. Oversampling means that the signal is sampled at a rate (frequency) that is many times higher than the bandwidth of interest. For example, the sampling rate in the ADE7763 is CLKIN/4 (894 kHz) and the band of interest is 40 Hz to 2 kHz. Oversampling has the effect of spreading the quantization noise (noise due to sampling) over a wider bandwidth. With the noise spread more thinly over a wider bandwidth, the quantization noise in the band of interest decreases—see Figure 40. However, oversampling alone is not efficient enough to improve the signal-to-noise ratio (SNR) in the band of interest. For example, an oversampling ratio of 4 is required just to increase the SNR by 6 dB (1 bit). To keep the oversampling ratio at a reasonable level, it is possible to shape the quantization noise so that the majority of the noise lies at higher frequencies. In the Σ-∆ modulator, the noise is shaped by the integrator, which has a high-pass-type response for the quantization noise. The result is that most of the noise is at higher frequencies, where it can be removed by the digital low-pass filter. This noise shaping is shown in Figure 40. DIGITAL FILTER SIGNAL The analog-to-digital conversion is carried out using two second-order Σ-∆ ADCs. For simplicity, the block diagram in Figure 39 shows a first-order Σ-∆ ADC. The converter comprises two parts: the Σ-∆ modulator and the digital lowpass filter. NOISE 0 C + – LATCHED COMPARATOR – 447 FREQUENCY (kHz) 894 HIGH RESOLUTION OUTPUT FROM DIGITAL LPF SIGNAL DIGITAL LOW-PASS FILTER 2 NOISE 24 VREF .....10100101..... 1-BIT DAC 04481-A-040 0 Figure 39. First-Order Σ-∆ ADC A Σ-∆ modulator converts the input signal into a continuous serial stream of 1s and 0s at a rate determined by the sampling clock. In the ADE7763, the sampling clock is equal to CLKIN/4. The 1-bit DAC in the feedback loop is driven by the serial data stream. The DAC output is subtracted from the input signal. If the loop gain is high enough, the average value of the DAC Rev. C | Page 20 of 56 2 447 FREQUENCY (kHz) 894 Figure 40. Noise Reduction due to Oversampling and Noise Shaping in the Analog Modulator 04481-A-041 INTEGRATOR + R SAMPLING FREQUENCY SHAPED NOISE MCLK/4 ANALOG LOW-PASS FILTER ANTIALIAS FILTER (RC) Data Sheet ADE7763 Antialias Filter Reference Circuit Figure 39 also shows an analog low-pass filter (RC) on the input to the modulator. This filter prevents aliasing, which is an artifact of all sampled systems. Aliasing means that frequency components in the input signal to the ADC that are higher than half the sampling rate of the ADC appear in the sampled signal at a frequency below half the sampling rate. Figure 41 illustrates the effect. Frequency components (shown as arrows) above half the sampling frequency (also known as the Nyquist frequency, i.e., 447 kHz) are imaged or folded back down below 447 kHz. This happens with all ADCs, regardless of the architecture. In the example shown, only frequencies near the sampling frequency, i.e., 894 kHz, move into the band of interest for metering, i.e., 40 Hz to 2 kHz. This allows the use of a very simple LPF (low-pass filter) to attenuate high frequency (near 900 kHz) noise, and it prevents distortion in the band of interest. For conventional current sensors, a simple RC filter (single-pole LPF) with a corner frequency of 10 kHz produces an attenuation of approximately 40 dB at 894 kHz—see Figure 41. The 20 dB per decade attenuation is usually sufficient to eliminate the effects of aliasing for conventional current sensors; however, for a di/dt sensor such as a Rogowski coil, the sensor has a 20 dB per decade gain. This neutralizes the –20 dB per decade attenuation produced by one simple LPF. Therefore, when using a di/dt sensor, care should be taken to offset the 20 dB per decade gain. One simple approach is to cascade two RC filters to produce the –40 dB per decade attenuation. Figure 42 shows a simplified version of the reference output circuitry. The nominal reference voltage at the REFIN/OUT pin is 2.42 V. This is the reference voltage used for the ADCs. However, Channel 1 has three input range options that are selected by dividing down the reference value used for the ADC in Channel 1. The reference value used for Channel 1 is divided down to ½ and ¼ of the nominal value by using an internal resistor divider, as shown in Figure 42. ALIASING EFFECTS IMAGE FREQUENCIES 0 2 447 04481-A-042 SAMPLING FREQUENCY 894 FREQUENCY (kHz) Figure 41. ADC and Signal Processing in Channel 1 Outline Dimensions ADC Transfer Function The following expression relates the output of the LPF in the Σ-∆ ADC to the analog input signal level. Both ADCs in the ADE7763 are designed to produce the same output code for the same input signal level. Code ( ADC )= 3.0492 × VIN × 262,144 VOUT (1) Therefore, with a full-scale signal on the input of 0.5 V and an internal reference of 2.42 V, the ADC output code is nominally 165,151, or 0x2851F. The maximum code from the ADC is ±262,144; this is equivalent to an input signal level of ±0.794 V. However, for specified performance, do not exceed the 0.5 V full-scale input signal level. MAXIMUM LOAD = 10µA PTAT OUTPUT IMPEDANCE 6kΩ REFIN/OUT 2.42V 60µA 1.7kΩ 2.5V 12.5kΩ 12.5kΩ 12.5kΩ REFERENCE INPUT TO ADC CHANNEL 1 (RANGE SELECT) 2.42V, 1.21V, 0.6V 04481-A-043 12.5kΩ Figure 42. Reference Circuit Output The REFIN/OUT pin can be overdriven by an external source such as a 2.5 V reference. Note that the nominal reference value supplied to the ADCs is now 2.5 V, not 2.42 V, which increases the nominal analog input signal range by 2.5/2.42 × 100% = 3% or from 0.5 V to 0.5165 V. The voltage of the ADE7763 reference drifts slightly with changes in temperature—see Table 1 for the temperature coefficient specification (in ppm/°C). The value of the temperature drift varies from part to part. Because the reference is used for the ADCs in both Channels 1 and 2, any x% drift in the reference results in 2x% deviation in the meter accuracy. The reference drift that results from a temperature change is usually very small, typically much smaller than the drift of other components on a meter. However, if guaranteed temperature performance is needed, use an external voltage reference. Alternatively, the meter can be calibrated at multiple temperatures. Real-time compensation can be achieved easily by using the on-chip temperature sensor. CHANNEL 1 ADC Figure 43 shows the ADC and signal processing chain for Channel 1. In waveform sampling mode, the ADC outputs a signed, twos complement, 24-bit data-word at a maximum of 27.9 kSPS (CLKIN/128). With the specified full-scale analog input signal of 0.5 V (or 0.25 V or 0.125 V—see the Analog Inputs section), the ADC produces an output code that is approximately between 0x28 51EC (+2,642,412d) and 0xD7 AE14 (–2,642,412d)—see Figure 43. Rev. C | Page 21 of 56 ADE7763 Data Sheet 2.42V, 1.21V, 0.6V ×1, ×2, ×4, REFERENCE ×8, ×16 {GAIN[2:0]} V1P {GAIN[4:3]} HPF DIGITAL INTEGRATOR* ADC 1 PGA1 V1 CURRENT RMS (IRMS) CALCULATION WAVEFORM SAMPLE REGISTER ACTIVE AND REACTIVE POWER CALCULATION dt V1N 50Hz CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (50Hz) 0x1E F73C V1 0.5V, 0.25V, 0.125V, 62.5mV, 31.3mV, 15.6mV, 0x28 51EC 0V 0x00 0000 CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE 0x0 0000 0xEI 08C4 0x28 51EC 0xD7 AE14 ANALOG INPUT RANGE ADC OUTPUT WORD RANGE 0x00 0000 60Hz 0xD7 AE14 CHANNEL 1 (CURRENT WAVEFORM) DATA RANGE AFTER INTEGRATOR (60Hz) 0x19 CE08 0xE6 31F8 04481-A-044 0x00 0000 *WHEN DIGITAL INTEGRATOR IS ENABLED, FULL-SCALE OUTPUT DATA IS ATTENUATED DEPENDING ON THE SIGNAL FREQUENCY BECAUSE THE INTEGRATOR HAS A –20dB/DECADE FREQUENCY RESPONSE. WHEN DISABLED, THE OUTPUT IS NOT ATTENUATED FURTHER. Figure 43. ADC and Signal Processing in Channel 1 Figure 44. Waveform Sampling Channel 1 Channel 1 Sampling The waveform samples may be routed to the waveform register (MODE[14:13] = 1, 0) for the system master (MCU) to read. To enable waveform sampling mode, set the WSMP bit (Bit 3) in the interrupt enable register to Logic 1. The active and apparent power as well as the energy calculation remain uninterrupted during waveform sampling. Channel 1 RMS Calculation In waveform sampling mode, choose one of four output sample rates using Bits 11 and 12 of the mode register (WAVSEL 1, 0). The output sample rate can be 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see the Mode Register (0X09) section. The interrupt request output, IRQ, signals a new sample availability by going active low. The timing is shown in Figure 44. The 24-bit waveform samples are transferred from the ADE7763 one byte (eight bits) at a time, with the most significant byte shifted out first. The 24-bit data-word is right justified—see the Serial Interface section. The Channel 1 waveform samples have a settling time of approximately 150 μs. The interrupt request output IRQ stays low until the interrupt routine reads the reset status register— see the Interrupts section. For time sampling signals, the rms calculation involves squaring the signal, taking the average, and obtaining the square root: IRQ SCLK DOUT IRMS = IRMS = 1 N T × ∫ I 2 ( t ) dt (2) 0 N ×∑ I 2 (i ) (3) i =1 Figure 45 shows the detail of the signal processing chain for the rms calculation on Channel 1. The Channel 1 rms value is processed from the samples used in the Channel 1 waveform sampling mode. The Channel 1 rms value is stored in an unsigned, 24-bit register (IRMS). One LSB of the Channel 1 rms register is equivalent to 1 LSB of a Channel 1 waveform sample. The update rate of the Channel 1 rms measurement is CLKIN/4. The channel 1 rms measurement has a settling time of approximately 876 ms with the integrator off and 1340 ms with the integrator on. READ FROM WAVEFORM 0 0 0 01 HEX SIGN CHANNEL 1 DATA (24 BITS) 1 T 04481-A-045 DIN The root mean square (rms) value of a continuous signal I(t) is defined as Rev. C | Page 22 of 56 Data Sheet ADE7763 CURRENT SIGNAL (i(t)) 0x28 51EC IRMSOS[11:0] IRMS(t) 0x00 LPF3 HPF1 + 24 24 IRMS 04481-A-046 0xD7 AE14 CHANNEL 1 217 216 215 0x1C 82B3 0x00 sgn 225 226 227 Figure 45. Channel 1 RMS Signal Processing IRMS = IRMS0 2 + IRMSOS × 32768 To measure the offset of the rms measurement, two data points are needed from nonzero input values, for example, the base current, Ib, and Imax/100. The offset can be calculated from these measurements. Note that for correct operation, only positive values should be written to the IRMSOS register. 0 –2 –4 –20 50Hz, –19.7° –6 –30 60Hz, –23.2° –40 –8 –50 –10 –60 –12 –70 –14 –80 –16 –90 101 102 FREQUENCY (Hz) –18 103 Figure 46. Magnitude and Phase Response of LPF1 The LPF1 has the effect of attenuating the signal. For example, if the line frequency is 60 Hz, the signal at the output of LPF1 will be attenuated by about 8%. |H(f)| = Channel 2 Sampling = 0.919 = −0.73 db 1  60 Hz   1+   140 Hz    CHANNEL 2 ADC To enable waveform sampling mode, set the WSMP bit (Bit 3) in the interrupt enable register to Logic 1. In Channel 2 waveform sampling mode (MODE[14:13] = 1, 1 and WSMP = 1), 50Hz, –0.52dB –10 (4) where IRMS0 is the rms measurement without offset correction. 60Hz, –0.73dB GAIN (dB) One LSB of the Channel 1 rms offset is equivalent to 32,768 LSB of the square of the Channel 1 rms register. Assuming that the maximum value from the Channel 1 rms calculation is 1,868,467d with full-scale ac inputs, then 1 LSB of the Channel 1 rms offset represents 0.46% of the measurement error at –60 dB down of full scale. 0 04481-A-047 Channel 1 RMS Offset Compensation The ADE7763 incorporates a Channel 1 rms offset compensation register (IRMSOS). This is a 12-bit, signed register that can be used to remove offset in the Channel 1 rms calculation. An offset might exist in the rms calculation due to input noises that are integrated in the dc component of V2(t). The offset calibration eliminates the influence of input noises from the rms measurement. the ADC output code scaling for Channel 2 is not the same as it is for Channel 1. The Channel 2 waveform sample is a 16-bit word and sign extended to 24 bits. The Channel 2 waveform samples have a settling time of approximately 1.23 ms.For normal operation, the differential voltage signal between V2P and V2N should not exceed 0.5 V. With maximum voltage input (±0.5 V at PGA gain of 1), the output from the ADC swings between 0x2852 and 0xD7AE (±10,322d). However, before being passed to the waveform register, the ADC output is passed through a single-pole, low-pass filter with a cutoff frequency of 140 Hz. The plots in Figure 46 show the magnitude and phase response of this filter. PHASE (Degrees) With the specified full-scale analog input signal of 0.5 V, the ADC produces an output code that is approximately ±2,642,412d— see the Channel 1 ADC section. The equivalent rms value of a full-scale ac signal is 1,868,467d (0x1C82B3). The current rms measurement provided in the ADE7763 is accurate to within 0.5% for signal input between full scale and full scale/100. Converting the register value to its equivalent in amps must be done externally in the microprocessor using an amps/LSB constant. To minimize noise, synchronize the reading of the rms register with the zero crossing of the voltage input and take the average of a number of readings. (5) 2 Note LPF1 does not affect the active power calculation. The signal processing chain in Channel 2 is illustrated in Figure 47. Rev. C | Page 23 of 56 ADE7763 Data Sheet 2.42V ×1, ×2, ×4, REFERENCE ×8, ×16 {GAIN[7:5]} V2P PGA2 V2 ACTIVE AND REACTIVE ENERGY CALCULATION ADC 2 LPF1 V2N ANALOG V1 INPUT RANGE 0.5V, 0.25V, 0.125V, 62.5mV, 31.25mV 0V 0x2852 0x2581 VRMS CALCULATION AND WAVEFORM SAMPLING (PEAK/SAG/ZX) LPF OUTPUT WORD RANGE 04481-A-048 0x0000 0xDAE8 0xD7AE Figure 47. ADC and Signal Processing in Channel 2 VOLTAGE SIGNAL (V(t)) 0x2518 VRMOS[11:0] sgn 29 28 22 21 20 0xDAE8 LPF1 CHANNEL 2 VRMS[23:0] 0x17D338 LPF3 + |x| + 0x00 04481-A-049 0x0 Figure 48. Channel 2 RMS Signal Processing Channel 2 has only one analog input range (0.5 V differential). Like Channel 1, Channel 2 has a PGA with gain selections of 1, 2, 4, 8, and 16. For energy measurement, the output of the ADC is passed directly to the multiplier and is not filtered. An HPF is not required to remove any dc offset; it is only required that the offset is removed from one channel to eliminate errors caused by offsets in the power calculation. In waveform sampling mode, one of four output sample rates can be chosen by using Bits 11 and 12 of the mode register. The available output sample rates are 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see the Mode Register (0X09) section. The interrupt request output IRQ indicates that a sample is available by going active low. The timing is the same as that for Channel 1, as shown in Figure 44. Channel 2 RMS Calculation Figure 48 shows the details of the signal processing chain for the rms estimation on Channel 2. This Channel 2 rms estimation is done in the ADE7763 using the mean absolute value calculation, as shown in Figure 48.The Channel 2 rms value is processed from the samples used in the Channel 2 waveform sampling mode. The rms value is slightly attenuated due to LPF1. The Channel 2 rms value is stored in the unsigned, 24-bit VRMS register. The update rate of the Channel 2 rms measurement is CLKIN/4. The Channel 2 rms measurement has a settling time of approximately 670 ms. With the specified full-scale ac analog input signal of 0.5 V, the output from LPF1 swings between 0x2518 and 0xDAE8 at 60 Hz—see the Channel 2 ADC section. The equivalent rms value of this full-scale ac signal is approximately 1,561,400 (0x17 D338) in the VRMS register. The voltage rms measurement provided in the ADE7763 is accurate to within ±0.5% for signal input between full scale and full scale/20. The conversion from the register value to volts must be done externally in the microprocessor using a volts/LSB constant. Because the low-pass filter used for calculating the rms value is imperfect, there is some ripple noise from 2ω term present in the rms measurement. To minimize the effect of noise in the reading, synchronize the rms reading with the zero crossings of the voltage input. Channel 2 RMS Offset Compensation The ADE7763 incorporates a Channel 2 rms offset compensation register (VRMSOS). This is a 12-bit, signed register that can be used to remove offset in the Channel 2 rms calculation. An offset could exist in the rms calculation due to input noises and dc offset in the input samples. One LSB of the Channel 2 rms offset is equivalent to 1 LSB of the rms register. Assuming that the maximum value of the Channel 2 rms calculation is 1,561,400d with full-scale ac inputs, then 1 LSB of the Channel 2 rms offset represents 0.064% of measurement error at –60 dB down of full scale. VRMS = VRMS0 + VRMSOS (6) where VRMS0 is the rms measurement without offset correction. The voltage rms offset compensation should be done by testing the rms results at two nonzero input levels. One measurement can be done close to full scale and the other at approximately full scale/10. The voltage offset compensation can be derived from these measurements. If the voltage rms offset register does not have enough range, the CH2OS register can also be used. PHASE COMPENSATION When the HPF is disabled, the phase error between Channel 1 and Channel 2 is 0 from dc to 3.5 kHz. When HPF is enabled, Channel 1 has the phase response illustrated in Figure 50 and Rev. C | Page 24 of 56 Data Sheet ADE7763 The phase calibration register (PHCAL[5:0]) is a twos complement, signed, single-byte register that has values ranging from 0x21 (–31d) to 0x1F (+31d). 0.7 0.6 0.5 0.4 0.3 0.2 0.1 104 FREQUENCY (Hz) Figure 50. Combined Phase Response of HPF and Phase Compensation (10 Hz to 1 kHz) 0.20 0.18 PHASE (Degrees) 0.14 0.12 0.10 0.08 0.06 0.04 0 40 45 50 55 60 65 70 FREQUENCY (Hz) 04481-A-052 0.02 Figure 51. Combined Phase Response of HPF and Phase Compensation (40 Hz to 70 Hz) 0.4 0.3 0.2 ERROR (%) 0.1 0.0 –0.1 24 ADC 1 –0.2 V1N LPF2 –0.4 54 V2P ADC 2 DELAY BLOCK 2.22µs/LSB V2N 5 0 0 0 1 0 1 1 V2 0.1° V1 CHANNEL 2 DELAY REDUCED BY 4.44µs (0.1°LEAD AT 60Hz) 0x0B IN PHCAL [5.0] V2 V1 PHCAL[5:0] –102.12µs TO +39.96µs 60Hz 60Hz Figure 49. Phase Calibration 04481-A-050 1 PGA2 56 58 60 62 64 66 FREQUENCY (Hz) 04481-A-053 –0.3 24 V2 103 102 04481-A-051 0 –0.1 HPF PGA1 V1 0.8 0.16 The register is centered at 0Dh, so that writing 0Dh to the register produces 0 delay. By changing the PHCAL register, the time delay in the Channel 2 signal path can change from –102.12 µs to +39.96 µs (CLKIN = 3.579545 MHz). One LSB is equivalent to 2.22 µs (CLKIN/8) time delay or advance. A line frequency of 60 Hz gives a phase resolution of 0.048° at the fundamental (i.e., 360° × 2.22 µs × 60 Hz). Figure 49 illustrates how the phase compensation is used to remove a 0.1° phase lead in Channel 1 due to the external transducer. To cancel the lead (0.1°) in Channel 1, a phase lead must also be introduced into Channel 2. The resolution of the phase adjustment allows the introduction of a phase lead in increments of 0.048°. The phase lead is achieved by introducing a time advance in Channel 2. A time advance of 4.44 µs is made by writing −2 (0x0B) to the time delay block, thus reducing the amount of time delay by 4.44 µs, or equivalently, a phase lead of approximately 0.1° at line frequency of 60 Hz. 0x0B represents –2 because the register is centered with 0 at 0Dh. V1P 0.9 PHASE (Degrees) Figure 51. Figure 52 shows the magnitude response of the filter. As seen from the plots, the phase response is almost 0 from 45 Hz to 1 kHz, which is all that is required in typical energy measurement applications. However, despite being internally phase-compensated, the ADE7763 must work with transducers, which could have inherent phase errors. For example, a phase error of 0.1° to 0.3° is not uncommon for a current transformer (CT). Phase errors can vary from part to part and must be corrected in order to perform accurate power calculations. The errors associated with phase mismatch are particularly noticeable at low power factors. The ADE7763 provides a means of digitally calibrating these small phase errors by allowing a short time delay or time advance to be introduced into the signal processing chain to compensate for these errors. Because the compensation is in time, this technique should only be used for small phase errors in the range of 0.1° to 0.5°. Correcting large phase errors using a time shift technique can introduce significant phase errors at higher harmonics. Figure 52. Combined Gain Response of HPF and Phase Compensation ACTIVE POWER CALCULATION Power is defined as the rate of energy flow from the source to the load. It is defined as the product of the voltage and current waveforms. The resulting waveform is called the instantaneous power signal and is equal to the rate of energy flow at any given time. The unit of power is the watt or joules/s. Equation 9 gives an expression for the instantaneous power signal in an ac system. Rev. C | Page 25 of 56 ADE7763 Data Sheet v(t )  2 V sin(ω t ) i(t )  2  I sin(ω t ) (7) (8) 0x19 999A INSTANTANEOUS POWER SIGNAL p(t) = v  i-v  i  cos(2t) ACTIVE REAL POWER SIGNAL = v  i where: V is the rms voltage. I is the rms current. VI 0xC CCCD p (t )  v (t )  i (t ) p(t )  VI  VI cos(2t ) (9) 0x0 0000 The average power over an integral number of line cycles (n) is given by the expression in Equation 10.  nT p (t ) dt  VI 04481-A-054 1 nT VOLTAGE v(t) = 2  v  sin(t) (10) 0 Figure 53. Active Power Calculation where: T is the line cycle period. P is the active or real power. Note that the active power is equal to the dc component of the instantaneous power signal p(t) in Equation 8, i.e., VI. This is the relationship used to calculate active power in the ADE7763. The instantaneous power signal p(t) is generated by multiplying the current and voltage signals. The dc component of the instantaneous power signal is then extracted by LPF2 (low-pass filter) to obtain the active power information. This process is illustrated in Figure 53. Because LPF2 does not have an ideal “brick wall” frequency response (see Figure 54), the active power signal has some ripple due to the instantaneous power signal. This ripple is sinusoidal and has a frequency equal to twice the line frequency. Because the ripple is sinusoidal in nature, it is removed when the active power signal is integrated to calculate energy—see the Energy Calculation section. 0 –4 dB –8 –12 –16 –20 –24 1 3 10 30 FREQUENCY (Hz) Figure 54. Frequency Response of LPF2 Rev. C | Page 26 of 56 100 04481-A-055 P CURRENT i(t) = 2  i  sin(t) Data Sheet ADE7763 APOS[15:0] CURRENT CHANNEL LPF2 + WDIV[7:0] 23 + AENERGY[23:0] 0 UPPER 24 BITS ARE ACCESSIBLE THROUGH AENERGY[23:0] REGISTER % VOLTAGE CHANNEL WGAIN[11:0] 48 0 4 CLKIN OUTPUT LPF2 T WAVEFORM REGISTER VALUES OUTPUTS FROM THE LPF2 ARE ACCUMULATED (INTEGRATED) IN THE INTERNAL ACTIVE ENERGY REGISTER 04481-A-056 ACTIVE POWER SIGNAL TIME (nT) Figure 55. Active Energy Calculation 0x1 3333 POSITIVE POWER 0xCCCD 0x6666 0x0 0000 0xF 999A NEGATIVE POWER 0xF 3333 0xE CCCD 0x000 0x7FF 0x800 {WGAIN[11:0]} ACTIVE POWER CALIBRATION RANGE (11) 04481-A-057   WGAIN   Output WGAIN   Active Power  1    212     ACTIVE POWER OUTPUT Figure 55 shows the signal processing chain for the active power calculation. The active power is calculated by low-pass filtering the instantaneous power signal. Note that when reading the waveform samples from the output of LPF2, the gain of the active energy can be adjusted by using the multiplier and watt gain register (WGAIN[11:0]). The gain is adjusted by writing a twos complement 12-bit word to the watt gain register. Equation 11 shows how the gain adjustment is related to the contents of the watt gain register: Figure 56. Active Power Calculation Output Range For example, when 0x7FF is written to the watt gain register, the power output is scaled up by 50%. 0x7FF = 2047d, 2047/212 = 0.5. Similarly, 0x800 = –2048d (signed twos complement) and power output is scaled by –50%. Each LSB scales the power output by 0.0244%. Figure 56 shows the maximum code (hexadecimal) output range for the active power signal (LPF2). Note that the output range changes depending on the contents of the watt gain register. The minimum output range is given when the watt gain register contents are equal to 0x800, and the maximum range is given by writing 0x7FF to the watt gain register. This can be used to calibrate the active power (or energy) calculation. ENERGY CALCULATION As stated earlier, power is defined as the rate of energy flow. This relationship is expressed mathematically in Equation 12. P dE dt (12) where: P is power. E is energy. Conversely, energy is given as the integral of power.  E  Pdt Rev. C | Page 27 of 56 (13) ADE7763 Data Sheet APOS[15:0] sgn 26 25 I MULTIPLIER 1 V VOLTAGE SIGNAL– v(t) LPF2 24 + 2-6 2-7 2-8 0x1 9999 + 32 INSTANTANEOUS POWER SIGNAL – p(t) WGAIN[11:0] FOR WAVEFORM ACCUMULATION 0xC CCCD 0x19 999A 04481-A-058 CURRENT SIGNAL – i(t) FOR WAVEF0RM SAMPLING 24 HPF 0x00 0000 Figure 57. Active Power Signal Processing The ADE7763 achieves the integration of the active power signal by continuously accumulating the active power signal in an internal unreadable 49-bit energy register. The active energy register (AENERGY[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 14 expresses this relationship. (14) where: n is the discrete time sample number. T is the sample period. Figure 58 shows this energy accumulation for full-scale signals (sinusoidal) on the analog inputs. The three curves illustrate the minimum time for the energy register to roll over when the active power gain register contents are 0x7FF, 0x000, and 0x800. The watt gain register is used to carry out power calibration. As shown, the fastest integration time occurs when the watt gain register is set to maximum full scale, i.e., 0x7FF. AENERGY[23:0] The discrete time sample period (T) for the accumulation register is 1.1 μs (4/CLKIN). In addition to calculating the energy, this integration removes any sinusoidal components that might be in the active power signal. 0x7F FFFF WGAIN = 0x7FF WGAIN = 0x000 WGAIN = 0x800 0x3F FFFF Figure 57 shows this discrete time integration, or accumulation. The active power signal in the waveform register is continuously added to the internal active energy register. This addition is a signed addition; therefore, negative energy is subtracted from the active energy contents. The exception to this is when POAM is selected in the MODE[15:0] register, in which case only positive energy contributes to the active energy accumulation— see the Positive-Only Accumulation Mode section. The output of the multiplier is divided by WDIV. If the value in the WDIV register is equal to 0, then the internal active energy register is divided by 1. WDIV is an 8-bit, unsigned register. After dividing by WDIV, the active energy is accumulated in a 49-bit internal energy accumulation register. The upper 24 bits of this register are accessible through a read to the active energy register (AENERGY[23:0]). A read to the RAENERGY register returns the content of the AENERGY register, and the upper 24 bits of the internal register are cleared. As shown in Figure 57, the active power signal is accumulated in an internal 49-bit, signed register. The active power signal can be read from the 0x00 0000 4 6.2 8 12.5 TIME (minutes) 0x40 0000 0x80 0000 04481-A-059   E   p (t )dt  Lim  p(nT )  T  t 0  n 1   waveform register by setting MODE[14:13] = 0, 0 and setting the WSMP bit (Bit 3) in the interrupt enable register to 1. Like Channel 1 and Channel 2 waveform sampling modes, the waveform data is available at sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS—see Figure 44. The active power waveform sampling signal has a settling time of approximately 2 ms. Figure 58. Energy Register Rollover Time for Full-Scale Power (Minimum and Maximum Power Gain) Note that the energy register contents roll over to full-scale negative (0x80 0000) and continue increasing in value when the power or energy flow is positive—see Figure 58. Conversely, if the power was negative, the energy register would underflow to full-scale positive (0x7F FFFF) and continue decreasing in value. By using the interrupt enable register, the ADE7763 can be configured to issue an interrupt (IRQ) when the active energy register is more than half full (positive or negative), or when an overflow or underflow occurs. Rev. C | Page 28 of 56 Data Sheet ADE7763 Integration Time under Steady Load A digital-to-frequency converter (DFC) is used to generate the CF pulsed output. The DFC generates a pulse each time 1 LSB in the active energy register is accumulated. An output pulse is generated when (CFDEN + 1)/(CFNUM + 1) number of pulses are generated at the DFC output. Under steady load conditions, the output frequency is proportional to the active power. As mentioned in the last section, the discrete time sample period (T) for the accumulation register is 1.1 µs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the WGAIN register set to 0x000, the average word value from each LPF2 is 0xC CCCD—see Figure 53. The maximum positive value that can be stored in the internal 49-bit register before it overflows is 248, or 0xFFFF FFFF FFFF. The integration time under these conditions with WDIV = 0 is calculated as follows: Time = 0xFFFF FFFF FFFF × 1.12 µs = 375.8 s = 6.26 min 0xC CCCD When WDIV is set to a value other than 0, the integration time varies, as shown in Equation 16. Time = TimeWDIV = 0 × WDIV (16) POWER OFFSET CALIBRATION The ADE7763 incorporates an active power offset register (APOS[15:0]). This is a signed, twos complement, 16-bit register that can be used to remove offsets in the active power calculation—see Figure 57. An offset could exist in the power calculation due to crosstalk between channels on the PCB or in the IC itself. The 256 LSBs (APOS = 0x0100) written to the active power offset register are equivalent to 1 LSB in the waveform sample register. Assuming the average value output from LPF2 is 0xC CCCD (838,861d) when inputs on Channels 1 and 2 are both at full scale. At −60 dB down on Channel 1 (1/1000 of the Channel 1 full-scale input), the average word value output from LPF2 is 838.861 (838,861/1,000). One LSB in the LPF2 output has a measurement error of 1/838.861 × 100% = 0.119% of the average value. The active power offset register has a resolution equal to 1/256 LSB of the waveform register; therefore, the power offset correction resolution is 0.00047%/LSB (0.119%/256) at –60 dB. ENERGY-TO-FREQUENCY CONVERSION The maximum output frequency, with ac input signals at full scale, CFNUM = 0x00, and CFDEN = 0x00, is approximately 23 kHz. (15) There are two unsigned, 12-bit registers, CFNUM[11:0] and CFDEN[11:0], that can be used to set the CF frequency to a wide range of values. These frequency-scaling registers are 12-bit registers that can scale the output frequency by 1/212 to 1 with a step of 1/212. If the value 0 is written to any of these registers, the value 1 will be applied to the register. The ratio (CFNUM + 1)/(CFDEN + 1) should be smaller than 1 to ensure proper operation. If the ratio of the registers (CFNUM + 1)/(CFDEN + 1) is greater than 1, the register values will be adjusted to a ratio (CFNUM + 1)/ (CFDEN + 1) of 1. For example, if the output frequency is 1.562 kHz while the contents of CFDEN are 0 (0x000), then the output frequency can be set to 6.1 Hz by writing 0xFF to the CFDEN register. When CFNUM and CFDEN are both set to one, the CF pulse width is fixed at 16 CLKIN/4 clock cycles, approximately 18 µs with a CLKIN of 3.579545 MHz. If the CF pulse output is longer than 180 ms for an active energy frequency of less than 5.56 Hz, the pulse width is fixed at 90 ms. Otherwise, the pulse width is 50% of the duty cycle. The output frequency has a slight ripple at a frequency equal to twice the line frequency. This is due to imperfect filtering of the instantaneous power signal to generate the active power signal— see the Active Power Calculation section. Equation 8 gives an expression for the instantaneous power signal. This is filtered by LPF2, which has a magnitude response given by Equation 17. The ADE7763 provides energy-to-frequency conversion for calibration purposes. After initial calibration at manufacturing, the manufacturer or end customer often verifies the energy meter calibration. One convenient way to verify the meter calibration is for the manufacturer to provide an output frequency, which is proportional to the energy or active power under steady load conditions. This output frequency can provide a simple, singlewire, optically isolated interface to external calibration equipment. Figure 59 illustrates the energy-to-frequency conversion. CFNUM[11:0] 11 % DFC 48 0 CF 0 11 0 CFDEN[11:0] 04481-A-060 AENERGY[48:0] Figure 59. Energy-to-Frequency Conversion Rev. C | Page 29 of 56 H( f ) = 1 f2 1+ 8.9 2 (17) ADE7763 Data Sheet The active power signal (output of LPF2) can be rewritten as       VI p (t )  VI     cos( 4 f L t ) 2   2 fL    1     8.9    higher output frequencies. The ripple becomes larger as a percentage of the frequency at larger loads and higher output frequencies. This occurs because the integration or averaging time in the energy-to-frequency conversion process is shorter at higher output frequencies. Consequently, some of the sinusoidal ripple in the energy signal is observable in the frequency output. Choosing a lower output frequency at CF for calibration can significantly reduce the ripple. Also, averaging the output frequency by using a longer gate time for the counter achieves the same results. (18) where fL is the line frequency, for example, 60 Hz. From Equation 13,       VI E (t )  VIt     sin( 4 f L t ) 2   2 fL    4 f L 1      8.9    E(t) Vlt Note that in Equation 19 there is a small ripple in the energy calculation due to a sin(2ωt) component. This is shown graphically in Figure 60. The active energy calculation is represented by the dashed, straight line and is equal to V × I × t. The sinusoidal ripple in the active energy calculation is also shown. Because the average value of a sinusoid is 0, the ripple does not contribute to the energy calculation over time. However, the ripple might be observed in the frequency output, especially at VI 4fL(1+2fL/8.9Hz ) – sin(4fLt) t Figure 60. Output Frequency Ripple WGAIN[11:0] OUTPUT FROM LPF2 + % 0 WDIV[7:0] 23 LPF1 FROM CHANNEL 2 ADC 48 ZERO CROSSING DETECTION CALIBRATION CONTROL 0 LAENERGY[23:0] LINECYC[15:0] Figure 61. Energy Calculation Line Cycle Energy Accumulation Mode Rev. C | Page 30 of 56 ACCUMULATE ACTIVE ENERGY IN INTERNAL REGISTER AND UPDATE THE LAENERGY REGISTER AT THE END OF LINECYC LINE CYCLES 04481-A-062 APOS[15:0] + 04481-0-061 (19) Data Sheet ADE7763 LINE CYCLE ENERGY ACCUMULATION MODE In line cycle energy accumulation mode, the energy accumulation of the ADE7763 can be synchronized to the Channel 2 zero crossing so that active energy accumulates over an integral number of half line cycles. The advantage of summing the active energy over an integral number of line cycles is that the sinusoidal component in the active energy is reduced to 0. This eliminates ripple in the energy calculation. Energy is calculated more accurately and in a shorter time because the integration period is shortened. By using the line cycle energy accumulation mode, the energy calibration can be greatly simplified, and the time required to calibrate the meter can be significantly reduced. The ADE7763 is placed in line cycle energy accumulation mode by setting Bit 7 (CYCMODE) in the mode register. In line cycle energy accumulation mode, the ADE7763 accumulates the active power signal in the LAENERGY register (Address 0x04) for an integral number of line cycles, as shown in Figure 61. The number of half line cycles is specified in the LINECYC register (Address 0x1C). The ADE7763 can accumulate active power for up to 65,535 half line cycles. Because the active power is integrated on an integral number of line cycles, the CYCEND flag in the interrupt status register is set (Bit 2) at the end of a line cycle energy accumulation cycle. If the CYCEND enable bit in the interrupt enable register is enabled, the IRQ output also will go active low. Therefore, the IRQ line can also be used to signal the completion of the line cycle energy accumulation. Another calibration cycle can start as long as the CYCMODE bit in the mode register is set. Note that in this mode, the 16-bit LINECYC register can hold a maximum value of 65,535. In other words, the line energy accumulation mode can be used to accumulate active energy for a maximum duration of 65,535 half line cycles. At 60 Hz line frequency, this translates to a total duration of 65,535/ 120 Hz = 546 seconds. POSITIVE-ONLY ACCUMULATION MODE In positive-only accumulation mode, the active energy accumulation is only done for positive power, ignoring any occurrence of negative power above or below the no-load threshold, as shown in Figure 62. The CF pulse also reflects this accumulation method when in this mode. Positive-only accumulation mode is activated by setting the MSB of the mode register (MODE[15]) and effects only the active power. The default setting for this mode is off. Transitions in the direction of power flow, going from negative to positive or positive to negative, set the IRQ pin to active low if the PPOS and PNEG bits are set in the interrupt enable register. The corresponding PPOS and PNEG bits in the interrupt status register show which transition has occurred—see the register descriptions in Table 9. ACTIVE ENERGY From Equations 13 and 18,    nT    cos( 2 f t ) dt  0    NO-LOAD THRESHOLD (20) ACTIVE POWER NO-LOAD THRESHOLD where: IRQ n is an integer. T is the line cycle period. PPOS Since the sinusoidal component is integrated over an integral number of line cycles, its value is always 0. Therefore,  nT E  VIdt  0 (21) 0 E  t   VInT PNEG PPOS PNEG PPOS PNEG INTERRUPT STATUS REGISTERS (22) 04481-A-063   nT  VI E (t )  VI dt   2   f  0   1   8.9   Figure 62. Energy Accumulation in Positive-Only Accumulation Mode NO-LOAD THRESHOLD The ADE7763 includes a no-load threshold feature on the active energy that eliminates any creep effects in the meter. This is accomplished because energy does not accumulate if the multiplier output is below the no-load threshold. This threshold is 0.001% of the full-scale output frequency of the multiplier. Compare this value to the IEC1036 specification, which states that the meter must start up with a load equal to or less than 0.4% Ib. This standard translates to 0.0167% of the full-scale output frequency of the multiplier. Rev. C | Page 31 of 56 ADE7763 Data Sheet The apparent power is the maximum power that can be delivered to a load. Vrms and Irms are the effective voltage and current delivered to the load; the apparent power (AP) is defined as Vrms × Irms. The angle θ between the active power and the apparent power generally represents the phase shift due to nonresistive loads. For single-phase applications, θ represents the angle between the voltage and the current signals—see Figure 63. Equation 24 gives an expression of the instantaneous power signal in an ac system with a phase shift. APPARENT POWER 04481-A-064 REACTIVE POWER  ACTIVE POWER Figure 63. Power Triangle v(t )  2 Vrms sin( t ) i (t )  2 I rms sin(t   ) (23) The gain of the apparent energy can be adjusted by using the multiplier and VAGAIN register (VAGAIN[11:0]). The gain is adjusted by writing a twos complement, 12-bit word to the VAGAIN register. Equation 25 shows how the gain adjustment is related to the contents of the VAGAIN register.   VAGAIN   OutputVAGAIN   Apparent Power  1    (25) 212     For example, when 0x7FF is written to the VAGAIN register, the power output is scaled up by 50%. 0x7FF = 2047d, 2047/212 = 0.5. Similarly, 0x800 = –2047d (signed, twos complement) and power output is scaled by –50%. Each LSB represents 0.0244% of the power output. The apparent power is calculated with the current and voltage rms values obtained in the rms blocks of the ADE7763. Figure 65 shows the maximum code (hexadecimal) output range of the apparent power signal. Note that the output range changes depending on the contents of the apparent power gain registers. The minimum output range is given when the apparent power gain register content is equal to 0x800; the maximum range is given by writing 0x7FF to the apparent power gain register. This can be used to calibrate the apparent power (or energy) calculation in the ADE7763. APPARENT POWER 100% FS APPARENT POWER 150% FS APPARENT POWER 50% FS p (t )  v (t )  i (t ) p (t )  Vrms I rms cos( )  Vrms I rms cos( 2t   ) (24) 0x10 3880 The apparent power is defined as Vrms × Irms. This expression is independent from the phase angle between the current and the voltage. 0xA D055 0x5 682B 0x0 0000 Figure 64 illustrates the signal processing in each phase for the calculation of the apparent power in the ADE7763. CURRENT RMS SIGNAL – i(t) MULTIPLIER 0x7FF 0x800 {VAGAIN[11:0]} APPARENT POWER CALIBRATION RANGE, VOLTAGE AND CURRENT CHANNEL INPUTS: 0.5V/GAIN APPARENT POWER SIGNAL (P) IRMS 0x000 0xA D055 0x1C 82B3 04481-A-066 APPARENT POWER CALCULATION Figure 65. Apparent Power Calculation Output Range 0x00 Apparent Power Offset Calibration VRMS VAGAIN 0x17 D338 0x00 Figure 64. Apparent Power Signal Processing 04481-A-065 VOLTAGE RMS SIGNAL– v(t) Each rms measurement includes an offset compensation register to calibrate and eliminate the dc component in the rms value—see the Channel 1 RMS Calculation and Channel 2 RMS Calculation sections. The Channel 1 and Channel 2 rms values are then multiplied together in the apparent power signal processing. Because no additional offsets are created in the multiplication of the rms values, there is no specific offset compensation in the apparent power signal processing. The offset compensation of the apparent power measurement is done by calibrating each individual rms measurement. Rev. C | Page 32 of 56 Data Sheet ADE7763 APPARENT ENERGY CALCULATION 23 VAENERGY[23:0] 0 The apparent energy is given as the integral of the apparent power. 48 (26) % VADIV APPARENT POWER 48 + 0 +    Apparent Energy  Lim  Apparent Power ( nT )  T  (27) T 0    n 0  ACTIVE POWER SIGNAL = P T where: n is the discrete number of time samples. T is the time sample period. The discrete time sample period (T) for the accumulation register is 1.1 μs (4/CLKIN). APPARENT POWER IS ACCUMULATED (INTEGRATED) IN THE APPARENT ENERGY REGISTER 04481-A-067 The ADE7763 achieves the integration of the apparent power signal by continuously accumulating the apparent power signal in an internal 49-bit register. The apparent energy register (VAENERGY[23:0]) represents the upper 24 bits of this internal register. This discrete time accumulation or summation is equivalent to integration in continuous time. Equation 29 expresses this relationship. 0 TIME (nT) Figure 66. Apparent Energy Calculation Figure 66 shows this discrete time integration or accumulation. The apparent power signal is continuously added to the internal register. This addition is a signed addition, even if the apparent energy always remains positive in theory. The 49 bits of the internal register are divided by VADIV. If the value in the VADIV register is 0, then the internal active energy register is divided by 1. VADIV is an 8-bit, unsigned register. The upper 24 bits are then written in the 24-bit apparent energy register (VAENERGY[23:0]). RVAENERGY register (24 bits long) is provided to read the apparent energy. This register is reset to 0 after a read operation. Figure 67 shows this apparent energy accumulation for fullscale signals (sinusoidal) on the analog inputs. The three curves illustrate the minimum time for the energy register to roll over when the VAGAIN registers content is equal to 0x7FF, 0x000, and 0x800. The VAGAIN register is used to carry out an apparent power calibration. As shown in the figure, the fastest integration time occurs when the VAGAIN register is set to maximum full scale, i.e., 0x7FF. VAENERGY[23:0] 0xFF FFFF VAGAIN = 0x7FF VAGAIN = 0x000 VAGAIN = 0x800 0x80 0000 0x40 0000 0x20 0000 0x00 0000 6.26 12.52 18.78 25.04 TIME (minutes) 04481-A-068  Apparent Energy  Apparent Power (t ) dt Figure 67. Energy Register Rollover Time for Full-Scale Power (Maximum and Minimum Power Gain) Note that the apparent energy register is unsigned—see Figure 67. By using the interrupt enable register, the ADE7763 can be configured to issue an interrupt (IRQ) when the apparent energy register is more than half full or when an overflow occurs. The half full interrupt for the unsigned apparent energy register is based on 24 bits, as opposed to 23 bits for the signed active energy register. Rev. C | Page 33 of 56 ADE7763 Data Sheet Integration Times under Steady Load By using the on-chip zero-crossing detection, the ADE7763 accumulates the apparent power signal in the LVAENERGY register for an integral number of half cycles, as shown in Figure 68. The line apparent energy accumulation mode is always active. As mentioned in the last section, the discrete time sample period (T) for the accumulation register is 1.1 µs (4/CLKIN). With full-scale sinusoidal signals on the analog inputs and the VAGAIN register set to 0x000, the average word value from the apparent power stage is 0xA D055. The maximum value that can be stored in the apparent energy register before it overflows is 224 or 0xFF FFFF. The average word value is added to the internal register, which can store 248 or 0xFFFF FFFF FFFF before it overflows. Therefore, the integration time under these conditions with VADIV = 0 is calculated as follows: 0xFFFF FFFF FFFF × 1.2 µs = 888 s = 12.52 min (28) 0xAD055 When VADIV is set to a value other than 0, the integration time varies, as shown in Equation 29. Time = TimeWDIV = 0 × VADIV (29) LINE APPARENT ENERGY ACCUMULATION The line apparent energy accumulation uses the same signal path as the apparent energy accumulation. The LSB size of these two registers is equivalent. The ADE7763 is designed with a special apparent energy accumulation mode, which simplifies the calibration process. APPARENT POWER + + 48 LVAENERGY REGISTER IS UPDATED EVERY LINECYC ZERO CROSSINGS WITH THE TOTAL APPARENT ENERGY DURING THAT DURATION VADIV[7:0] LPF1 FROM CHANNEL 2 ADC ZERO-CROSSING DETECTION 0 % CALIBRATION CONTROL 0 23 LVAENERGY[23:0] LINECYC[15:0] Figure 68. Apparent Energy Calibration Rev. C | Page 34 of 56 04481-A-069 Time = The number of half line cycles is specified in the LINECYC register, which is an unsigned, 16-bit register. The ADE7763 can accumulate apparent power for up to 65,535 combined half cycles. Because the apparent power is integrated on the same integral number of line cycles as the line active energy register, these two values can be easily compared. The active and apparent energies are calculated more accurately because of this precise timing control. At the end of an energy calibration cycle, the CYCEND flag in the interrupt status register is set. If the CYCEND mask bit in the interrupt mask register is enabled, the IRQ output also will go active low. Thus, the IRQ line can also be used to signal the end of a calibration. Data Sheet ADE7763 ENERGIES SCALING PF = 1 Integrator on at 50 Hz Active Wh Apparent Wh × 0.848 Integrator off at 50 Hz Active Wh Apparent Wh × 0.848 Integrator on at 60 Hz Active Wh Apparent Wh × 0.827 Integrator off at 60 Hz Active Wh Apparent Wh × 0.827 PF = 0.707 PF = 0 Wh × 0.707 Wh × 0.848 0 Wh × 0.848 Wh × 0.707 Wh × 0.848 0 Wh × 0.848 Wh × 0.707 Wh × 0.827 0 Wh × 0.827 Wh × 0.707 Wh × 0.827 0 Wh × 0.827 CALIBRATING AN ENERGY METER The ADE7763 provides gain and offset compensation for active and apparent energy calibration. Its phase compensation corrects phase error in active and apparent energy. If a shunt is used, offset and phase calibration may not be required. A reference meter or an accurate source can be used to calibrate the ADE7763. The ADE7763 provides a line cycle accumulation mode for calibration using an accurate source. In this method, the active energy accumulation rate is adjusted to produce a desired CF frequency. The benefit of using this mode is that the effect of the ripple noise on the active energy is eliminated. Up to 65,535 half line cycles can be accumulated, therefore providing a stable energy value to average. The accumulation time is calculated from the line cycle period, measured by the period register, and the number of half line cycles in the accumulation, fixed by the LINECYC register. Current and voltage rms offset calibration removes apparent energy offset. A gain calibration is also provided for apparent energy. Figure 70 shows an optimized calibration flow for active energy, rms, and apparent energy. Active and apparent energy gain calibrations can take place concurrently, with a read of the accumulated apparent energy register following that of the accumulated active energy register. Figure 69 shows the calibration flow for the active energy portion of the ADE7763. WATT GAIN CALIBRATION RMS CALIBRATION PHASE CALIBRATION Figure 69. Active Energy Calibration When using a reference meter, the ADE7763 calibration output frequency, CF, is adjusted to match the frequency output of the reference meter. A pulse output is only provided for the active WATT/VA GAIN CALIBRATION WATT OFFSET CALIBRATION WATT OFFSET CALIBRATION Figure 70. Apparent and Active Energy Calibration Rev. C | Page 35 of 56 PHASE CALIBRATION 04481-A-083 Table 7. Energies Scaling energy measurement in the ADE7763. If a reference meter is used to calibrate the VA, then additional code must be written in a microprocessor to produce a pulsed output for this quantity. Otherwise, VA calibration requires an accurate source. 04481-A-084 The ADE7763 provides measurements of active and apparent energies. These measurements do not have the same scaling and therefore cannot be compared directly to each other. ADE7763 Data Sheet Watt Gain The first step of calibrating the gain is to define the line voltage, the base current, and the maximum current for the meter. A meter constant, such as 3200 imp/kWh or 3.2 imp/Wh, needs to be determined for CF. Note that the line voltage and the maximum current scale to half of their respective analog input ranges in this example. The expected CF in Hz is CFexpected (Hz) = MeterConstant (imp/Wh) × Load(W) 3600 s/h × cos(ϕ) (30) where: ϕ is the angle between I and V. cos (ϕ) is the power factor. The ratio of active energy LSBs per CF pulse is adjusted using the CFNUM, CFDEN, and WDIV registers. CFexpected = (CFNUM + 1) LAENERGY × WDIV × AccumulationTime(s) (CFDEN + 1) (31) LSB = Load(W) × Accumulation Time(s) LAENERGY × 3600 s/h (32) where Accumulation Time can be determined from the value in the line period and the number of half line cycles fixed in the LINECYC register. Accumulation time(s) = LINECYC IB × Line Period(s) 2 (33) The line period can be determined from the period register: 8 Line Period(s) = PERIOD × CLKIN (CFNUM + 1) (CFDEN + 1) WGAIN  × 1 +  2 12   (37) When calibrating with a reference meter, WGAIN is adjusted until CF matches the reference meter pulse output. If an accurate source is used to calibrate, WGAIN will be modified until the active energy accumulation rate yields the expected CF pulse rate. The steps of designing and calibrating the active energy portion of a meter with either a reference meter or an accurate source are outlined in the following examples. The specifications for this example are Meter Constant: Base Current: Maximum Current: Line Voltage: Line Frequency: MeterConstant(imp/Wh) = 3.2 Ib = 10 A IMAX = 60 A Vnominal = 220 V fl = 50 Hz The expected CF output for this meter with the base current applied is 1.9556 Hz using Equation 30. CFIB(expected)(Hz) = 3.200 imp/Wh × 10 A × 220 V 3600 s/h × cos(ϕ) = 1.9556 Hz Alternatively, CFexpected can be measured from a reference meter pulse output. CFexpected(Hz) = CFref (34) The AENERGY Wh/LSB ratio can also be expressed in terms of the meter constant: (CFNUM + 1) × WDIV (CFDEN + 1) Wh = LSB MeterConstant (imp/Wh) CFexpected (Hz) = CFnominal × (36) The first step in calibration with either a reference meter or an accurate source is to calculate the CF denominator, CFDEN. This is done by comparing the expected CF pulse output to the nominal CF output with the default CFDEN = 0x3F and CFNUM = 0x3F when the base current is applied. The relationship between watt-hours accumulated and the quantity read from AENERGY can be determined from the amount of active energy accumulated over time with a given load: Wh WGAIN  AENERGYexpected = AENERGYnominal × 1 +  212   (35) In a meter design, WDIV, CFNUM, and CFDEN should be kept constant across all meters to ensure that the Wh/LSB constant is maintained. Leaving WDIV at its default value of 0 ensures maximum resolution. The WDIV register is not included in the CF signal chain, so it does not affect the frequency pulse output. The WGAIN register is used to finely calibrate each meter. Calibrating the WGAIN register changes both CF and AENERGY for a given load condition. (38) The maximum CF frequency measured without any frequency division and with ac inputs at full scale is 23 kHz. For this example, the nominal CF with the test current, Ib, applied is 958 Hz. In this example the line voltage and maximum current scale half of their respective analog input ranges. The line voltage and maximum current should not be fixed at the maximum analog inputs to account for occurrences such as spikes on the line. CFnominal(Hz) = 23 kHz × 1 2 × 1 2 × I I MAX (39) CFIB(nominal)(Hz) = 23 kHz × 1 2 × 1 2 × 10 60 = 958 Hz The nominal CF on a sample set of meters should be measured using the default CFDEN, CFNUM, and WDIV to ensure that the best CFDEN is chosen for the design. With the CFNUM register set to 0, CFDEN is calculated to be 489 for the example meter: Rev. C | Page 36 of 56 Data Sheet ADE7763  CFIB(nominal) CFDEN = INT   CFIB(expected )    −1   (40) 958  CFDEN = INT   − 1 = (490 − 1) = 489  1.9556  This value for CFDEN should be loaded into each meter before calibration. The WGAIN register can then be used to finely calibrate the CF output. The following sections explain how to calibrate a meter based on ADE7763 when using a reference meter or an accurate source. For this example: Meter Constant: MeterConstant(imp/Wh) = 3.2 CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 %ERROR Measured at Base Current: %ERRORCF(IB) = −3.07% One LSB change in WGAIN changes the active energy registers and CF by 0.0244%. WGAIN is a signed, twos complement register and can correct up to a 50% error. Assuming a −3.07% error, WGAIN is 126: Calibrating Watt Gain Using a Reference Meter Example The CFDEN and CFNUM values for the design should be written to their respective registers before beginning the calibration steps shown in Figure 71. When using a reference meter, the percent error in CF is measured by comparing the CF output of the ADE7763 meter with the pulse output of the reference meter, using the same test conditions for both meters. Equation 41 defines the percent error with respect to the pulse outputs of both meters (using the base current, Ib): %ERRORCF(IB) = CFIB − CFref ( IB ) CFref ( IB ) × 100 (41)  % ERRORCF (IB ) WGAIN = INT  − 0.0244%  (42) −3.07%  WGAIN = INT  −  = 126  0.0244%  When CF is calibrated, the AENERGY register has the same Wh/LSB constant from meter to meter if the meter constant, WDIV, and the CFNUM/CFDEN ratio remain the same. The Wh/LSB ratio for this meter is 6.378 × 10−4 using Equation 35 with WDIV at the default value. (CFNUM + 1) × WDIV (CFDEN + 1) Wh = LSB MeterConstant (imp/Wh) CALCULATE CFDEN VALUE FOR DESIGN Wh WRITE CFDEN VALUE TO CFDEN REGISTER ADDR. 0x15 = CFDEN 1 (490 + 1) 1 /4 LSB = 3.200 imp/Wh = 490 × 3.2 = 6.378 × 10 Calibrating Watt Gain Using an Accurate Source Example SET ITEST = Ib, VTEST = VNOM, PF = 1 MEASURE THE % ERROR BETWEEN THE CF OUTPUT AND THE REFERENCE METER OUTPUT 04481-A-085 CALCULATE WGAIN. SEE EQUATION 42. WRITE WGAIN VALUE TO THE WGAIN REGISTER: ADDR. 0x12    Figure 71. Calibrating Watt Gain Using a Reference Meter The CFDEN value calculated using Equation 40 should be written to the CFDEN register before beginning calibration and zero should be written to the CFNUM register. Enable the line accumulation mode and the line accumulation interrupt. Then, write the number of half line cycles for the energy accumulation to the LINECYC register to set the accumulation time. Reset the interrupt status register and wait for the line cycle accumulation interrupt. The first line cycle accumulation results might not use the accumulation time set by the LINECYC register and, therefore, should be discarded. After resetting the interrupt status register, the following line cycle readings will be valid. When LINECYC half line cycles have elapsed, the IRQ pin goes active low and the nominal LAENERGY with the test current applied can be read. This LAENERGY value is compared to the expected LAENERGY value to determine the WGAIN value. If apparent energy gain calibration is performed at the same time, LVAENERGY can be read directly after LAENERGY. Both registers should be read before the next interrupt is issued on the IRQ pin. Figure 72 details steps to calibrate the watt gain using an accurate source. Rev. C | Page 37 of 56 ADE7763 Data Sheet LAENERGYIB(expected) = CALCULATE CFDEN VALUE FOR DESIGN     CF Accumulati (s) × on Time  IB(expected )  INT   CFNUM + 1   × WDIV   CFDEN + 1   WRITE CFDEN VALUE TO CFDEN REGISTER ADDR. 0x15 = CFDEN SET ITEST = Ib, VTEST = VNOM, PF = 1 where CFIB(expected) (Hz) is calculated from Equation 30, accumulation time is calculated from Equation 33, and the line period is determined from the period register according to Equation 34. SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR. 0x1C SET MODE FOR LINE CYCLE ACCUMULATION ADDR. 0x09 = 0x0080 For this example: Meter Constant: MeterConstant(imp/Wh) = 3.2 Test Current: Ib = 10 A Line Voltage: Vnominal = 220 V Line Frequency: fl = 50 Hz Half Line Cycles: LINECYCIB = 2000 CF Numerator: CFNUM = 0 CF Denominator: CFDEN = 489 Energy Reading at Base Current: LAENERGYIB (nominal) = 17174 Period Register Reading: PERIOD = 8959 Clock Frequency: CLKIN = 3.579545 MHz ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR. 0x0A = 0x04 RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C INTERRUPT? NO YES RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C INTERRUPT? CFexpected is calculated to be 1.9556 Hz according to Equation 30. LAENERGYexpected is calculated to be 19186 using Equation 44. CFIB(expected)(Hz) = 3.200 imp/Wh × 220 V × 10 A NO 3600 s/h YES × cos(ϕ) = 1.9556 Hz LAENERGYIB(expected) = INT READ LINE ACCUMULATION ENERGY ADDR. 0x04     CF LINECYC PERIOD CLKIN × × × / 2 8 /  IB(expected )  IB   CFNUM + 1   × WDIV   CFDEN + 1   04481-A-086 CALCULATE WGAIN. SEE EQUATION 43. WRITE WGAIN VALUE TO THE WGAIN REGISTER: ADDR. 0x12 (44) Figure 72. Calibrating Watt Gain Using an Accurate Source LAENERGYIB(expected) = Equation 43 describes the relationship between the expected LAENERGY value and the LAENERGY measured in the test condition:    6  1 . 9556 2000 / 2 8959 8 /( 3 . 579545 10 ) × × × × 1 = INT    1   489 + 1     LAENERGYIB (expected )   WGAIN = INT   − 1 × 212  (43)   LAENERGYIB ( nominal )      INT (19186.4) = 19186 The nominal LAENERGY reading, LAENERGYIB(nominal), is the LAENERGY reading with the test current applied. The expected LAENERGY reading is calculated from the following equation: WGAIN is calculated to be 480 using Equation 43. Rev. C | Page 38 of 56 Data Sheet ADE7763 Figure 73. Calibrating Watt Offset Using a Reference Meter  19186  WGAIN = INT   − 1 × 2 12  = 480 17174     For this example: Note that WGAIN is a signed, twos complement register. With WDIV and CFNUM set to 0, LAENERGY can be expressed as LAENERGYIB(expected) = INT (CFIB(expected ) × LINECYCIB / 2 × PERIOD × 8 / CLKIN × (CFDEN + 1)) Using Equation 45, APOS is −522 for this example. The calculated Wh/LSB ratio for the active energy register, using Equation 35 is 6.378 × 10−4 is Wh 1 (489 + 1) LSB = 3.200 imp/Wh = 6.378 × 10 CF Absolute Error = CFIMIN(nominal) − CFIMIN(expected) (%ERRORCF(IMIN)) × WIMIN × Offset calibration allows outstanding performance over a wide dynamic range, for example, 1000:1. To do this calibration two measurements are needed at unity power factor, one at Ib and the other at the lowest current to be corrected. Either calibration frequency or line cycle accumulation measurements can be used to determine the energy offset. Gain calibration should be performed prior to offset calibration. AENERGY Error Rate × 2 35 The AENERGY registers update at a rate of CLKIN/4. The twos complement APOS register provides a fine adjustment to the active power calculation. It represents a fixed amount of power offset to be adjusted every CLKIN/4. The 8 LSBs of the APOS register are fractional such that one LSB of APOS represents 1/256 of the least significant bit of the internal active energy register. Therefore, one LSB of the APOS register represents 2−33 of the AENERGY[23:0] active energy register. (47) Then, AENERGY Error Rate (LSB/s) = CFDEN + 1 CF Absolute Error × CFNUM + 1 (48) AENERGY Error Rate (LSB/s) = 490 0.000110933 × = 0.05436 1 (45) CLKIN MeterConstant (imp/Wh) 3600 CF Absolute Error =  1.3%  × 9.6 × 3.200 = 0.000110933 Hz   3600  100  Offset calibration is performed by determining the active energy error rate. After determining the active energy error rate, calculate the value to write to the APOS register to correct the offset. Using Equation 45, APOS is −522. APOS = − 0.05436 × 2 35 3.579545 × 10 6 = − 522 APOS can be represented as follows with CFNUM and WDIV set at 0: See the following sections for steps to determine the active energy error rate for both line accumulation and reference meter calibration options. APOS = − Calibrating Watt Offset Using a Reference Meter Example Figure 73 shows the steps involved in calibrating watt offset with a reference meter. SET ITEST = IMIN, VTEST = VNOM, PF = 1 MEASURE THE % ERROR BETWEEN THE CF OUTPUT AND THE REFERENCE METER OUTPUT, AND THE LOAD IN WATTS 04481-A-087 CALCULATE APOS. SEE EQUATION 45. WRITE APOS VALUE TO THE APOS REGISTER: ADDR. 0x11 (46) CF Absolute Error = /4 Watt Offset APOS = − MeterConstant(imp/Wh) = 3.2 IMIN = 40 mA WIMIN = 9.6 W %ERRORCF(IMIN) = 1.3% CFNUM = 0 CDEN = 489 CKIN = 3.579545 MHz Meter Constant: Minimum Current: Load at Minimum Current: CF Error at Minimum Current: CF Numerator: CF Denominator: Clock Frequency: Rev. C | Page 39 of 56 (% ERRORCF ( IMIN ) ) × WIMIN × MeterConstant (imp/Wh) × (CFDEN + 1) × 235 3600 CLKIN ADE7763 Data Sheet Calibrating Watt Offset with an Accurate Source Example Figure 74 is the flowchart for watt offset calibration with an accurate source. SET ITEST = IMIN, VTEST = VNOM, PF = 1 Number of Half Line Cycles used at Minimum Current: LINECYC(IMIN) = 35700 Active Energy Reading at Minimum Current: LAENERGYIMIN(nominal) = 1395 The LAENERGYexpected at IMIN is 1255 using Equation 49. LAENERGYIMIN(expected) = SET HALF LINE CYCLES FOR ACCUMULATION IN LINECYC REGISTER ADDR. 0x1C I LINECYCI MIN INT  MIN × LAENERGY IB(expected ) × LINECYC IB  IB SET MODE FOR LINE CYCLE ACCUMULATION ADDR. 0x09 = 0x0080 LAENERGYIMIN(expected) = 0.04 35700  INT  × 19186 ×  = INT (1369.80) = 1370 2000   10 ENABLE LINE CYCLE ACCUMULATION INTERRUPT ADDR. 0x0A = 0x04 where: RESET THE INTERRUPT STATUS READ REGISTER ADDR. 0x0C INTERRUPT? LAENERGYIB(expected) is the expected LAENERGY reading at Ib from the watt gain calibration. LINECYCIMIN is the number of half line cycles that energy is accumulated over when measuring at IMIN. NO More line cycles could be required at the minimum current to minimize the effect of quantization error on the offset calibration. For example, if a test current of 40 mA results in an active energy accumulation of 113 after 2000 half line cycles, one LSB variation in this reading represents a 0.8% error. This measurement does not provide enough resolution to calibrate a