ADF4001BRU

a 200 MHz Clock Generator PLL ADF4001 FEATURES 200 MHz Bandwidth 2.7 V to 5.5 V Power Supply Separate Charge Pump Supply (VP) Allows Extended Tuning Voltage in 5 V Systems Programmable Charge Pump Currents 3-Wire Serial Interface Hardware and Software Power-Down Mode Analog and Digital Lock Detect Hardware Compatible to the ADF4110/ADF4111/ ADF4112/ADF4113 Typical Operating Current 4.5 mA Ultralow Phase Noise 16-Lead TSSOP 20-Lead LFCSP GENERAL DESCRIPTION The ADF4001 clock generator can be used to implement clock sources for PLLs that require very low noise, stable reference signals. It consists of a low noise digital PFD (phase frequency detector), a precision charge pump, a programmable reference divider, and a programmable 13-bit N counter. In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete PLL (phase-locked loop) can be implemented if the synthesizer is used with an external loop filter and VCO (voltage controlled oscillator) or VCXO (voltage controlled crystal oscillator). The N minimum value of 1 allows flexibility in clock generation. APPLICATIONS Clock Generation Low Frequency PLLs Low Jitter Clock Source Clock Smoothing Frequency Translation SONET, ATM, ADM, DSLAM, SDM FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP RSET CPGND REFERENCE ADF4001 14-BIT R COUNTER REFIN PHASE FREQUENCY DETECTOR 14 CP CHARGE PUMP R COUNTER LATCH DATA 24-BIT INPUT REGISTER 22 FUNCTION LATCH LE CPI3 CPI2 SDOUT CPI1 CPI6 CPI5 CPI4 N COUNTER LATCH HIGH Z AVDD 13 MUXOUT MUX RFINA 13-BIT N COUNTER RFINB SDOUT M3 REV. B CURRENT SETTING 2 CURRENT SETTING 1 LOCK DETECT CLK CE AGND Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. M2 M1 DGND One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/461-3113 © 2013 Analog Devices, Inc. All rights reserved. ADF4001–SPECIFICATIONS1 (AV DD = DVDD = 3 V
10%, 5 V
10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND = CPGND = 0 V; RSET = 4.7 k; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .) Parameter B Version Unit RF CHARACTERISTICS (3 V) RF Input Frequency RF Input Sensitivity 5/165 –10/0 MHz min/max dBm min/max 10/200 20/200 MHz min/max MHz min/max 5/104 MHz min/max REFIN Input Sensitivity2 –5 dBm min REFIN Input Capacitance REFIN Input Current 10 ± 100 pF max µA max PHASE DETECTOR Phase Detector Frequency3 55 MHz max CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature 5 625 2.5 2.7/10 1 2 1.5 2 mA typ µA typ % typ kΩ typ nA typ % typ % typ % typ LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance 0.8 × DVDD 0.2 × DVDD ±1 10 V min V max µA max pF max LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage DVDD – 0.4 0.4 V min V max 2.7/5.5 AVDD AVDD/6.0 V min/V max V min/V max AVDD ≤ VP ≤ 6.0 V 5.5 0.4 1 mA max mA max µA typ 4.5 mA typical TA = 25°C –161 –153 dBc/Hz typ dBc/Hz typ –99 dBc/Hz typ @ 200 kHz PFD Frequency @ 1 MHz PFD Frequency @ VCXO Output @ 1 kHz Offset and 200 kHz PFD Frequency –90/–95 dBc typ/dBc typ @ 200 kHz/400 kHz and 200 kHz PFD Frequency RF CHARACTERISTICS (5 V) RF Input Frequency REFIN CHARACTERISTICS REFIN Input Frequency POWER SUPPLIES AVDD DVDD VP IDD4 (AIDD + DIDD) ADF4001 IP Low Power Sleep Mode NOISE CHARACTERISTICS ADF4001 Phase Noise Floor5 Phase Noise Performance6 200 MHz Output7 Spurious Signals 200 MHz Output7 Test Conditions/Comments See Figure 3 for Input Circuit –5/0 dBm min/max –10/0 dBm min/max See Figure 2 for Input Circuit For f < 5 MHz, Use DC-Coupled Square Wave (0 to VDD) AC-Coupled. When DC-Coupled: 0 to VDD Max (CMOS Compatible) Programmable: See Table V With RSET = 4.7 kΩ With RSET = 4.7 kΩ See Table V 0.5 V ≤ VCP ≤ VP – 0.5 0.5 V ≤ VCP ≤ VP – 0.5 VCP = VP/2 IOH = 500 µA IOL = 500 µA NOTES 1 Operating temperature range (B Version) is –40°C to +85°C. 2 AVDD = DVDD = 3 V; for AVDD = DVDD = 5 V, use CMOS compatible levels. 3 Guaranteed by design. Sample tested to ensure compliance. 4 TA = 25°C; AVDD = DVDD = 3 V; RFIN = 100 MHz. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 logN (where N is the N divider value). 6 The phase noise is measured with the EVAL-ADF4001EB1 evaluation board and the HP8562E spectrum analyzer. 7 fREFIN = 10 MHz; f PFD = 200 kHz; Offset Frequency = 1 kHz; f RF = 200 MHz; N = 1000; Loop B/W = 20 kHz. Specifications subject to change without notice. –2– REV. B ADF4001 TIMING CHARACTERISTICS (AV DD = DVDD = 3 V
10%, 5 V
10%; AVDD ≤ VP ≤ 6.0 V ; AGND = DGND = CPGND= 0 V; RSET = 4.7 k; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 .) Parameter Limit at TMIN to TMAX (B Version) Unit Test Conditions/Comments t1 t2 t3 t4 t5 t6 10 10 25 25 10 20 ns min ns min ns min ns min ns min ns min DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulsewidth Guaranteed by design but not production tested. Specifications subject to change without notice. t3 t4 CLOCK t1 DATA DB20 (MSB) t2 DB19 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE t5 LE Figure 1. Timing Diagram TSSOP θJA Thermal Impedance . . . . . . . . . . . . . . 150.4°C/W LFCSP θJA Thermal Impedance (Paddle Soldered) . . 122°C/W LFCSP θJA Thermal Impedance (Paddle Not Soldered) 216°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C ABSOLUTE MAXIMUM RATINGS 1, 2 (TA = 25°C, unless otherwise noted.) AVDD to GND3 . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . . . 0 V to +0.3 V VP to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V VP to AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +5.5 V Digital I/O Voltage to GND . . . . . . . . . –0.3 V to VDD + 0.3 V Analog I/O Voltage to GND . . . . . . . . . . –0.3 V to VP + 0.3 V REFIN, RFINA, RFINB to GND . . . . . . . –0.3 V to VDD + 0.3 V RFINA to RFINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±600 mV Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Maximum Junction Temperature . . . . . . . . . . . . . . . . . . 150°C NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 This device is a high performance RF integrated circuit with an ESD rating of