ADF4153YCPZ-RL

Fractional-N Frequency Synthesizer ADF4153 Data Sheet FEATURES GENERAL DESCRIPTION RF bandwidth to 4 GHz 2.7 V to 3.3 V power supply Separate VP allows extended tuning voltage Y version available: −40°C to +125°C Programmable fractional modulus Programmable charge pump currents 3-wire serial interface Analog and digital lock detect Power-down mode Pin-compatible with ADF4110/ADF4111/ADF4112/ADF4113 and ADF4106 Consistent RF output phase Loop filter design possible with ADIsimPLL Qualified for automotive applications The ADF4153 is a fractional-N frequency synthesizer that implements local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise digital phase frequency detector (PFD), a precision charge pump, and a programmable reference divider. There is a Σ-Δ based fractional interpolator to allow programmable fractional-N division. The INT, FRAC, and MOD registers define an overall N divider (N = (INT + (FRAC/MOD))). In addition, the 4-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phaselocked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and a voltage controlled oscillator (VCO). APPLICATIONS A simple 3-wire interface controls all on-chip registers. The device operates with a power supply ranging from 2.7 V to 3.3 V and can be powered down when not in use. CATV equipment Base stations for mobile radio (GSM, PCS, DCS, WiMAX, SuperCell 3G, CDMA, W-CDMA) Wireless handsets (GSM, PCS, DCS, CDMA, W-CDMA) Wireless LANs, PMR Communications test equipment FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP SDVDD RSET ADF4153 REFERENCE 4-BIT R COUNTER ×2 DOUBLER REFIN + PHASE FREQUENCY DETECTOR – VDD HIGH-Z CHARGE PUMP DGND LOCK DETECT MUXOUT CP OUTPUT MUX CURRENT SETTING VDD RDIV RFCP3 RFCP2 RFCP1 NDIV N-COUNTER RFINA RFINB THIRD ORDER FRACTIONAL INTERPOLATOR CLK DATA MODULUS REG INTEGER REG 03685-001 LE FRACTION REG 24-BIT DATA REGISTER AGND DGND CPGND Figure 1. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADF4153 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 R Divider Register, R1................................................................ 16 Applications ....................................................................................... 1 Control Register, R2 ................................................................... 16 General Description ......................................................................... 1 Noise and Spur Register, R3 ...................................................... 17 Functional Block Diagram .............................................................. 1 Reserved Bits ............................................................................... 17 Revision History ............................................................................... 3 Initialization Sequence .............................................................. 18 Specifications..................................................................................... 4 RF Synthesizer: A Worked Example ........................................ 18 Timing Specifications .................................................................. 5 Modulus ....................................................................................... 18 Absolute Maximum Ratings ............................................................ 6 Reference Doubler and Reference Divider ............................. 18 ESD Caution .................................................................................. 6 12-Bit Programmable Modulus ................................................ 18 Pin Configurations and Function Descriptions ........................... 7 Fastlock with Spurious Optimization ...................................... 19 Typical Performance Characteristics ............................................. 8 Spur Mechanisms ....................................................................... 19 Circuit Description ........................................................................... 9 Spur Consistency ........................................................................ 20 Reference Input Section ............................................................... 9 Phase Resync ............................................................................... 20 RF Input Stage ............................................................................... 9 Filter Design—ADIsimPLL....................................................... 20 RF INT Divider ............................................................................. 9 Interfacing ................................................................................... 20 INT, FRAC, MOD, and R Relationship ..................................... 9 PCB Design Guidelines for Chip Scale Package .................... 21 RF R Counter ................................................................................ 9 Applications Information .............................................................. 22 Phase Frequency Detector (PFD) and Charge Pump ............ 10 Local Oscillator for a GSM Base Station Transmitter ........... 22 MUXOUT and Lock Detect ...................................................... 10 Outline Dimensions ....................................................................... 23 Input Shift Registers ................................................................... 10 Ordering Guide .......................................................................... 24 Program Modes .......................................................................... 10 Automotive Products ................................................................. 24 N Divider Register, R0 ............................................................... 16 Rev. F | Page 2 of 24 Data Sheet ADF4153 REVISION HISTORY 11/13—Rev. E to Rev. F Change to ICP Sink/Source Parameter, Table 1 .............................. 4 Changes to Ordering Guide ...........................................................24 7/12—Rev. D to Rev. E Updated Outline Dimensions ........................................................23 Changes to Ordering Guide ...........................................................24 8/10—Rev. C to Rev. D Changes to Features Section ............................................................ 1 Changes to Noise Characteristics Parameter, Table 1 .................. 5 Changes to Figure 4........................................................................... 7 Changes to Ordering Guide ...........................................................24 Added Automotive Products Section ...........................................24 10/08—Rev. B to Rev. C Added Y Version (Throughout) ...................................................... 1 Changes to Ordering Guide ...........................................................23 08/05—Rev. A to Rev. B Changes to Features .......................................................................... 1 Changes to Applications ................................................................... 1 Changes to Specifications ................................................................. 3 Changes to Absolute Maximum Ratings ........................................ 5 Changes to Figure 7 to Figure 9....................................................... 7 Deleted Figure 8 to Figure 10; Renumbered Sequentially ........... 8 Deleted Figure 11 and Figure 14; Renumbered Sequentially ...... 9 Changes to Table 9 ..........................................................................13 Added Initialization Sequence Section ........................................ 17 Changes to Fastlock with Spurious Optimization Section ........ 18 Inserted Figure 16; Renumbered Sequentially ............................ 18 Added Spur Mechanisms Section ................................................. 18 Added Table 11; Renumbered Sequentially ................................. 18 Added Spur Consistency Section .................................................. 19 Changes to Phase Resync Section ................................................. 19 Inserted Figure 17; Renumbered Sequentially ............................ 19 Deleted Spurious Signals— Predicting Where They Will Appear Section .............................. 20 Changes to Figure 19 ...................................................................... 20 Changes to Figure 20 ...................................................................... 21 Added Applications Section .......................................................... 21 Changes to Figure 22 Caption ....................................................... 22 Changes to Ordering Guide ........................................................... 22 1/04—Rev. 0 to Rev. A Renumbered Figures and Tables ...................................... Universal Changes to Specifications................................................................. 3 Changes to Pin Function Description ............................................ 7 Changes to RF Power-Down Section ........................................... 17 Changes to PCB Design Guidelines for Chip Scale Package Section ............................................................................... 21 Updated Outline Dimensions........................................................ 22 Updated Ordering Guide ............................................................... 22 7/03—Revision 0: Initial Version Rev. F | Page 3 of 24 ADF4153 Data Sheet SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 1. Parameter RF CHARACTERISTICS (3 V) RF Input Frequency (RFIN) REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 4 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD, SDVDD VP IDD Low Power Sleep Mode B Version 1 Y Version 2 Unit 0.5/4.0 0.5/4.0 0.5/4.0 0.5/4.0 GHz min/max GHz min/max 1.0/4.0 1.0/4.0 GHz min/max 10/250 10/250 MHz min/max 0.7/AVDD 10 ±100 0.7/AVDD 10 ±100 V p-p min/max pF max µA max 32 32 MHz max 5 312.5 2.5 1.5/10 1 2 2 2 5 312.5 2.5 1.5/10 4.5 2 2 2 mA typ µA typ % typ kΩ min/max nA typ % typ % typ % typ 1.4 0.6 ±1 10 1.4 0.6 ±1 10 V min V max µA max pF max 1.4 0.4 1.4 0.4 V min V max 2.7/3.3 AVDD AVDD/5.5 24 1 2.7/3.3 AVDD AVDD/5.5 24 1 V min/V max V min/V max mA max µA typ Rev. F | Page 4 of 24 Test Conditions/Comments See Figure 12 for input circuit B Version: −8 dBm minimum/0 dBm maximum Y Version: −6.5 dBm minimum/0 dBm maximum For lower frequencies, ensure slew rate (SR) > 400 V/µs −10 dBm/0 dBm minimum/maximum See Figure 11 for input circuit For f < 10 MHz, use a dc-coupled, CMOS-compatible square wave; slew rate > 25 V/µs Biased at AVDD/2 3 Programmable; see Table 9 With RSET = 5.1 kΩ With RSET = 5.1 kΩ Sink and source current 0.5 V < VCP < VP – 0.5 0.5 V < VCP < VP – 0.5 VCP = VP/2 Open-drain 1 kΩ pull-up to 1.8 V IOL = 500 µA 20 mA typical Data Sheet ADF4153 Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 5 Normalized 1/f Noise (PN1_f) 6 Phase Noise Performance 7 1750 MHz Output 8 B Version 1 Y Version 2 Unit Test Conditions/Comments −220 −220 dBc/Hz typ PLL loop BW = 500 kHz −114 −114 dBc/Hz typ −102 −102 dBc/Hz typ Measured at 10 kHz offset, normalized to 1 GHz @ VCO output @ 5 kHz offset, 25 MHz PFD frequency Operating temperature for B version is −40°C to +85°C. Operating temperature for Y version is −40°C to +125°C. 3 AC coupling ensures AVDD/2 bias. 4 Guaranteed by design. Sample tested to ensure compliance. 5 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log(N) (where N is the N divider value) and 10 log(FPFD). PNSYNTH = PNTOT − 10 log(FPFD) − 20 log(N). 6 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, FRF, and at an offset frequency, f, is given by PN = P1_f + 10 log(10 kHz/f) + 20 log(FRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 7 The phase noise is measured with the EV-ADF4153SD1Z and the Agilent E5500 phase noise system. 8 fREFIN = 100 MHz; FPFD = 25 MHz; offset frequency = 5 kHz; RFOUT = 1750 MHz; N = 70; loop BW = 20 kHz; lowest noise mode. 1 2 TIMING SPECIFICATIONS AVDD = DVDD = SDVDD = 2.7 V to 3.3 V; VP = AVDD to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min t4 Test Conditions/Comments LE setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width t5 CLK t3 t2 DATA DB23 (MSB) DB22 DB2 DB0 (LSB) (CONTROL BIT C1) DB1 (CONTROL BIT C2) t7 LE t1 03685-026 t6 LE Figure 2. Timing Diagram Rev. F | Page 5 of 24 ADF4153 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, GND = AGND = DGND = 0 V, VDD = AVDD = DVDD = SDVDD, unless otherwise noted. Table 3. Parameter VDD to GND VDD to VDD VP to GND VP to VDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFIN to GND Operating Temperature Range Industrial (B Version) Extended (Y Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Maximum Junction Temperature Rating −0.3 V to +4 V −0.3 V to +0.3 V −0.3 V to +5.8 V −0.3 V to +5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −40°C to +85°C −40°C to +125°C −65°C to +125°C 150°C 112°C/W 30.4°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of