ADF4360-7BCPZRL

Integrated Synthesizer and VCO ADF4360-7 Data Sheet FEATURES GENERAL DESCRIPTION Output frequency range: 350 MHz to 1800 MHz Divide-by-2 output 3.0 V to 3.6 V power supply 1.8 V logic compatibility Integer-N synthesizer Programmable dual-modulus prescaler 8/9, 16/17 Programmable output power level 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode The ADF4360-7 is an integrated integer-N synthesizer and voltage controlled oscillator (VCO). The ADF4360-7 center frequency is set by external inductors. This allows a frequency range of between 350 MHz to 1800 MHz. In addition, a divideby-2 option is available, whereby the user receives an RF output of between 175 MHz and 900 MHz. Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use. APPLICATIONS Wireless handsets (DECT, GSM, PCS, DCS, WCDMA) Test equipment Wireless LANs CATV equipment FUNCTIONAL BLOCK DIAGRAM AVDD DVDD RSET CE ADF4360-7 MUXOUT MULTIPLEXER 14-BIT R COUNTER REFIN LOCK DETECT CLK DATA MUTE 24-BIT FUNCTION LATCH 24-BIT DATA REGISTER LE CHARGE PUMP CP PHASE COMPARATOR VVCO VTUNE L1 L2 CC CN INTEGER REGISTER RFOUTA VCO CORE 13-BIT B COUNTER 5-BIT A COUNTER MULTIPLEXER N = (BP + A) RFOUTB LOAD LOAD AGND DGND DIVSEL = 1 DIVSEL = 2 ÷2 04441-001 PRESCALER P/P+1 OUTPUT STAGE CPGND Figure 1. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2004–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF4360-7 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Shift Register .................................................................... 11 Applications ....................................................................................... 1 VCO ............................................................................................. 11 General Description ......................................................................... 1 Output Stage................................................................................ 12 Functional Block Diagram .............................................................. 1 Latch Structure ........................................................................... 13 Revision History ............................................................................... 2 Power-Up ..................................................................................... 17 Specifications..................................................................................... 3 Control Latch .............................................................................. 19 Timing Characteristics ..................................................................... 5 N Counter Latch ......................................................................... 20 Absolute Maximum Ratings ............................................................ 6 R Counter Latch ......................................................................... 20 Transistor Count ........................................................................... 6 Applications Information .............................................................. 21 ESD Caution .................................................................................. 6 Frequency Generator ................................................................. 21 Pin Configuration and Function Descriptions ............................. 7 Choosing the Correct Inductance Value ................................. 22 Typical Performance Characteristics ............................................. 8 Choosing the Appropriate PFD Frequency ............................ 22 Circuit Description ......................................................................... 10 Fixed Frequency LO ................................................................... 22 Reference Input Section ............................................................. 10 Interfacing ................................................................................... 23 Prescaler (P/P + 1) ...................................................................... 10 PCB Design Guidelines for Chip Scale Package........................... 23 A and B Counters ....................................................................... 10 Output Matching ........................................................................ 24 R Counter .................................................................................... 10 Outline Dimensions ....................................................................... 25 PFD and Charge Pump .............................................................. 10 Ordering Guide .......................................................................... 25 MUXOUT and Lock Detect ...................................................... 11 REVISION HISTORY 9/2018—Rev. E to Rev. F Added Choosing the Appropriate PFD Frequency Section ...... 22 4/2016—Rev. D to Rev. E Changed ADF4360 Family to ADF4360-7, ADSP-21xx to ADSP-2181, and EV-ADF4360-xEB1 to EV-ADF4360-7EB1Z..................................................... Throughout Changes to Figure 3 .......................................................................... 7 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 3/2013—Rev. C to Rev. D Changes to Prescaler (P/P + 1) Section ....................................... 10 11/2012—Rev. B to Rev. C Changes to Table 3 ............................................................................ 6 Updated Outline Dimensions ....................................................... 25 2/2012—Rev. A to Rev. B Changes to Figure 3 and Table 4......................................................8 Changes to Output Matching Section.......................................... 24 Updated Outline Dimensions ....................................................... 25 Changes to Ordering Guide .......................................................... 25 11/2004—Rev. 0 to Rev. A Updated Format .................................................................. Universal Changes to General Description .....................................................1 Changes to Specifications .................................................................3 Changes to the Reference Input Section...................................... 10 Changes to Power-Up Section ...................................................... 17 Added Table 10 ............................................................................... 17 Added Figure 22 ............................................................................. 17 Updated Outline Dimensions ....................................................... 25 2/2004—Revision 0: Initial Version Rev. F | Page 2 of 25 Data Sheet ADF4360-7 SPECIFICATIONS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency2 CHARGE PUMP ICP Sink/Source3 High Value Low Value RSET Range ICP Three-State Leakage Current Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage IOH, Output High Current VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VVCO AIDD4 DIDD4 IVCO4, 5 IRFOUT4 Low Power Sleep Mode B Version Unit Test Conditions/Comments 10/250 MHz min/max 0.7/AVDD 0 to AVDD 5.0 ±60 V p-p min/max V max pF max µA max For f < 10 MHz, use a dc-coupled CMOS-compatible square wave, slew rate > 21 V/µs. AC-coupled. CMOS compatible. 8 MHz max 2.5 0.312 2.7/10 0.2 2 1.5 2 mA typ mA typ kΩ nA typ % typ % typ % typ 1.5 0.6 ±1 3.0 V min V max µA max pF max DVDD – 0.4 500 0.4 V min µA max V max 3.0/3.6 AVDD AVDD 10 2.5 14.0 3.5 to 11.0 7 V min/V max With RSET = 4.7 kΩ. mA typ mA typ mA typ mA typ µA typ 1.25 V ≤ VCP ≤ 2.5 V. 1.25 V ≤ VCP ≤ 2.5 V. VCP = 2.0 V. CMOS output chosen. IOL = 500 µA. ICORE = 5 mA. RF output stage is programmable. Rev. F | Page 3 of 25 ADF4360-7 Parameter RF OUTPUT CHARACTERISTICS5 Maximum VCO Output Frequency Data Sheet B Version Unit Test Conditions/Comments 1800 MHz ICORE = 5 mA. Depending on L. See the Choosing the Correct Inductance Value section. Minimum VCO Output Frequency VCO Output Frequency 350 490/585 MHz MHz min/max VCO Frequency Range VCO Sensitivity 1.2 12 Ratio MHz/V typ 400 6 15 −19 −9 −14/−5 ±3 1.25/2.5 µs typ MHz/V typ kHz typ dBc typ dBc typ dBm typ dB typ V min/max −116 −138 −144 −148 −172 −163 −147 −92 0.3 −70 dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ dBc/Hz typ Degrees typ dBc typ −44 dBm typ Lock Time6 Frequency Pushing (Open Loop) Frequency Pulling (Open Loop) Harmonic Content (Second) Harmonic Content (Third) Output Power5, 7 Output Power Variation VCO Tuning Range NOISE CHARACTERISTIC5 VCO Phase-Noise Performance8 Synthesizer Phase-Noise Floor9 In-Band Phase Noise10, 11 RMS Integrated Phase Error12 Spurious Signals due to PFD Frequency11, 13 Level of Unlocked Signal with MTLD Enabled L1, L2 = 13 nH. See the Choosing the Correct Inductance Value section for other frequency values. FMAX/FMIN L1, L2 = 13 nH. See the Choosing the Correct Inductance Value section for other sensitivity values. To within 10 Hz of final frequency. Into 2.00 VSWR load. Programmable in 3 dB steps. See Table 7. For tuned loads, see Output Matching section. At 100 kHz offset from carrier. At 1 MHz offset from carrier. At 3 MHz offset from carrier. At 10 MHz offset from carrier. At 25 kHz PFD frequency. At 200 kHz PFD frequency. At 8 MHz PFD frequency. At 1 kHz offset from carrier. 100 Hz to 100 kHz. Operating temperature range is –40°C to +85°C. Guaranteed by design. Sample tested to ensure compliance. 3 ICP is internally modified to maintain constant loop gain over the frequency range. 4 TA = 25°C; AVDD = DVDD = VVCO = 3.3 V; P = 32. 5 Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 13 nH, 470 Ω resistors to GND in parallel with L1, L2. 6 Jumping from 490 MHz to 585 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz. 7 Using 50 Ω resistors to VVCO, into a 50 Ω load. For tuned loads, see the Output Matching section. 8 The noise of the VCO is measured in open-loop conditions. 9 The synthesizer phase-noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). 10 The phase noise is measured with the EV-ADF4360-7EB1Z Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REFIN for the synthesizer; offset frequency = 1 kHz. 11 fREFIN = 10 MHz; fPFD = 200 kHz; N = 2500; loop B/W = 10 kHz. 12 fREFIN = 10 MHz; fPFD = 1 MHz; N = 500; loop B/W = 25 kHz. 13 The spurious signals are measured with the EV-ADF4360-7EB1Z Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REFIN for the synthesizer; fREFOUT = 10 MHz at 0 dBm. 1 2 Rev. F | Page 4 of 25 Data Sheet ADF4360-7 TIMING CHARACTERISTICS1 AVDD = DVDD = VVCO = 3.3 V ± 10%; AGND = DGND = 0 V; 1.8 V and 3 V logic levels used; TA = TMIN to TMAX, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 t7 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE Setup Time DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width Refer to the Power-Up section for the recommended power-up procedure for this device. t4 t5 CLOCK t2 DATA DB23 (MSB) t3 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 LE t1 t6 04441-002 1 Limit at TMIN to TMAX (B Version) 20 10 10 25 25 10 20 LE Figure 2. Timing Diagram Rev. F | Page 5 of 25 ADF4360-7 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VVCO to GND VVCO to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN to GND Operating Temperature Maximum Junction Temperature CSP θJA Thermal Impedance Paddle Soldered Paddle Not Soldered Peak Soldering Reflow Temperature 1 Rating −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to +3.9 V −0.3 V to +0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V −0.3 V to VDD + 0.3 V 150°C 50°C/W 88°C/W 260°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. This device is a high performance RF integrated circuit with an ESD rating of