FEATURES
FUNCTIONAL BLOCK DIAGRAM
SPI interface with error detection
Includes CRC, invalid read/write address, and SCLK count
error detection
Supports burst mode and daisy-chain mode
Industry-standard SPI Mode 0 and Mode 3 interface compatible
Guaranteed break-before-make switching allowing external
wiring of switches to deliver multiplexer configurations
1.5 Ω typical on resistance at 25°C
0.3 Ω typical on resistance flatness at 25°C
0.1 Ω typical on resistance match between channels at 25°C
VSS to VDD analog signal range
Fully specified at ±15 V, ±5 V, and +12 V
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
24-lead LFCSP
ADGS1412
S1
D1
S2
D2
S3
D3
S4
D4
SPI
INTERFACE
SCLK SDI
CS
SDO
RESET/VL
14960-001
Data Sheet
SPI Interface, 1.5 Ω RON, ±15 V/+12 V,
Quad SPST Switch, Mux Configurable
ADGS1412
Figure 1.
APPLICATIONS
Automated test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communications systems
Relay replacement
GENERAL DESCRIPTION
The ADGS1412 contains four independent single-pole/singlethrow (SPST) switches. A serial peripheral interface (SPI)
controls the switches. The SPI interface has robust error detection
features such as cyclic redundancy check (CRC) error detection,
invalid read/write address detection, and SCLK count error
detection.
It is possible to daisy-chain multiple ADGS1412 devices together.
Daisy-chain mode enables the configuration of multiple devices
with a minimal amount of digital lines. The ADGS1412 can also
operate in burst mode to decrease the time between SPI
commands.
iCMOS construction ensures ultralow power dissipation, making
the device ideally suited for portable and battery-powered
instruments.
Each switch conducts equally well in both directions when on,
and each switch has an input signal range that extends to the
supplies. In the off condition, signal levels up to the supplies
are blocked.
Rev. B
The on-resistance profile is flat over the full analog input range,
which ensures good linearity and low distortion when switching
audio signals.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
SPI interface removes the need for parallel conversion,
logic traces and reduces general-purpose input/output
(GPIO) channel count.
Daisy-chain mode removes additional logic traces when
multiple devices are used.
CRC error detection, invalid read/write address detection,
and SCLK count error detection ensures a robust digital
interface.
CRC and error detection capabilities allow the use of the
ADGS1412 in safety critical systems.
Guaranteed break-before-make switching allows the use of
the ADGS1412 in multiplexer configurations with external
wiring.
Minimum distortion.
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Technical Support
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ADGS1412
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Error Detection Features ........................................................... 20
Applications ....................................................................................... 1
Clearing the Error Flags Register ............................................. 21
Functional Block Diagrams ............................................................. 1
Burst Mode .................................................................................. 21
General Description ......................................................................... 1
Software Reset ............................................................................. 21
Product Highlights ........................................................................... 1
Daisy-Chain Mode ..................................................................... 21
Revision History ............................................................................... 2
Power-On Reset .......................................................................... 22
Specifications..................................................................................... 3
Applications Information .............................................................. 23
±15 V Dual Supply ....................................................................... 3
Break-Before-Make Switching .................................................. 23
±5 V Dual Supply ......................................................................... 5
Digital Input Buffers .................................................................. 23
12 V Single Supply ........................................................................ 7
Power Supply Rails ..................................................................... 23
Continuous Current per Channel, Sx or Dx ............................. 9
Power Supply Recommendations............................................. 23
Timing Characteristics ................................................................ 9
Register Summary .......................................................................... 24
Absolute Maximum Ratings .......................................................... 11
Register Details ............................................................................... 25
Thermal Resistance .................................................................... 11
Switch Data Register .................................................................. 25
ESD Caution ................................................................................ 11
Error Configuration Register.................................................... 25
Pin Configurations and Function Descriptions ......................... 12
Error Flags Register .................................................................... 26
Typical Performance Characteristics ........................................... 13
Burst Enable Register ................................................................. 26
Test Circuits ..................................................................................... 17
Software Reset Register ............................................................. 26
Terminology .................................................................................... 19
Outline Dimensions ....................................................................... 27
Theory of Operation ...................................................................... 20
Ordering Guide .......................................................................... 27
Address Mode ............................................................................. 20
REVISION HISTORY
8/2017—Rev. A to Rev. B
Changes to Product Title, Features Section, and Product
Highlights Section ............................................................................ 1
Changes to Table 1 ............................................................................ 3
Changes to Table 2 ............................................................................ 5
Changes to Table 3 ............................................................................ 7
Changes to VL to GND Parameter and Digital Inputs Parameter,
Table 7 .............................................................................................. 11
Changes to Figure 17 ...................................................................... 14
Added Figure 27; Renumbered Sequentially .............................. 16
Changes to Figure 30 ...................................................................... 17
Added Figure 35.............................................................................. 17
Added Figure 36.............................................................................. 18
Change to Theory of Operation Section ..................................... 20
Added Break-Before-Make Switching Section, Figure 45, and
Digital Input Buffers Section......................................................... 23
Changes to Ordering Guide .......................................................... 27
3/2017—Rev. 0 to Rev. A
Changes to Features Section and Product Highlights Section ....1
Change to IL Inactive Parameter, Table 1........................................4
Change to VDD = 15 V, VSS = −15 V (θJA = 54°C/W) Parameter,
Table 5 ..................................................................................................7
Change to Theory of Operation Section ..................................... 18
Updated Outline Dimensions Section ......................................... 25
10/2016—Revision 0: Initial Version
Rev. B | Page 2 of 27
Data Sheet
ADGS1412
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
+25°C
−40°C to
+85°C
VDD to VSS
1.5
1.8
0.1
0.18
0.3
0.36
±0.03
±0.55
±0.03
±0.55
±0.15
±2
2.3
2.6
0.19
0.21
0.4
0.45
±2
±12.5
±2
±12.5
±4
±30
DIGITAL OUTPUT
Output Voltage
Low, VOL
High Impedance Leakage Current
−40°C to
+125°C
0.4
0.2
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = ±10 V, IS = −10 mA
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD = 10 V, see Figure 32
VS = ±10 V, VD = 10 V, see Figure 32
VS = VD = ±10 V, see Figure 28
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
4
400
ns typ
Load resistance (RL) = 300 Ω, load capacitance
(CL) = 35 pF
VS = 10 V, see Figure 37
RL = 300 Ω, CL = 35 pF
VS = 10 V, see Figure 37
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V, see Figure 36
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 30
RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz,
see Figure 33
4
2
1.35
0.8
0.8
0.001
Break-Before-Make Time Delay, tD
475
160
190
215
Charge Injection, QINJ
Off Isolation
Channel to Channel Crosstalk
Total Harmonic Distortion + Noise
−20
−76
−100
0.014
tOFF
VS = ±10 V, IS = −10 mA, see Figure 29
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −10 mA
V min
V min
V max
V max
μA typ
μA max
pF typ
0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
V
Ω typ
Ω max
Ω typ
ISINK = 5 mA
ISINK = 1 mA
Output voltage (VOUT) = ground voltage (VGND) or VL
Low, VINL
Input Current, IINL or IINH
Test Conditions/Comments
V max
V max
μA typ
μA max
pF typ
±0.1
High Impedance Output Capacitance
DIGITAL INPUTS
Input Voltage
High, VINH
Unit
480
485
210
225
170
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
Rev. B | Page 3 of 27
ADGS1412
Parameter
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
Data Sheet
+25°C
170
−0.2
22
23
113
−40°C to
+85°C
−40°C to
+125°C
0.001
1
220
380
230
380
Load current (IL)
Inactive
6.3
8.0
Inactive, SCLK = 1 MHz
SCLK = 50 MHz
Inactive, SDI = 1 MHz
SDI = 25 MHz
Active at 50 MHz
14
7
390
210
15
7.5
230
120
1.8
2
2.1
0.7
1.0
ISS
0.001
VDD/VSS
1
1.0
±4.5/±16.5
Unit
MHz typ
dB typ
pF typ
pF typ
pF typ
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
mA typ
mA max
mA typ
mA max
μA typ
μA max
V min/
V max
Guaranteed by design; not subject to production test.
Rev. B | Page 4 of 27
Test Conditions/Comments
RL = 50 Ω, CL = 5 pF, see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V
All switches open
All switches closed, VL = 5.5 V
All switches closed, VL = 2.7 V
Digital inputs = 0 V or VL
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Digital inputs toggle between 0 V and VL, VL = 5.5 V
Digital inputs toggle between 0 V and VL, VL = 2.7 V
Digital inputs = 0 V or VL
GND = 0 V
Data Sheet
ADGS1412
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
+25°C
−40°C to
+85°C
VDD to VSS
3.3
4
0.13
0.22
0.9
1.1
±0.03
±0.55
±0.03
±0.55
±0.05
±1.0
4.9
5.4
0.23
0.25
1.24
1.31
±2
±12.5
±2
±12.5
±4
±30
DIGITAL OUTPUT
Output Voltage
Low, VOL
High Impedance Leakage Current
−40°C to
+125°C
0.4
0.2
0.001
±0.1
High Impedance Output Capacitance
DIGITAL INPUTS
Input Voltage
High, VINH
4
2
1.35
0.8
0.8
Low, VINL
Input Current, IINL or IINH
0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
4
Break-Before-Make Time Delay, tD
510
645
280
365
245
Charge Injection, QINJ
Off Isolation
Channel to Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD (On), CS (On)
10
−76
−100
0.03
130
−0.3
32
33
116
tOFF
680
710
400
435
200
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = ±4.5 V, IS = −10 mA, see Figure 29
VDD = +4.5 V, VSS = −4.5 V
VS = ±4.5 V, IS = −10 mA
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = ±4.5 V, IS = −10 mA
VDD = +5.5 V, VSS = −5.5 V
VS = ±4.5 V, VD = 4.5 V, see Figure 32
VS = ±4.5 V, VD = 4.5 V, see Figure 32
VS = VD = ±4.5 V, see Figure 28
V max
V max
μA typ
μA max
pF typ
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
V min
V min
V max
V max
μA typ
μA max
pF typ
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF
VS = 3 V, see Figure 37
RL = 300 Ω, CL = 35 pF
VS = 3 V, see Figure 37
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 3 V, see Figure 36
VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 30
RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz, see Figure 33
RL = 50 Ω, CL = 5 pF, see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
Rev. B | Page 5 of 27
ADGS1412
Parameter
POWER REQUIREMENTS
IDD
Data Sheet
+25°C
−40°C to
+85°C
−40°C to
+125°C
0.001
1.0
14
20
Unit
μA typ
μA max
μA typ
μA max
Test Conditions/Comments
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or VL, VL = 5.5 V
All switches closed, VL = 2.7 V
IL
Inactive
6.3
8.0
Inactive, SCLK = 1 MHz
SCLK = 50 MHz
Inactive, SDI = 1 MHz
SDI = 25 MHz
Active at 50 MHz
14
7
390
210
15
7.5
230
120
1.8
2.1
0.7
1.0
ISS
0.001
VDD/VSS
1
1.0
±4.5/±16.5
μA typ
μA max
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
mA typ
mA max
mA typ
mA max
μA typ
μA max
V min/
V max
Guaranteed by design; not subject to production test.
Rev. B | Page 6 of 27
Digital inputs = 0 V or VL
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Digital inputs toggle between 0 V and VL, VL = 5.5 V
Digital inputs toggle between 0 V and VL, VL = 2.7 V
Digital inputs = 0 V or VL
GND = 0 V
Data Sheet
ADGS1412
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, and GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
+25°C
−40°C to
+85°C
0 V to VDD
2.8
3.5
0.13
0.21
0.6
1.1
±0.02
±0.55
±0.02
±0.55
±0.15
±1.5
4.3
4.8
0.23
0.25
1.2
1.3
±2
±12.5
±2
±12.5
±4
±30
DIGITAL OUTPUT
Output Voltage
Low, VOL
High Impedance Leakage Current
−40°C to
+125°C
0.4
0.2
0.001
±0.1
High Impedance Output Capacitance
DIGITAL INPUTS
Input Voltage
High, VINH
4
2
1.35
0.8
0.8
Low, VINL
Input Current, IINL or IINH
0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS1
tON
4
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VS = 0 V to 10 V, IS = −10 mA, see Figure 29
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 37
RL = 300 Ω, CL = 35 pF
VS = 8 V, see Figure 37
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V, see Figure 36
VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 38
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 30
RL = 110 Ω, 6 V p-p, f = 20 Hz to20 kHz,
see Figure 33
RL = 50 Ω, CL = 5 pF, see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 34
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
Charge Injection, QINJ
Off Isolation
Channel to Channel Crosstalk
Total Harmonic Distortion + Noise
10
−76
−100
0.06
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD (On), CS (On)
130
−0.3
29
30
116
MHz typ
dB typ
pF typ
pF typ
pF typ
240
265
225
Rev. B | Page 7 of 27
VS = VD = 1 V/10 V, see Figure 28
V min
V min
V max
V max
μA typ
μA max
pF typ
Break-Before-Make Time Delay, tD
tOFF
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
300
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V, see Figure 32
V max
V max
μA typ
μA max
pF typ
470
570
170
215
280
615
VS = 0 V to 10 V, IS = −10 mA
ADGS1412
Parameter
POWER REQUIREMENTS
IDD
Data Sheet
+25°C
−40°C to
+85°C
−40°C to
+125°C
0.001
1.0
220
380
250
430
Unit
µA typ
µA max
µA typ
µA max
µA typ
µA max
Test Conditions/Comments
VDD = 13.2 V
All switches open
All switches closed, VL = 5.5 V
All switches closed, VL = 2.7 V
IL
Inactive
6.3
8.0
Inactive, SCLK = 1 MHz
SCLK = 50 MHz
Inactive, SDI = 1 MHz
SDI = 25 MHz
Active at 50 MHz
14
7
390
210
15
7.5
230
120
1.8
2.1
0.7
VDD
1
1.0
5/20
Guaranteed by design; not subject to production test.
Rev. B | Page 8 of 27
µA typ
µA max
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
µA typ
mA typ
mA max
mA typ
mA max
V min/
V max
Digital inputs = 0 V or VL
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Digital inputs toggle between 0 V and VL,
VL = 5.5 V
Digital inputs toggle between 0 V and VL,
VL = 2.7 V
GND = 0 V, VSS = 0 V
Data Sheet
ADGS1412
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 4. Four Channels On
Parameter
CONTINUOUS CURRENT, Sx OR Dx 1
VDD = 15 V, VSS = −15 V (θJA = 54°C/W)
VDD = 12 V, VSS = 0 V (θJA = 54°C/W)
VDD = 5 V, VSS = −5 V (θJA = 54°C/W)
1
25°C
85°C
125°C
Unit
297
240
224
165
142
135
79
74
72
mA maximum
mA maximum
mA maximum
25°C
85°C
125°C
Unit
531
433
404
235
210
202
87
85
84
mA maximum
mA maximum
mA maximum
Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
Table 5. One Channel On
Parameter
CONTINUOUS CURRENT, Sx OR Dx 1
VDD = 15 V, VSS = −15 V (θJA = 54°C/W)
VDD = 12 V, VSS = 0 V (θJA = 54°C/W)
VDD = 5 V, VSS = −5 V (θJA = 54°C/W)
1
Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V, GND = 0 V, and all specifications TMIN to TMAX, unless otherwise noted. Guaranteed by design and characterization,
not production tested.
Table 6.
Parameter
TIMING CHARACTRISTICS
t1
t2
t3
t4
t5
t6
t7
t8
t9 1
t10
t11
t12
t13
1
Limit
Unit
Test Conditions/Comments
20
8
8
10
6
8
10
20
20
20
20
8
8
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
SCLK period
SCLK high pulse width
SCLK low pulse width
CS falling edge to SCLK active edge
Data setup time
Data hold time
SCLK active edge to CS rising edge
CS falling edge to SDO data available
SCLK falling edge to SDO data available
CS rising edge to SDO returns to high impedance
CS high time between SPI commands
CS falling edge to SCLK becomes stable
CS rising edge to SCLK becomes stable
Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t9 determines the maximum SCLK frequency when SDO is used.
Rev. B | Page 9 of 27
ADGS1412
Data Sheet
Timing Diagrams
t1
SCLK
t4
t2
t3
t7
CS
t5
A6
R/W
SDI
t6
A5
D2
D1
D0
t10
t9
0
0
1
D2
D1
D0
14960-002
SDO
t8
Figure 2. Address Mode Timing Diagram
t1
SCLK
t2
t3
t4
t7
CS
SDI
D7
t6
D6
D0
INPUT BYTE FOR DEVICE N
D7
D6
D1
D0
INPUT BYTE FOR DEVICE N + 1
t9
0
t8
0
0
ZERO BYTE
D7
D6
D1
INPUT BYTE FOR DEVICE N
Figure 3. Daisy-Chain Timing Diagram
t11
CS
SCLK
t13
t12
14960-004
SDO
Figure 4. SCLK/CS Timing Relationship
Rev. B | Page 10 of 27
t10
D0
14960-003
t5
Data Sheet
ADGS1412
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter
VDD to VSS
VDD to GND
VSS to GND
VL to GND
Analog Inputs1
Digital Inputs1
Peak Current, Sx or Dx Pins2
Continuous Current, Sx or Dx2, 3
Temperature Range
Operating
Storage
Junction Temperature
Reflow Soldering Peak
Temperature, Pb Free
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
−0.3 V to +6 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
−0.3 V to +6 V
600 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data + 15%
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 8. Thermal Resistance
−40°C to +125°C
−65°C to +150°C
150°C
260(+0/−5)°C
Package Type
CP-24-172
1
2
Overvoltages at the digital Sx and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2
Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
3
See Table 4 and Table 5.
θJA
54
θJCB1
3
Unit
°C/W
θJCB is the junction to the bottom of the case value.
Thermal impedance simulated values are based on JEDEC 2S2P thermal test
board with four thermal vias. See JEDEC JESD-51.
1
ESD CAUTION
Rev. B | Page 11 of 27
ADGS1412
Data Sheet
20 SDO
19 NIC
22 SCLK
21 CS
24 NIC
23 SDI
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D1 1
18 D2
S1 2
17 S2
VSS 3
ADGS1412
16 NIC
GND 4
TOP VIEW
(Not to Scale)
15 VDD
S4 5
14 S3
D4 6
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
14960-005
NIC 12
GND 11
NIC 10
RESET/VL 9
NIC 8
NIC 7
13 D3
Figure 5. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
1
2
3
4, 11
5
6
7, 8, 10, 12,
16, 19, 24
9
Mnemonic
D1
S1
VSS
GND
S4
D4
NIC
Description
Drain Terminal 1. This pin can be an input or output.
Source Terminal 1. This pin can be an input or output.
Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
Ground (0 V) Reference.
Source Terminal 4. This pin can be an input or output.
Drain Terminal 4. This pin can be an input or output.
Not Internally Connected.
RESET/VL
13
14
15
17
18
20
D3
S3
VDD
S2
D2
SDO
21
22
23
CS
SCLK
SDI
EPAD
RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply.
Pull the RESET pin low to complete a hardware reset. After a reset, all switches open, and the appropriate registers
are set to their default.
Drain Terminal 3. This pin can be an input or output.
Source Terminal 3. This pin can be an input or output.
Most Positive Power Supply Potential.
Source Terminal 2. This pin can be an input or output.
Drain Terminal 2. This pin can be an input or output.
Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK. Pull this open-drain output to VL with an external resistor.
Active Low Control Input. CS is the frame synchronization signal for the input data.
Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.
Serial Data Input. Data is captured on the positive edge of SCLK.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.
Rev. B | Page 12 of 27
Data Sheet
ADGS1412
TYPICAL PERFORMANCE CHARACTERISTICS
2.5
3.0
VDD = +10V,
VSS = –10V
2.5
VDD = +12V,
VSS = –12V
1.5
VDD = +13.5V,
VSS = –13.5V
1.0
VDD = +16.5V,
VSS = –16.5V
VDD = +15V,
VSS = –15V
0.5
TA = +125°C
2.0
TA = +85°C
1.5
TA = +25°C
TA = –40°C
1.0
0.5
VDD = +15V
VSS = –15V
IS = –10mA
TA = 25°C
IS = –10mA
–12.5
–8.5
–4.5
–0.5
3.5
7.5
11.5
15.5
VS OR VD (V)
–10
–5
0
5
10
15
VS OR VD (V)
Figure 6. On Resistance vs. VS or VD for Various Dual Supplies
Figure 9. On Resistance vs. VS or VD for Various Temperatures,
±15 V Dual Supply
4.0
5.0
VDD = +4.5V,
VSS = –4.5V
3.5
4.5
VDD = +5V,
VSS = –5V
4.0
ON RESISTANCE (Ω)
3.0
ON RESISTANCE (Ω)
0
–15
14960-006
0
–16.5
2.5
2.0
VDD = +7V,
VSS = –7V
VDD = +5.5V,
VSS = –5.5V
1.5
14960-009
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
2.0
3.5
TA = +85°C
3.0
TA = +25°C
2.5
2.0
TA = –40°C
1.5
1.0
1.0
0.5
TA = 25°C
IS = –10mA
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
VS OR VD (V)
0
–5
14960-007
0
–7
VDD = +5V
VSS = –5V
IS = –10mA
–4
–3
–2
–1
0
1
2
3
4
5
VS OR VD (V)
Figure 7. On Resistance vs. VS or VD for Various Dual Supplies
14960-010
0.5
Figure 10. On Resistance vs. VS or VD for Various Temperatures,
±5 V Dual Supply
7
4.5
VDD = 5V,
VSS = 0V
6
4.0
ON RESISTANCE (Ω)
VDD = 12V,
VSS = 0V
3
2
VDD = 13.2V,
VSS = 0V
1
TA = 25°C
IS = –10mA
0
2
4
6
8
10
12
14
VS OR VD (V)
TA = +85°C
2.5
TA = +25°C
2.0
TA = –40°C
1.5
1.0
VDD = 15V,
VSS = 0V
0
3.0
VDD = 12V
VSS = 0V
IS = –10mA
0.5
Figure 8. On Resistance vs. VS or VD for Various Single Supplies
0
0
2
4
6
8
10
12
VS OR VD (V)
Figure 11. On Resistance vs. VS or VD for Various Temperatures,
12 V Single Supply
Rev. B | Page 13 of 27
14960-011
VDD = 10.8V,
VSS = 0V
VDD = 8V,
VSS = 0V
4
14960-008
ON RESISTANCE (Ω)
3.5
5
ADGS1412
Data Sheet
5.0
9
4.5
8
TA = 125°C
IS = 100mA
3.5
3.0
2.5
TA = 25°C
IS = 190mA
2.0
1.5
6
5
4
3
2
1
1.0
0
–4
–1
–3
–2
–1
0
1
2
3
4
5
0
VS OR VD (V)
40
60
80
100
120
TEMPERATURE (°C)
Figure 15. Leakage Current vs. Temperature, 12 V Single Supply
Figure 12. On Resistance vs. VS or VD for Various Current Levels and
Temperatures, ±5 V Dual Supply
400
1.5
TA = 25°C
ID, IS (ON) + +
1.0
ID (OFF) – +
0.5
VDD = +15V, VSS = –15V
300
IS (OFF) + –
200
CHARGE INJECTION (pC)
0
–0.5
–1.0
ID, IS (ON) – –
–1.5
ID (OFF) + –
–2.0
–2.5
100
VDD = +5V, VSS = –5V
0
–100
VDD = +12V, VSS = 0V
–200
–300
IS (OFF) – +
60
80
100
120
TEMPERATURE (°C)
–500
–15
0
5
10
15
Figure 16. Charge Injection vs. Source Voltage (VS)
700
VDD = +5V
VSS = –5V
VBIAS = +4.5V/–4.5V
1.0
–5
VS (V)
Figure 13. Leakage Current vs. Temperature, ±15 V Dual Supply
1.5
–10
14960-016
–400
14960-013
VDD = +15V
–3.0 VSS = –15V
VBIAS = +10V/–10V
–3.5
0
20
40
600
15V DS, tON
15V DS, tOFF
5V DS, tON
5V DS, tOFF
12V SS, tON
12V SS, tOFF
500
tTRANSITION (ns)
0.5
400
0
300
–0.5
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) ++
ID, IS (ON) – –
–1.5
0
20
40
100
60
80
100
120
TEMPERATURE (°C)
14960-014
–1.0
200
Figure 14. Leakage Current vs. Temperature, ±5 V Dual Supply
0
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
100
120
14960-017
LEAKAGE CURRENT (nA)
20
14960-015
0
–5
VDD = +5V
VSS = –5V
14960-012
0.5
LEAKAGE CURRENT (nA)
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) ++
ID, IS (ON) – –
7
LEAKAGE CURRENT (nA)
ON RESISTANCE (Ω)
4.0
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
Figure 17. tON/tOFF Time vs. Temperature for Single Supply (SS) and
Dual Supply (DS)
Rev. B | Page 14 of 27
Data Sheet
ADGS1412
0
VDD = +15V
VSS = –15V
TA = 25°C
–20
–40
–40
AC PSRR (dB)
–60
–80
100nF DECOUPLING
CAPACITORS
–60
–80
–100
–100
–120
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
–120
100
14960-018
–140
100
10µF + 100nF DECOUPLING
CAPACITORS
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
14960-021
OFF ISOLATION (dB)
–20
0
VDD = +15V
VSS = –15V
TA = 25°C
Figure 21. AC Power Supply Rejection Ratio (AC PSRR) vs. Frequency, ±15 V
Dual Supply
Figure 18. Off Isolation vs. Frequency, ±15 V Dual Supply
0
TA = 25°C
0.025
RL = 110Ω, VS = 20V p-p
0.020
THD + N (%)
CROSSTALK (dB)
–40
–60
–80
0.015
RL = 110Ω, VS = 15V p-p
0.010
RL = 110Ω, VS = 10V p-p
–100
RL = 1kΩ, VS = 20V p-p
0.005
–120
RL = 1kΩ, VS = 15V p-p
100k
1M
10M
100M
1G
FREQUENCY (Hz)
0
20
14960-019
–140
10k
RL = 1kΩ, VS = 10V p-p
200
2k
20k
FREQUENCY (Hz)
14960-022
–20
VDD = +15V
VSS = –15V
TA = 25°C
Figure 22. THD + N vs. Frequency, ±15 V Dual Supply
Figure 19. Crosstalk vs. Frequency, ±15 V Dual Supply
0
VDD = +15V
VSS = –15V
TA = 25°C
RL = 110Ω, VS = 10V p-p
0.15
–3
0.10
–4
0.05
–5
–6
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
Figure 20. Insertion Loss vs. Frequency, ±15 V Dual Supply
0
20
RL = 110Ω, VS = 5V p-p
RL = 1kΩ, VS = 10V p-p
RL = 110Ω, VS = 2.5V p-p
RL = 1kΩ, VS = 5V p-p
RL = 1kΩ, VS = 2.5V p-p
200
2k
FREQUENCY (Hz)
Figure 23. THD + N vs. Frequency, ±5 V Dual Supply
Rev. B | Page 15 of 27
20k
14960-023
THD + N (%)
–2
14960-020
INSERTION LOSS (dB)
–1
0.20 TA = 25°C
ADGS1412
Data Sheet
0.14
80
TA = 25°C
70
0.12
RL = 110Ω, VS = 9V p-p
VDD = +15V
VSS = –15V
60
0.10
50
0.08
IDD (µA)
THD + N (%)
TA = 25°C
IDD PER CLOSED SWITCH
RL = 110Ω, VS = 6V p-p
0.06
0.04
RL = 110Ω, VS = 3V p-p
RL = 1kΩ, VS = 9V p-p
0.02
RL = 1kΩ, VS = 6V p-p
40
VDD = +12V
VSS = 0V
30
20
10
200
2k
14960-124
0
20
20k
FREQUENCY (Hz)
0
2.7
3.0
3.5
VDD = +15V
VSS = –15V
TA = 25°C
1.5
5.0
5.5
Figure 26. IDD vs. VL
450
SCLK = 2.5MHz
SCLK IDLE
TA = 25°C
400
350
1.0
300
IL (uA)
0.5
0
250
200
–0.5
150
–1.0
100
50
–2.0
0
2
4
6
TIME (µs)
8
0
VL = 5V
VL = 3V
1
10
20
30
40
SCLK FREQUENCY (MHz)
Figure 27. IL vs. SCLK Frequency when CS High
Figure 25. Digital Feedthrough
Rev. B | Page 16 of 27
50
14960-226
–1.5
14960-125
VOUT (mV)
4.5
VL (V)
Figure 24 . THD + N vs. Frequency, 12 V Single Supply
2.0
4.0
14960-126
VDD = +5V
VSS = –5V
RL = 1kΩ, VS = 3V p-p
Data Sheet
ADGS1412
TEST CIRCUITS
ID (ON)
Dx
A
VS
VD
ID (OFF)
Dx
A
VS
14960-024
Sx
Sx
A
14960-028
IS (OFF)
VD
Figure 28. On Leakage
Figure 32. Off Leakage
VDD
VSS
0.1µF
0.1µF
AUDIO PRECISION
VDD
VSS
RS
IDS
Sx
VS
V p-p
V1
Dx
Dx
Figure 33. THD + Noise
Figure 29. On Resistance
VDD
VOUT
0.1µF
VDD
VSS
S1
RL
50Ω
VDD
VSS
0.1µF
NETWORK
ANALYZER
D1
VSS
0.1µF
0.1µF
VDD
NC
NETWORK
ANALYZER
VSS
50Ω
Sx
S2
VS
D2
VS
RL
50Ω
Dx
GND
V
RL OUT
50Ω
14960-026
GND
VOUT
VS
CHANNEL TO CHANNEL CROSSTALK = 20 log
14960-029
RON = V1/IDS
VOUT
RL
110Ω
GND
14960-025
VS
INSERTION LOSS = 20 log
Figure 30. Channel to Channel Crosstalk
VOUT WITH SWITCH
VS WITHOUT SWITCH
14960-030
Sx
Figure 34. −3 dB Bandwidth
VSS
VDD
NETWORK
ANALYZER
VSS
0.1µF
0.1µF
VDD
RL
50Ω
NETWORK
ANALYZER
VSS
INTERNAL
BIAS
VDD
VSS
VS
50Ω
50Ω
VOUT
VS
Dx
V
RL OUT
50Ω
OFF ISOLATION = 20 log
VOUT
VS
AC PSRR = 20 log
14960-027
GND
S1
RL
50Ω
GND
D1
VOUT
VS
NOTES
1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED
FROM THE AC PSRR MEASUREMENT.
Figure 31. Off Isolation
Figure 35. AC PSRR
Rev. B | Page 17 of 27
NC
14960-235
Sx
ADGS1412
Data Sheet
V SS
VDD
0.1µF
0.1µF
50%
SCLK
50%
0V
V SS
VS1
S1
D1
VS2
S2
D2
INPUT LOGIC
80%
VOUT1
R L2
300Ω
C L2
35pF
RL1
300Ω
VOUT2
CL1
35pF
VOUT1
80%
0V
80%
80%
VOUT2
0V
GND
14960-236
V DD
tD
tD
Figure 36. Break-Before-Make Time Delay, tD
VDD
VSS
0.1µF
0.1µF
VSS
Sx
VOUT
Dx
RL
300Ω
VS
INPUT LOGIC
CL
35pF
SCLK
50%
50%
90%
VOUT
GND
10%
tON
tOFF
14960-031
VDD
Figure 37. Switching Times, tON and tOFF
3V
SCLK
RS
VDD
VSS
VDD
VSS
Sx
Dx
QINJ = CL × ΔVOUT
INPUT LOGIC
ΔVOUT
SWITCH OFF
SWITCH ON
Figure 38. Charge Injection, QINJ
Rev. B | Page 18 of 27
GND
14960-032
VOUT
VOUT
CL
1nF
VS
Data Sheet
ADGS1412
TERMINOLOGY
IDD
IDD represents the positive supply current.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
ISS
ISS represents the negative supply current.
CIN
CIN is the digital input capacitance.
VD, VS
VD and VS represent the analog voltage on Terminal Dx and
Terminal Sx, respectively.
RON
RON represents the ohmic resistance between Terminal Dx and
Terminal Sx.
ΔRON
ΔRON represents the difference between the RON of any two
channels.
RFLAT (ON)
Flatness that is defined as the difference between the maximum
and minimum value of on resistance measured over the specified
analog signal range is represented by RFLAT (ON).
tON
tON represents the delay between applying the digital control
input and the output switching on.
tOFF
tOFF represents the delay between applying the digital control
input and the output switching off.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
VINL
VINL is the maximum input voltage for Logic 0.
On Response
On response is the frequency response of the on switch.
VINH
VINH is the minimum input voltage for Logic 1.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental is represented by THD + N.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the ratio of the amplitude of signal on the output to the
amplitude of the modulation. AC PSRR is a measure of the ability
of the device to avoid coupling noise and spurious signals that
appear on the supply voltage pin to the output of the switch. The dc
voltage on the device is modulated by a sine wave of 0.62 V p-p.
IS (Off)
IS (Off) is the source leakage current with the switch off.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
Rev. B | Page 19 of 27
ADGS1412
Data Sheet
THEORY OF OPERATION
The ADGS1412 is a set of serially controlled, quad SPST switches
with error detection features. SPI Mode 0 and Mode 3 can be
used with the device, and it operates with SCLK frequencies up
to 50 MHz. The default mode for the ADGS1412 is address mode
in which the registers of the device are accessed by a 16-bit SPI
command that is bounded by CS. The SPI command becomes
24 bit if the user enables CRC error detection. Other error detection
features include SCLK count error and invalid read/write error.
If any of these SPI interface errors occur, they are detectable by
reading the error flags register. The ADGS1412 can also operate
in two other modes, namely burst mode and daisy-chain mode.
During any SPI command, SDO sends out eight alignment bits
on the first eight SCLK falling edges. The alignment bits observed
at SDO are 0x25.
The interface pins of the ADGS1412 are CS, SCLK, SDI, and SDO.
Hold CS low when using the SPI interface. Data is captured on
the SDI on the rising edge of SCLK, and data is propagated out on
the SDO on the falling edge of SCLK. SDO has an open-drain
output; thus, connect a pull-up to this output. When not pulled
low by the ADGS1412, SDO is in a high impedance state.
Cyclic Redundancy Check (CRC) Error Detection
ERROR DETECTION FEATURES
Protocol and communication errors on the SPI interface are
detectable. There are three detectable errors, which are incorrect
SCLK count error detection, invalid read/write address error
detection, and CRC error detection. Each of these errors has a
corresponding enable bit in the error configuration register. In
addition, there is an error flag bit for each of these errors in the
error flags register.
The CRC error detection feature extends a valid SPI frame by
8 SCLK cycles. These eight extra cycles are needed to send the CRC
byte for that SPI frame. The CRC byte is calculated by the SPI block
using the 16-bit payload: the R/W bit, Register Address Bits[6:0],
and Register Data Bits[7:0]. The CRC polynomial used in the
SPI block is x8 + x2 + x1 + 1 with a seed value of 0. For a timing
diagram with CRC enabled, see Figure 40. Register writes occur
at the 24th SCLK rising edge with CRC error checking enabled.
ADDRESS MODE
Address mode is the default mode for the ADGS1412 upon
power up. A single SPI frame in address mode is bounded by
a CS falling edge and the succeeding CS rising edge. It is comprised
of 16 SCLK cycles. The timing diagram for address mode is shown
in Figure 39. The first SDI bit indicates if the SPI command is a
read or write command. When the first bit is set to 0, a write
command is issued, and if the first bit is set to 1, a read command
is issued. The next seven bits determine the target register address.
The remaining eight bits provide the data to the addressed register.
The last eight bits are ignored during a read command, because
during these clock cycles, SDO propagates out the data contained
in the addressed register.
During an SPI write, the microcontroller/central processing
unit (CPU) provides the CRC byte through SDI. The SPI block
checks the CRC byte just before the 24th SCLK rising edge. On
this same edge, the register write is prevented if an incorrect CRC
byte is received by the SPI interface. The CRC error flag is
asserted in the error flags register in the case of the incorrect
CRC byte being detected.
During an SPI read, the CRC byte is provided to the microcontroller through SDO.
The CRC error detection feature is disabled by default and can
be configured by the user through the error configuration register.
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates out
on SDO from the 9th to the 16th SCLK falling edge during SPI
reads. A register write occurs on the 16th SCLK rising edge
during SPI writes.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
CS
SDI
SDO
0
0
1
0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
14960-033
SCLK
Figure 39. Address Mode Timing Diagram
1
2
8
9
10
16
17
18
19
20
21
22
23
24
R/W
A6
A0
D7
D6
D0
C7
C6
C5
C4
C3
C2
C1
C0
CS
SDI
SDO
0
0
1
D7
D6
D0
C7
C6
C5
Figure 40. Timing Diagram with CRC Enabled
Rev. B | Page 20 of 27
C4
C3
C2
C1
C0
14960-034
SCLK
Data Sheet
ADGS1412
SCLK Count Error Detection
BURST MODE
SCLK count error detection allows the user to detect if an
incorrect number of SCLK cycles are sent by the microcontroller/
CPU. When in address mode, with CRC disabled, 16 SCLK
cycles are expected. If 16 SCLK cycles are not detected, the
SCLK count error flag asserts in the error flags register. When
less than 16 SCLK cycles are received by the device, a write to
the register map never occurs. When the ADGS1412 receives
more than 16 SCLK cycles, a write to the memory map still
occurs at the 16th SCLK rising edge, and the flag asserts in the
error flags register. With CRC enabled, the expected number of
SCLK cycles becomes 24. SCLK count error detection is enabled
by default and can be configured by the user through the error
configuration register.
The SPI interface can accept consecutive SPI commands
without the need to deassert the CS line, which is called burst
mode. Burst mode is enabled through the burst enable register.
This mode uses the same 16-bit command to communicate
with the device. In addition, the response of the device at SDO
is still aligned with the corresponding SPI command. Figure 41
shows an example of SDI and SDO during burst mode.
The invalid read/write address and CRC error checking functions
operate similarly during burst mode as they do during address
mode. However, SCLK count error detection operates in a
slightly different manner. The total number of SCLK cycles
within a given CS frame are counted, and if the total is not a
multiple of 16, or a multiple of 24 when CRC is enabled, the
SCLK count error flag asserts.
Invalid Read/Write Address Error
An invalid read/write address error detects when a nonexistent
register address is a target for a read or write. In addition, this
error asserts when a write to a read only register is attempted.
The invalid read/write address error flag asserts in the error
flags register when an invalid read/write address error happens.
The invalid read/write address error is detected on the ninth
SCLK rising edge, which means a write to the register never
occurs when an invalid address is targeted. Invalid read/write
address error detection is enabled by default and can be
disabled by the user through the error configuration register.
SDI
COMMAND0[15:0]
COMMAND1[15:0]
COMMAND2[15:0]
COMMAND3[15:0]
SDO
RESPONSE0[15:0]
RESPONSE1[15:0]
RESPONSE2[15:0]
RESPONSE3[15:0]
Figure 41. Burst Mode Frame
SOFTWARE RESET
When in address mode, the user can initiate a software reset.
To do so, write two consecutive SPI commands, 0xA3 followed
by 0x05, targeting Register 0x0B. After a software reset, all
register values are set to default.
CLEARING THE ERROR FLAGS REGISTER
DAISY-CHAIN MODE
To clear the error flags register, write the special 16-bit SPI
frame, 0x6CA9, to the device. This SPI command does not
trigger the invalid R/W address error. When CRC is enabled,
the user must also send the correct CRC byte for a successful
error clear command. At the 16th or 24th SCLK rising edge, the
error flags register resets to zero.
The connection of several ADGS1412 devices in a daisy-chain
configuration is possible, and Figure 42 illustrates this setup. All
devices share the same CS and SCLK line, whereas the SDO of a
device forms a connection to the SDI of the next device, creating a
shift register. In daisy-chain mode, SDO is an 8 cycle delayed
version of SDI. When in daisy-chain mode, all commands target
the switch data register. Therefore, it is not possible to make
configuration changes while in daisy-chain mode.
ADGS1412
ADGS1412
DEVICE 1
DEVICE 2
S1
D1
S1
D1
S2
D2
S2
D2
S3
D3
S3
D3
S4
D4
S4
D4
SPI
INTERFACE
14960-035
CS
VL
SDO
SPI
INTERFACE
14960-036
SDI
SCLK
CS
SDO
VL
Figure 42. Two ADGS1412 Devices Connected in a Daisy-Chain Configuration
Rev. B | Page 21 of 27
ADGS1412
Data Sheet
An SCLK rising edge reads in data on SDI while data is
propagated out SDO on an SCLK falling edge. The expected
number of SCLK cycles must be a multiple of eight before CS
goes high. When this is not the case, the SPI interface sends the
last eight bits received to the switch data register.
The ADGS1412 can only enter daisy-chain mode when in
address mode by sending the 16-bit SPI command, 0x2500
(see Figure 43). When the ADGS1412 receives this command,
the SDO of the device sends out the same command because
the alignment bits at SDO are 0x25, which allows multiple
daisy-connected devices to enter daisy-chain mode in a single
SPI frame. A hardware reset is required to exit daisy-chain mode.
POWER-ON RESET
The digital section of the ADGS1412 goes through an initialization
phase during VL power up. This initialization also occurs after a
hardware or software reset. After VL power-up or a reset, ensure
that a minimum of 120 μs from the time of power-up or reset
before any SPI command is issued. Ensure that VL does not
drop out during the 120 μs initialization phase because it may
result in incorrect operation of the ADGS1412.
For the timing diagram of a typical daisy-chain SPI frame, see
Figure 44. When CS goes high, Device 1 writes Command 0,
Bits[7:0] to its switch data register, Device 2 writes Command 1,
Bits[7:0] to its switches, and so on. The SPI block uses the last
eight bits it received through SDI to update the switches. After
entering daisy-chain mode, the first eight bits sent out by SDO
on each device in the chain are 0x00. When CS goes high, the
internal shift register value does not reset back to zero.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
CS
SDI
SDO
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
14960-037
SCLK
0
Figure 43. SPI Command to Enter Daisy-Chain Mode
SDI
COMMAND3[7:0]
COMMAND2[7:0]
COMMAND1[7:0]
COMMAND0[7:0]
DEVICE 1
SDO
8’h00
COMMAND3[7:0]
COMMAND2[7:0]
COMMAND1[7:0]
DEVICE 2
SDO2
8’h00
8’h00
COMMAND3[7:0]
COMMAND2[7:0]
DEVICE 3
SDO3
8’h00
8’h00
8’h00
COMMAND3[7:0]
DEVICE 4
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 44. Example of an SPI Frame Where Four ADGS1412 Devices Connect in Daisy-Chain Mode
Rev. B | Page 22 of 27
14960-038
CS
Data Sheet
ADGS1412
APPLICATIONS INFORMATION
BREAK-BEFORE-MAKE SWITCHING
POWER SUPPLY RECOMMENDATIONS
The ADGS1412 exhibits break-before-make switching action.
This feature allows the use of the device in multiplexer
applications. Using the device like a multiplexer can be
accomplished by externally hardwiring the device into the
desired mux configuration, as shown in Figure 45.
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
4 × SPST
S1
S2
An example of a bipolar power solution is shown in Figure 46.
The ADP5070 (dual switching regulator) generates a positive and
negative supply rail for the ADGS1412, an amplifier, and/or a
precision converter in a typical signal chain. Also shown in
Figure 46 are two optional low dropout regulators (LDOs), the
ADP7118 and ADP7182 positive and negative LDOs respectively,
that can be used to reduce the output ripple of the ADP5070 in
ultralow noise sensitive applications.
ADM7160
+3.3V
ADP7118
+15V
ADP7182
–15V
LDO
S4
SPI
INTERFACE
14960-045
SCLK SDI CS RESET/VL
+16.5V
+5V
INPUT
ADP5070
LDO
–16.5V
LDO
Figure 45. An SPI Controlled Switch Configured into a 4:1 Mux
14960-042
The ADM7160 can be used to generate VL voltage that is
required to power digital circuitry within the ADGS1412.
Dx
S3
.
Figure 46. Bipolar Power Solution
DIGITAL INPUT BUFFERS
There are input buffers present on the digital input pins (CS,
SCLK, and SDI). These buffers are active at all times. Therefore,
there is current draw from the VL supply if SCLK or SDI is toggling,
regardless of whether CS is active. For typical values of this
current draw, refer to the Specifications section and Figure 27.
POWER SUPPLY RAILS
Table 10. Recommended Power Management Devices
Product
ADP5070
ADM7160
ADP7118
ADP7182
To guarantee correct operation of the ADGS1412, 0.1 μF
decoupling capacitors are required.
The ADGS1412 can operate with bipolar supplies between
±4.5 V and ±16.5 V. The supplies on VDD and VSS do not have to
be symmetrical; however, the VDD to VSS range must not exceed
33 V. The ADGS1412 can also operate with single supplies
between 5 V and 20 V with VSS connected to GND.
The voltage range that can be supplied to VL is from 2.7 V to 5.5 V.
The device is fully specified at ±15 V, ±5 V, and +12 V analog
supply voltage ranges.
Rev. B | Page 23 of 27
Description
1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
5.5 V, 200 mA, ultralow noise, linear regulator
20 V, 200 mA, low noise, CMOS LDO linear regulator
−28 V, −200 mA, low noise, LDO linear regulator
ADGS1412
Data Sheet
REGISTER SUMMARY
Table 11. Register Summary
Register (Hex)
0x01
0x02
0x03
0x05
0x0B
Name
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
SW_DATA
Reserved
SW4_EN SW3_EN
SW2_EN
ERR_CONFIG
Reserved
RW_ERR_EN
SCLK_ERR_EN
ERR_FLAGS
Reserved
RW_ERR_FLAG SCLK_ERR_FLAG
BURST_EN
Reserved
SOFT_RESETB
SOFT_RESETB
Rev. B | Page 24 of 27
Bit 0
SW1_EN
CRC_ERR_EN
CRC_ERR_FLAG
BURST_MODE_EN
Default
0x00
0x06
0x00
0x00
0x00
R/W
R/W
R/W
R
R/W
R/W
Data Sheet
ADGS1412
REGISTER DETAILS
SWITCH DATA REGISTER
Address: 0x01, Reset: 0x00, Name: SW_DATA
The switch data register controls the status of the four switches of the ADGS1412.
Table 12. Bit Descriptions for SW_DATA
Bits
[7:4]
3
Bit Name
Reserved
SW4_EN
Settings
0
1
2
SW3_EN
0
1
1
SW2_EN
0
1
0
SW1_EN
0
1
Description
These bits are reserved; set these bits to 0.
Enable bit for SW4.
SW4 open.
SW4 closed.
Enable bit for SW3.
SW3 open.
SW3 closed.
Enable bit for SW2.
SW2 open.
SW2 closed.
Enable bit for SW1.
SW1 open.
SW1 closed.
Default
0x0
0x0
Access
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Default
0x0
0x1
Access
R
R/W
0x1
R/W
0x0
R/W
ERROR CONFIGURATION REGISTER
Address: 0x02, Reset: 0x06, Name: ERR_CONFIG
The error configuration register allows the user to enable and disable the relevant error features as required.
Table 13. Bit Descriptions for ERR_CONFIG
Bits
[7:3]
2
Bit Name
Reserved
RW_ERR_EN
Settings
0
1
1
SCLK_ERR_EN
0
1
0
CRC_ERR_EN
0
1
Description
These bits are reserved; set these bits to 0.
Enable bit for detecting invalid read/write address.
Disabled.
Enabled.
Enable bit for detecting the correct number of SCLK cycles in an SPI frame.
16 SCLK cycles are expected when CRC is disabled and burst mode is
disabled. 24 SCLK cycles are expected when CRC is enabled and burst
mode is disabled. A multiple of 16 SCLK cycles are expected when CRC is
disabled and burst mode is enabled. A multiple of 24 SCLK cycles are
expected when CRC is enabled and burst mode is enabled.
Disabled.
Enabled.
Enable bit for CRC error detection. SPI frames are 24 bits wide when
enabled.
Disabled.
Enabled.
Rev. B | Page 25 of 27
ADGS1412
Data Sheet
ERROR FLAGS REGISTER
Address: 0x03, Reset: 0x00, Name: ERR_FLAGS
The error flags register allows the user to determine if an error has occurred. To clear the error flags register, write the special 16-bit SPI
command 0x6CA9 to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user must
include the correct CRC byte during the SPI write for the clear error flags register command to succeed.
Table 14. Bit Descriptions for ERR_FLAGS
Bits
[7:3]
2
Bit Name
Reserved
RW_ERR_FLAG
Settings
0
1
1
SCLK_ERR_FLAG
0
1
0
CRC_ERR_FLAG
0
1
Description
These bits are reserved and are set to 0.
Error flag for invalid read/write address. The error flag asserts during an
SPI read if the target address does not exist. The error flag also asserts
when the target address of an SPI write does not exist or is read only.
No error.
Error.
Error flag for the detection of the correct number of SCLK cycles in an SPI
frame.
No error.
Error.
Error flag that determines if a CRC error has occurred during a register
write.
No error.
Error.
Default
0x0
0x0
Access
R
R
0x0
R
0x0
R
BURST ENABLE REGISTER
Address: 0x05, Reset: 0x00, Name: BURST_EN
The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI
commands without deasserting CS.
Table 15. Bit Descriptions for BURST_EN
Bits
[7:1]
0
Bit Name
Reserved
BURST_MODE_EN
Settings
0
1
Description
These bits are reserved; set these bits to 0.
Burst mode enable bit.
Disabled.
Enabled.
Default
0x0
0x0
Access
R
R/W
SOFTWARE RESET REGISTER
Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB
Use the software reset register to perform a software reset. Consecutively, write 0xA3 followed by 0x05 to this register, and the registers of
the device reset to their default state.
Table 16. Bit Descriptions for SOFT_RESETB
Bits
[7:0]
Bit Name
SOFT_RESETB
Settings
Description
To perform a software reset, consecutively write 0xA3 followed by 0x05 to
this register.
Rev. B | Page 26 of 27
Default
0x0
Access
R
Data Sheet
ADGS1412
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
TOP VIEW
1.00
0.95
0.90
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-004677
0.50
0.40
0.30
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8.
02-09-2017-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 47. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.95 mm Package Height
(CP-24-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADGS1412BCPZ
ADGS1412BCPZ-RL7
EVAL-ADGS1412SDZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14960-0-8/17(B)
Rev. B | Page 27 of 27
Package Option
CP-24-17
CP-24-17
工商网监
湘ICP备2023018690号
