FEATURES
FUNCTIONAL BLOCK DIAGRAM
SPI interface with error detection
Includes CRC, invalid read/write address, and SCLK count
error detection
Supports burst mode and daisy-chain mode
Industry-standard SPI Mode 0 and SPI Mode 3 interface
compatible
Guaranteed break-before-make switching allowing external
wiring of switches to deliver multiplexer configurations
1 Ω typical on resistance at 25°C
0.23 Ω typical on resistance flatness at 25°C
VSS to VDD analog signal range
Fully specified at ±5 V, 12 V, 5 V, and 3.3 V
±3.3 V to ±8 V dual-supply operation
3.3 V to 16 V single-supply operation
1.8 V logic compatibility with 2.7 V ≤ VL ≤ 3.3 V
4 mm × 4 mm, 24-lead LFCSP package
ADGS1612
S1
D1
S2
D2
S3
D3
S4
D4
SPI
INTERFACE
SCLK
SDI
CS
SDO
RESET/VL
16054-001
Data Sheet
SPI Interface, 1 Ω RON, ±5 V, 12 V, 5 V,
3.3 V, Mux Configurable, Quad SPST Switch
ADGS1612
Figure 1.
APPLICATIONS
Communication systems
Medical systems
Audio and video signal routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Relay replacements
GENERAL DESCRIPTION
The ADGS1612 contains four independent single-pole/singlethrow (SPST) switches. A serial peripheral interface (SPI) controls
the switches. The SPI interface has robust error detection features,
including cyclic redundancy check (CRC) error detection,
invalid read/write address detection, and serial clock (SCLK)
count error detection.
It is possible to daisy-chain multiple ADGS1612 devices together.
Daisy-chaining enables the configuration of multiple devices with a
minimal amount of digital lines. The ADGS1612 can also operate
in burst mode to decrease the time between SPI commands.
Each switch conducts equally well in both directions when on, and
each switch has an input signal range that extends to the supplies.
In the off condition, signal levels up to the supplies are blocked.
The ultralow on resistance (RON) of these switches make them
ideal solutions for data acquisition and gain switching
applications where low RON and low distortion are critical. The
RON profile is very flat over the full analog input range, ensuring
excellent linearity and low distortion when switching audio
Rev. 0
signals. The ADGS1612 exhibits break-before-make switching
action for use in multiplexer applications. Note that throughout
this data sheet, the multifunction pin, RESET/VL, is referred to
either by the entire pin name or by a single function of the pin,
for example, VL, when only that function is relevant.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
The SPI interface removes the need for parallel conversion
and logic traces and reduces general-purpose input/output
(GPIO) channel count.
Daisy-chain mode removes additional logic traces when
multiple devices are used.
CRC, invalid read/write address, and SCLK count error
detection ensure a robust digital interface.
CRC error detection capabilities allow the use of the
ADGS1612 in safety critical systems.
Guaranteed break-before-make switching allows the use of
the ADGS1612 in multiplexer configurations with external
wiring.
Minimum distortion.
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©2018 Analog Devices, Inc. All rights reserved.
Technical Support
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ADGS1612
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Address Mode ............................................................................. 22
Applications ....................................................................................... 1
Error Detection Features ........................................................... 22
Functional Block Diagram .............................................................. 1
Clearing the Error Flags Register ............................................. 23
General Description ......................................................................... 1
Burst Mode .................................................................................. 23
Product Highlights ........................................................................... 1
Software Reset ............................................................................. 23
Revision History ............................................................................... 2
Daisy-Chain Mode ..................................................................... 23
Specifications..................................................................................... 3
Power-On Reset .......................................................................... 24
±5 V Dual Supply ......................................................................... 3
Applications Information .............................................................. 25
12 V Single Supply ........................................................................ 5
Break-Before-Make Switching .................................................. 25
5 V Single Supply .......................................................................... 7
Digital Input Buffers .................................................................. 25
3.3 V Single Supply ....................................................................... 9
Power Supply Rails ..................................................................... 25
Continuous Current per Channel, Sx or Dx ........................... 11
Register Summary .......................................................................... 26
Timing Characteristics .............................................................. 11
Register Details ............................................................................... 27
Absolute Maximum Ratings.......................................................... 13
Switch Data Register .................................................................. 27
Thermal Resistance .................................................................... 13
Error Configuration Register.................................................... 27
ESD Caution ................................................................................ 13
Error Flags Register .................................................................... 28
Pin Configuration and Function Descriptions ........................... 14
Burst Enable Register ................................................................. 28
Typical Performance Characteristics ........................................... 15
Software Reset Register ............................................................. 28
Test Circuits ..................................................................................... 19
Outline Dimensions ....................................................................... 29
Terminology .................................................................................... 21
Ordering Guide .......................................................................... 29
Theory of Operation ...................................................................... 22
REVISION HISTORY
1/2018—Revision 0: Initial Version
Rev. 0 | Page 2 of 29
Data Sheet
ADGS1612
SPECIFICATIONS
±5 V DUAL SUPPLY
Positive supply (VDD) = 5 V ± 10%, negative supply (VSS) = −5 V ± 10%, digital supply (VL) = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between
Channels, ∆RON
On Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
25°C
−40°C to +85°C
Unit
VDD to VSS
V
Ω typ
1
1.2
0.04
1.4
1.6
Ω max
Ω typ
0.08
0.23
0.28
0.09
0.1
Ω max
Ω typ
Ω max
±0.1
±0.3
±0.1
±0.3
±0.2
±0.4
0.32
0.37
±1.0
±6.0
±1.0
±6.0
±1.5
±10.0
DIGITAL OUTPUT
Output Voltage
Low, VOL
Output Current, Low (IOL) or High (IOH)
−40°C to +125°C
0.4
0.2
0.001
±0.1
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
4
2
1.35
0.8
0.8
Low, VINL
Input Current, Low (IINL) or High (IINH)
0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
On Time, tON
4
nA typ
nA max
nA typ
nA max
nA typ
nA max
Off Isolation
−65
dB typ
Channel to Channel Crosstalk
−93
dB typ
115
Rev. 0 | Page 3 of 29
VS = VD = ±4.5 V; see Figure 28
RL = 300 Ω, CL = 35 pF
VS = 2.5 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 2.5 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 2.5 V, see Figure 35
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 37
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see
Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 30
120
360
VS = ±4.5 V, VD = ∓4.5 V; see Figure 32
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
Charge Injection, QINJ
335
VDD = +5.5 V, VSS = −5.5 V
VS = ±4.5 V, VD = ∓4.5 V; see Figure 32
V min
V min
V max
V max
μA typ
μA max
pF typ
Break-Before-Make Time Delay, tD
Off Time, tOFF
VS = ±4.5 V, IS = −10 mA
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
485
VS = ±4.5 V, IS = −10 mA;
see Figure 29
VDD = +4.5 V, VSS = −4.5 V
VS = ±4.5 V, IS = −10 mA
V max
V max
μA typ
μA max
pF typ
385
480
250
305
175
485
Test Conditions/Comments
ADGS1612
Data Sheet
Parameter
Total Harmonic Distortion Plus Noise,
THD + N
−3 dB Bandwidth
Insertion Loss
25°C
0.007
−40°C to +85°C
−40°C to +125°C
34
−0.08
MHz typ
dB typ
Off Switch Source Capacitance,
CS (Off )
Off Switch Drain Capacitance, CD (Off )
On Switch Capacitance, CD (On), CS (On)
POWER REQUIREMENTS
Positive Supply Current, IDD
63
pF typ
63
154
pF typ
pF typ
0.01
1
0.01
1
130
220
Digital Supply Current, IL
Inactive
6.3
8.0
Inactive, SCLK = 1 MHz
SCLK = 50 MHz
Inactive, SDI = 1 MHz
SDI = 25 MHz
Active at 50 MHz
14
7
390
210
15
7.5
230
120
1.8
2.1
0.7
1.0
Negative Supply Current, ISS
VDD/VSS
0.01
1
±3.3
±8
Rev. 0 | Page 4 of 29
Unit
% typ
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
μA typ
mA typ
mA max
mA typ
mA max
μA typ
μA max
V min
V max
Test Conditions/Comments
RL = 110 Ω, 5 V p-p, f = 20 Hz to
20 kHz; see Figure 33
RL = 50 Ω, CL = 5 pF; see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 34
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +5.5 V, VSS = −5.5 V
All switches open
All switches closed, VL = 5.5 V
All switches closed, VL = 2.7 V
Digital inputs = 0 V or VL
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS = VL and SDI = 0 V or VL, VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Digital inputs toggle between 0 V
and VL, VL = 5.5 V
E
E
E
E
E
E
E
E
Digital inputs toggle between 0 V
and VL, VL = 2.7 V
Digital inputs = 0 V or VL
GND = 0 V
GND = 0 V
Data Sheet
ADGS1612
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels,
∆RON
On Resistance Flatness, RFLAT (ON)
25°C
−40°C to +85°C
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
0.95
1.25
1.45
Ω max
Ω typ
0.06
0.2
0.23
0.07
0.08
VS = 0 V to 10 V, IS = −10 mA
0.27
0.32
Ω max
Ω typ
Ω max
nA typ
VDD = 10.8 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 32
±0.1
±0.3
±0.1
±1.0
Drain Off Leakage, ID (Off )
±0.3
±0.2
±0.4
±1.0
±6.0
±1.5
±10.0
DIGITAL OUTPUT
Output Voltage
Low, VOL
Output Current, Low (IOL) or High (IOH)
±6.0
0.4
0.2
0.001
±0.1
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
4
2
1.35
0.8
0.8
Low, VINL
Input Current, Low (IINL) or High (IINH)
0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
On Time, tON
4
nA max
nA typ
nA max
nA typ
nA max
V min
V min
V max
V max
μA typ
μA max
pF typ
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V, see Figure 35
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 37
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 30
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
140
Off Isolation
−65
dB typ
Channel to Channel Crosstalk
−93
dB typ
470
260
280
140
Rev. 0 | Page 5 of 29
VS = VD = 1 V/10 V; see Figure 28
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
470
VS = 1 V/10 V, VD = 10 V/1 V; see
Figure 32
V max
V max
μA typ
μA max
pF typ
365
460
190
235
200
Off Time, tOFF
VS = 0 V to 10 V, IS = −10 mA;
see Figure 29
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −10 mA
1.1
0.03
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID (On), IS (On)
Test Conditions/Comments
ADGS1612
Data Sheet
Parameter
Total Harmonic Distortion Plus Noise,
THD + N
−3 dB Bandwidth
Insertion Loss
25°C
0.012
−40°C to +85°C
−40°C to +125°C
34
−0.07
MHz typ
MHz typ
Off Switch Source Capacitance, CS (Off )
Off Switch Drain Capacitance, CD (Off )
On Switch Capacitance, CD (On), CS (On)
POWER REQUIREMENTS
Positive Supply Current, IDD
60
60
154
dB typ
pF typ
pF typ
0.01
1
320
480
320
480
Digital Supply Current, IL
Inactive
6.3
SCLK = 50 MHz
Inactive, SDI = 1 MHz
SDI = 25 MHz
Active at 50 MHz
14
7
μA typ
390
μA typ
210
15
7.5
230
120
1.8
μA typ
μA typ
μA typ
μA typ
μA typ
mA typ
2.1
0.7
VDD
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
8.0
Inactive, SCLK = 1 MHz
Unit
% typ
1.0
3.3
16
Rev. 0 | Page 6 of 29
mA max
mA typ
mA max
V min
V max
Test Conditions/Comments
RL = 110 Ω, 5 V p-p, f = 20 Hz to
20 kHz; see Figure 33
RL = 50 Ω, CL = 5 pF; see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 34
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 12 V
All switches open
All switches closed, VL = 5.5 V
All switches closed, VL = 2.7 V
Digital inputs = 0 V or VL
CS = VL and SDI = 0 V or VL,
VL = 5 V
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS = VL and SDI = 0 V or VL,
VL = 5 V
CS = VL and SDI = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Digital inputs toggle between 0 V
and VL, VL = 5.5 V
E
E
E
E
E
E
E
E
Digital inputs toggle between 0 V
and VL, VL = 2.7 V
GND = 0 V, VSS = 0 V
GND = 0 V, VSS = 0 V
Data Sheet
ADGS1612
5 V SINGLE SUPPLY
VDD = 5 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On Resistance Match Between Channels,
∆RON
On Resistance Flatness, RFLAT (ON)
25°C
−40°C to +85°C
−40°C to +125°C
Unit
0 V to VDD
V
Ω typ
1.7
2.4
2.7
Ω max
Ω typ
0.09
0.4
0.53
0.12
0.15
VS = 0 V to 4.5 V, IS = −10 mA
0.55
0.6
Ω max
Ω typ
Ω max
nA typ
VDD = 5.5 V, VSS = 0 V
VS = 1 V or 4.5 V, VD = 4.5 V/1 V;
see Figure 32
±0.1
±0.3
±0.1
±1.0
Drain Off Leakage, ID (Off )
±0.3
±0.2
±0.4
±1.0
±6.0
±1.5
±10.0
DIGITAL OUTPUT
Output Voltage
Low, VOL
Output Current, Low (IOL) or High (IOH)
±6.0
0.4
0.2
0.001
±0.1
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
4
2
1.35
0.8
0.8
Low, VINL
Input Current, Low (IINL) or High (IINH)
0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
On Time, tON
4
nA max
nA typ
nA max
nA typ
nA max
V min
V min
V max
V max
μA typ
μA max
pF typ
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
3.3 V < VL ≤ 5.5 V
2.7 V ≤ VL ≤ 3.3 V
VIN = VGND or VL
RL = 300 Ω, CL = 35 pF
VS = 2.5 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 2.5 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 2.5 V, see Figure 35
VS = 0 V, RS = 0 Ω, CL = 1 nF; see
Figure 37
RL = 50 Ω, CL = 5 pF, f = 100 kHz; see
Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 30
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
72
Off Isolation
−65
dB typ
Channel to Channel Crosstalk
−93
dB typ
525
410
455
95
Rev. 0 | Page 7 of 29
VS = VD = 1 V/4.5 V; see Figure 28
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
ns typ
ns max
ns typ
Ns max
ns typ
ns min
pC typ
515
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see
Figure 32
V max
V max
μA typ
μA max
pF typ
405
510
290
365
165
Off Time, tOFF
VS = 0 V to 4.5 V, IS = −10 mA; see
Figure 29
VDD = 4.5 V, VSS = 0 V
VS = 0 V to 4.5 V, IS = −10 mA
2.15
0.05
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Channel On Leakage, ID (On), IS (On)
Test Conditions/Comments
ADGS1612
Data Sheet
Parameter
Total Harmonic Distortion Plus Noise,
THD + N
−3 dB Bandwidth
Insertion Loss
25°C
0.093
−40°C to +85°C
−40°C to +125°C
38
−0.15
MHz typ
dB typ
Off Switch Source Capacitance, CS (Off )
Off Switch Drain Capacitance, CD (Off )
On Switch Capacitance, CD (On), CS (On)
POWER REQUIREMENTS
Positive Supply Current, IDD
72
72
160
pF typ
pF typ
pF typ
0.01
1
0.01
1
130
220
Digital Supply Current, IL
Inactive
6.3
SCLK = 50 MHz
Inactive, SDI = 1 MHz
SDI = 25 MHz
Active at 50 MHz
14
7
μA typ
390
μA typ
210
μA typ
15
7.5
230
120
1.8
μA typ
μA typ
μA typ
μA typ
mA typ
2.1
0.7
VDD
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
μA max
μA typ
8.0
Inactive, SCLK = 1 MHz
Unit
% typ
1.0
3.3
16
Rev. 0 | Page 8 of 29
mA max
mA typ
mA max
V min
V max
Test Conditions/Comments
RL = 110 Ω, f = 20 Hz to 20 kHz,
VS = 3.5 V p-p ; see Figure 33
RL = 50 Ω, CL = 5 pF; see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 34
VS = 2.5 V, f = 1 MHz
VS = 2.5 V, f = 1 MHz
VS = 2.5 V, f = 1 MHz
VDD = 5.5 V
All switches open
All switches closed, VL = 5.5 V
All switches closed, VL = 2.7 V
Digital inputs = 0 V or VL
CS = VL and SDI = 0 V or VL,
VL = 5 V
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS = VL and SDI = 0 V or VL,
VL = 5 V
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 5 V
CS and SCLK = 0 V or VL, VL = 3 V
Digital inputs toggle between 0 V
and VL, VL = 5.5 V
E
E
E
E
E
E
E
E
Digital inputs toggle between 0 V
and VL, VL = 2.7 V
GND = 0 V, VSS = 0 V
GND = 0 V, VSS = 0 V
Data Sheet
ADGS1612
3.3 V SINGLE SUPPLY
VDD = 3.3 V, VSS = 0 V, VL = 2.7 V to 3.3 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
25°C
−40°C to +85°C
−40°C to +125°C
Unit
3.2
3.4
0 V to VDD
3.6
V
Ω typ
On Resistance Match Between Channels,
∆RON
On Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
0.06
0.07
0.08
Ω typ
1.2
1.3
1.4
Ω typ
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
±0.1
nA typ
±0.3
±0.1
±1.0
±0.3
±0.2
±0.4
±1.0
±6.0
nA max
±1.5
±10.0
V max
0.4
0.2
V max
V max
μA typ
μA max
pF typ
0.001
±0.1
Digital Output Capacitance, COUT
DIGITAL INPUTS
Input Voltage
High, VINH
Low, VINL
Input Current, Low (IINL) or High (IINH)
4
1.35
0.8
0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS
On Time, tON
nA max
nA typ
4
V min
V max
μA typ
μA max
pF typ
Break-Before-Make Time Delay, tD
545
720
470
630
155
Charge Injection, QINJ
50
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
Channel to Channel Crosstalk
−65
−93
dB typ
dB typ
Total Harmonic Distortion Plus Noise,
THD + N
−3 dB Bandwidth
Insertion Loss
0.18
% typ
50
−0.27
MHz typ
dB typ
Off Switch Source Capacitance, CS (Off )
Off Switch Drain Capacitance, CD (Off )
On Switch Capacitance, CD (On), CS (On)
76
76
160
pF typ
pF typ
pF typ
Off Time, tOFF
VS = 0 V to VDD, IS = −10 mA, VDD =
3.3 V, VSS = 0 V; see Figure 29
VS = 0 V to VDD, IS = −10 mA
VS = 0 V to VDD, IS = −10 mA
VDD = 3.3 V, VSS = 0 V
VS = 0.6 V/3 V, VD = 3 V/0.6 V; see
Figure 32
VS = 0.6 V/3 V, VD = 3 V/0.6 V; see
Figure 32
VS = VD = 0.6 V/3 V; see Figure 28
DIGITAL OUTPUT
Output Voltage
Low, VOL
Output Current, Low (IOL) or High (IOH)
±6.0
Test Conditions/Comments
730
735
695
760
50
Rev. 0 | Page 9 of 29
ISINK = 5 mA
ISINK = 1 mA
VOUT = VGND or VL
VIN = VGND or VL
RL = 300 Ω, CL = 35 pF
VS = 1.5 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS = 1.5 V; see Figure 36
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 1.5 V, see Figure 35
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see
Figure 37
CL = 5 pF, f = 100 kHz; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 30
RL = 110 Ω, f = 20 Hz to 20 kHz,
VS = 2 V p-p; see Figure 33
RL = 50 Ω, CL = 5 pF; see Figure 34
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 34
VS = 1.5 V, f = 1 MHz
VS = 1.5 V, f = 1 MHz
VS = 1.5 V, f = 1 MHz
ADGS1612
Parameter
POWER REQUIREMENTS
Positive Supply Current, IDD
Data Sheet
25°C
−40°C to +85°C
−40°C to +125°C
0.01
1
0.01
1
Digital Supply Current, IL
Inactive
3.2
Unit
μA typ
μA max
μA typ
μA max
7
μA typ
μA max
μA typ
SCLK = 50 MHz
210
μA typ
Inactive, SDI = 1 MHz
SDI = 25 MHz
Active at 50 MHz
7.5
120
0.7
μA typ
μA typ
mA typ
4.8
Inactive, SCLK = 1 MHz
VDD
1.0
3.3
16
Rev. 0 | Page 10 of 29
mA max
V min
V max
Test Conditions/Comments
VDD = 3.3 V
All switches open
All switches closed, VL = 3.3 V
Digital inputs = 0 V or VL
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS = VL and SDI = 0 V or VL,
VL = 3 V
CS and SCLK = 0 V or VL, VL = 3 V
CS and SCLK = 0 V or VL, VL = 3 V
Digital inputs toggle between 0 V
and VL, VL = 2.7 V
E
E
E
E
GND = 0 V, VSS = 0 V
GND = 0 V, VSS = 0 V
Data Sheet
ADGS1612
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5. Four Channels On
Parameter
CONTINUOUS CURRENT, Sx OR Dx
VDD = +5 V, VSS = −5 V (θJA = 60°C/W)
VDD = 12 V, VSS = 0 V (θJA = 60°C/W)
VDD = 5 V, VSS = 0 V (θJA = 60°C/W)
VDD = 3.3 V, VSS = 0 V (θJA = 60°C/W)
25°C
85°C
125°C
Unit
315
330
249
203
194
200
161
137
106
108
96
87
mA max
mA max
mA max
mA max
25°C
85°C
125°C
Unit
566
591
450
366
292
301
251
218
126
127
120
113
mA max
mA max
mA max
mA max
Table 6. One Channel On
Parameter
CONTINUOUS CURRENT, Sx OR Dx
VDD = +5 V, VSS = −5 V (θJA = 60°C/W)
VDD = 12 V, VSS = 0 V (θJA = 60°C/W)
VDD = 5 V, VSS = 0 V (θJA = 60°C/W)
VDD = 3.3 V, VSS = 0 V (θJA = 60°C/W)
TIMING CHARACTERISTICS
VL = 2.7 V to 5.5 V; GND = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 7.
Parameter
t1
t2
t3
t4
t5
t6
t7
t8
t91
t10
t11
t12
t13
1
Limit at TMIN, TMAX
20
8
8
10
6
8
10
20
20
20
20
8
8
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns max
ns min
ns min
ns min
Description
SCLK period
SCLK high pulse width
SCLK low pulse width
CS falling edge to SCLK rising edge
Data setup time
Data hold time
SCLK active edge to CS rising edge
CS falling edge to SDO data available
SCLK falling edge to SDO data available
CS rising edge to SDO returns to high impedance
CS high time between SPI commands
CS falling edge to SCLK becomes stable
CS rising edge to SCLK becomes stable
Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. The t9 parameter determines the maximum SCLK frequency when SDO is used.
Rev. 0 | Page 11 of 29
ADGS1612
Data Sheet
Timing Diagrams
t1
SCLK
t4
t2
t3
t7
CS
t5
SDI
R/W
t6
A6
A5
D2
D1
D0
t10
t9
0
0
1
D2
D1
D0
16054-002
SDO
t8
Figure 2. Addressable Mode Timing Diagram
t1
SCLK
t2
t3
t4
t7
CS
D7
D6
D0
INPUT BYTE FOR DEVICE N
t9
SDO
0
t8
0
0
ZERO BYTE
D7
D6
D1
INPUT BYTE FOR DEVICE N + 1
D7
D6
D1
INPUT BYTE FOR DEVICE N
Figure 3. Daisy-Chain Timing Diagram
t11
CS
SCLK
t13
D0
t12
Figure 4. SCLK/CS Timing Diagram
Rev. 0 | Page 12 of 29
t10
D0
16054-003
SDI
t6
16054-004
t5
Data Sheet
ADGS1612
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 8.
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Parameter
VDD to VSS
VDD to GND
VSS to GND
RESET/VL to GND
VDD ≤ 5.5 V
VDD > 5.5 V
Analog Inputs1
Digital Inputs1
Peak Current, Sx or Dx Pins2
Continuous Current, Sx or Dx2, 3
Temperature Ranges
Operating
Storage
Junction Temperature
Reflow Soldering Peak
Temperature, Pb-Free
Rating
18 V
−0.3 V to +18 V
+0.3 V to −18 V
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
−0.3V to VDD + 0.3 V
−0.3 V to +6 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
−0.3 V to +6 V
546 mA (pulsed at 1 ms, 10%
duty cycle maximum)
Data + 15%
Table 9. Thermal Resistance
Package Type
CP-24-171
1
θJA
60
θJC
13
Unit
°C/W
Thermal impedance simulated values are based on a JEDEC 2S2P thermal
test board. See JEDEC JESD51.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
260°C
1
Overvoltages at the digital, Sx, and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2
Sx refers to the S1 to S4 pins, and Dx refers to the D1 to D4 pins.
3
See Table 5 and Table 6.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
Rev. 0 | Page 13 of 29
ADGS1612
Data Sheet
20 SDO
19 NIC
22 SCLK
21 CS
23 SDI
24 NIC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
18 D2
D1 1
VSS 3
17 S2
ADGS1612
16 NIC
TOP VIEW
(Not to Scale)
GND 4
S4 5
15 VDD
14 S3
D4 6
NIC 12
GND 11
NIC 10
RESET/VL 9
NIC 8
NIC 7
13 D3
NOTES
1. THE EXPOSED PAD IS CONNECTED
INTERNALLY. FOR INCREASED RELIABILITY
OF THE SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE EXPOSED PAD BE SOLDEREDTO
THE SUBSTRATE, VSS.
2. NIC = NOT INTERNALLY CONNECTED.
16054-005
S1 2
Figure 5. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
1
2
3
4, 11
5
6
7, 8, 10, 12,
16, 19, 24
9
Mnemonic
D1
S1
VSS
GND
S4
D4
NIC
Description
Drain Terminal 1. This pin can be an input or an output.
Source Terminal 1. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
Ground (0 V) Reference.
Source Terminal 4. This pin can be an input or an output.
Drain Terminal 4. This pin can be an input or an output.
Not Internally Connected. These pins are not internally connected.
RESET/VL
13
14
15
17
18
20
D3
S3
VDD
S2
D2
SDO
21
CS
22
23
SCLK
SDI
EPAD
Reset/Logic Power Supply Input. Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply.
Pull the pin low to complete a hardware reset. All switches are opened, and the appropriate registers are set
to their default settings.
Drain Terminal 3. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Most Positive Power Supply Potential.
Source Terminal 2. This pin can be an input or an output.
Drain Terminal 2. This pin can be an input or an output.
Serial Data Output. This pin can be used for daisy-chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK. Pull this open-drain output to VL with an external resistor.
Active Low Control Input. CS is the frame synchronization signal for the input data. When CS goes low, it
powers on the SCLK buffers and enables the input shift register. Data is transferred in on the falling edges of
the following clocks. Taking CS high updates the switch condition.
Serial Clock Input. Data is captured on the positive edge of SCLK. Data is transferred at rates of up to 50 MHz.
Serial Data Input. Data is captured on the positive edge of the serial clock input.
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.
Rev. 0 | Page 14 of 29
Data Sheet
ADGS1612
TYPICAL PERFORMANCE CHARACTERISTICS
1.4
1.4
TA = +125°C
TA = +85°C
VDD = 12V
VSS = 0V
1.2
ON RESISTANCE (Ω)
1.0
0.8
1.0
0.8
0.6
0.6
TA = 25°C
VDD = +5V, VSS = –5V
–6
–4
–2
0
2
4
6
8
VS OR VD VOLTAGE (V)
0.4
16054-006
0.4
–8
VDD = +3.3V,VSS = –3.3V
VDD = +8V, VSS = –8V
0
2
4
6
8
10
12
VS OR VD VOLTAGE (V)
16054-009
ON RESISTANCE (Ω)
1.2
Figure 9. On Resistance (RON) as a Function of VS (VD) for Various
Temperatures, 12 V Single Supply
Figure 6. On Resistance (RON) as a Function of VS, VD (Dual Supply)
2.5
3.5
VDD = 5V
VSS = 0V
TA = 25°C
VDD = 16V, VSS = 0V
VDD = 12V, VSS = 0V
VDD = 5V, VSS = 0V
VDD = 3.3V, VSS = 0V
ON RESISTANCE (Ω)
3.0
ON RESISTANCE (Ω)
TA = +25°C
TA = –40°C
2.5
2.0
1.5
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
2.0
1.5
0
2
4
6
8
10
12
14
16
VS OR VD VOLTAGE (V)
1.0
16054-007
0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VS OR VD VOLTAGE (V)
Figure 7. On Resistance (RON) as a Function of VS, VD (Single Supply)
16054-010
1.0
Figure 10. On Resistance (RON) as a Function of VS (VD) for Various
Temperatures, 5 V Single Supply
1.4
2.5
VDD = 5V
VSS = 0V
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
0.8
0.6
TA = +125°C
TA = +85°C
TA = +25°C
TA = –40°C
VDD = +5V
VSS = –5V
0.4
–6
–4
–2
0
2
4
6
VS OR VD VOLTAGE (V)
Figure 8. On Resistance (RON) as a Function of VS (VD) for Various
Temperatures, ±5 V Dual Supply
2.0
1.5
1.0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
VS OR VD VOLTAGE (V)
Figure 11. On Resistance (RON) as a Function of VS (VD) for Various
Temperatures, 3.3 V Single Supply
Rev. 0 | Page 15 of 29
16054-010
ON RESISTANCE (Ω)
1.0
16054-008
ON RESISTANCE (Ω)
1.2
ADGS1612
Data Sheet
20
18
+ID (ON), +IS (ON)
–ID (OFF), +ID (OFF)
+IS (OFF), –IS (OFF)
–ID (ON), –IS (ON)
–IS (OFF), +IS (OFF)
+ID (OFF), –ID (OFF)
10
+ID (OFF), +IS (OFF)
–ID (OFF), –IS (OFF)
–ID (OFF), +ID (OFF)
+IS (OFF), –IS (OFF)
–IS (OFF), +IS (OFF)
+ID (OFF), –ID (OFF)
16
14
LEAKAGE CURRENT (nA)
LEAKAGE CURRENT (nA)
15
5
0
–5
12
10
8
6
4
2
0
–10
0
20
40
60
80
100
120
TEMPERATURE (°C)
–4
16054-012
–15
40
60
80
100
120
Figure 15. Leakage Current vs. Temperature, 3.3 V Single Supply
0
25
+ID (ON), +IS (ON)
–ID (OFF), +ID (OFF)
+IS (OFF), –IS (OFF)
–ID (ON), –IS (ON)
–IS (OFF), +IS (OFF)
+ID (OFF), –ID (OFF)
15
TA = 25°C
VDD = +5V
VSS = –5V
–20
OFF ISOLATION (dB)
20
10
5
0
–5
–40
–60
–80
–100
–10
0
20
40
60
80
100
120
TEMPERATURE (°C)
–140
100
16054-013
–20
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 13. Leakage Current vs. Temperature, 12 V Single Supply
16054-016
–120
–15
Figure 16. Off Isolation vs. Frequency, ±5 V Dual Supply
20
0
+ID (OFF), +IS (OFF)
–ID (OFF), –IS (OFF)
–ID (OFF), +ID (OFF)
+IS (OFF), –IS (OFF)
–IS (OFF), +IS (OFF)
+ID (OFF), –ID (OFF)
TA = 25°C
VDD = +5V
VSS = –5V
–40
CROSSTALK (dB)
15
–20
10
5
–60
–80
–100
–120
0
–5
0
20
40
60
80
100
120
TEMPERATURE (°C)
16054-014
–140
–160
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 17. Crosstalk vs. Frequency, ±5 V Dual Supply
Figure 14. Leakage Current vs. Temperature, 5 V Single Supply
Rev. 0 | Page 16 of 29
1G
16054-017
LEAKAGE CURRENT (nA)
20
TEMPERATURE (°C)
Figure 12. Leakage Current vs. Temperature, ±5 V Dual Supply
LEAKAGE CURRENT (nA)
0
16054-015
–2
Data Sheet
ADGS1612
0
300
–1
200
BANDWIDTH (dB)
CHARGE INJECTION (pC)
250
TA = 25°C
VDD = 12.0V, VSS = 0V
VDD = 5V, VSS = –5V
VDD = 5V, VSS = 0V
VDD = 3.3V, VSS = 0V
150
100
–2
–3
–4
–5
50
–2
0
2
4
6
8
10
12
14
VS (V)
–6
1k
10k
100k
600
WITH 10µF AND 100nF DECOUPLING CAP
WITH 100nF DECOUPLING CAP
WITHOUT DECOUPLING CAP
–10
–30
–40
–50
–60
–70
–90
300
200
5.5V DUAL SUPPLY, tOFF
13.2V SINGLE SUPPLY, tOFF
5.5V SINGLE SUPPLY, tOFF
100
TA = 25°C
VDD = +5V
VSS = –5V
–110
–120
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
0
–40
600
125
tON, tOFF TIMES (ns)
500
0.12
0.10
0.08
0.06
400
300
200
0.04
0
0
5k
10k
15k
FREQUENCY (Hz)
20k
Figure 20. THD + N vs. Frequency, ±5 V Dual Supply
0
–40
25
60
85
TEMPERATURE (°C)
Figure 23. tON, tOFF Times vs. Temperature, VL = 3.3 V
Rev. 0 | Page 17 of 29
125
16054-023
100
0.02
16054-020
THD + N (%)
85
3.3V SINGLE SUPPLY, tON
3.3V SINGLE SUPPLY, tOFF
0.18
0.14
60
Figure 22. tON, tOFF Times vs. Temperature, VL = 5.5 V
0.20
RL = 110Ω, TA = 25°C
VDD = +12.0V, VS = 5V p-p
VDD = +5V , VSS = –5V, VS = 5V p-p
VDD = +5V, VS = 3.5V
VDD = +3.3V, VS = 2V
25
TEMPERATURE (°C)
Figure 19. AC Power Supply Power Rejection Ratio (AC PSRR) vs. Frequency,
±5 V Dual Supply
0.16
1G
400
–80
–100
100M
5.5V DUAL SUPPLY, tON
13.2V SINGLE SUPPLY, tON
5.5V SINGLE SUPPLY, tON
500
tON, tOFF TIMES (ns)
–20
10M
Figure 21. Bandwidth
16054-019
AC POWER SUPPLY POWER REJECTION RATIO (PSRR)
Figure 18. Charge Injection vs. Source Voltage, VS
0
1M
FREQUENCY (Hz)
16054-022
–4
16054-018
0
–6
16054-021
TA = 25°C
VDD = +5V
ADGS1612
Data Sheet
100
2.0
90
1.5
80
1.0
70
0.5
VOUT (mV)
60
TA = 25°C
VDD = +5V
VSS = –5V
40
12.0V SINGLE SUPPLY
5.0V DUAL SUPPLY
5.0V SINGLE SUPPLY
3.3V SINGLE SUPPLY
30
0
–0.5
–1.0
20
–1.5
10
–2.0
0
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VL (V)
TA = 25°C
VDD = +5V
VSS = –5V
–2.5
16054-026
50
16054-024
IDD (µA)
SCLK = 2.5MHz
SCLK IDLE
TIME (µs)
Figure 26. Digital Feedthrough
Figure 24. IDD vs. VL
180
450
TA = 25°C
160
350
250
200
150
100
VL = 5V
VL = 3V
50
0
0
10
20
30
40
SCLK FREQUENCY (MHz)
50
16054-025
IL (µA)
300
140
120
100
80
60
TA = 25°C
VDD = +5V
VSS = –5V
CS OFF
CD OFF
CD/CS ON
40
20
0
–5
–4
–3
–2
–1
0
1
2
3
4
SOURCE VOLTAGE
Figure 27. Source/Drain Capacitance vs. Source Voltage (VS)
Figure 25. IL vs. SCLK Frequency When CS Is High
Rev. 0 | Page 18 of 29
5
16054-027
SOURCE/DRAIN CAPACITANCE (pF)
400
Data Sheet
ADGS1612
TEST CIRCUITS
IS (OFF)
A
A
VD
NC = NO CONNECT
Sx
Dx
ID (OFF)
A
VS
16054-032
ID (ON)
Dx
16054-028
Sx
NC
VD
Figure 28. On Leakage
Figure 32. Off Leakage
VDD
VSS
0.1µF
0.1µF
AUDIO PRECISION
VDD
VSS
IDS
V1
Dx
16054-033
16054-029
Figure 33. THD + N
Figure 29. On Resistance
VDD
VDD
VSS
VDD
VSS
S1
VSS
0.1µF
0.1µF
0.1µF
0.1µF
RL
50Ω
VOUT
RL
1kΩ
GND
RON = V1/IDS
VOUT
VS
V p-p
Dx
VS
NETWORK
ANALYZER
50Ω
VDD
NC
D1
NETWORK
ANALYZER
VSS
Sx
D2
S2
VS
RL
50Ω
VS
50Ω
Dx
RL
50Ω
GND
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
16054-030
GND
VOUT
VS
INSERTION LOSS = 20 log
Figure 30. Channel to Channel Crosstalk
VDD
0.1µF
VDD
NETWORK
ANALYZER
VSS
Sx
50Ω
VS
RL
50Ω
GND
VOUT
OFF ISOLATION = 20 log
VOUT
VS
16054-031
Dx
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 34. Bandwidth
VSS
0.1µF
Figure 31. Off Isolation
Rev. 0 | Page 19 of 29
VOUT
16054-034
Sx
RS
Sx
ADGS1612
Data Sheet
VDD
VSS
0.1µF
0.1µF
SCLK
50%
VSS
VS1
S1
D1
VS2
S2
D2
RL
300Ω
INPUT LOGIC
CL2
35pF
RL1
300Ω
V OUT2
CL1
35pF
VOUT1
80%
VOUT1
80%
0V
80%
VOUT2
80%
0V
GND
tD
16054-035
VDD
50%
0V
tD
Figure 35. Break-Before-Make Time Delay, tD
VDD
VSS
0.1µF
0.1µF
VSS
Sx
VOUT
Dx
RL
300Ω
VS
INPUT LOGIC
CL
35pF
SCLK
50%
50%
90%
VOUT
10%
GND
tON
tOFF
16054-036
VDD
Figure 36. Switching Times
3V
SYNC
RS
VDD
VSS
VDD
VSS
S
D
QINJ = CL × ∆VOUT
SWITCH OFF
GND
SWITCH ON
Figure 37. Charge Injection
VSS
NETWORK
ANALYZER
RL
50Ω
VDD
INTERNAL
BIAS
VSS
VS
VOUT
RL
50Ω
S1
D1
NIC
GND
V
AC PSRR = 20 log OUT
VS
NOTES
1. BOARD AND COMPONENT EFFECTS ARE NOT DE-EMBEDDED
FROM THE AC PSRR MEASUREMENT.
Figure 38. AC PSRR
Rev. 0 | Page 20 of 29
16054-037
INPUT LOGIC
∆VOUT
16054-038
VOUT
VOUT
CL
1nF
VS
Data Sheet
ADGS1612
TERMINOLOGY
IDD
IDD is the positive supply current.
CD (On), CS (On)
CD (On) and CS (On) are the on switch capacitances, measured
with reference to ground.
ISS
ISS is the negative supply current.
VD, VS
VD and VS are the analog voltages on Terminal D and Terminal
S, respectively.
RON
RON is the ohmic resistance between Terminal D and Terminal
S.
ΔRON
ΔRON is the difference between the RON of any two channels.
RFLAT (ON)
RFLAT (ON) is the difference between the maximum and minimum
values of on resistance, measured over the specified analog
signal range.
IS (Off)
IS (Off) is the source leakage current with the switch off.
CIN
CIN is the digital input capacitance.
tON
tON is the delay between applying the digital control input and
the output switching on.
tOFF
tOFF is the delay between applying the digital control input and
the output switching off.
tD
tD is the off time measured between the 80% point of both
switches when switching from one address state to another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) are the channel leakage currents with the
switch on.
IDS
IDS is the drain to source current.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
V1
V1 is the voltage drop across the switch, Sx, to Dx.
On Response
On response is the frequency response of the on switch.
VINL
VINL is the maximum input voltage for Logic 0.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
VINH
VINH is the minimum input voltage for Logic 1.
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
IINL, IINH
IINL and IINH is the low and high input currents of the digital
inputs.
CD (Off)
CD (Off) is the off switch drain capacitance, which is measured
with reference to ground.
CS (Off)
CS (Off) is the off switch source capacitance, which is measured
with reference to ground.
AC Power Supply Rejection Ratio (AC PSRR)
AC PSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. AC PSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the switch.
The dc voltage on the device is modulated by a sine wave of
0.62 V p-p.
Rev. 0 | Page 21 of 29
ADGS1612
Data Sheet
THEORY OF OPERATION
reads. A register write occurs on the 16th SCLK rising edge
during SPI writes.
The ADGS1612 is a set of serially controlled, quad SPST switches
with error detection features. SPI Mode 0 and SPI Mode 3 can
be used with the device, and it operates with SCLK frequencies
of up to 50 MHz. The default mode for the ADGS1612 is address
mode, in which the registers of the device are accessed by a 16-bit
SPI command bounded by CS. The SPI command becomes 24-bit
if the user enables CRC error detection. Other error detection
features include SCLK count error and invalid read/write error. If
any of these SPI interface errors occur, they are detectable by
reading the error flags register. The ADGS1612 can also operate
in two other modes, namely burst mode and daisy-chain mode.
During any SPI command, SDO sends out eight alignment bits
on the first eight SCLK falling edges. The alignment bits observed
at SDO are 0x25.
ERROR DETECTION FEATURES
Protocol and communication errors on the SPI interface are
detectable. There are three detectable errors: incorrect SCLK error
detection, invalid read and write address error detection, and
CRC error detection. Each of these errors has a corresponding
enable bit in the error configuration register. In addition, there
is an error flag bit for each of these errors in the error flags
register.
The interface pins of the ADGS1612 are CS, SCLK, SDI, and
SDO. Hold CS low when using the SPI interface. Data is captured
on the SDI pin on the rising edge of SCLK, and data is propagated
out on the SDO pin on the falling edge of SCLK. SDO has an
open-drain output; thus, connect a pull-up resistor to this
output. When not pulled low by the ADGS1612, SDO is in a
high impedance state.
Cyclic Redundancy Check (CRC) Error Detection
The CRC error detection feature extends a valid SPI frame by
eight SCLK cycles. These eight extra cycles are needed to send the
CRC byte for that SPI frame. The CRC byte is calculated by the SPI
block using the 16-bit payload: the R/W bit, Address Bits[6:0], and
Data Bits[7:0]. The CRC polynomial used in the SPI block is
x8 + x2 + x1 + 1 with a seed value of 0. For a timing diagram with
CRC enabled, see Figure 40. Register writes occur at the 24th SCLK
rising edge with CRC error checking enabled.
ADDRESS MODE
Address mode is the default mode for the ADGS1612 on
power-up. A single SPI frame in address mode is bounded by a
CS falling edge and the succeeding CS rising edge. The SPI frame
is composed of 16 SCLK cycles. The timing diagram for address
mode is shown in Figure 39. The first SDI bit indicates whether
the SPI command is a read or write command. When the first
bit is set to 0, a write command is issued, and if the first bit is set
to 1, a read command is issued. The next seven bits determine the
target register address. The remaining eight bits provide the data
to the addressed register. The last eight bits are ignored during a
read command, because during these clock cycles, SDO
propagates out the data contained in the addressed register.
During an SPI write, the microcontroller/CPU provides the
CRC byte through SDI. The SPI block checks the CRC byte just
before the 24th SCLK rising edge. On this same edge, the register
write is prevented if an incorrect CRC byte is received by the
SPI interface. The CRC error flag is asserted in the error flags
register in the case of the incorrect CRC byte being detected.
During an SPI read, the CRC byte is provided to the microcontroller through SDO.
The target register address of an SPI command is determined on
the eighth SCLK rising edge. Data from this register propagates out
on SDO from the ninth to the 16th SCLK falling edge during SPI
The CRC error detection feature is disabled by default and can
be configured by the user through the error configuration register.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
R/W
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
CS
SDI
SDO
0
0
1
0
0
1
0
1
D7
D6
D5
D4
D3
D2
D1
D0
16054-039
SCLK
Figure 39. Address Mode Timing Diagram
1
2
8
9
10
16
17
18
19
20
21
22
23
24
R/W
A6
A0
D7
D6
D0
C7
C6
C5
C4
C3
C2
C1
C0
CS
SDI
SDO
0
0
1
D7
D6
D0
C7
C6
C5
Figure 40. Timing Diagram with CRC Enabled
Rev. 0 | Page 22 of 29
C4
C3
C2
C1
C0
16054-040
SCLK
Data Sheet
ADGS1612
SCLK Count Error Detection
BURST MODE
SCLK count error detection allows the user to detect if an incorrect
number of SCLK cycles are sent by the microcontroller or CPU.
When in address mode, with CRC disabled, 16 SCLK cycles are
expected. If 16 SCLK cycles are not detected, the SCLK count
error flag asserts in the error flags register. When less than
16 SCLK cycles are received by the device, a write to the register
map never occurs. When the ADGS1612 receives more than
16 SCLK cycles, a write to the memory map still occurs at the
16th SCLK rising edge, and the flag asserts in the error flags
register. With CRC enabled, the expected number of SCLK
cycles is 24. SCLK count error detection is enabled by default
and can be configured by the user through the error
configuration register.
The SPI interface can accept consecutive SPI commands
without the need to deassert the CS line, which is called burst
mode. Burst mode is enabled through the burst enable register.
This mode uses the same 16-bit command to communicate
with the device. In addition, the response of the device at SDO
is still aligned with the corresponding SPI command. Figure 41
shows an example of SDI and SDO during burst mode.
An invalid read/write address error detects when a nonexistent
register address is a target for a read or write. In addition, this
error asserts when a write to a read only register is attempted.
The invalid read/write address error flag asserts in the error
flags register when an invalid read/write address error occurs.
The invalid read/write address error is detected on the ninth
SCLK rising edge, which means a write to the register never
occurs when an invalid address is targeted. Invalid read/write
address error detection is enabled by default and can be
disabled by the user through the error configuration register.
CLEARING THE ERROR FLAGS REGISTER
CS
SDI
COMMAND 0[15:0] COMMAND 1[15:0] COMMAND 2[15:0] COMMAND 3[15:0]
SDO
RESPONSE 0[15:0] RESPONSE 1[15:0] RESPONSE 2[15:0] RESPONSE 3[15:0]
Figure 41. Burst Mode Frame
SOFTWARE RESET
When in address mode, the user can initiate a software reset. To
do so, write two consecutive SPI commands, namely 0xA3 followed by 0x05, targeting Register 0x0B. After a software reset,
all register values are set to default.
DAISY-CHAIN MODE
To clear the error flags register, write the special 16-bit SPI
frame, 0x6CA9, to the device. This SPI command does not
trigger the invalid R/W address error. When CRC is enabled,
the user must also send the correct CRC byte to complete an
error clear command. At the 16th or 24th SCLK rising edge, the
error flags register resets to zero.
The connection of several ADGS1612 devices in a daisy-chain
configuration is possible, and Figure 42 shows this setup. All
devices share the same CS and SCLK line, whereas the SDO pin of
a device forms a connection to the SDI pin of the next device,
creating a shift register. In daisy-chain mode, SDO is an eight-cycle
delayed version of SDI. When in daisy-chain mode, all commands
target the switch data register. Therefore, it is not possible to
make configuration changes while in daisy-chain mode.
DEVICE 1
DEVICE 2
ADGS1612
ADGS1612
S1
D1
S1
D1
S2
D2
S2
D2
S3
D3
S3
D3
S4
D4
S4
D4
SPI
INTERFACE
16054-041
Invalid Read/Write Address Error
The invalid read/write address and CRC error checking functions
operate similarly during burst mode as they do during address
mode. However, SCLK count error detection operates in a
slightly different manner. The total number of SCLK cycles
within a given CS frame are counted, and if the total is not a
multiple of 16 or a multiple of 24 when CRC is enabled, the
SCLK count error flag asserts.
RESET/VL
SDO
SPI
INTERFACE
16054-042
SDI
SCLK
CS
SDO
RESET/VL
Figure 42. Two SPI Controlled Switches Connected in a Daisy-Chain Configuration
Rev. 0 | Page 23 of 29
ADGS1612
Data Sheet
The ADGS1612 can only enter daisy-chain mode when in
address mode by sending the 16-bit SPI command, 0x2500
(see Figure 43). When the ADGS1612 receives this command,
the SDO of the device sends out the same command because
the alignment bits at SDO are 0x25, which allows multiple
daisy-connected devices to enter daisy-chain mode in a single
SPI frame. A hardware reset is required to exit daisy-chain mode.
An SCLK rising edge reads in data on SDI while data is
propagated out of SDO on an SCLK falling edge. The expected
number of SCLK cycles must be a multiple of eight before CS
goes high; if this is not the case, the SPI interface sends the last
eight bits received to the switch data register.
POWER-ON RESET
The digital section of the ADGS1612 enters an initialization phase
during VL power-up. This initialization also occurs after a
hardware or software reset. After VL power-up or a reset, ensure
that a minimum of 120 μs from the time of power-up or reset
before any SPI command is issued. Ensure that VL does not
drop out during the 120 μs initialization phase because this may
result in incorrect operation of the ADGS1612.
For the timing diagram of a typical daisy-chain SPI frame, see
Figure 44. When CS goes high, Device 1 writes Command 0,
Bits[7:0] to its switch data register, Device 2 writes Command 1,
Bits[7:0] to its switches, and so on. The SPI block uses the last
eight bits it received through SDI to update the switches. After
entering daisy-chain mode, the first eight bits sent out by SDO
on each device in the chain are 0x00. When CS goes high, the
internal shift register value does not reset back to zero.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
0
CS
SDI
SDO
0
0
1
0
0
1
0
1
0
0
0
0
0
0
0
16054-043
SCLK
0
Figure 43. SPI Command to Enter Daisy-Chain Mode
SDI
COMMAND 3[7:0]
COMMAND 2[7:0]
COMMAND 1[7:0]
COMMAND 0[7:0]
DEVICE 1
SDO
8’h00
COMMAND 3[7:0]
COMMAND 2[7:0]
COMMAND 1[7:0]
DEVICE 2
SDO2
8’h00
8’h00
COMMAND 3[7:0]
COMMAND 2[7:0]
DEVICE 3
SDO3
8’h00
8’h00
8’h00
COMMAND 3[7:0]
DEVICE 4
NOTES
1. SDO2 AND SDO3 ARE THE OUTPUT COMMANDS FROM DEVICE 2 AND DEVICE 3, RESPECTIVELY.
Figure 44. Example of an SPI Frame When Four ADGS1612 Devices Are Connected in Daisy-Chain Mode
Rev. 0 | Page 24 of 29
16054-044
CS
Data Sheet
ADGS1612
APPLICATIONS INFORMATION
BREAK-BEFORE-MAKE SWITCHING
DIGITAL INPUT BUFFERS
The ADGS1612 exhibits break-before-make switching action,
which allows the use of the device in multiplexer applications. A
multiplexer can be achieved by externally hardwiring the device
in the mux configuration that is required, as shown in Figure 45.
There are input buffers present on the digital inputs pins, CS,
SCLK, and SDI. These buffers are active at all times. Therefore,
there is current draw from the VL supply if SCLK or SDI is
toggling, regardless of whether CS is active. For typical values of
this current draw, refer to the Specifications section and Figure 26.
4:1 MUX
POWER SUPPLY RAILS
4 × SPST
To guarantee correct operation of the ADGS1612, 0.1 μF
decoupling capacitors are required.
S1
The ADGS1612 can operate with bipolar supplies between
±3.3 V and ±8 V. The supplies on VDD and VSS do not have to be
symmetrical; however, the VDD to VSS range must not exceed
16 V. The ADGS1612 can also operate with single supplies
between 3.3 V and 16 V with VSS connected to GND.
S2
D1
S3
The voltage range that can be supplied to VL is from 2.7 V to 5.5 V.
S4
SPI
INTERFACE
SDI
CS
RESET/VL
Dx PINS ARE CONNECTED AS ONE DRAIN.
16054-045
SCLK
1ALL
The device is fully specified at ±5 V, 12 V, 5 V, and 3.3 V analog
supply voltage ranges.
Figure 45. SPI Controlled Switch Configured as a 4:1 Mux
Rev. 0 | Page 25 of 29
ADGS1612
Data Sheet
REGISTER SUMMARY
Table 11. Register Summary
Reg.
0x01
0x02
0x03
0x05
0x0B
Name
SW_DATA
ERR_CONFIG
ERR_FLAGS
BURST_EN
SOFT_RESETB
Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
Bit 2
[7:0]
RESERVED
SW4_EN SW3_EN
[7:0]
RESERVED
RW_ERR_EN
[7:0]
RESERVED
RW_ERR_FLAG
[7:0]
RESERVED
[7:0]
SOFT_RESETB
Rev. 0 | Page 26 of 29
Bit 1
SW2_EN
SCLK_ERR_EN
SCLK_ERR_FLAG
Bit 0
SW1_EN
CRC_ERR_EN
CRC_ERR_FLAG
BURST_MODE_EN
Default
0x00
0x06
0x00
0x00
0x00
RW
R/W
R/W
R
R/W
R/W
Data Sheet
ADGS1612
REGISTER DETAILS
SWITCH DATA REGISTER
Address: 0x01, Reset: 0x00, Name: SW_DATA
The switch data register controls the status of the four switches of the ADGS1612.
Table 12. Bit Descriptions for SW_DATA
Bits
[7:4]
3
Bit Name
RESERVED
SW4_EN
Settings
0
1
2
SW3_EN
0
1
1
SW2_EN
0
1
0
SW1_EN
0
1
Description
These bits are reserved; set these bits to 0.
Enable bit for SW4.
SW4 open.
SW4 closed.
Enable bit for SW3.
SW3 open.
SW3 closed.
Enable bit for SW2.
SW2 open.
SW2 closed.
Enable bit for SW1.
SW1 open.
SW1 closed.
Default
0x0
0x0
Access
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
ERROR CONFIGURATION REGISTER
Address: 0x02, Reset: 0x06, Name: ERR_CONFIG
The error configuration register allows the user to enable or disable the relevant error features as required.
Table 13. Bit Descriptions for ERR_CONFIG
Bits
[7:3]
2
Bit Name
RESERVED
RW_ERR_EN
Settings
0
1
1
SCLK_ERR_EN
0
1
0
CRC_ERR_EN
0
1
Description
These bits are reserved; set these bits to 0.
Enable bit for detecting an invalid read/write address.
Disabled.
Enabled.
Enable bit for detecting the correct number of SCLK cycles in an SPI frame. When
CRC is disabled and burst mode is disabled, 16 SCLK cycles are expected. When
CRC is enabled and burst mode is disabled, 24 SCLK cycles are expected. A multiple
of 16 SCLK cycles is expected when CRC is disabled and burst mode is enabled. A
multiple of 24 SCLK cycles is expected when CRC is enabled and burst mode is
enabled.
Disabled.
Enabled.
Enable bit for CRC error detection. SPI frames must be 24 bits wide when enabled.
Disabled.
Enabled.
Rev. 0 | Page 27 of 29
Default
0x0
0x1
Access
R
R/W
0x1
R/W
0x0
R/W
ADGS1612
Data Sheet
ERROR FLAGS REGISTER
Address: 0x03, Reset: 0x00, Name: ERR_FLAGS
The error flags register allows the user to determine if an error occurred. To clear the error flags register, the special 16-bit SPI command,
0x6CA9, must be written to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, then
the user must include the correct CRC byte during the SPI write for the clear error flags register command to complete.
Table 14. Bit Descriptions for ERR_FLAGS
Bits
[7:3]
2
Bit Name
RESERVED
RW_ERR_FLAG
Settings
Description
These bits are reserved and are set to 0.
Error flag for invalid read/write address. The error flag asserts during an SPI read
if the target address does not exist. The error flag also asserts when the target
address of an SPI write does not exist or is read only.
No error.
Error.
Error flag for the detection of the correct number of SCLK cycles in an SPI frame.
No error.
Error.
Error flag that determines if a CRC error occurs during a register write.
No error.
Error.
0
1
1
SCLK_ERR_FLAG
0
1
0
CRC_ERR_FLAG
0
1
Default
0x0
0x0
Access
R
R
0x0
R
0x0
R
BURST ENABLE REGISTER
Address: 0x05, Reset: 0x00, Name: BURST_EN
The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI
commands without deasserting CS.
Table 15. Bit Descriptions for BURST_EN
Bits
[7:1]
0
Bit Name
RESERVED
BURST_MODE_EN
Settings
0
1
Description
These bits are reserved; set these bits to 0.
Burst mode enable bit.
Disabled.
Enabled.
Default
0x0
0x0
Access
R
R/W
SOFTWARE RESET REGISTER
Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB
This software reset register is used to perform a software reset. Consecutively write 0xA3 and 0x05 to this register, and the device registers
reset to their default states.
Table 16. Bit Descriptions for SOFT_RESETB
Bits
[7:0]
Bit Name
SOFT_RESETB
Settings
Description
To perform a software reset, consecutively write 0xA3 followed by 0x05 to this
register.
Rev. 0 | Page 28 of 29
Default
0x0
Access
R/W
Data Sheet
ADGS1612
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
1
0.50
BSC
2.70
2.60 SQ
2.50
EXPOSED
PAD
13
TOP VIEW
1.00
0.95
0.90
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
PKG-004677
0.50
0.40
0.30
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8.
02-09-2017-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 46. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.95 mm Package Height
(CP-24-17)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADGS1612BCPZ
ADGS1612BCPZ-RL7
EVAL-ADGS1612SDZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D16054-0-1/18(0)
Rev. 0 | Page 29 of 29
Package Option
CP-24-17
CP-24-17
工商网监
湘ICP备2023018690号
