30 MHz to 2200 MHz
Quadrature Modulator
ADL5385
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Output frequency range: 30 MHz to 2200 MHz
1 dB output compression: 11 dBm at 350 MHz
Noise floor: –159 dBm/Hz at 350 MHz
Sideband suppression: −50 dBc at 350 MHz
Carrier feedthrough: −46 dBm at 350 MHz
Single supply: 4.75 V to 5.5 V
24-lead, RoHS-compliant, LFCSP with exposed pad
ENBL
BIAS
IBBP
TEMPERATURE
SENSOR
TEMP
IBBN
APPLICATIONS
Radio-link infrastructure
Cable modem termination systems
UHF/VHF radio
Wireless infrastructure systems
Wireless local loop
WiMAX/broadband wireless access systems
LOIP
DIVIDE-BY-2
QUADRATURE
PHASE
SPLITTER
VOUT
LOIN
06118-001
QBBP
QBBN
Figure 1.
GENERAL DESCRIPTION
The ADL5385 is a silicon, monolithic, quadrature modulator
designed for use from 30 MHz to 2200 MHz. Its excellent phase
accuracy and amplitude balance enable both high performance
intermediate frequency (IF) and direct radio frequency (RF)
modulation for communication systems.
The ADL5385 takes the signals from two differential baseband
inputs and modulates them onto two carriers in quadrature
with each other. The two internal carriers are derived from a
single-ended, external local oscillator input signal at twice the
frequency as the desired carrier output. The two modulated
signals are summed together in a differential-to-single-ended
amplifier designed to drive 50 Ω loads.
Rev. D
The ADL5385 can be used as either an IF or a direct-to-RF
modulator in digital communication systems. The wide
baseband input bandwidth allows for either baseband drive or
drive from a complex IF. Typical applications are in radio-link
transmitters, cable modem termination systems, and broadband
wireless access systems.
The ADL5385 is fabricated using the Analog Devices, Inc.,
advanced silicon germanium bipolar process and is packaged in
a 24-lead, RoHS-compliant LFCSP with exposed pad. Performance
is specified over –40°C to +85°C. A RoHS-compliant evaluation
board is also available.
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Tel: 781.329.4700 ©2006–2016 Analog Devices, Inc. All rights reserved.
Technical Support
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ADL5385
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Baseband Inputs ......................................................................... 15
Applications ....................................................................................... 1
LO Input ...................................................................................... 15
Functional Block Diagram .............................................................. 1
RF Output .................................................................................... 15
General Description ......................................................................... 1
Optimization ............................................................................... 16
Revision History ............................................................................... 2
Applications Information .............................................................. 17
Specifications..................................................................................... 3
DAC Modulator Interfacing ..................................................... 17
Absolute Maximum Ratings............................................................ 7
155 Mbps (STM-1) 128 QAM Transmitter ............................. 18
ESD Caution .................................................................................. 7
CMTS Transmitter Application................................................ 18
Pin Configuration and Function Descriptions ............................. 8
Spectral Products from Harmonic Mixing ............................. 19
Typical Performance Characteristics ............................................. 9
RF Second-Order Products ....................................................... 19
Circuit Description ......................................................................... 14
LO Generation Using PLLs ....................................................... 20
Overview...................................................................................... 14
Transmit DAC Options ............................................................. 20
LO Interface................................................................................. 14
Modulator/Demodulator Options ........................................... 20
V-to-I Converter ......................................................................... 14
Evaluation Board ............................................................................ 21
Mixers .......................................................................................... 14
Characterization Setup .................................................................. 23
D-to-S Amplifier......................................................................... 14
SSB Setup ..................................................................................... 23
Bias Circuit .................................................................................. 14
Outline Dimensions ....................................................................... 24
Basic Connections .......................................................................... 15
Ordering Guide .......................................................................... 24
Power Supply and Grounding ................................................... 15
REVISION HISTORY
12/2016—Rev. C to Rev. D
Changes to Evaluation Board Section .......................................... 21
Deleted Figure 46 and Table 9; Renumbered Sequentially ....... 23
Deleted Figure 47 ............................................................................ 24
Changes to Ordering Guide .......................................................... 24
3/2016—Rev. B to Rev. C
Changes to Figure 2 .......................................................................... 8
Changes to Figure 29 ...................................................................... 15
Changes to LO Generation Using PLLs Section and Table 7.... 20
Changes to Figure 43 ...................................................................... 21
Changes to Figure 46 ...................................................................... 23
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
12/2014—Rev. A to Rev. B
Changes to Output Voltage Parameter, Test Conditions/Comments
Column, Table 1 ................................................................................ 6
Changes to D-to-S Amplifier Section .......................................... 14
Changes to Evaluation Board Section, Figure 43, and Table 8 ........ 21
Changes to Figure 44 ...................................................................... 22
Added Figure 45; Renumbered Sequentially .............................. 22
Added Figure 46 and Table 9......................................................... 23
Added Figure 47 ............................................................................. 24
Changes to Ordering Guide .......................................................... 26
10/2012—Rev. 0 to Rev. A
Added 30 MHz Output Frequency ............................. Throughout
Changes to Applications Section .....................................................1
Changes to Table 1.............................................................................3
Added EPAD Notation to Figure 2 and Table 3 ............................8
Added Figure 8; Renumbered Sequentially ...................................9
Added Figure 9................................................................................ 10
Changes to Figure 17...................................................................... 11
Changes to Figure 21...................................................................... 12
Changes to LO Input Section and RF Output Section .............. 15
Changes to LO Generation Using PLLs Section and Transmit
DAC Options Section .................................................................... 20
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
10/2006—Revision 0: Initial Version
Rev. D | Page 2 of 24
Data Sheet
ADL5385
SPECIFICATIONS
Unless otherwise noted, VS = 5 V; TA = 25°C; LO = −7 dBm; I/Q inputs = 1.4 V p-p differential sine waves in quadrature on a 500 mV dc
bias; baseband frequency = 1 MHz; LO source and RF output load impedances are 50 Ω.
Table 1.
Parameter
OUTPUT FREQUENCY RANGE
EXTERNAL LO FREQUENCY RANGE
OUTPUT FREQUENCY = 30 MHz
(LO = 0 dBm)
Output Power
Output P1dB
Carrier Feedthrough
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
Output Return Loss
OUTPUT FREQUENCY = 50 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
Test Conditions/Comments
External LO frequency 2× output frequency
Min
30
60
Single (lower) sideband output
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
Unadjusted (nominal drive level)
@ +85°C after optimization at +25°C
@ −40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO + (3 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Output Return Loss
Rev. D | Page 3 of 24
Max
2200
4400
4.7
11
−57
−68
−65
−51
−59
−60
−88
−57
76
24
0.43
0.015
−155
−150
−20
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO − (2 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
Single (lower) sideband output
Typ
4
5.6
11
−57
−67
−67
−57
−64
−68
−83
−58
69
26
−0.17
−0.03
−155
−150
−19
Unit
MHz
MHz
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
Degrees
dB
dBm/Hz
dBm/Hz
dB
8
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
Degrees
dB
dBm/Hz
dBm/Hz
dB
ADL5385
Parameter
OUTPUT FREQUENCY = 140 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
Output Return Loss
OUTPUT FREQUENCY = 350 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
Output Return Loss
OUTPUT FREQUENCY = 860 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
Quadrature Phase Error
I/Q Amplitude Balance
Data Sheet
Test Conditions/Comments
Min
Single (lower) sideband output
20 MHz offset from LO, all BB inputs at a bias of 500 mV
Rev. D | Page 4 of 24
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
Degrees
dB
dBm/Hz
dB
5.6
11
−46
−65
−66
−50
−63
−61
−80
−53
71
26
0.39
−0.03
−159
−157
−21
7
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
Degrees
dB
dBm/Hz
dBm/Hz
dB
2.5
5.3
11
−41
−63
−65
−41
−58
−59
−73
−50
70
25
0.67
−0.03
6.5
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
Degrees
dB
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO + (3 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
Unit
3
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at+25°C
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO + (3 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
Single (lower) sideband output
Max
5.7
11
−52
−66
−67
−53
−63
−68
−83
−57
70
26
−0.33
−0.03
−160
−20
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 5 dBm
(fLO + (3 × fBB)), POUT = 5 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT =−3 dBm per tone
Single (lower) sideband output
Typ
−35
−35
−57
−45
Data Sheet
Parameter
Noise Floor
Output Return Loss
OUTPUT FREQUENCY = 1450 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
Output Return Loss
OUTPUT FREQUENCY = 1900 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
Quadrature Phase Error
I/Q Amplitude Balance
Noise Floor
Output Return Loss
OUTPUT FREQUENCY = 2150 MHz
Output Power
Output P1 dB
Carrier Feedthrough
Sideband Suppression
Second Baseband Harmonic
Third Baseband Harmonic
Output IP2
Output IP3
Quadrature Phase Error
I/Q Amplitude Balance
ADL5385
Test Conditions/Comments
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Single (lower) sideband output
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 4 dBm
(fLO + (3 × fBB)), POUT = 4 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
20 MHz offset from LO, all BB inputs at a bias of 500 mV
Single (lower) sideband output
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
(fLO − (2 × fBB)), POUT = 3 dBm
(fLO + (3 × fBB)), POUT = 3 dBm
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT = −3 dBm per tone
F1 = +3.5 MHz, F2 = +4.5 MHz, POUT = −3 dBm per tone
20 MHz offset from LO, all BB inputs at a bias of 500 mV
20 MHz offset from LO, output power = −5 dBm
Single (lower) sideband output
Unadjusted (nominal drive level)
+85°C after optimization at +25°C
−40°C after optimization at +25°C
Unadjusted (nominal drive level)
(fLO − (2 × fBB)), POUT = 2.6 dBm
(fLO + (3 × fBB)), POUT = 2.6 dBm
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
F1 = 3.5 MHz, F2 = 4.5 MHz, POUT = −3 dBm per tone
Rev. D | Page 5 of 24
Min
Typ
−159
−157
−19
Max
Unit
dBm/Hz
dBm/Hz
dB
4.4
10
−36
−50
−50
−44
−61
−51
−64
−52
63
24
0.42
−0.02
−160
−33
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
Degrees
dB
dBm/Hz
dB
3.4
9
−35
−51
−51
−33
−43
−47
−58
−47
57
22
2.6
0.003
−160
−156
−20
dBm
dBm
dBm
dBm
dBm
dBc
dBc
dBc
dBc
dBc
dBm
dBm
Degrees
dB
dBm/Hz
dBm/Hz
dB
2.6
8
−36
−47
−48
−37
−56
−45
54
21
1.5
500
mV
µA
MHz
MHz
1.0
1.4
µs
µs
V
V
1.5
0.4
TEMP
TA = 27.15°C, 300.3 K, RL = 1 MΩ (after full warm up)
−40°C ≤ TA ≤ +85°C, RL = 1 MΩ
1.56
4.6
1.0
V
mV/°C
kΩ
Pin VPS1 and Pin VPS2
4.75
ENBL = high
ENBL = low
215
80
Rev. D | Page 6 of 24
5.5
240
V
mA
µA
Data Sheet
ADL5385
ABSOLUTE MAXIMUM RATINGS
ESD CAUTION
Table 2.
Parameter
Supply Voltage VPOS
IBBP, IBBN, QBBP, QBBN Range
LOIP and LOIN
Internal Power Dissipation
θJA (Exposed Pad Soldered Down)
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
5.5 V
0 V to 2.0 V
13 dBm
1.375 W
58°C/W
164°C
−40°C to +85°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. D | Page 7 of 24
ADL5385
Data Sheet
NC 1
18 QBBP
NC 2
17 QBBN
NC 3
COM1 4
ADL5385
16 COM2
TOP VIEW
(Not to Scale)
15 COM2
ENBL 12
VPS2 11
TEMP 10
VPS1 9
VPS1 8
14 IBBN
13 IBBP
VOUT 7
COM1 5
COM1 6
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. EXPOSED PAD. SOLDER THE EXPOSED PAD TO A
LOW IMPEDANCE GROUND PLANE.
06118-002
20 COM3
19 COM3
21 LOIP
22 LOIN
23 VPS3
24 VPS3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 2, 3
4, 5, 6, 15,
16, 19, 20
7
8, 9, 11, 23,
24
10
12
13, 14,
17, 18
Mnemonic
NC
COM1, COM2,
COM3
VOUT
VPS1, VPS2,
VPS3
TEMP
ENBL
IBBP, IBBN,
QBBN, QBBP
21
LOIP
22
LOIN
EPAD
Description
No Connect. Leave these pins open or tie them to ground.
Power Supply Common Pins. Connect COM1, COM2, and COM3 to a ground plane via a low impedance path.
Device Output. Single-ended, 50 Ω internally biased RF/IF output; pin must be ac-coupled to the load.
Power Supply Pins. Decouple each pin with a 0.1 μF capacitor; Pin 8 and Pin 9 can share a single capacitor,
as can Pin 23 and Pin 24. Connect all pins to the same supply.
Temperature Sensor Output. Provides dc voltage proportional to die temperature. Slope is 4.6 mV/°C
Device Enable. Shuts device down when grounded and enables device when pulled to supply voltage.
Differential In-Phase and Quadrature Baseband Inputs. These high impedance inputs must be externally dcbiased to 500 mV dc and driven from a low impedance source. Nominal characterized ac signal swing is 700 mV
p-p on each pin (150 mV to 850 mV). This results in a differential drive of 1.4 V p-p with a 500 mV dc bias.
Single-Ended Two-Times Local Oscillator Input. This input is internally biased and must be ac-coupled to
the LO source.
Common for LO Input. Must be ac-coupled to ground through a low impedance path.
Exposed Pad. Solder the exposed pad to a low impedance ground plane.
Rev. D | Page 8 of 24
Data Sheet
ADL5385
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, VS = 5 V; TA = 25°C; LO = −7 dBm; I/Q inputs = 1.4 V p-p differential sine waves in quadrature on a 500 mV dc bias;
baseband frequency = 1 MHz; LO source and RF output load impedances are 50 Ω.
8
6
12
5
4
3
2
1
0
10
9
8
7
6
550
1050
1550
4
06118-003
–4
50
2050
OUTPUT FREQUENCY (MHz)
1050
1550
2050
Figure 6. Output 1 dB Compression Point (OP1dB) vs. Output Frequency
and Power Supply
14
TA = –40°C
TA = +25°C
TA = +85°C
7
550
OUTPUT FREQUENCY (MHz)
Figure 3. Single Sideband (SSB) Output Power (POUT) vs. Output Frequency
and Power Supply
8
50
06118-006
5
–3
TA = –40°C
TA = +25°C
TA = +85°C
12
6
OUTPUT P1dB (dBm)
5
4
3
2
1
8
6
4
1050
1550
2050
OUTPUT FREQUENCY (MHz)
0
50
1.5
–30
SECOND-ORDER DISTORTION,
CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION (dB)
–20
1.0
0.5
0
–0.5
–1.0
–1.5
2050
5.5
CARRIER FEEDTHROUGH (dBm)
4.5
SIDEBAND SUPPRESSION (dBc)
4.0
–50
3.5
–60
THIRD-ORDER DISTORTION (dBc)
–70
3.0
–80 SECOND-ORDER DISTORION (dBc)
2.5
30
40
50
60
70
80
90
100
110
OUTPUT FREQUENCY (MHz)
Figure 5. Baseband Frequency Response Normalized to Response for 1 MHz
BB Signal; Carrier Frequency = 500 MHz
5.0
SSB OUTPUT POWER (dBm)
–40
–90
06118-005
BASEBAND FREQUENCY (Hz)
1G
1550
Figure 7. Output 1 dB Compression Point (OP1dB) vs. Output Frequency
and Temperature
2.0
100M
1050
OUTPUT FREQUENCY (MHz)
Figure 4. Single Sideband (SSB) Output Power (POUT) vs. Output Frequency
and Temperature
–2.0
10M
550
120
130
2.0
140
SSB OUTPUT POWER (dBm)
550
06118-007
2
06118-004
0
50
10
06118-108
SSB OUTPUT POWER (dBm)
11
–1
–2
OUTPUT POWER VARIANCE (dB)
VS = 5.5V
VS = 5.V
VS = 4.75V
13
OUTPUT P1dB (dBm)
SSB OUTPUT POWER (dBm)
14
VS = 5.5V
VS = 5.V
VS = 4.75V
7
Figure 8. SSB Output Power, Second- and Third-Order Distortion,
Carrier Feedthrough, and Sideband Suppression vs. Output Frequency;
LO Amplitude = 0 dBm
Rev. D | Page 9 of 24
ADL5385
Data Sheet
0
10
–10
–10
CARRIER FEEDTHROUGH (dBm)
–50
–20
–60
THIRD-ORDER DISTORTION (dBc)
–70
SECOND-ORDER DISTORION (dBc)
–80
–90
–10
–8
–6
–4
–2
0
2
4
–30
–40
–20
–30
–40
–50
–60
–70
–50
–80
–60
–90
LO AMPLITUDE (dBm)
1550
2050
–25
0
–60
–5
SIDEBAND SUPPRESSION (dBc)
–50
OUTPUT AMPLITUDE (dBm)
5
–10
–70
–30
–35
–40
–45
–50
–55
–60
1.0
1.4
1.8
2.2
2.6
3.0
–15
3.4
BASEBAND AMPLITUDE (V p-p)
–70
1M
0.7100
15
SSB OUTPUT POWER (dBm)
CARRIER FEEDTHROUGH (dBm)
SIDEBAND SUPPRESSION (dBc)
–30 SECOND-ORDER DISTORTION (dBc)
THIRD-ORDER DISTORTION (dBc)
0.7075
–50
0
–60
–5
–70
–10
0.7050
AMPLITUDE (V)
5
OUTPUT AMPLITUDE (dBm)
10
–40
100M
Figure 13. Sideband Suppression vs. Baseband Frequency;
Output Frequency = 350 MHz
Figure 10. SSB Output Power, Second- and Third-Order Distortion,
Carrier Feedthrough and Sideband Suppression vs. Differential
Baseband Input Level; Output Frequency = 350 MHz
–20
10M
BASEBAND FREQUENCY (Hz)
06118-011
–65
0.6
06118-008
0.7025
0.7000
0.6975
0.6950
0.6
1.0
1.4
1.8
2.2
2.6
3.0
–15
3.4
BASEBAND AMPLITUDE (V p-p)
Figure 11. SSB Output Power, Second- and Third-Order Distortion,
Carrier Feedthrough and Sideband Suppression vs. Baseband SingleEnded Input Level; Output Frequency = 860 MHz
06118-009
0.6925
–80
0.2
0.6900
50
250
450
650
850
1050 1250 1450 1650 1850
OUTPUT FREQUENCY (MHz)
06118-012
SECOND-ORDER DISTORTION, THIRD-ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
1050
–20
10
–40
–80
0.2
SECOND-ORDER DISTORTION, THIRD-ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION
550
Figure 12. Sideband Suppression vs. Output Frequency and
Temperature
15
SSB OUTPUT POWER (dBm)
CARRIER FEEDTHROUGH (dBm)
SIDEBAND SUPPRESSION (dBc)
–30 SECOND-ORDER DISTORTION (dBc)
THIRD-ORDER DISTORTION (dBc)
50
OUTPUT FREQUENCY (MHz)
Figure 9. SSB Output Power, Second- and Third-Order Distortion,
Carrier Feedthrough, and Sideband Suppression vs. LO Amplitude;
Output Frequency = 30 MHz
–20
TA = –40°C
TA = +25°C
TA = +85°C
06118-010
0
SSB OUTPUT POWER (dBm)
–40
SIDEBAND SUPPRESSION (dBc)
–30
20
SSB OUTPUT POWER (dBm)
SIDEBAND SUPPRESSION (dBc)
06118-109
SECOND-ORDER DISTORTION,THIRD-ORDER
DISTORTION, CARRIER FEEDTHROUGH,
SIDEBAND SUPPRESSION (dBm)
–20
Figure 14. Distribution of Peak Q Amplitude to Null Undesired Sideband
(Peak I Amplitude Held Constant at 0.7 V)
Rev. D | Page 10 of 24
Data Sheet
ADL5385
–20
98
TA = –40°C
TA = +25°C
TA = +85°C
97
95
PHASE (Degrees)
–30
CARRIER FEEDTHROUGH (dBm)
96
94
93
92
91
90
–40
–50
–60
–70
250
450
650
850
1050 1250 1450 1650 1850
OUTPUT FREQUENCY (MHz)
Figure 15. Distribution of IQ Phase to Null Undesired Sideband
1550
2050
Figure 18. Distribution Carrier Feedthrough vs. Output Frequency and
Temperature
TA = –40°C
TA = +25°C
TA = +85°C
CARRIER FEEDTHROUGH (dBm)
–10
–20
–30
–40
–50
–60
–70
–20
–30
–40
–50
–60
–70
450
650
850
1050 1250 1450 1650 1850
OUTPUT FREQUENCY (MHz)
–90
50
06118-014
250
Figure 16. Sideband Suppression Distribution at Temperature Extremes,
After Sideband Suppression Nulled to < −50 dBc at TA = +25°C
1050
1550
2050
OUTPUT FREQUENCY (MHz)
Figure 19. Carrier Feedthrough Distribution at Temperature Extremes,
After Nulling to < −65 dBm at TA = +25°C
–20
0.010
30MHz
50MHz
350MHz
–30
550
06118-017
–80
–80
0.008
Q OFFSET
0.006
–40
0.004
OFFSET (V)
SIDEBAND SUPPRESSION (dBc)
1050
OUTPUT FREQUENCY (MHz)
TA = –40°C
TA = +25°C
TA = +85°C
–10
–90
50
550
0
0
SIDEBAND SUPRESSION (dBc)
–80
50
06118-013
88
50
06118-016
89
–50
–60
–70
0.002
0
I OFFSET
–0.002
–0.004
–0.006
–80
–6
–4
–2
0
LO AMPLITUDE (dBm)
2
4
Figure 17. Distribution of Sideband Suppression vs. LO Input Power at
30 MHz, 50 MHz, and 350 MHz Output Frequencies
–0.010
50
550
1050
1550
2050
OUTPUT FREQUENCY (MHz)
Figure 20. Distribution of I and Q Offset Required to Null Carrier
Feedthrough
Rev. D | Page 11 of 24
06118-018
–8
06118-015
–0.008
–90
–10
ADL5385
Data Sheet
–20
–30
18
16
–40
14
NUMBER OF PARTS
–50
–60
–70
12
10
8
6
4
–80
–8
–6
–4
–2
0
2
4
LO AMPLITUDE (dBm)
0
06118-019
–90
–10
2
dBm/Hz AT 20MHz OFFSET FROM LO FREQUENCY
Figure 21. Distribution Carrier Feedthrough vs. LO Input Power at
30 MHz, 50 MHz, and 350 MHz Output Frequencies
80
Figure 23. 20 MHz Offset Noise Floor Distribution,
Output Frequency = 350 MHz, POUT = −5 dBm, QPSK Carrier,
Symbol Rate = 3.84 MSPS
20
TA = –40°C
TA = +25°C
TA = +85°C
OIP2
70
–156.7 –156.6 –156.5 –156.4 –156.3 –156.2 –156.1 –156.0 –155.9
06118-021
CARRIER FEEDTHROUGH (dBm)
20
30MHz
50MHz
350MHz
18
16
50
40
OIP3
30
14
NUMBER OF PARTS
12
10
8
6
20
4
10
0
550
1050
1550
2050
OUTPUT FREQUENCY (MHz)
Figure 22. OIP3 and OIP2 vs. Output Frequency and Temperature
06118-020
0
50
2
–155.2 –155.1 –155.0 –154.9 –154.8 –154.7 –154.6 –154.5 –154.4
dBm/Hz AT 12MHz OFFSET FROM LO FREQUENCY
Figure 24. 12 MHz Offset Noise Floor Distribution,
Output Frequency = 860 MHz, POUT = −5 dBm, 64 QAM Carrier,
Symbol Rate = 5 MSPS
Rev. D | Page 12 of 24
06118-022
OIP2 AND OIP3 (dBm)
60
Data Sheet
ADL5385
0
0.300
0.275
SUPPLY CURRENT (A)
–10
–15
–20
0.250
0.225
0.200
530
960
1390 1820 2250 2680 3110 3540 3970 4400
LOIP FREQUENCY (MHz)
06118-023
0.175
Figure 25. LO Port Input Return Loss vs. Frequency
0.150
S11 OF LOIP
4400MHz
30
S22 OF OUTPUT
2200MHz
180
0
50MHz
100MHz
330
210
240
06118-024
300
270
85
Figure 27. Power Supply Current vs. Temperature and Supply Voltage
60
150
25
TEMPERATURE (°C)
90
120
–40
06118-025
RETURN LOSS (dB)
–5
–25
100
VS = 5.5V
VS = 5V
VS = 4.75V
Figure 26. Output Impedance and LO Input Impedance vs. Frequency
Rev. D | Page 13 of 24
ADL5385
Data Sheet
CIRCUIT DESCRIPTION
OVERVIEW
LO INTERFACE
The ADL5385 can be divided into five sections: the local
oscillator (LO) interface, the baseband voltage-to-current (V-to-I)
converter, the mixers, the differential-to-single-ended (D-to-S)
amplifier, and the bias circuit. A detailed block diagram of the
device is shown in Figure 28.
The LO interface consists of a buffer amplifier followed by a
pair of frequency dividers that generate two carriers at half the
input frequency and in quadrature with each other. Each carrier
is then amplified and amplitude-limited to drive the doublebalanced mixers.
V-TO-I CONVERTER
ENBL
BIAS
IBBP
TEMPERATURE
SENSOR
The differential baseband input voltages that are applied to the
baseband input pins are fed to a pair of common-emitter,
voltage-to-current converters. The output currents then
modulate the two half-frequency LO carriers in the mixer stage.
TEMP
MIXERS
IBBN
The ADL5385 has two double-balanced mixers: one for the inphase channel (I channel) and one for the quadrature channel
(Q channel). These mixers are based on the Gilbert cell design
of four cross-connected transistors. The output currents from
the two mixers are summed together in the resistor-inductor
(RL) loads in the D-to-S amplifier.
LOIP
DIVIDE-BY-2
QUADRATURE
PHASE
SPLITTER
VOUT
LOIN
D-TO-S AMPLIFIER
06118-001
QBBP
QBBN
Figure 28. ADL5385 Block Diagram
The LO interface generates two LO signals at 90° of phase
difference to drive two mixers in quadrature. Baseband signals
are converted into currents by the V-to-I converters that feed
into the two mixers. The outputs of the mixers are combined in
the differential-to-single-ended amplifier, which provides a 50 Ω
output interface. Reference currents to each section are
generated by the bias circuit. A detailed description of each
section follows.
The output D-to-S amplifier consists of two emitter followers
driving a totem-pole output stage that converts the differential
signal to a single-ended signal. Output impedance is established
by the emitter resistors in the output transistors. The output of
this stage connects to the output (VOUT) pin.
BIAS CIRCUIT
A band gap reference circuit generates the proportional-toabsolute-temperature (PTAT) as well as temperature-independent reference currents used by different sections. The band-gap
circuit is turned on by a logic high at the ENBL pin, which in
turn powers up the whole device. A PTAT voltage output is
available at the TEMP pin, which can be used for temperature
monitoring as well as for temperature compensation purposes.
Rev. D | Page 14 of 24
Data Sheet
ADL5385
BASIC CONNECTIONS
Figure 29 shows the basic connections for the ADL5385.
LO INPUT
POWER SUPPLY AND GROUNDING
A single-ended LO signal is applied to the LOIP pin through
an ac coupling capacitor. The LO return pin, LOIN, must be
ac-coupled to ground though a low impedance path.
All the VPS pins must be connected to the same 5 V source.
Adjacent pins of the same name can be tied together and decoupled
with a 0.1 µF capacitor. Locate these capacitors as close as possible
to the device. The power supply can range from 4.75 V to 5.5 V.
The LO input can be driven differentially, in which case the user
ac couples both sides of the differential LO source through a pair of
series capacitors to the LOIP and LOIN pins. The nominal LO
drive of −7 dBm, which is recommended, can be increased to up
to 5 dBm. For operation below 50 MHz, it is recommended to
use a minimum LO drive level of 0 dBm. The effect of LO power
on sideband suppression and carrier feedthrough is shown in
Figure 17 and Figure 21. The performance vs. LO power at
30 MHz output frequency is shown at Figure 9.
The COM1 pin, COM2 pin, and COM3 pin are tied to the same
ground plane through low impedance paths. The exposed pad
on the underside of the package is also soldered to a low thermal
and electrical impedance ground plane. If the ground plane spans
multiple layers on the circuit board, stitch the layers together
with nine vias under the exposed pad. The Analog Devices
AN-722 Application Note discusses the thermal and electrical
grounding of the LFCSP in greater detail.
RF OUTPUT
BASEBAND INPUTS
The RF output is available at the VOUT pin (Pin 7). This pin
must also be ac-coupled. Below 150 MHz, output power decreases
due to internal ac-coupling. This is shown in Figure 8. The
VOUT pin has a nominal broadband impedance of 50 Ω and
does not need further external matching.
The baseband inputs QBBP, QBBN, IBBP, and IBBN must be
driven from a differential source. The nominal drive level of
1.4 V p-p differential (700 mV p-p on each pin) is biased to a
common-mode level of 500 mV dc.
The dc common-mode bias level for the baseband inputs can
range from 400 mV to 600 mV. This results in a reduction in
the usable input ac swing range. The nominal dc bias of 500 mV
allows for the largest ac swing, limited on the bottom end by the
ADL5385 input range and on the top end by the output
compliance range on most Analog Devices DACs.
QBBP
CFPQ
OPEN
IBBN
QBBN
RFPQ
0Ω
RFNQ
0Ω
CFNQ
OPEN
RTQ
OPEN
CFNI
OPEN
IBBP
RFNI
0Ω
RFPI
0Ω
RTI
OPEN
CFPI
OPEN
CLOP
0.1µF
LO
IBBP 13
IBBN 14
COM2 15
COM2 16
QBBN 17
QBBP 18
R21
49.9Ω
ENB
ENBL 12
20 COM3
VPS2 11
21 LOIP
TEMP 10
ENBL
CLON
0.1µF
C16
0.1µF
23 VPS3
C14
0.1µF
C13
OPEN
VOUT 7
6 COM1
5 COM1
4 COM1
3 NC
2 NC
1 NC
VOUT
COUT
0.1µF
06118-041
VPOS
C12
0.1µF
VPOS
VPS1 8
24 VPS3
C11
OPEN
TEMP
R12
0Ω
EXPOSED PADDLE
R11
0Ω
RTEMP
200Ω
VPS1 9
4 × 4 LFCSP
R22
10kΩ
VPOS
C15
OPEN
R13
0Ω
ADL5385
U1
ON
SW21
19 COM3
22 LOIN
OFF
GND
Figure 29. Basic Connections for the ADL5385
Rev. D | Page 15 of 24
ADL5385
Data Sheet
OPTIMIZATION
The carrier feedthrough and sideband suppression performance
of the ADL5385 can be improved through the use of optimization
techniques.
It is often desirable to perform a one-time carrier null calibration.
This is usually performed at a single frequency. Figure 31 shows
how carrier feedthrough varies with LO frequency over a range
of ±50 MHz on either side of a null at 350 MHz.
–25
Carrier Feedthrough Nulling
–58
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
300
310
320
330
340
350
360
370
380
390
400
OUTPUT FREQUENCY (MHz)
Figure 31. Carrier Feedthrough vs. Frequency After Nulling at 350 MHz
Sideband Suppression Optimization
Sideband suppression results from relative gain and relative phase
offsets between the I and Q channels and can be suppressed
through adjustments to those two parameters. Figure 32 illustrates
how sideband suppression is affected by the gain and phase
imbalances.
0
–66
–70
–74
–78
–82
–86
The same applies to the Q channel.
–70
0dB
0.1
1
10
100
PHASE ERROR (Degrees)
Note that throughout the nulling process, the dc bias for the
baseband inputs remains at 500 mV. When no offset is applied,
VIOPP = 500 mV + VIOS/2, while
VIOPN = 500 mV − VIOS/2, such that
VIOPP − VIOPN = VIOS
–50 0.05dB
0.025dB
–60 0.0125dB
06118-028
360
Figure 30. Carrier Feedthrough vs. DC Offset Voltage at 450 MHz
When an offset of +VIOS is applied to the I-channel inputs,
–30 0.5dB
0.25dB
–40 0.125dB
–90
0.01
VP-VN OFFEST (µV)
VIOPP = VIOPN = 500 mV, or
VIOPP − VIOPN = VIOS = 0 V
2.5dB
–20 1.25dB
–80
420
300
240
180
120
0
60
–120
–180
–240
–300
–420
–360
–94
–60
–90
SIDEBAND SUPRESSION (dBc)
–10
06118-029
CARRIER FEEDTHROUGH (dBm)
–62
–35
06118-027
Carrier feedthrough results from minute dc offsets that occur
between each of the differential baseband inputs. In an ideal
modulator, the quantities (VIOPP − VIOPN) and (VQOPP − VQOPN)
are equal to zero, and this results in no carrier feedthrough. In a
real modulator, those two quantities are nonzero and, when mixed
with the LO, result in a finite amount of carrier feedthrough. The
ADL5385 is designed to provide a minimal amount of carrier
feedthrough. If even lower carrier feedthrough levels are required,
minor adjustments can be made to the (VIOPP − VIOPN) and (VQOPP −
VQOPN) offsets. The I-channel offset is held constant while the
Q-channel offset is varied until a minimum carrier feedthrough
level is obtained. The Q-channel offset required to achieve this
minimum is held constant while the offset on the I-channel is
adjusted, until a better minimum is reached. Through two
iterations of this process, the carrier feedthrough can be reduced to
as low as the output noise. The ability to null is sometimes limited
by the resolution of the offset adjustment. Figure 30 shows the
relationship of carrier feedthrough vs. dc offset.
CARRIER FEEDTHROUGH (dBm)
–30
Figure 32. Sideband Suppression vs. Quadrature Phase Error for Various
Quadrature Amplitude Offsets
Figure 32 underscores the fact that adjusting one parameter
improves the sideband suppression only to a point; the other
parameter must also be adjusted. For example, if the amplitude
offset is 0.25 dB, improving the phase imbalance better than 1°
does not yield any improvement in the sideband suppression. For
optimum sideband suppression, an iterative adjustment
between phase and amplitude is required.
The sideband suppression nulling can be performed either through
adjusting the gain for each channel or through the modification
of the phase and gain of the digital data coming from the digital
signal processor.
Rev. D | Page 16 of 24
Data Sheet
ADL5385
APPLICATIONS INFORMATION
AD9777
The ADL5385 is designed to interface with minimal components
to members of the Analog Devices family of digital-to-analog
converters (DAC). These DACs feature an output current swing
from 0 mA to 20 mA, and the interface described in this section
can be used with any DAC that has a similar output.
IOUTA1
AD9777
IOUTA1
IOUTB1
IOUTB1
13
IBBP
RBIP
50Ω
72
RBIN
50Ω
14
IOUTB2
IOUTA2
72
IBBP
RSLI
100Ω
RBIN
50Ω
14
69
17
RBQN
50Ω
RBQP
68
50Ω
IBBN
QBBN
RSLQ
100Ω
18
QBBP
Figure 34. AC Voltage Swing Reduction Through Introduction of Shunt
Resistor Between Differential Pair
The value of this ac voltage swing limiting resistor is chosen
based on the desired ac voltage swing. Figure 35 shows the
relationship between the swing-limiting resistor and the peakto-peak ac swing that it produces when 50 Ω bias setting
resistors are used.
ADL5385
73
13
RBIP
50Ω
Driving the ADL5385 with an Analog Devices TxDAC®
An example of the interface using the AD9777 TxDAC is shown
in Figure 33. The baseband inputs of the ADL5385 require a dc
bias of 500 mV. The average output current on each of the outputs
of the AD9777 is 10 mA. Therefore, a single 50 Ω resistor to
ground from each of the DAC outputs results in an average current
of 10 mA flowing through each of the resistors, thus producing
the desired 500 mV dc bias for the inputs to the ADL5385.
ADL5385
73
06118-032
DAC MODULATOR INTERFACING
2.0
IBBN
RBQN
50Ω
RBQP
50Ω
68
17
18
QBBN
QBBP
Figure 33. Interface Between AD9777 and ADL5385 with 50 Ω Resistors to
Ground to Establish the 500 mV DC Bias for the ADL5385 Baseband Inputs
The AD9777 output currents have a swing that ranges from
0 mA to 20 mA. With the 50 Ω resistors in place, the ac voltage
swing going into the ADL5385 baseband inputs ranges from
0 V to 1 V. A full-scale sine wave out of the AD9777 can be
described as a 1 V p-p single-ended (or 2 V p-p differential)
sine wave with a 500 mV dc bias.
1.6
1.4
1.2
1.0
0.8
0.6
0.4
06118-031
IOUTA2
69
06118-030
IOUTB2
DIFFERENTIAL SWING (V p-p)
1.8
0.2
0
10
100
1000
10000
RL (Ω)
Figure 35. Relationship Between AC Swing Limiting Resistor and
Peak-to-Peak Voltage Swing with 50 Ω Bias Setting Resistors
Filtering
Limiting the AC Swing
There are situations in which it is desirable to reduce the
ac voltage swing for a given DAC output current. This can
be achieved through the addition of another resistor to the
interface. This resistor is placed in shunt between each side of
the differential pair, as illustrated in Figure 34. It has the effect
of reducing the ac swing without changing the dc bias already
established by the 50 Ω resistors.
When driving a modulator from a DAC, it is necessary to
introduce a low-pass filter between the DAC and the modulator
to reduce the DAC images. The interface for setting up the
biasing and ac swing lends itself well to the introduction of such
a filter. The filter can be inserted in between the dc bias setting
resistors and the ac swing-limiting resistor, thus establishing the
input and output impedances for the filter.
Examples of filters are discussed in the 155 Mbps (STM-1) 128
QAM Transmitter section and the CMTS Transmitter
Application section.
Rev. D | Page 17 of 24
ADL5385
Data Sheet
Using AD9777 Auxiliary DAC for Carrier Feedthrough
Nulling
79
0.7
SNR
77
0.6
SNR (dB)
75
0.5
EVM WITHOUT EQUALIZATION
73
71
0.3
155 Mbps (STM-1) 128 QAM TRANSMITTER
–8
317.4nH
67.5pF
–110
–120
–130
–140
–150
–160
440
450
460
470
480
490
317.4nH
372.5nH
372.5nH
156.9pF
317.4nH
67.5pF
67.5pF
500
510
520
530
540
Figure 38. Spectrum of 4-Carrier 256 QAM CMTS Signal at 485 MHz
156.9pF
67.5pF
50Ω LINE
50Ω
0
–90
100Ω LINE
0Ω
124.7pF
100Ω LINE
IBBP
200Ω
0Ω
IBBN
124.7pF
372.5nH
156.9pF
317.4nH
372.5nH
156.9pF
100Ω LINE
0Ω
124.7pF
100Ω LINE
QBBP
200Ω
0Ω
QBBN
124.7pF
Figure 39. Recommended DAC-Modulator Interconnect for128 QAM Transmitter
Rev. D | Page 18 of 24
06118-046
AD9777
50Ω
0
–100
ADL5385
1/2
–2
FREQUENCY (MHz)
FREQUENCY (MHz)
50Ω LINE
–4
–80
–170
430
Figure 36. Spectral Plot of 128 QAM Transmitter at −6.3 dBm Output Power
Q
CHANNEL
–6
06118-043
POWER SPECTRAL DENSITY (dBm/Hz)
–140
06118-044
POWER SPECTRAL DENSITY (dBm/Hz)
–130
50Ω
–10
–70
–120
50Ω LINE
–12
The same DAC and DAC-to-modulator interface and filtering
circuit shown in Figure 39 was used in this application. Figure 38
shows a plot of a 4-carrier 256 QAM spectrum at an output
frequency of 485 MHz.
–110
AD9777
–14
Because of its broadband operating range from 30 MHz to
2200 MHz, the ADL5385 can be used in direct-launch cable
modem termination systems (CMTS) applications in the
50 MHz to 860 MHz cable band.
–100
50Ω LINE
–16
CMTS TRANSMITTER APPLICATION
–90
50Ω
0.1
CARRIER POWER (dBm)
–80
1/2
67
Figure 37. EVM and SNR vs. Output Power for 128 QAM Transmitter
Application
–70
–160
290 300 310 320 330 340 350 360 370 380 390 400 410 420
0.2
65
–18
Figure 36 shows a spectral plot of the 128 QAM spectrum at
a carrier power of −6.3 dBm. Figure 37 shows how EVM
(measured with the analyzer’s internal equalizer both on and
off) and SNR, measured at 55 MHz carrier offset (2.5 times the
carrier bandwidth) varies with output power.
–150
69
06118-042
EVM WITH EQUALIZATION
Figure 39 shows how the ADL5385 can be interfaced to the
AD9777 DAC (or any Analog Devices dual DAC with an output
bias level of 0.5 V) to generate a 155 Mbps 128 QAM carrier at
355 MHz. Because the TxDAC output and the IQ modulator
inputs operate at the same bias levels of 0.5 V, a simple dccoupled connection can be implemented without any active or
passive level shifting. The bias level and modulator drive level is
set by the 50 Ω ground-referenced resistors and the 100 Ω shunt
resistors, respectively (see the DAC Modulator Interfacing
section). A baseband filter is placed between the bias and signal
swing resistors. This 5-pole Chebychev filter with in-band ripple
of 0.1 dB has a corner frequency of 39 MHz.
I
CHANNEL
0.4
EVM (%)
The AD9777 features an auxiliary DAC that can be used to
inject small currents into the differential outputs for each
channel. The auxiliary DAC can produce the small offset
currents necessary to implement the nulling described in the
Carrier Feedthrough Nulling section.
Data Sheet
ADL5385
Figure 40 shows how adjacent channel power (measured at
750 kHz, 5.25 MHz, and 12 MHz offset from the last carrier)
and modulation error ratio (MER) vary with carrier power.
47
–60
46
ACPR2 (5.25MHz)
–65
45
ACPR3 (6.00MHz)
–70
44
ACPR1 (750kHz)
–75
–20
–40
–50
P2LO – BB
–60
P4LO + BB
P6LO – BB
–80
–90
42
0
100
200
MER
–16
500
600
700
800
900
1000
–14
–12
RF SECOND-ORDER PRODUCTS
CARRIER POWER (dBm)
Figure 40. ACP1, ACP2, ACP3, and Modulation Error Ratio (MER) vs. Output
Power for 256 QAM Transmitter
SPECTRAL PRODUCTS FROM HARMONIC MIXING
For broadband applications such as cable TV head-end
modulators, special attention must be paid to harmonics of the
LO. Figure 41 shows the level of these harmonics (out to 3 GHz)
as a function of the output frequency from 50 MHz to 1000 MHz,
in a single-sideband (SSB) test configuration, with a baseband
signal of 1 MHz and a SSB level of approximately −5 dBm. To
read this plot correctly, first pick the output frequency of interest on
the trace called POUT. The associated harmonics can be read off
the harmonic traces at multiples of this frequency. For example,
at an output frequency of 500 MHz, the fundamental power is
−5 dBm. The power of the second (P2fc − BB) and third (P3fc + BB)
harmonics is −63 dBm (at 1000 MHz) and −16 dBm (at 1500
MHz), respectively. Of particular importance are the products
from odd-harmonics of the LO, generated from the switching
operation in the mixers.
For cable TV operation at frequencies above approximately
500 MHz, these harmonics fall out of the band and can be
filtered by a fixed filter. However, as the frequency drops below
500 MHz, these harmonics start to fall close to or inside the
cable band. This calls for either limitation of the frequency
range to above 500 MHz or the use of a switchable filter bank to
block in-band harmonics at low frequencies.
A two-tone RF output signal produces second-order spectral
components at sum and difference frequencies. In broadband
systems, these intermodulation products fall inside the carrier
or in the adjacent channels. Output second-order RF
intermodulation intercept is defined as
OIP2_RF = POUT + (POUT − PIM(RF))
where PIM(RF) is the level of the intermodulation product at
fOUT1 + fOUT2. OIP2_RF levels from a two-tone test are plotted
as a function of carrier frequency in Figure 42, where the
baseband tones are 3.5 MHz and 4.5 MHz at −5 dBm each.
70
60
50
40
30
20
10
06118-036
–18
400
Figure 41. Spectral Components for Output Frequencies
from 50 MHz to 1000 MHz
OIP2_RF (dBm)
–20
40
–10
06118-045
41
–22
300
OUTPUT FREQUENCY (MHz)
–85
–90
–24
P5LO – BB
–70
43
–80
P3LO + BB
P7LO + BB
–30
06118-035
–55
POUT
–10
POUT, P_HARM (dBm)
48
MER (dBc)
ACPR (dBc)
–50
0
0
0
250
500
750
1000
1250
1500
1750
2000
2250
OUTPUT FREQUENCY (MHz)
Figure 42. Output Second-Order Intermodulation vs. Carrier Frequency
Rev. D | Page 19 of 24
ADL5385
Data Sheet
LO GENERATION USING PLLs
TRANSMIT DAC OPTIONS
Analog Devices has a line of phase-locked loops (PLLs) that can be
used for generating the LO signal. Table 4 lists the PLLs together
with their maximum frequency and phase noise performance.
The AD9777 recommended in the previous sections is by no
means the only DAC that can be used to drive the ADL5385.
There are other appropriate DACs depending on the level of
performance required. Table 6 lists the dual TxDACs that
Analog Devices offers.
Table 4. PLL Selection Table
Device
ADF4110
ADF4111
ADF4112
ADF4113
ADF4116
ADF4117
ADF4118
Frequency fIN (MHz)
550
1200
3000
4000
550
1200
3000
At 1 kHz Phase Noise
dBc/Hz, 200 kHz PFD
−91 at 540 MHz
−87 at 900 MHz
−90 at 900 MHz
−91 at 900 MHz
−89 at 540 MHz
−87 at 900 MHz
−90 at 900 MHz
Table 6. Dual TxDAC Selection Table
The ADF4360-0 through the ADF4360-8 (see Table 5 for the
full list of devices included in this range) come as a family of
chips, with nine operating frequency ranges. One device can be
chosen depending on the local oscillator frequency required.
While the use of the integrated synthesizer might come at the
expense of slightly degraded noise performance from the
ADL5385, it can be a cheaper alternative to a separate PLL
and VCO solution. Alternatively, the ADF4351 can be used,
which covers a frequency range of 35 MHz to 4400 MHz.
Table 5 shows the options available.
Table 5. PLL/VCO Family Operating Frequencies
Device
ADF4351
ADF4360-0
ADF4360-1
ADF4360-2
ADF4360-3
ADF4360-4
ADF4360-5
ADF4360-6
ADF4360-7
ADF4360-8
Output Frequency Range (MHz)
35 to 4400
2400 to 2725
2050 to 2450
1850 to 2150
1600 to 1950
1450 to 1750
1200 to 1400
1050 to 1250
350 to 1800
65 to 400
Device
AD9709
AD9761
AD9763
AD9765
AD9767
AD9773
AD9775
AD9777
AD9776
AD9778
AD9779
AD9122
Resolution (Bits)
8
10
10
12
14
12
14
16
12
14
16
16
Update Rate (MSPS Minimum)
125
40
125
125
125
160
160
160
1000
1000
1000
1200
All DACs listed have nominal bias levels of 0.5 V and use the
same DAC-modulator interface shown in Figure 33.
MODULATOR/DEMODULATOR OPTIONS
Table 7 lists other Analog Devices discrete modulators and
demodulators.
Table 7. Modulator/Demodulator Options
Device
AD8345
AD8346
AD8349
ADL5390
Mod/Demod
Mod
Mod
Mod
Mod
Frequency
Range (MHz)
140 to 1000
800 to 2500
700 to 2700
20 to 2400
ADL5370
ADL5371
ADL5372
ADL5373
ADL5375
ADL5386
Mod
Mod
Mod
Mod
Mod
Mod
300 to 1000
500 to 1500
1500 to 2500
2300 to 3000
400 to 6000
50 to 2200
AD8347
AD8348
ADL5380
ADL5382
ADL5387
AD8340
AD8341
Demod
Demod
Demod
Demod
Demod
Vector mod
Vector mod
800 to 2700
50 to 1000
400 to 6000
700 to 2700
30 to 2000
700 to 1000
1500 to 2400
Rev. D | Page 20 of 24
Comments
External
quadrature
Includes VVA
and AGC
Data Sheet
ADL5385
EVALUATION BOARD
The modulator output can be measured directly at the RF_OUT
SMA connector. Alternatively, by removing R40, and installing a
0 Ω resistor in the R25 pad, the modulator output can be fed to
the RF amplifier.
One populated, RoHS-compliant ADL5385 evaluation board is
available, the ADL5385-DIFFLO-EBZ. The ADL5385-DIFFLOEBZ can be configured to allow a differential LO drive through a
balun or direct interfacing to a PLL evaluation board. It also
includes component pads in its LO path to accommodate a
harmonic filter. The four baseband inputs are located on one
edge of the board to allow direct connection to a high speed
DAC evaluation board. The ADL5385-DIFFLO-EBZ also
includes an RF/IF amplifier.
QNBB
GND
C82
D.N.I
C88
D.N.I
R2
R17
C75
D.N.I
0Ω
C81
D.N.I
C41
D.N.I
0Ω
C80
D.N.I
0Ω
C87
D.N.I
GND
GND
R61
10kΩ
23
C3
10µF
GND
C8
0.1µF
GND
IBBN
COM2
GND
VP
R62
49.9Ω
T1 OR T2.
T1 TC1-1-43A+
T2 TC1-1-13M+
GND
C9
100pF
GND
VPS2
TEMP
RTEMP
VPS1
C6
0.1µF
200Ω
GND
VP
C5
100pF
TEMP
YEL
GND
VPS1
C4
0.1µF
GND
RF_OUT
VOUT
6
5
GND
R40
D.N.I
C31
0.1µF
VPOS_AMP
RED
R8
0Ω
GND
(2)
R25
0Ω
C45
68pF
U2
ADL5601
GND2
VP
D.N.I
GND
GND
C44
1.2nF
C43
1µF
GND
GND
L8
470nH
BLACK
RF IN
1SINGLE-ENDED LO DRIVINGAT LOIP.
2DIFFERENTIAL LO DRIVINGAT LOIP WITH
IPBB
GND
ENBL
GND
BLACK
0Ω
C77
D.N.I
INBB
GND
ON S1 OFF
3
2
IBBP
8
7
GND1
R3
0Ω
C83
D.N.I
13
14
15
QBBN
COM2
24
C11
100pF
GND
9
EXPOSED PADDLE
VP
R33
COM1
VP1
RED
GND GND
U1
4
VPS3
ADL5385
22
COM1
C15
0.1µF
10
COM1
VPS3
11
21
3
R10 R111
0Ω
D.N.I
LOIN
R4
0Ω
C78
D.N.I
GND
20
NC
0Ω
LOIP
16
QBBP
R32
D.N.I
R13
0Ω
GND
SEC
PRI
T1 OR T22
4
3
17
18
GND
R15
D.N.I
6
C16
D.N.I
COM3
2
LO_IN
C17
D.N.I
C14
1 0.1µF
C79
D.N.I
0Ω
C84
D.N.I
1
12
1
GND
C18
D.N.I
0Ω
19
NC
LO_IP
R34
0Ω
COM3
GND
R36
GND
VP
NC
C40
0Ω
C85
D.N.I
C89
D.N.I
GND
R431
C91
D.N.I
C90
D.N.I
0Ω
C86
D.N.I
GND
GND
GND
R6
R1
QPBB
GND
1
2
GND
GND
3
AMP_OUT
C47
0.1µF
GND
Figure 43. ADL5385-DIFFLO-EBZ Schematic
Table 8. ADL5385-DIFFLO-EBZ Configuration Options
Component
VP1, VPOS_AMP, GND1, GND2
GND
S1, R61, R62
R1, R2, R3, R4, R6, R17,
R33, R36, C41, C75 to C91
C14, C15
R15, R32, R34, C16 to C18, C40
Description
Power supply clip leads, and ground clip leads.
Device enable select. Set S1 to VP to enable the device. Set S1
to GND to power down the device.
Baseband input filters. These components can be used to
implement a low-pass filter for the baseband signals.
LO driving capacitor.
LO input filters. These components can be used to
implement a filter for the LO input signals.
Rev. D | Page 21 of 24
Default Value
Red (VP1) = 5 V, red (VPOS_AMP) = GND, GND1
and GND2 = black
Not applicable
S1 = on, R61 = 10 kΩ, R62 = 49.9 Ω
R1, R2, R3, R4, R6, R17, R33, R36 = 0 Ω,
C41, C75 to C91 = open
C14, C15 = 0.1 μF
R15, R32 = open, R34, C40 = 0 Ω,
C16 to C18 = open
06118-143
C76
D.N.I
GND
RF OUT
GND
GND
The ADL5385-DIFFLO-EBZ ships installed with an ADL5601
amplifier (50 MHz to 4000 MHz RF/IF amplifier). The ADL5602
can be used if more gain is needed. Figure 43, Table 8, Figure 44,
and Figure 45 show the schematic, configuration options, and
layouts for the ADL5385-DIFFLO-EBZ, respectively.
ADL5385
Data Sheet
Component
LO_IP SMA, R10, R11, R13,
R15, R32, R34, R43, C40, T1, T2
LO_IN SMA, R10, R11, R13, R15,
R32, R34, R43, C40, T1, T2
LO_IP SMA, LO_IN SMA, R10,
R11, R13, R15, R32, R34, R43,
C40, T1, T2
LO_IP SMA, R10, R11, R13,
R15, R32, R34, R43, C40, T1, T2
Description
Single-ended LO input at LOIP.
C31
AC-coupling capacitor connects ADL5385 VOUT to
RF_OUT RF connector or to ADL5601 RF input.
AC-coupling capacitor connects ADL5601 RFOUT to
AMP_OUT connector.
Resistor connects ADL5385 VOUT to RF_OUT SMA. To
check ADL5385 performance itself, insert a 0 Ω at R40 and
open R25. To check ADL5601 performance itself, insert a
0 Ω at R40 and be inserted 0.1 μF on R25, open C31.
Resistor connects ADL5385 VOUT to ADL5601 RFIN.
Resistor connects ADL5385 TEMP to TEMP test clip lead.
DC bias inductor.
Power supply bypassing capacitors.
C47
R40
R25
RTEMP
L8
C3, C4, C5, C6, C8, C9, C11,
C43, C44, C45
Optional differential LO input.
Optional differential LO driving with balun (T1or T2) at LOIP.
Resistor to share power supply between the ADL5385 and
the ADL5601. To turn on the ADL5601 with the power
supply on VP1, install a 0 Ω resistor in this location.
ADL5385 quadrature modulator.
SOT-89 RF/IF gain block.
R13, R34, C40 = 0 Ω,
R10, R11, R15, R32, R43 = open,
T1 = TC1-1-43A+, T2 = TC1-1-13M+
C31 = 0.1 μF
C47 = 0.1 μF
R40 = open
R25 = 0 Ω
RTEMP = 200 Ω
L8 = 470 nH
C3 = 10 μF,
C4, C6, C8 = 0.1 μF, C5, C9, C11 = 100 pF,
C43 = 1 μF, C44 = 1.2 nF, C45 = 68 pF
R8 = open
ADL5385
ADL5601
06118-145
U1
U2
Optional single-ended LO input at LOIN.
06118-144
R8
Default Value
R11, R13, R34, R43, C40 = 0 Ω,
R10, R15, R32 = open, T1, T2 = open
R10, R11, R15, R32, R43 = 0 Ω,
R13, R34, C40 = open, T1, T2 = open
R11, R15, R32, R34, R43, C40 = 0 Ω,
R10, R13 = open, T1, T2 = open
Figure 45. Layout of ADL5385-DIFFLO-EBZ, Bottom View
Figure 44. Layout of ADL5385-DIFFLO-EBZ, Top View
Rev. D | Page 22 of 24
Data Sheet
ADL5385
CHARACTERIZATION SETUP
Output signals are measured directly using the spectrum
analyzer, and currents and voltages are measured using the
Agilent 34401A multimeter.
SSB SETUP
Figure 46 is a diagram of the characterization test stand setup
for the ADL5385, which is intended to test the product as a
single-sideband modulator. The Aeroflex IFR3416 signal
generator provides the I and Q inputs as well as the LO input.
FREQ 100MHz TO 4GHz LEVEL 0dBm
BIAS 0.5V
BIAS 0.5V
GAIN 0.7V
GAIN 0.7V
AEROFLEX IFR 3416 250kHz TO 6GHz
SIGNAL GENERATOR
RF
OUT
R&S SPECTRUM ANALYZER FSU 20Hz TO 8GHz
LO
50MHz TO 2GHz
+6dBm
CONNECT TO BACK OF UNIT
90 DEG
Q
I
RF
IN
0 DEG
OUTPUT
AGILENT 34401A MULTIMETER
0.210 ADC
GND
VPOS
J1(OUT)
J3(QN)
J4(QP)
ADL5385
RLM TEST RACK 1
J7(LO)
J6(IP)
J5(IN)
VPOS +5V
5.0000 0.210A
DELL
Figure 46. ADL5385 Characterization Board SSB Test Setup
Rev. D | Page 23 of 24
06118-040
AGILENT E3631A
POWER SUPPLY
±25V
6V
+ –
+ COM –
ADL5385
Data Sheet
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.50
BSC
PIN 1
INDICATOR
24
19
18
1
2.40
2.30 SQ
2.20
EXPOSED
PAD
6
13
0.80
0.75
0.70
SEATING
PLANE
0.50
0.40
0.30
12
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.30
0.25
0.20
7
BOTTOM VIEW
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8.
01-18-2012-A
TOP VIEW
Figure 47. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADL5385ACPZ-WP
ADL5385ACPZ-R7
ADL5385-DIFFLO-EBZ
1
Temperature Range
–40°C to +85°C
–40°C to +85°C
Package Description
24-Lead LFCSP, Waffle Pack
24-Lead LFCSP, 7” Tape and Reel
Evaluation Board with Differential LO Input
Z = RoHS Compliant Part.
©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06118-0-12/16(D)
Rev. D | Page 24 of 24
Package Option
CP-24-14
CP-24-14
Ordering Quantity
64
1500
1
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