4.5 GHz Ultrahigh Dynamic Range,
Dual Differential Amplifier
ADL5566
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
−3 dB bandwidth of 4.5 GHz (AV = 16 dB)
Fixed 16 dB gain
Channel-to-channel gain error: 0.1 dB at 100 MHz
Channel-to-channel phase error: 0.06° at 100 MHz
Differential or single-ended input to differential output
I/O dc-coupled or ac-coupled
Low noise input stage: 1.3 nV/√Hz RTI at AV = 16 dB
Low broadband distortion (AV = 16 dB), supply = 5 V
10 MHz: −103 dBc (HD2), −107 dBc (HD3)
100 MHz: −95 dBc (HD2), −100 dBc (HD3)
200 MHz: −94.5 dBc (HD2), −87 dBc (HD3)
500 MHz: −83 dBc (HD2), −64 dBc (HD3)
IMD3 of −95 dBc at 200 MHz center
Maintains low single-ended distortion performance out to
500 MHz
Slew rate: 16 V/ns
Maintains low distortion down to 1.2 V VCOM
Fixed 16 dB gain can be reduced by adding external resistors
Fast settling and overdrive recovery of 2.5 ns
Single-supply operation: 2.8 V to 5.2 V
Power-down
Low dc power consumption, 462 mW at 3.3 V supply
ENBL1
VCC1/VCC2
RF
VON1
VIP1
VIN1
RG
VCOM1
RG
VOP1
RF
RF
VON2
VIP2
VIN2
RG
VCOM2
RG
VOP2
APPLICATIONS
Differential ADC drivers
Single-ended to differential conversion
RF/IF gain blocks
SAW filter interfacing
ADL5566
GND
ENBL2
10916-001
RF
Figure 1.
GENERAL DESCRIPTION
The ADL5566 is a high performance, dual differential amplifier
optimized for IF and dc applications. The amplifier offers low
noise of 1.3 nV/√Hz and excellent distortion performance over
a wide frequency range, making it an ideal driver for high speed
16-bit analog-to-digital converters (ADCs). The ADL5566 is
ideally suited for use in high performance, zero IF/complex
IF receiver designs. In addition, this device has excellent low
distortion for single-ended input drive applications.
The ADL5566 provides a gain of 16 dB. For the single-ended input
configuration, the gain is reduced to 14 dB. Using two external
series resistors for each amplifier expands the gain flexibility of
the amplifier and allows for any gain selection from 0 dB to 16 dB
for a differential input and 0 dB to 14 dB for a single-ended input.
In addition, this device maintains low distortion down to output
(VOCM) levels of 1.2 V providing an added capability for driving
CMOS ADCs at ac levels up to 2 V p-p.
Rev. C
The quiescent current of the ADL5566, using a 3.3 V supply, is
typically 70 mA per amplifier. When disabled, it consumes less
than 3.5 mA per amplifier and has −25 dB of input to output
isolation at 100 MHz.
The device is optimized for wideband, low distortion, and noise
performance, giving it unprecedented performance for overall
spurious-free dynamic range (SFDR). These attributes, together
with the adjustable gain capability, make this device the amplifier of
choice for driving a wide variety of ADCs, mixers, pin diode
attenuators, SAW filters, and multi-element discrete devices.
Fabricated on an Analog Devices, Inc., high speed SiGe process, the
ADL5566 is supplied in a compact 4 mm × 4 mm, 24-lead LFCSP
package and operates over the −40°C to +85°C temperature range.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2019 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADL5566
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications Information .............................................................. 15
Applications ....................................................................................... 1
Basic Connections ...................................................................... 15
Functional Block Diagram .............................................................. 1
Input and Output Interfacing ................................................... 16
General Description ......................................................................... 1
Gain Adjustment and Interfacing ............................................ 16
Revision History ............................................................................... 2
ADC Interfacing ......................................................................... 18
Specifications..................................................................................... 3
DC-Coupled Receiver Application .......................................... 18
Absolute Maximum Ratings............................................................ 6
Layout Considerations ............................................................... 19
Thermal Resistance ...................................................................... 6
Soldering Information and Recommended Land Pattern .... 21
ESD Caution .................................................................................. 6
Evaluation Board ........................................................................ 21
Pin Configuration and Function Descriptions ............................. 7
Outline Dimensions ....................................................................... 24
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 24
Circuit Description ......................................................................... 14
REVISION HISTORY
8/2019—Rev. B to Rev. C
Changes to Figure 36 ...................................................................... 15
Changes to Figure 48 ...................................................................... 19
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
12/2013—Rev. 0 to Rev. A
Changes to ENBL1/ENBL2 Threshold Parameter, Table 1 ..........3
Change to Table 2 ..............................................................................6
11/2012—Revision 0: Initial Version
4/2019—Rev. A to Rev. B
Changes to Figure 26 ...................................................................... 11
Updated Outline Dimensions ....................................................... 24
Rev. C | Page 2 of 24
Data Sheet
ADL5566
SPECIFICATIONS
VS = 3.3 V, VCM = 1.65 V, VS = 5 V, VCM = 2.5 V, RL = 200 Ω differential, AV = 16 dB, CL = 1 pF differential, f = 100 MHz, TA = 25°C,
parameters specified as ac-coupled differential input and differential output, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Bandwidth 0.1 dB Flatness
Gain Accuracy
Gain Error
Phase Error
Gain Supply Sensitivity
Gain Temperature Sensitivity
Slew Rate
Settling Time
Overdrive Recovery Time
Reverse Isolation (S12)
Channel Isolation
INPUT/OUTPUT CHARACTERISTICS
Input Common-Mode Range
Input Resistance (Differential)
Input Resistance (Single-Ended)
Input Capacitance (Single-Ended)
Input Bias Current
CMRR
Output Common-Mode Range
Output Common-Mode Offset
Output Common-Mode Drift
Output Differential Offset Voltage
Output Differential Offset Drift
Output Resistance (Differential)
Maximum Output Voltage Swing
POWER INTERFACE
Supply Voltage
ENBL1/ENBL2 Threshold
ENBL1/ENBL2 Input Bias Current
Quiescent Current
Test Conditions/
Comments
Min
AV = 16 dB, VOUT ≤ 0.5 V p-p
VOUT ≤ 1.0 V p-p
≤1000 MHz, Channel A to
Channel B
≤1000 MHz, Channel A to
Channel B
VS ± 5%
−40°C to +85°C
Rise, AV = 16 dB, RL = 200 Ω,
VOUT = 2 V step
Fall, AV = 16 dB, RL = 200 Ω,
VOUT = 2 V step
2 V step to 1%
VIN = 4 V to 0 V step,
VOUT ≤ ±10 mV
Channel A to Channel B
AV = 16 dB
3.3 V
Typ
Min
≤0.5
≤0.5
Degrees
3.4
0.5
16
5.6
0.5
18
mdB/V
mdB/°C
V/ns
18
20
V/ns
890
2.5
750
2.5
ps
ns
75
82.5
75
82.5
dB
dB
1.8
1.3
1.8
+20
−20
1.25
−100
2.8
+20
3.3
3
+20
3.5
−20
1.1
11
3.4
Device disabled, ENBL low
Device enabled, ENBL high
ENBL high
ENBL low
ENBL high
ENBL low
3.5
160
150
1.1
±5
44
2
1 dB compressed
Unit
MHz
MHz
dB
dB
1.25
−100
−40°C to +85°C
Max
4500
500
±1
≤0.02
160
150
1.1
±5
44
Referenced to VCC/2
−40°C to +85°C
Typ
4500
500
±1
≤0.02
1.2
AV = 16 dB
AV = 14 dB
5V
Max
+20
1.7
11
5
5.2
0.5
1.5
2.8
5
5.2
0.6
1.5
500
−165
140
7
Rev. C | Page 3 of 24
150
500
−165
160
9
175
V
Ω
Ω
pF
µA
dB
V
mV
mV/°C
mV
mV/°C
Ω
V p-p
V
V
V
nA
µA
mA
mA
ADL5566
Parameter
NOISE/HARMONIC PERFORMANCE
10 MHz
Second/Third Harmonic
Distortion (HD2/HD3)
Output IP3/Third-Order
Intermodulation
Distortion (OIP3/IMD3)
Output IP2 Second-Order
Intermodulation
Distortion (OIP2/IMD2)
1 dB Compression Point, RTO
(OP1dB)
Noise Spectral Density,
RTI (NSD)
Noise Figure (NF)
100 MHz
Second/Third Harmonic
Distortion (HD2/HD3)
Output IP3/Third-Order
Intermodulation
Distortion (OIP3/IMD3)
Output IP2 Second-Order
Intermodulation
Distortion (OIP2/IMD2)
1 dB Compression Point, RTO
(OP1dB)
Noise Spectral Density,
RTI (NSD)
Noise Figure (NF)
200 MHz
Second/Third Harmonic
Distortion (HD2/HD3)
Output IP3/Third-Order
Intermodulation
Distortion (OIP3/IMD3)
Output IP2 Second-Order
Intermodulation
Distortion (OIP2/IMD2)
1 dB Compression Point, RTO
(OP1dB)
Noise Spectral Density,
RTI (NSD)
Noise Figure (NF)
500 MHz
Second/Third Harmonic
Distortion (HD2/HD3)
Output IP3/Third-Order
Intermodulation
Distortion (OIP3/IMD3)
Output IP2 Second-Order
Intermodulation
Distortion (OIP2/IMD2)
Noise Spectral Density,
RTI (NSD)
Noise Figure (NF)
Data Sheet
Test Conditions/
Comments
Min
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 16 dB
3.3 V
Typ
5V
Max
Min
Typ
Max
Unit
−99.1/−111
−103.1/−107.3
dBc
+50.2/−103.3
+49.4/−101.8
dBm/dBc
+90.8/−92.1
+91.2/−92.5
dBm/dBc
14
17.7
dBm
AV = 16 dB
1.28
1.32
nV/√Hz
AV = 16 dB
6.47
6.66
dB
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 16 dB
−89/−92.1
−94.7/−100
dBc
+49.4/−101.9
+50.9/−104.7
dBm/dBc
+96.9/−98.2
+98.9/−100.2
dBm/dBc
14.2
17.8
dBm
AV = 16 dB
1.26
1.3
nV/√Hz
AV = 16 dB
6.36
6.58
dB
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 16 dB
−92.7/−80.2
−94.5/−87.2
dBc
+45.9/−94.7
+46/−95
dBm/dBc
+80.4/−81.7
+82.6/−83.9
dBm/dBc
14.1
17.7
dBm
AV = 16 dB
1.25
1.28
nV/√Hz
AV = 16 dB
6.31
6.48
dB
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 16 dB
−82.6/−60.5
−82.8/−64.2
dBc
+30.7/−64.7
+32.4/−67.8
dBm/dBc
+74.2/−75.5
+75.8/−77.1
dBm/dBc
1.32
1.35
nV/√Hz
6.64
6.83
dB
AV = 16 dB
Rev. C | Page 4 of 24
Data Sheet
Parameter
1000 MHz
Second/Third Harmonic
Distortion (HD2/HD3)
Output IP3/Third-Order
Intermodulation
Distortion (OIP3/IMD3)
Output IP2 Second-Order
Intermodulation
Distortion (OIP2/IMD2)
Noise Spectral Density,
RTI (NSD)
Noise Figure (NF)
ADL5566
Test Conditions/
Comments
Min
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 16 dB, RL = 200 Ω,
VOUT = 2 V p-p composite
(2 MHz spacing)
AV = 16 dB
AV = 16 dB
3.3 V
Typ
5V
Max
Min
Typ
Max
Unit
−57.6/−43
−57.1/−45.9
dBc
+23.2/−49.4
+24.8/−52.6
dBm/dBc
+56.1/−57.4
+55.9/−57.2
dBm/dBc
1.93
1.99
nV/√Hz
9.45
9.66
dB
Rev. C | Page 5 of 24
ADL5566
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 2.
Parameter
Output Voltage Swing × Bandwidth Product
Supply Voltage, VCC
VIPx, VINx
±IOUT Maximum
Internal Power Dissipation
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
Rating
2300 V p-p MHz
5.25 V
VCC + 0.5 V
±30 mA
900 mW
135°C
−40°C to +105°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 3 lists the junction to air thermal resistance (θJA) and the
junction to paddle thermal resistance (θJC) for the ADL5566.
Table 3. Thermal Resistance
Package Type
24-Lead LFCSP
1
θJA1
34.0
θJC2
1.8
Unit
°C/W
Measured on Analog Devices evaluation board. For more information about
board layout, see the Soldering Information and Recommended Land Pattern
section.
2
Based on simulation with JEDEC standard JESD51.
ESD CAUTION
Rev. C | Page 6 of 24
Data Sheet
ADL5566
VIN1 1
18 VON1
VIP1 2
17 VOP1
NC 3
ADL5566
16 NC
NC 4
TOP VIEW
15 NC
NC 12
9
ENBL2
VCC2 11
8
VCOM2 10
7
NC
14 VOP2
13 VON2
NC
VIP2 5
VIN2 6
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PADDLE IS INTERNALLY CONNECTED TO
GND AND MUST BE SOLDERED TO A LOW IMPEDANCE
GROUND PLANE.
10916-002
20 VCC1
19 NC
22 ENBL1
21 VCOM1
24 NC
23 NC
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2
3, 4, 7, 8, 12, 15,
16, 19, 23, 24
5
6
9
10
Mnemonic
VIN1
VIP1
NC
Description
Balanced Differential Input for Amplifier 1. Biased to VCC/2, typically ac-coupled. Input for AV = 16 dB.
Balanced Differential Input for Amplifier 1. Biased to VCC/2, typically ac-coupled. Input for AV = 16 dB.
No Connect. Do not connect to this pin. Solder to ground.
VIP2
VIN2
ENBL2
VCOM2
11
13
14
17
18
20
21
VCC2
VON2
VOP2
VOP1
VON1
VCC1
VCOM1
22
ENBL1
EP
Balanced Differential Input for Amplifier 2. Biased to VCC/2, typically ac-coupled. Input for AV = 16 dB.
Balanced Differential Input for Amplifier 2. Biased to VCC/2, typically ac-coupled. Input for AV = 16 dB.
Enable for Amplifier 2. Apply positive voltage (1.3 V < ENBL2 < VCC2) to activate device.
Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the inputs and
outputs of Amplifier 2. If left open, VCOM2 = VCC/2. Typically, it is decoupled to ground with a 0.1 µF
capacitor.
Positive Supply for Amplifier 2.
Balanced Differential Output for Amplifier 2. Biased to VCC/2, typically ac-coupled.
Balanced Differential Output for Amplifier 2. Biased to VCC/2, typically ac-coupled.
Balanced Differential Output for Amplifier 1. Biased to VCC/2, typically ac-coupled.
Balanced Differential Output for Amplifier 1. Biased to VCC/2, typically ac-coupled.
Positive Supply for Amplifier 1.
Common-Mode Voltage. A voltage applied to this pin sets the common-mode voltage of the inputs and
outputs of Amplifier 1. If left open, VCOM1 = VCC/2. Typically, it is decoupled to ground with a 0.1 µF
capacitor.
Enable for Amplifier 1. Apply positive voltage (1.3 V < ENBL1 < VCC1) to activate device.
The exposed paddle is internally connected to GND and must be soldered to a low impedance ground plane.
Rev. C | Page 7 of 24
ADL5566
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 3.3 V, VCM = 1.65 V, RL = 200 Ω differential, AV = 16 dB, CL = 1 pF differential, f = 100 MHz, TA = 25°C, parameters specified as
ac-coupled differential input and differential output, unless otherwise noted.
PHASE ERROR (Degrees)
15
GAIN (dB)
10
5
0
–5
–10
100M
1G
FREQUENCY (Hz)
Figure 3. Gain vs. Frequency Response for 200 Ω Differential Load,
VPOS = 3.3 V and VPOS = 5 V, 25°C
25
20
3.3V,
3.3V,
3.3V,
3.3V,
0.06
0.5
0.05
0.4
0.04
0.3
0.03
0.2
0.02
0.1
0.01
0
10
10916-003
–15
10M
0.6
FREQUENCY (MHz)
25
–40°C
+25°C
+85°C
+105°C
20
OP1dB (dBm)
GAIN (dB)
10
5
0
15
10
5V, +25°C
5V, –40°C
5V, +85°C
5V, +105°C
3.3V, +25°C
3.3V, –40°C
3.3V, +85°C
3.3V, +105°C
–5
5
–10
100M
1G
FREQUENCY (Hz)
0
10916-004
–15
10M
5V,
5V,
5V,
5V,
50
100
150
200
250
Figure 7. OP1dB vs. Frequency for 200 Ω Differential Load, Four
Temperatures, VPOS = 3.3 V, VPOS = 5 V
10.0
–40°C
+25°C
+85°C
+105°C
9.5
3.3V SUPPLY
5V SUPPLY
9.0
8.5
NOISE FIGURE (dB)
15
10
GAIN (dB)
0
FREQUENCY (MHz)
Figure 4. Gain vs. Frequency Response for 200 Ω Differential Load,
Four Temperatures, VPOS = 3.3 V
20
0
1000
100
Figure 6. Channel-to-Channel Gain Error and Phase Error vs. Frequency
15
25
GAIN ERROR (dB)
20
0.07
SDD21 PHASE
SDD21 MAG
10916-106
0.7
3.3V, 25°C
5V, 25°C
10916-006
25
5
0
–5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
–10
1G
FREQUENCY (Hz)
3.0
10M
10916-005
100M
100M
1G
FREQUENCY (Hz)
Figure 5. Gain vs. Frequency Response for 200 Ω Differential Load,
Four Temperatures, VPOS = 5 V
Figure 8. Noise Figure vs. Frequency at VPOS = 3.3 V, VPOS = 5 V, 25°C
Rev. C | Page 8 of 24
10916-007
3.5
–15
10M
Data Sheet
3.00
60
3.3V SUPPLY
5V SUPPLY
2.75
2.50
50
OIP3, 5V, 25°C
OIP3, 3.3V, 25°C
2.25
2.00
40
OIP3 (dBm)
NOISE SPECTRAL DENSITY (nV/√Hz)
ADL5566
1.75
1.50
1.25
1.00
30
20
0.75
0.50
10
1G
FREQUENCY (Hz)
Figure 9. Noise Spectral Density vs. Frequency at VPOS = 3.3 V and VPOS = 5 V
60
OIP3,
OIP3,
OIP3,
OIP3,
50
0
–6 –5 –4 –3 –2 –1
0
–40
10
–100
200
300
400
500
600
700
800
900
1000
FREQUENCY (MHz)
–120
10916-009
OIP3 (dBm)
IMD3 (dBm)
–80
100
3
4
5
6
7
8
9
10
IMD3,
IMD3,
IMD3,
IMD3,
IMD3,
IMD3,
IMD3,
IMD3,
3.3V, +25°C, 1V p-p
5V, +25°C, 1V p-p
3.3V, +85°C, 1V p-p
5V, +85°C, 1V p-p
3.3V, –40°C, 1V p-p
5V, –40°C, 1V p-p
3.3V, +105°C, 1V p-p
5V, +105°C, 1V p-p
–60
20
0
2
IMD3, 3.3V, +25°C, 2V p-p
IMD3, 5V, +25°C, 2V p-p
IMD3, 3.3V, +85°C, 2V p-p
IMD3,5V, +85°C, 2V p-p
IMD3, 3.3V, –40°C, 2V p-p
IMD3, 5V, –40°C, 2V p-p
IMD3, 3.3V, +105°C, 2V p-p
IMD3, 5V, +105°C, 2V p-p
–20
40
0
1
Figure 12. OIP3 vs. Output Power (POUT) per Tone, Frequency 200 MHz,
VPOS = 3.3 V and VPOS = 5 V
3.3V, 25°C, 2V p-p
5V, 25°C, 2V p-p
3.3V, 25°C, 1V p-p
5V, 25°C, 1V p-p
30
0
POUT/TONE (dBm)
0
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (MHz)
Figure 10. Output Third-Order Intercept (OIP3) at Output Level at 2 V p-p
Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V
10916-012
100M
10916-008
0
10M
10916-011
0.25
Figure 13. IMD3 vs. Frequency, Over Temperature, Output Level at
2 V p-p Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V
60
–20
–30
50
–40
–50
IMD3 (dBc)
30
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
10
0
0
100
3.3V, +25°C, 2V p-p
5V, +25°C, 2V p-p
3.3V, +85°C, 2V p-p
5V, +85°C, 2V p-p
3.3V, –40°C, 2V p-p
5V, –40°C, 2V p-p
3.3V, +105°C, 2V p-p
5V, +105°C, 2V p-p
200
300
400
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
OIP3,
500
3.3V, +25°C, 1V p-p
5V, +25°C, 1V p-p
3.3V, +85°C, 1V p-p
5V, +85°C, 1V p-p
3.3V, –40°C, 1V p-p
5V, –40°C, 1V p-p
3.3V, +105°C, 1V p-p
5V, +105°C, 1V p-p
600
FREQUENCY (MHz)
700
800
900
–60
5V
SUPPLY
–70
3.3V
SUPPLY
–80
–90
–100
–110
1000
–120
Figure 11. OIP3 vs. Frequency, Overtemperature, Output Level at 2 V p-p
Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V
0
0.5
1.0
1.5
2.0
VCOM (V)
2.5
3.0
3.5
4.0
10916-017
20
10916-010
OIP3 (dBm)
40
Figure 14. IMD3 vs. VCOM, Output Level at 2 V p-p Composite, RL = 200 Ω,
VPOS = 3.3 V and VPOS = 5 V, Frequency = 100 MHz
Rev. C | Page 9 of 24
ADL5566
–50
Data Sheet
0
IMD3 100Ω LOAD
IMD3 150Ω LOAD
IMD3 200Ω LOAD
–55
–60
HD3,
HD3,
HD3,
HD3,
–20
–40
5V, 25°C, 1V p-p
3.3V, 25°C, 2V p-p
5V, 25°C, 2V p-p
3.3V, 25°C, 1V p-p
–60
–65
HD2 (dBc)
IMD3 (dBc)
–75
–80
–85
–90
–95
–40
–80
–60
–100
–80
–120
HD3 (dBc)
–70
–100
–105
HD2,
HD2,
HD2,
HD2,
–115
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
–120
10916-031
–120
0
100
200
300
400
500
600
–140
3.3V, 25°C, 2V p-p
5V, 25°C, 2V p-p
3.3V, 25°C, 1V p-p
5V, 25°C, 1V p-p
700
800
–160
1000
900
10916-013
–100
–110
FREQUENCY (MHz)
Figure 18. Harmonic Distortion (HD2/HD3) vs. Frequency,
Output Level at 2 V p-p Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V
Figure 15. IMD3 vs. Frequency, RL = 100 Ω, RL = 150 Ω, and RL = 200 Ω, VPOS = 3.3 V,
Input Common-Mode = 1.65 V, Output Common-Mode = 1.25 V, VOUT = 1.5 V p-p
0
60
55
HD2,
HD2,
HD2,
HD2,
–20
3.3V,
3.3V,
3.3V,
3.3V,
+25°C
+85°C
–40°C
+105°C
HD2,
HD2,
HD2,
HD2,
5V,
5V,
5V,
5V,
–40
+25°C
+85°C
–40°C
+105°C
–60
40
35
–40
–80
–60
–100
–80
–120
HD3 (dBc)
45
HD2 (dBc)
OIP3 (dBm)
50
30
HD3,
HD3,
HD3,
HD3,
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
–120
50
100
150
200
250
300
350
5V,
5V,
5V,
5V,
–140
+25°C
+85°C
–40°C
+105°C
400
450
–160
500
FREQUENCY (MHz)
Figure 19. Harmonic Distortion (HD2/HD3) vs. Frequency,
Output Level at 2 V p-p Composite, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V
Figure 16. Single-Ended OIP3 vs. Frequency, VPOS = 3.3 V,
2 V p-p Composite Output, RL = 200 Ω
0
–60
100
0
3.3V OIP2
5V OIP2
3.3V IMD2
5V IMD2
–20
–80
–20
80
–40
–100
–40
60
–60
–120
–60
40
–80
–140
–80
20
–100
–160
HD2 (dBc)
3.3V, HD2, 25°C
5V, HD2, 25°C
IMD2 (dBc)
120
–100
0
0
100
200
300
400
500
600
700
800
FREQUENCY (MHz)
Figure 17. OIP2/IMD2 vs. Frequency
900
–120
1000
–180
–2
0
2
4
POUT/TONE (dBm)
6
8
–120
10
10916-015
3.3V, HD3, 25°C
5V, HD3, 25°C
10916-053
OIP2 (dBm)
0
HD3,
HD3,
HD3,
HD3,
+25°C
+85°C
–40°C
+105°C
HD3 (dBc)
0
10916-032
20
3.3V,
3.3V,
3.3V,
3.3V,
10916-014
–100
25
Figure 20. Harmonic Distortion (HD2/HD3) vs. Output Power (POUT) per Tone,
Frequency = 200 MHz, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V
Rev. C | Page 10 of 24
Data Sheet
HD2,
HD3,
HD2,
HD3,
–10
–20
–60
3.3V
3.3V
5V
5V
–40
–50
–60
–70
–80
–90
–70
–75
–80
–85
–90
–95
–100
1.0
1.5
2.0
2.5
3.0
VCOM (V)
Figure 21. Harmonic Distortion (HD2/HD3) vs. VCOM, Output Level at
2 V p-p, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V, Frequency = 100 MHz
–50
–110
10916-016
–110
0.5
100
200
300
400
500
FREQUENCY (MHz)
Figure 24. Single-Ended Harmonic Distortion (HD2/HD3) vs. Frequency,
VPOS = 3.3 V and VPOS = 5 V, VOUT = 2 V p-p, RL = 200 Ω
–80
HD2 100Ω LOAD
HD2 200Ω LOAD
–55
0
–85
–60
DISTORTION PRODUCT (dBc)
–65
–70
–75
–80
–85
–90
–95
–100
–105
–110
–90
–95
HD2
–100
IMD3
–105
HD3
–110
–115
–115
50
100
150
200
250
300
350
400
450
500
Figure 22. HD2 vs. Frequency, RL = 100 Ω and RL = 200 Ω, VPOS = 3.3 V, Input
Common-Mode = 1.65 V, Output Common-Mode = 1.25 V, VOUT = 1.5 V p-p
–50
–120
10916-029
0
FREQUENCY (MHz)
0
1
2
3
4
5
6
FREQUENCY (MHz)
Figure 25. Low Frequency Distortion (HD2/HD3/IMD3) vs. Frequency,
Output Level at 2 V p-p, RL = 200 Ω, VPOS = 3.3 V
HD3 200Ω LOAD
HD3 100Ω LOAD
–55
–60
–65
–70
HD3 (dBc)
–75
–80
–85
3
–90
–95
–100
–105
2
–110
–115
50
100
150
200
250
300
FREQUENCY (MHz)
350
400
450
500
Figure 23. HD3 vs. Frequency, RL = 100 Ω and RL = 200 Ω, VPOS = 3.3 V, Input
Common-Mode = 1.65 V, Output Common-Mode = 1.25 V, VOUT = 1.5 V p-p
Rev. C | Page 11 of 24
CH2 100mV/DIV 50Ω
CH3 500mV/DIV 50Ω
8G
8G
A CH3
1.1V
Figure 26. ENBLx Time Domain Response, VPOS = 3.3 V
10916-020
2ns/DIV
0
10916-030
–120
10916-033
–105
–100
HD2 (dBc)
3.3V
3.3V
5.0V
5.0V
10916-019
HD2 AND HD3 (dBc)
–30
–120
HD2 AT
HD3 AT
HD2 AT
HD3 AT
–65
HARMONIC DISTORTION (dBc)
0
ADL5566
ADL5566
Data Sheet
0
–10
REVERSE ISOLATION (dB)
–20
1
–30
–40
–50
–60
–70
–80
100
1000
FREQUENCY (MHz)
60
EQUIVALENT SERIES INPUT RESISTANCE (Ω)
220
50
45
35
30
25
20
15
10
0
10
100
1000
FREQUENCY (MHz)
1.6
190
1.4
180
1.2
170
1.0
160
0.8
150
0.6
140
0.4
130
0.2
120
10
10916-022
5
EQUIVALENT SERIES OUTPUT RESISTANCE (Ω)
900
700
600
500
400
300
200
100
200
300
400
500
600
700
800
FREQUENCY (MHz)
900
1000
10916-023
GROUP DELAY (ps)
800
100
0
1000
Figure 31. S11 Equivalent RLC Parallel Network
1000
0
100
FREQUENCY (MHz)
Figure 28. Common-Mode Rejection Ratio (CMRR) vs. Frequency
0
1.8
200
20
18
10
RESISTANCE
CAPACITANCE
9
16
8
14
7
12
6
10
5
8
4
6
3
4
2
2
1
0
10
100
FREQUENCY (MHz)
Figure 32. S22 Equivalent RLC Parallel Network
Figure 29. Group Delay vs. Frequency
Rev. C | Page 12 of 24
0
1000
EQUIVALENT SERIES OUTPUT INDUCTANCE (nH)
CMRR (dB)
40
210
2.0
RESITANCE
CAPACITANCE
EQUIVALENT PARALLEL INPUT CPAPCITANCE (pF)
Figure 30. Reverse Isolation (S12) vs. Frequency
Figure 27. Large Signal Pulse Response Using a Slow Transient Signal
Generator, 4 V p-p, VPOS = 3.3 V
55
10916-024
0V
10916-025
A CH1
10916-026
2ns
10916-021
CH1 400mV
–90
–100
10
85
80
5V
ISUPPLY (mA)
75
3.3V
70
65
100M
FREQUENCY (Hz)
1G
10G
60
–40
Figure 33. Output Referred Crosstalk, Channel A to Channel B, VPOS = 3.3 V,
VCOM = 1.65 V
–20
0
20
40
TEMPERATURE (°C)
60
80
100
09959-027
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–100
10M
ADL5566
10916-028
CROSSTALK (dB)
Data Sheet
Figure 34. ISUPPLY vs. Temperature, RL = 200 Ω, VPOS = 3.3 V and VPOS = 5 V
Rev. C | Page 13 of 24
ADL5566
Data Sheet
CIRCUIT DESCRIPTION
The ADL5566 is a high gain, fully differential dual amplifier/ADC
driver that uses a 2.8 V to 5 V supply. It provides a 16 dB gain
that can be reduced by adding external series resistors. The 3 dB
bandwidth is 4.5 GHz, and it has a differential input impedance of
160 Ω. It has a differential output impedance of 10 Ω and an
output common-mode adjust voltage of 1.1 V to 1.8 V.
500Ω
+
80Ω
5Ω
+
½ RS
+
0.1µF
0.1µF
½
ADL5566
AC
80Ω
5Ω
–
+
½ RS
RL
500Ω
0.1µF
+
10916-034
0.1µF
Figure 35. Basic Structure
The ADL5566 is composed of a dual fully differential amplifier
with on-chip feedback and feed-forward resistors. The gain is fixed
at 16 dB but can be reduced by adding two resistors in series with
the two inputs (see the Gain Adjustment and Interfacing section).
The amplifier is designed to provide a high differential open-loop
gain and has an output common-mode circuit that enables the
user to change the output common-mode voltage by applying a
voltage to a VCOMx pin. The amplifier is designed to provide
superior low distortion at frequencies to and beyond 300 MHz
with low noise and low power consumption. The low distortion
and noise are realized with a 3.3 V power supply at 140 mA.
The dual amplifier has an extremely high gain bandwidth (GBW)
product that results in distortion levels that are the best in the
industry for power consumed at frequencies beyond 100 MHz.
This amplifier achieves greater than −69 dBc IMD3 at 500 MHz
and −100 dBc at 200 MHz for 2 V p-p operation. In addition,
the ADL5566 can also deliver 5 V p-p operation under heavy
loads. The internal gain is set at 16 dB, and the part has a noise
figure of 6.5 dB and a RTI of 1.5 nV/√Hz. When comparing noise
figure and distortion performance, this amplifier delivers the
best in category spurious-free dynamic range (SFDR).
The ADL5566 is very flexible in terms of I/O coupling. It can be
ac- or dc-coupled. For dc coupling, the output common-mode
voltage (VCOMx) can be adjusted (using the VCOMx pin) from
1.1 V to 1.8 V output for VCCx at 3.3 V and up to 3 V with VCCx
at 5 V. For the best distortion, the common-mode output should
not go below 1.25 V at VCCx equal to 3.3 V and 1.35 V for 5 V
VCCx operation. Note that the input common-mode voltage
slaves to the VCOMx output voltage when ac-coupled at the
inputs. For dc-coupled inputs, the input common-mode voltage
should also stay between 1.25 V and 1.8 V for a 3.3 V supply and
1.35 V to 3.5 V for a 5 V supply. Note again that, for ac-coupled
applications with series capacitors at the inputs, as in Figure 37,
the output common-mode voltage, VCOMx, sets the commonmode input to the same level. Because of the wide input commonmode range, this part can easily be dc-coupled to many types of
mixers, demodulators, and amplifiers. Forcing a higher input
VCOMx does not affect the output VCOMx in dc-coupled mode.
Note that, if the outputs are ac-coupled (see the ADC Interfacing
section), no external VCOMx adjust is required because the
amplifier common-mode outputs are set at VCCx/2.
Rev. C | Page 14 of 24
Data Sheet
ADL5566
APPLICATIONS INFORMATION
6 (VIN2), and the output pins, Pin 13 (VON2) and Pin 14
(VOP2), are biased by applying a voltage to VCOM2. If
VCOM2 is left open, VCOM2 equals ½ of VCC2. The ADL5566
can be ac-coupled as shown in Figure 36 or can be dc-coupled if
within the specified input and output common-mode voltage
ranges (see the Circuit Description section). To enable the
ADL5566, the ENBL1 and ENBL2 pins must be pulled high.
Pulling the ENBL1/ENBL2 pins low puts the ADL5566 in sleep
mode, reducing the current consumption to 7 mA at ambient.
BASIC CONNECTIONS
Figure 36 shows the basic connections for operating the ADL5566.
Apply a voltage between 3 V and 5 V to the VCC1 and VCC2
pins through a 5.1 nH inductor and decouple the supply side of the
inductor with at least one low inductance, 0.1 μF surface-mount
ceramic capacitor. In addition, decouple the VCOM1 and VCOM2
pins (Pin 21 and Pin 10) using a 0.1 μF capacitor. The ENBL1
and ENBL2 pins (Pin 22 and Pin 9) are tied to their amplifiers
VCC_x pin to enable each amplifier. A differential signal is
applied to Amplifier 1 through Pin 1 (VIN1) and Pin 2 (VIP1)
and to Amplifier 2 through Pin 5 (VIP2) and Pin 6 (VIN2).
Each amplifier has a gain of 16 dB.
A series 5.1 nH inductor can be connected to the VCCx pins with
the VCC decoupling capacitor connected to the VCC bus side (see
Figure 36 and Figure 53). This inductor with the internal
capacitance of the amplifier results in a two pole low-pass
network and reduces the amplifier VCC noise.
The input pins, Pin 1 (VIN1) and Pin 2 (VIP1), and the output
pins, Pin 18 (VON1) and Pin 17 (VOP1), are biased by
applying a voltage to Pin 21 (VCOM1). If VCOM1 is left open,
VCOM1 equals ½ of VCC1. The input pins, Pin 5 (VIP2) and Pin
0.01µF
0.01µF
5.1nH
VCC2
+
VCC
10µF
5.1nH
VCC1
18
11
18
20
EXPOSED PAD
RF
18
0.01µF
VIP1
VIN1
RG
2
1
0.01µF
21
RG
17
VCC
VCC
ENBL1
ENBL2
½ RS
0.01µF
VIP2
VIN2
VCOM1
0.01µF
0.01µF
22
2
ADL5566
1
9
RF
RG
5
6
0.01µF
10
RG
14
VON2
0.01µF
24
VOP2
NC
23
NC
19
NC
16
NC
15
NC
12
NC
8
NC
NC
NC
7
BALANCED
LOAD
0.01µF
3
4
0.01µF
VCOM2
RF
NC
BALANCED
LOAD
VOP1
RF
13
BALANCED
SOURCE
½ RS
0.01µF
NOTES
1. EXPOSED PADDLE IS INTERNALLY CONNECTED TO GND AND MUST BE SOLDERED
TO A LOW IMPEDANCE GROUND PLANE.
Figure 36. Basic Connections
Rev. C | Page 15 of 24
10916-035
½ RS
BALANCED
SOURCE
½ RS
VON1
ADL5566
Data Sheet
VCC
INPUT AND OUTPUT INTERFACING
ADL5566
½ RL
–
+
+
0.1µF
0.1µF
10916-038
R1
30Ω
0.1µF
½
½ RL
ADL5566
AC
½ RL
The single-ended gain configuration of the ADL5566 is dependent
on the source impedance and load, as shown in Figure 40.
+
+
+
0.1µF
0.1µF
½
Figure 39. Single-Ended Input to Differential Output Configuration
ETC1-1-13
R2
+
0.1µF
AC
VCC
50Ω
R2
77Ω
RS
+
+
The ADL5566 can be configured as a differential input to
differential output driver, as shown in Figure 37. The 36 Ω
resistors, R1 and R2, combined with the ETC1-1-13 balun
transformer, provide a 50 Ω input match for the 160 Ω input
impedance. The input and output 0.1 μF capacitors isolate the
VCC/2 bias from the source and balanced load. The load should
equal 200 Ω to provide the expected ac performance (see the
Specifications section).
500Ω
½ RL
–
80Ω
10916-036
0.1µF
5Ω
+
RS
Figure 37. Differential Input to Differential Output Configuration
R2
77Ω
0.1µF
0.1µF
½
½ RL
ADL5566
AC
80Ω
½ RL
5Ω
–
+
0.1µF
+
The differential gain of the ADL5566 is dependent on the source
impedance and load, as shown in Figure 38.
+
+
0.1µF
+
+
R1
0.1µF
500Ω
10916-039
R1
30Ω
500Ω
Figure 40. Single-Ended Input Loading Circuit
+
80Ω
5Ω
+
½ RS
0.1µF
½
ADL5566
AC
80Ω
RL
R MATCH
5Ω
–
+
½ RS
The single-ended gain can be determined by the following two
equations:
+
0.1µF
500Ω
0.1µF
+
AV1
10916-037
0.1µF
Figure 38. Differential Input Loading Circuit
The differential gain can be determined by
500
RL
AV
80 10 RL
R2 131
R2 131
500
R R2
80 S
RS R2
R
RS
RL
R2
MATCH
10 RL
RS R2
R MATCH
GAIN ADJUSTMENT AND INTERFACING
(1)
The effective gain of the ADL5566 can be reduced by adding two
resistors in series with the inputs to reduce the 16 dB gain.
Single-Ended Input to Differential Output
500Ω
80Ω
5Ω
+
½ RS
AC
0.1µF
80Ω
RL
5Ω
–
+
Rev. C | Page 16 of 24
ADL5566
RSHUNT
0.1µF
½ RS
0.1µF
½
RSERIES
500Ω
0.1µF
Figure 41. Gain Adjustment Using a Series Resistor Show
10916-040
RSERIES
+
The ADL5566 can also be configured in a single-ended input to
differential output driver, as shown in Figure 39. In this
configuration, the gain of the part is reduced due to the application
of the signal to only one side of the amplifier. The input and output
0.1 μF capacitors isolate the VCC/2 bias from the source and the
balanced load. R2 is used to match the single-ended input
impedance of the amplifier (131 Ω) with the 50 Ω source. R1 is
selected to balance the input of the amplifier. See the Application
Note AN-0990 for more information on terminating single-ended
inputs. The performance for this configuration is shown in
Figure 16 and Figure 24.
Data Sheet
ADL5566
To find RSERIES for a given AV gain and RL, use the following:
500
RSERIES =
AV
RL
10 + RL
The necessary shunt component, RSHUNT, to match to the source
impedance, RS, can be expressed with the following:
− 80
RSHUNT =
The voltage gain for multiple shunt resistor values are summarized
in Table 5. The source resistance and input impedance need
careful attention when using Equation 5. The reactance of the
input impedance of the ADL5566 and the ac coupling capacitors
must be considered before assuming that they make a negligible
contribution.
–50
500
× RL
AGAIN =
RSERIES + 80 10 + RL
(4)
HD2 3.3V
HD3 3.3V
IMD 3.3V
HD2 5V
HD3 5V
IMD 5V
–55
–60
–65
DISTORTION (dBc)
–70
–75
–80
–85
–90
–95
–100
–105
–110
0
50
100
150
200
250
300
350
400
450
FREQUENCY (MHz)
10M
100M
1G
FREQUENCY (Hz)
10G
Figure 43. IMD, HD2, and HD3 vs. Frequency, AV = 6 dB, 2 V p-p Output,
VPOS = 3.3 and VPOS = 5 V
Figure 42. SDD21, VPOS = 3.3 V, Three Gains, 25°C
Table 5. Differential Gain Adjustment Using Series Resistor
Target Gain (dB)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Actual Gain (dB)
−0.1
+1.2
+2.1
+2.9
+4.1
+5.1
+6.1
+6.9
+8.1
+8.9
+10
+11.1
+12
+12.8
+14
+15.1
+15.8
500
10916-042
–115
–120
10916-041
GAIN (dB)
(5)
(3)
To calculate the AV gain for a given RSERIES and RL, use the following:
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
1M
1
1
1
−
RS 2RSERIES + 160
RS (Ω)
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
50
RSERIES (Ω)1
396.2
344.4
298.3
257.1
220.5
187.8
158.7
132.7
109.6
89
70.6
54.2
39.6
26.6
15
4.8
RSHUNT (Ω)1
52.8
53.1
53.5
54
54.5
55.1
55.8
56.7
57.6
58.7
60
61.4
63.2
65.3
67.9
70.9
50
0
72.7
The resistor values are rounded to the nearest real resistor value.
Rev. C | Page 17 of 24
ADL5566
Data Sheet
ADC INTERFACING
FUNDAMENTAL1 = –7.03dBFS
0 FUNDAMENTAL2 = –7.05dBFS
IMD (2f1 – f2) = –90.53dBc
–15 IMD (2f2 + f1) = –96.81dBc
NOISE FLOOR = –114.703dB
–30
AMPLITUDE (dBFS)
–30
–45
–60
–75
–90
–105
–120
–150
0
6
12
18
24
30
36
42
FREQUENCY (MHz)
48
60
NORMALIZED (dBFS)
Figure 45. Measured Two-Tone Performance of the Circuit in Figure 47 for a
32 MHz and 33 MHz Input Signals
2
1
0
–1
–2
–3
–4
–5
–6
–7
–8
–9
–10
–11
–12
–13
–14
–15
–16
–17
–18
–19
–20
0
20
40
60
80
100
120
FREQUENCY (MHz)
–60
140
160
Figure 46. Measured Relative Frequency Response of the Wideband ADC
Interface Depicted in Figure 47
–75
–90
3
–105
+
4
2
5
6
–120
0
6
12
18
24
30
36
42
48
54
60
FREQUENCY (MHz)
10916-043
–135
–150
54
10916-044
–135
SNR = 74.28dB
FUND FREQ = 32.123MHz
FUND POWER = –1.014dBFS
SECOND HARM = –94.629dBc
THIRD HARM = –95.19dBc
FOURTH HARM = –99.98dBc
FIFTH HARM = –104.971dBc
SIXTH HARM = –107.105dBc
–15
–45
10916-045
0
AMPLITUDE (dBFS)
The ADL5566 is a dual high output linearity amplifier that is
optimized for ADC interfacing. One option of applying the
ADL5566 to drive an ADC is shown in Figure 47. The wideband
1:1 transmission line balun provides a differential input to the
amplifier, and the 36 Ω resistors provide a 50 Ω match to the
source. The ADL5566 is ac-coupled from the input and output
to avoid common-mode loading. A reference voltage is
required to bias the AD9268 inputs and is delivered through
the 200 Ω resistors. These, in parallel with the 400 Ω resistor,
create the low frequency amplifier load of 200 Ω. The 56 nH
inductors and the 56 pF capacitor are used to create a 70 MHz
low-pass filter. The two 25 Ω resistors are added to raise the
ADL5566 output impedance, which reduces peaking when the
filter drives a light load. The two 25 Ω resistors provide isolation to
the switching currents of the ADC sample-and-hold circuitry.
The AD9268 dual ADC presents a 6 kΩ differential load
impedance and requires a 1 V p-p to 2 V p-p input signal to
reach full scale. The system frequency response is shown in
Figure 46. By applying a 2 V p-p, 32 MHz single-tone signal from
the ADL5566 in a gain of 16 dB, an SFDR of 94.6 dBc is achieved.
By applying two half scale signals of 32 MHz and 33 MHz from
the ADL5566 in a gain of 16 dB, an SFDR of 90.5 dBc is
realized.
Figure 44. Measured Single-Tone Performance of the Circuit in Figure 47 for a
32 MHz Input Signal
VCC
36Ω
0.1µF
25Ω
25Ω
+
+
+
50Ω
0.1µF
VIN_1
200Ω
½
VREF
ADL5566
AC
VIP_1
+
+
36Ω
25Ω
–
0.1µF
0.1µF
200Ω
56pF
400Ω
16
SIDE A
25Ω
Figure 47. Wideband ADC Interfacing Example Featuring the AD9268
Rev. C | Page 18 of 24
AD9268
10916-046
ETC1-1
Data Sheet
ADL5566
DC-COUPLED RECEIVER APPLICATION
The ADL5566 is well suited for dc-coupled applications, such
as zero-IF direct conversion receivers. An example receiver
configuration is shown in Figure 48, consisting of the ADL5380
quadrature demodulator and the ADL5566 dual differential
amplifier. This is an ideal combination because of the wide RF
input bandwidth from 400 MHz to 6 GHz, the high linearity of the
ADL5566, and when operating on a 5 V supply, level shifting to
align the common-mode voltage is not required.
performance. When using the ADL5566 as shown in Figure 48,
the OIP3s at the outputs are improved due to the high OIP3 of
the amplifier pair (see Table 6). In a real-world receiver where
blockers are present, it is advantageous to insert a low-pass
filter between the ADL5380 and the ADL5566 to remove
these undesired signals.
If the ADL5566 is followed by an ADC, insert an antialiasing
filter between the ADL5566 and the ADC to prevent broadband
noise from aliasing back in band. For more information on this
interface, see the ADC Interfacing section.
The interface between the ADL5380 and the ADL5566 is
straight forward because the impedance presented by the
ADL5566 is sufficiently high enough to permit directly
connecting the two devices without any degradation in
The cascade of the performance of the circuit shown in Figure 48 is
presented in Table 6.
VS
0.1µF
0.1µF
100pF
100pF
100pF
0.01µF
5.1nH
6
NC
13
24
3
23
ILO
18
IHI
VIP1
VIN1
GND3
2
1
RG
21
RG
17
RFIP
22
9
90°
RFIN
21
0°
10
GND3
1
20
GND1
16
2
15
LOIP
LOIN
100pF
TC1-1-13
VCC
VCC
100pF
ENBL1
ENBL2
RF
RG
5
6
10
RG
QLO
14
VCOM2
0.01µF
24
12
15
NC
8
NC
7
NC
4
16
BALANCED
LOAD
VOP2
0.01µF
3
NC
NC
GND3
NC
17
0.01µF
VON2
RF
GND2
14
GND2
11
GND4
8
GND4
18
VOP1
ADL5566
1
9
GND1
5
BALANCED
LOAD
0.01µF
13
VIP2
0.01µF
22
2
GND3
VIN2
VCOM1
RF
R4
0Ω
QHI
0.01µF
VON1
19
NC
23
NC
100pF
18
20
NC
0Ω
VCC1
18
11
NC
TC1-1-13
VCC
10µF
RF
ENBL
7
+
5.1nH
19
12
4
100pF
VCC2
ADJ
VCC3
VCC2
VCC1
1.5kΩ
0.01µF
10916-052
0.1µF
Figure 48. DC-Coupled Interface Example Featuring the ADL5380
Table 6. Cascade Performance of the ADL5380 and ADL5566
Frequency (MHz)
900
1900
2700
1
HD2 (dBc)
−79.3
−82.2
−80.7
HD3 (dBc)
−84.2
−80.5
−73.9
IF Frequency = 200 MHz, RL = 200 Ω, VOUT = 2 V p-p Composite
OIP3 (dBm) ADL5380 OIP3 (dBm)1 OIP2 (dBm) Voltage Gain (dB)
44.9
26.2
91.8
18.1
40.8
26.5
83.9
18.1
39.6
25.7
75.6
18.1
Output referred IP3 of the ADL5380, PIN = −14 dBm, and RL = 200 Ω.
Rev. C | Page 19 of 24
Power Gain (dB)
12.0
12.0
12.0
ADL5566
Data Sheet
LAYOUT CONSIDERATIONS
High-Q inductive drives and loads, as well as stray transmission
line capacitance in combination with package parasitics, can
potentially form a resonant circuit at high frequencies, resulting
in excessive gain peaking or possible oscillation. If RF transmission
lines connecting the input or output are used, design them such
that stray capacitance at the input/output pins is minimized. In
many board designs, the signal trace widths should be minimal
where the driver/receiver is no more than one-eighth of the wavelength from the amplifier. This nontransmission line configuration
requires that underlying and adjacent ground and low impedance
planes be dropped from the signal lines.
VCC
+
5.1nH
ETC1-1
0.1µF
VIN_1
0.1µF
36Ω
ETC1-1
84.5Ω
+
+
+
50Ω
0.1µF
34.8Ω
½
50Ω
ADL5566
AC
AMPLIFIER 1
+
+
36Ω
ANALYZER
84.5Ω
–
0.1µF
0.1µF
34.8Ω
10916-047
VIP_1
Figure 49. General-Purpose Characterization Circuit
VCC
+
5.1nH
0.1µF
PORT 1
0.1µF
0.1µF
VIN_1
+
+
50Ω
PORT 3
+
50Ω
50Ω
½
ADL5566
36Ω
AC
AC
AMPLIFIER 1
VIP_1
PORT 2
50Ω
–
+
0.1µF
+
0.1µF
50Ω
PORT 4
50Ω
AC
10916-048
AC
Figure 50. Differential Characterization Circuit Using Agilent E8357A Four-Port PNA
VCC
+
2kΩ
0.1µF
ETC1-1
50Ω
5.1nH
VIN_1
0.1µF
0.1µF
+
84.5Ω
ETC1-1
+
+
2kΩ
36Ω
34.8Ω
50Ω
ADL5566
AMPLIFIER 1
AC
ANALYZER
84.5Ω
VIP_1 –
+
+
36Ω
0.1µF
0.1µF
34.8Ω
VCOM
OUTPUT
Figure 51. Distortion Measurement Circuit for Various Common-Mode Voltages
Rev. C | Page 20 of 24
10916-049
INPUT
COMMON-MODE V
ADJUST
Data Sheet
ADL5566
SOLDERING INFORMATION AND RECOMMENDED
LAND PATTERN
Figure 52 shows the recommended land pattern for the ADL5566.
The ADL5566 is contained in a 4 mm × 4 mm LFCSP package,
which has an exposed ground paddle (EPAD). This paddle is
internally connected to the ground of the chip. To minimize
thermal impedance and ensure electrical performance, solder
the paddle to the low impedance ground plane on the printed
circuit board (PCB). To further reduce thermal impedance, it
is recommended that the ground planes on all layers under the
paddle be stitched together with vias.
For more information on land pattern design and layout, refer
to the AN-772 Application Note, A Design and Manufacturing
Guide for the Lead Frame Chip Scale Package (LFCSP).
This land pattern, on the ADL5566 evaluation board, provides a
measured thermal resistance (θJA) of 34.0°C/W. To measure θJA,
the temperature at the top of the LFCSP package is found with
an IR temperature gun. Thermal simulation suggests a junction
temperature 1.5°C higher than the top of package temperature.
With additional ambient temperature and I/O power measurements, θJA can be determined.
EVALUATION BOARD
Figure 53 shows the schematic of the ADL5566 evaluation board.
The board is powered by a single supply in the 3 V to 5 V range.
The power supply is decoupled by 10 µF and 0.1 µF capacitors.
The L1 and L2 inductors decouple the ADL5566 from the power
supply.
Table 7 details the various configuration options of the evaluation
board. Figure 54 and Figure 55 show the component and circuit
side layouts of the evaluation board.
The balanced input and output interfaces are converted to single
ended with a pair of baluns (M/A-COM ETC1-1-13). The baluns
at the input, T1 and T2, provide a 50 Ω single-ended-to-differential
transformation. The output baluns, T3 and T4, and the matching
components are configured to provide a 200 Ω to 50 Ω impedance
transformation with an insertion loss of about 11 dB.
91 MILS
13 MILS
13.7 MILS
39 MILS
19.7 MILS
12 MILS
10916-050
98.4 MILS
157.4 MILS
91 MILS
Figure 52. Recommended Land Pattern
Rev. C | Page 21 of 24
ADL5566
Data Sheet
ENBL_1
VCC
1
2
3
VCOM-1
C6
0.1µF
VPOS
R11
36Ω
C15
0.01µF
R24
0Ω
R2
DNI
R4
0Ω
C1
DNI
R21
0Ω
R12
36Ω
4
NC
NC
NC
VCC1
NC
VCOM1
3
ENBL1
VIP1
C18
0.01µF
VON1 18
ADL5566
VIN2
C16
0.01µF
R13
84.5Ω
R17
34.8Ω
C20
0.01µF
R16
84.5Ω
R20
34.8Ω
7
8
9
10
11
12
C19
0.01µF
R15
84.5Ω
C2
0.1µF
ENBL_2
VCOM-2
R19
34.8Ω
VOP2
DNI
R26
0Ω
2
C11
DNI
C5
0.1µF
1
2
3
C4
0.1µF
DNI
R25
0Ω
DNI
R28
L1
5.1nH
VPOS
VON1
T4
VOP2 14
VON2 13
2
R27
DNI
VON2
NC 15
6
T3
VOP1 17
EXPOSED PADDLE
VIP2
VOP1
R18
34.8Ω
C17
0.01µF
NC 16
5
R14
84.5Ω
VCC
10916-051
T2
C14
0.01µF
2
C10
DNI
NC
VIP2
R9
36Ω
VIIN1
2
19
VCC2
R3
0Ω
1
20
VCOM2
R8
0Ω
21
ENBL2
DNI
R5
0Ω
22
NC
C13
0.01µF
R1
DNI
VIP1
VIN2
DNI
R10
36Ω
NC
T1
23
NC
VIN1
+
L2
5.1nH
2
24
VCC
C21
10µF
C3
0.1µF
C12
DNI
VCC
GND
C7
0.1µF
Figure 53. Evaluation Board Schematic
Table 7. Evaluation Board Configuration Options
Component
VPOS, GND
C5, C7, C21, L1,
L2
VIN1, VIP1, VIP2,
VIN2, R1, R2, R3,
R4, R5, R8, R9,
R10, R11, R12,
R21, R24, C13,
C1, C12, C14,
C15, C16, T1, T2
VOP1, VON1,
VON2, VOP2,
C10, C11, C17,
C18, C19, C20,
R13, R14, R15,
R16, R17, R18,
R19, R20, R25,
R26, R27, R28,
T3, T4
Description
Ground and supply test loops.
Power supply decoupling. The supply decoupling consists of a 10 μF capacitor (C21) and
two 0.1μF capacitors, C5 and C7, connected between the supply lines and ground.
L1 and L2 decouple the ADL5566 from the power supply.
Input interface. The SMA labeled VIN1 is the input to Amplifier 1. T1 is a 1:1
impedance ratio balun to transform a single-ended input into a balanced differential
signal. Removing R3, installing R1 (0 Ω), and installing an SMA connector (VIP1) allow
driving from a differential source. C13 and C14 provide ac coupling. C12 is an
optional bypass capacitor. R9 and R10 provide a differential 50 Ω input termination. The
SMA labeled VIP2 is the input to Amplifier 2. T2 is a 1:1 impedance ratio balun to
transform a single-ended input into a balanced differential signal. Removing R4,
installing R2 (0 Ω), and installing an SMA connector (VIN2) allow driving from a
differential source. C15 and C16 provide ac coupling. C1 is an optional by pass capacitor.
R11 and R12 provide a differential 50 Ω input termination.
Output interface. The SMA labeled VOP1 is the output for Amplifier 1. T3 is a 1:1
impedance ratio balun used to transform a balanced differential signal to a singleended signal. Removing R25, installing R27 (0 Ω), and installing an SMA connector
(VON1) allow differential loading. C10 is an optional bypass capacitor. C17 and C18
provide ac coupling. R13, R14, R17, and R16 are provided for generic placement of
matching components.
The SMA labeled VON2 is the output for Amplifier 2. T4 is a 1:1 impedance ratio balun
used to transform a balanced differential signal to a single-ended signal. Removing R26,
installing R28 (0 Ω), and installing an SMA connector (VOP2) allow differential loading.
C11 is an optional bypass capacitor. C19 and C20 provide ac coupling. R15, R16, R19,
and R20 are provided for generic placement of matching components.
The evaluation board is configured to provide a 200 Ω to 50 Ω impedance
transformation with an insertion loss of 11 dB.
Rev. C | Page 22 of 24
Default Condition
VPOS, GND = installed
C21 = 10 μF (Size D),
C5, C7 = 0.1 μF (Size 0402),
L1, L2 = 5.1 nH (Size 0603)
VIN1, VIP2 = installed,
VIP1, VIN2 = not installed,
R1, R2 = DNI,
R3, R4, R5, R8, R21, R24 = 0 Ω
(Size 0402),
R9, R10, R11, R12 = 36 Ω (Size 0402),
C13, C14, C15, C16 = 0.01 μF
(Size 0402),
C1, C12 = DNI,
T1, T2 = ETC1-1-13 (M/A-COM)
VOP1, VON2 = installed,
VON1, VOP2 = not installed,
R13, R14, R15, R16 = 84.5 Ω
(Size 0402),
R17, R18, R19, R20 = 34.8 Ω
(Size 0402),
R25, R26 = 0 Ω (Size 0402),
R27, R28 = DNI (Size 0402),
C10, C11 = DNI (Size 0402),
C17, C18 = 0.01 μF (Size 0402),
C19, C20 = 0.01 μF (Size 0402),
T3, T4 = ETC1-1-13 (M/A-COM)
Data Sheet
Component
ENBL_1,
ENBL_2, C3, C4
Description
Device enable. ENBL_1 is the enable for Amplifier 1. Connecting a jumper between
Pin 2 and VPOS enables Amplifier 1. C3 is a bypass capacitor. ENBL_2 is the enable for
Amplifier 2. Connecting a jumper between Pin 2 and VPOS enables Amplifier 2. C4 is
a bypass capacitor.
Common-mode voltage interface. VCOM1 is the common-mode interface for
Amplifier 1. A voltage applied to this pin sets the common-mode voltage of the output
of Amplifier 1. VCOM2 is the common-mode interface for Amplifier 2. A voltage applied
to this pin sets the common-mode voltage of the output of Amplifier 2. Typically
decoupled to ground with a 0.1 µF capacitor (C2 and C6). With no reference applied,
input and output common mode float to midsupply (VCC/2).
Default Condition
ENBL_1, ENBL_2 = installed,
C3, C4 = 0.1 µF (Size 0402)
VCOM-1, VCOM-2 = installed
C2, C6 = 0.1 µF (Size 0402)
10916-055
10916-054
VCOM-1,
VCOM-2, C2, C6
ADL5566
Figure 55. Layout of Evaluation Board, Circuit Side
Figure 54. Layout of Evaluation Board, Component Side
Rev. C | Page 23 of 24
ADL5566
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.20
1
0.50
BSC
2.44
2.30 SQ
2.16
EXPOSED
PAD
13
TOP VIEW
0.80
0.75
0.70
SIDE VIEW
PKG-003994/5111
SEATING
PLANE
0.50
0.40
0.30
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
24
19
18
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8
09-07-2018-B
PIN 1
INDICATOR
AREA
4.10
4.00 SQ
3.90
Figure 56. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADL5566ACPZ-R7
ADL5566-EVALZ
1
Temperature Range
−40°C to +85°C
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP], 7” Tape and Reel
Evaluation Board
Z = RoHS Compliant Part.
©2012–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10916-0-8/19(C)
Rev. C | Page 24 of 24
Package Option
CP-24-14
工商网监
湘ICP备2023018690号
