Dual Channel, High IP3, 100 MHz to 6 GHz Active Mixer ADL5802
FEATURES
Power conversion gain of 1.6 dB Wideband RF, LO, and IF ports SSB noise figure of 11 dB Input IP3 of 28 dBm Input P1dB of 12 dBm Typical LO drive of 0 dBm Low LO leakage Single supply operation: 5 V @ 240 mA Exposed paddle, 4 mm × 4 mm, 24-lead LFCSP package
FUNCTIONAL BLOCK DIAGRAM
VPOS RF1+ RF1– GND RF2+ RF2–
24 23 22 21 20 19
GND GND OP1+ OP1– GND VPOS
1 2 3 4
18 17 16 15 14
GND GND OP2+ OP2– GND VPOS
5 6
APPLICATIONS
Cellular base station receivers Main and diversity receiver designs Radio link downconverters
ADL5802
IP3 BIAS
13
7
8
9
10
11
12
ENBL GND LOIP LOIN GND VSET
Figure 1.
GENERAL DESCRIPTION
The ADL5802 uses high linearity, double-balanced, active mixer cores with integrated LO buffer amplifiers to provide high dynamic range frequency conversion from 100 MHz to 6 GHz. The mixers benefit from a proprietary linearization architecture that provides enhanced input IP3 performance when subject to high input levels. A bias adjust feature allows the input linearity, SSB noise figure, and dc current to be optimized using a single control pin. The high input linearity allows the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in degradation in dynamic performance. The balanced active mixer arrangement provides superb LO to RF and LO to IF leakage, typically better than −30 dBm. The IF outputs are designed for a 200 Ω source impedance and provide a typical voltage conversion gain of 7.6 dB when loaded into a 200 Ω load. The ADL5802 is fabricated using a SiGe high performance IC process. The device is available in a compact 4 mm × 4 mm, 24-lead LFCSP package and operates over a −40°C to +85°C temperature range. An evaluation board is also available.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registeredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.461.3113 ©2009 Analog Devices, Inc. All rights reserved.
07882-001
ADL5802 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 5 ESD Caution .................................................................................. 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Downconverter Mode Using a Broadband Balun .................... 7 Downconverter Mode Using a Johanson 2.7 GHz Balun ..... 12 Downconverter Mode Using a Johanson 3.5 GHz Balun ..... 15 Downconverter Mode Using a Johanson 5.7 GHz Balun ..... 18 Spur Performance ........................................................................21 Circuit Description..........................................................................24 LO Amplifier and Splitter...........................................................24 RF Voltage to Current (V-to-I) Converter ...............................24 Mixer Cores ..................................................................................24 Mixer Load ...................................................................................24 Bias Circuit ...................................................................................24 Applications Information ...............................................................25 Basic Connections .......................................................................25 RF and LO Ports ..........................................................................25 IF Port ...........................................................................................26 Evaluation Board .............................................................................27 Outline Dimensions ........................................................................29 Ordering Guide............................................................................29
REVISION HISTORY
11/09—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
ADL5802 SPECIFICATIONS
VS = 5 V, VSET = 4 V, T A = 25°C, fLO = (f RF − 153) MHz, LO power = 0 dBm, Z0 1 = 50 Ω, unless otherwise noted. Table 1. Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage2 LO INTERFACE LO Power Return Loss Input Impedance LO Frequency Range POWER INTERFACE Supply Voltage Quiescent Current Disable Current Enable Time Disable Time DYNAMIC PERFORMANCE at fRF = 900 MHz/1900 MHz Power Conversion Gain3
Voltage Conversion Gain4 SSB Noise Figure SSB Noise Figure Under Blocking5 Input Third Order Intercept6 Input Second Order Intercept7 Input 1 dB Compression Point LO to IF Output Leakage LO to RF Input Leakage RF to IF Output Isolation RFI1 to RFI2 Channel Isolation IF/2 Spurious8 IF/3 Spurious8 IF/2 Spurious8 IF/3 Spurious8 DYNAMIC PERFORMANCE at fRF = 2500 MHz9 Power Conversion Gain10 Voltage Conversion Gain4 SSB Noise Figure SSB Noise Figure Under Blocking11 Input Third Order Intercept6 Test Conditions/Comments Tunable to >20 dB over a limited bandwidth 100 Differential impedance, f = 200 MHz Can be matched externally to 3000 MHz Externally generated 240 LF 4.75 −10 VS 0 18 50 600 5.25 +10 Min Typ 18 50 6000 Max Unit dB Ω MHz Ω MHz V dBm dB Ω MHz V mA mA ns ns dB dB dB dB dB dB dB dB dBm dBm dBm dBm dBm dBm dBm dBm dBc dBc dBc dBc dBc dBc dB dB dB dB dBm
100 4.75 Resistor programmable ENBL pin low Time from ENBL pin low to power-up Time from ENBL pin high to power-down fRF = 900 MHz fRF = 1900 MHz fRF = 900 MHz fRF = 1900 MHz fCENT = 900 MHz fCENT = 1900 MHz fCENT = 900 MHz fCENT = 1900 MHz fCENT = 890 MHz fCENT = 1890 MHz fCENT = 890 MHz fCENT = 1890 MHz fRF = 900 MHz fRF = 1900 MHz Unfiltered IF output 5 220 170 182 28 1.5 1.6 7.5 7.6 10 11 18 22 26 28 60 45 12 12 −35 −30 25 45 −68 −67 −53 −59 −0.5 5.67 11.5 18 30
6000 5.25 300
0 dBm input power, fRF = 900 MHz 0 dBm input power, fRF = 900 MHz 0 dBm input power, fRF = 1900 MHz 0 dBm input power, fRF = 1900 MHz
fCENT = 2145 MHz fCENT = 2500 MHz
Rev. 0 | Page 3 of 32
ADL5802
Parameter Input Second Order Intercept7 Input 1 dB Compression Point LO to IF Output Leakage LO to RF Input Leakage RF to IF Output Isolation RFI1 to RFI2 Channel Isolation IF/2 Spurious8 IF/3 Spurious8 DYNAMIC PERFORMANCE at fRF = 3500 MHz12 Power Conversion Gain13 Voltage Conversion Gain4 SSB Noise Figure SSB Noise Figure Under Blocking14 Input Third Order Intercept5 Input Second Order Intercept7 Input 1 dB Compression Point LO to IF Output Leakage LO to RF Input Leakage RF to IF Output Isolation RFI1 to RFI2 Channel Isolation IF/2 Spurious8 IF/3 Spurious8 DYNAMIC PERFORMANCE at fRF = 5500 MHz15 Power Conversion Gain16 Voltage Conversion Gain4 SSB Noise Figure SSB Noise Figure Under Blocking17 Input Third Order Intercept5 Input Second Order Intercept7 Input 1 dB Compression Point LO to IF Output Leakage LO to RF Input Leakage RF to IF Output Isolation RFI1 to RFI2 Channel Isolation IF/2 Spurious8 IF/3 Spurious8
1 2
Test Conditions/Comments fCENT = 2500 MHz Unfiltered IF output
Min
0 dBm input power 0 dBm input power
Typ 47 13 36 31 26 42 −52 −56 −0.5 5.5 12.5 18 25 39 13 33 28 31 39 −46 −63 −3 5.67 14 17 23 35 13 42 27 50 33 −49 −64
Max
Unit dBm dBm dBm dBm dBc dBc dBc dBc dB dB dB dB dBm dBm dBm dBm dBm dBc dBc dBc dBc dB dB dB dB dBm dBm dBm dBm dBm dBc dBc dBc dBc
fCENT = 3500 MHz fCENT = 3500 MHz fCENT = 3500 MHz Unfiltered IF output
0 dBm input power 0 dBm input power
fCENT = 5800 MHz fCENT = 5500 MHz fCENT = 5500 MHz Unfiltered IF output
0 dBm input power 0 dBm input power
Z0 is the characteristic impedance assumed for all measurements and the PCB. Supply voltage must be applied from an external circuit through choke inductors. 3 Excluding 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (TC1-1-13M+), and PCB loss. 4 ZSOURCE = 50 Ω, differential; ZLOAD = 200 Ω, differential 5 dBm; ZSOURCE is the impedance of the source instrument; ZLOAD is the load impedance at the output. 5 fRF1 = fCENT, fBLOCKER = (fCENT − 5) MHz, fLO = (fCENT − 153) MHz, blocker level = 0 dBm. 6 fRF1 = (fCENT − 1) MHz, fRF2 = fCENT, fLO = (fCENT − 153) MHz, each RF tone at −10 dBm. 7 fRF1 = fCENT, fRF2 = (fCENT + 100) MHz, fLO = (fCENT − 153) MHz, each RF tone at −10 dBm. 8 For details, see the Spur Performance section. 9 VS = 5 V, VSET = 4.5 V, TA = 25°C, fLO = (fRF − 211) MHz, LO power = 0 dBm, Z0 = 50 Ω. 10 Excluding 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (2500BL14M050), and PCB loss. 11 fRF1 = fCENT, fBLOCKER = (fCENT − 5) MHz, fLO = (fCENT − 235) MHz, blocker level = 0 dBm. 12 VS = 5 V, VSET = 5 V, TA = 25°C, fLO = (fRF − 153) MHz, LO power = 0 dBm, Z0 = 50 Ω. 13 Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (3600BL14M050), and PCB loss. 14 fRF1 = fCENT, fBLOCKER = (fCENT − 5) MHz, fLO = (fCENT − 153) MHz, blocker level = −20 dBm. 15 VS = 5 V, VSET = 4.8 V, TA = 25°C, fLO = (fRF − 380) MHz, LO power = 0 dBm, Z0 = 50 Ω. 16 Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (5400BL15B050), and PCB loss. 17 fRF1 = fCENT, fBLOCKER = (fCENT − 5) MHz, fLO = (fCENT − 300) MHz, blocker level = −20 dBm.
Rev. 0 | Page 4 of 32
ADL5802 ABSOLUTE MAXIMUM RATINGS
Table 2. Parameter Supply Voltage, VPOS VSET, ENBL OP1+, OP1−, OP2+, OP2− RF Input Power Internal Power Dissipation θJA (Exposed Paddle Soldered Down)1 θJC (at Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range
1
Rating 5.5 V 5.5 V 5.5 V 20 dBm 1.6 W 26.5°C/W 8.7°C/W 150°C −40°C to +85°C −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
As measured on the evaluation board. For details, see the Evaluation Board section.
Rev. 0 | Page 5 of 32
ADL5802 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
24 23 22 21 20 19 VPOS RF1+ RF1– GND RF2+ RF2–
GND GND OP1+ OP1– GND VPOS
1 2 3 4 5 6
PIN 1 INDICATOR
ADL5802
TOP VIEW (Not to Scale)
18 17 16 15 14 13
GND GND OP2+ OP2– GND VPOS
ENBL 7 GND 8 LOIP 9 LOIN 10 GND 11 VSET 12
NOTES 1. THERE IS AN EXPOSED PADDLE THAT MUST BE SOLDERED TO GROUND.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Function GND Device Common (DC Ground). 1, 2, 5, 8, 11, 14, 17, 18, 21 3, 4 OP1+, OP1− Channel 1 Mixer Differential Output Terminals. Bias must be applied through pull-up choke inductors or the center tap of the IF transformer. 6, 13, 24 VPOS Positive Supply Voltage. 5.0 V nominal. 7 ENBL Device Enable. Pull low or leave disconnected to enable the device; pull high to disable the device. 9, 10 LOIP, LOIN Differential LO Input Terminals. Internally matched to 50 Ω; must be ac-coupled. 12 VSET High Input IP3 Bias Control. For high input IP3 performance, apply ~4 V to 5 V. Improved noise figure (NF) performance and lower supply current can be set by applying ~2 V to 3 V to the VSET pin. A resistor can be connected to the supply to raise the voltage, whereas a resistor to GND lowers the voltage. 15, 16 OP2−, OP2+ Channel 2 Mixer Differential Output Terminals. Bias must be applied through pull-up choke inductors or the center tap of the IF transformer. 19, 20 RF2−, RF2+ Differential RF Input Terminals for Channel 2. Internally matched to 50 Ω; must be ac-coupled. 22, 23 RF1−, RF1+ Differential RF Input Terminals for Channel 1. Internally matched to 50 Ω; must be ac-coupled. EPAD Exposed Paddle. Must be soldered to ground.
Rev. 0 | Page 6 of 32
07882-002
ADL5802 TYPICAL PERFORMANCE CHARACTERISTICS
DOWNCONVERTER MODE USING A BROADBAND BALUN
VS = 5 V, TA = 25°C, VSET = 4 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement.
6 5 4 3 TA = –40°C TA = +25°C
GAIN (dB)
3.5 33.30 4.0 39.96
GAIN (dB)
2 1 0 –1 –2 –3 –4 0 500 1000 1500 2000 2500 RF FREQUENCY (MHz) 3000
07882-003
2.5
TA = +85°C
2.0
GAIN = 900MHz GAIN = 1900MHz INPUT IP3 = 900MHz INPUT IP3 = 1900MHz
19.98
13.32
1.5
6.66
3500
1.0 –15
–10
–5
0 5 LO POWER (dBm)
10
15
Figure 3. Power Conversion Gain vs. RF Frequency
4.0 3.5
Figure 6. Power Conversion Gain and Input IP3 vs. LO Power
100 MEAN = 1.5 SD = 0.039 80
3.0 2.5
FREQUENCY (%)
GAIN (dB)
60
2.0 1.5
900MHz
40
1900MHz 1.0
20
07882-004
07882-007
0.5 0 0 50 100 150 IF FREQUENCY (MHz) 200
1.00
1.08
1.16
1.24
1.32
1.40
1.48
1.56
1.64
1.72
1.80
1.88
GAIN (dB)
Figure 4. Power Conversion Gain vs. IF Frequency
3.0 0.30
2.5
Figure 7. Power Conversion Gain Distribution
2.5
0.25
2.0
TA = –40°C
2.0
0.20
SUPPLY CURRENT (A)
TA = +25°C
GAIN (dB)
1.5
0.15
GAIN (dB)
1.5 TA = +85°C 1.0
1.0
0.10
0.5
07882-005
0 0 1 2 3 VSET (V) 4 5 6
0
0 4.7
4.8
4.9
5.0 SUPPLY (V)
5.1
5.2
5.3
Figure 5. Power Conversion Gain and IPOS vs. VSET
Figure 8. Power Conversion Gain vs. Supply Voltage
Rev. 0 | Page 7 of 32
07882-008
GAIN = 900MHz GAIN = 1900MHz IPOS = 900MHz IPOS = 1900MHz
0.05
0.5
1.96
250
0
07882-006
0
INPUT IP3 (dBm)
3.0
26.64
ADL5802
40 TA = +25°C 35 TA = +85°C 30
INPUT IP3 (dBm)
80 TA = –40°C 70 60 TA = +85°C
INPUT IP2 (dBm)
25 TA = –40°C 20 15 10
07882-009
50 40 30 20
TA = +25°C
0 0 500 1000 1500 2000 2500 RF FREQUENCY (MHz) 3000
0 0 500 1000 1500 2000 2500 RF FREQUENCY (MHz) 3000
3500
3500
Figure 9. Input IP3 vs. RF Frequency
40
Figure 12. Input IP2 vs. RF Frequency
80 70
35
60
INPUT IP3 (dBm)
900MHz
30
1900MHz
INPUT IP2 (dBm)
50 40 30 20
1900MHz
25
900MHz
20
15
07882-010
10 0 50 100 150 IF FREQUENCY (MHz) 200
0 0 50 100 150 IF FREQUENCY (MHz) 200
250
250
Figure 10. Input IP3 vs. IF Frequency
35 30 25
INPUT IP3 (dBm)
80 70 60
Figure 13. Input IP2 vs. IF Frequency
900MHz
INPUT IP2 (dBm)
50 40 30 20
07882-014
20 15 10 5 0 0 1 2 3 VSET (V) 4 5 6 INPUT IP3 = 900MHz INPUT IP3 = 1900MHz NF = 900MHz NF = 1900MHz
1900MHz
07882-011
10 0 0 1 2 3 VSET (V) 4 5 6
Figure 11. Input IP3, Noise Figure vs. VSET
Figure 14. Input IP2 vs. VSET
Rev. 0 | Page 8 of 32
07882-013
10
07882-012
5
10
ADL5802
20 18 16
20 25
INPUT P1dB (dBm)
NOISE FIGURE (dB)
14 12 10 8 6 4 2 0 0
TA = –40°C
TA = +85°C
15 NF vs. IF, RF = 1900MHz
TA = +25°C
10 NF vs. IF, RF = 900MHz 5
07882-015
0 0 100 200 300 400 500 IF FREQUENCY (MHz) 600
500
1000 1500 2000 2500 RF FREQUENCY (MHz)
3000
3500
700
Figure 15. Input P1dB vs. RF Frequency
20 18 16
NOISE FIGURE (dB)
Figure 18. SSB Noise Figure vs. IF Frequency
30
25
INPUT P1dB (dBm)
14 900MHz 12 10 8 6 4
07882-016
20 NF, RF 1846MHz, IF 153MHz, BLOCKER 1841MHz 15
1900MHz
10 NF, RF 951MHZ, IF 153MHz, BLOCKER 946MHz 5
07882-019
2 0 0 50 100 150 IF FREQUENCY (MHz) 200
250
0 –30
–25
–20
–15 –10 –5 BLOCKER LEVEL (dBm)
0
5
10
Figure 16. Input P1dB vs. IF Frequency
18 16
20 18
Figure 19. SSB Noise Figure vs. Blocker Level
NOISE FIGURE (dB)
14 12 10 8 6 4 TA = +25°C
TA = +85°C
16
NOISE FIGURE (dB)
14 12 10 900MHz 8 6 4 1900MHz
TA = –40°C
07882-017
2 0 0 500 1000 1500 2000 2500 RF FREQUENCY (MHz) 3000
2 0 –15
3500
–10
–5
0 5 LO LEVEL (dBm)
10
15
Figure 17. SSB Noise Figure vs. RF Frequency
Figure 20. SSB Noise Figure vs. LO Drive
Rev. 0 | Page 9 of 32
07882-020
07882-018
ADL5802
–0
RF RETURN LOSS 5500MHz BALUN: 5400BL15B050 3pF INPUT CAPACITANCE
–10 –15 –20
–5 –10
LO TO IF LEAKAGE (dBm)
RETURN LOSS (dB)
–25 –30 –35 –40 –45 –50
TA = –40°C TA = +25°C
–15 –20 –25 –30 –35
RF RETURN LOSS 900MHz AND 1900MHz BALUN: TC1-1-13M+ 100pF INPUT CAPACITANCE RF RETURN LOSS 3500MHz BALUN: 3600BL14M050 1.5pF INPUT CAPACITANCE RF RETURN LOSS 2500MHz BALUN: 2500BL14M050 3pF INPUT CAPACITANCE
TA = +85°C
07882-021
–55 –60 0 500 1000 1500 2000 2500 LO FREQUENCY (MHz) 3000
–40 0 1000 2000 3000 4000 5000 FREQUENCY (MHz) 6000
7000
3500
Figure 21. RF Return Loss Measured Differentially at the RF Port
0
LO RETURN LOSS 2500MHz BALUN: 2500BL14M050 3pF LO RETURN LOSS 5500MHz BALUN: INPUT CAPACITANCE 5400BL15B050 3pF INPUT CAPACITANCE
Figure 24. LO to IF Leakage vs. LO Frequency
–10 –15 –20
–5
LO TO RF LEAKAGE (dBm)
TA = +85°C –25 TA = +25°C –30 –35 –40 –45 –50 TA = –40°C
RETURN LOSS (dB)
–10
–15
–20
LO RETURN LOSS BALUN: TC1-1-13M+ 100pF INPUT CAPACITANCE
–25
07882-022
LO RETURN LOSS 3500MHz BALUN: 3600BL14M050 1.5pF INPUT CAPACITANCE
–55 –60 0 500 1000 1500 2000 2500 LO FREQUENCY (MHz) 3000
–30 0 1000 2000 3000 4000 5000 FREQUENCY (MHz) 6000
7000
3500
Figure 22. LO Return Loss Measured Differentially at the LO Port
500 8
0
Figure 25. LO to RF Leakage vs. LO Frequency
RF TO IF OUTPUT ISOLATION (dBc)
400
6
CAPACITANCE (pF)
–10
RESISTANCE (Ω)
–20 TA = +25°C –30 TA = +85°C
300 RESISTANCE
4
200
2
–40 TA = –40°C –50
07882-026
CAPACITANCE 100 0
07882-023
0 10
100 IF FREQUENCY (MHz)
1000
–2 3000
–60 0 500 1000 1500 2000 2500 RF FREQUENCY (MHz) 3000
3500
Figure 23. IF Differential Output Impedance (R Parallel C Equivalent)
Figure 26. RF to IF Output Isolation vs. RF Frequency
Rev. 0 | Page 10 of 32
07882-025
07882-024
ADL5802
70
CHANNEL-TO-CHANNEL ISOLATION (dB)
65 60 55 50 45 40 35 30 25 20 0 500 1000 1500 2000 2500 RF FREQUENCY (MHz) 3000
07882-027
TA = –40°C TA = +25°C
TA = +85°C
3500
Figure 27. RF Channel Isolation
Rev. 0 | Page 11 of 32
ADL5802
DOWNCONVERTER MODE USING A JOHANSON 2.7 GHZ BALUN
VS = 5 V, TA = 25°C, VSET = 4.5 V, IF = 211 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise noted. Insertion loss of input and output baluns (2500BL14M050, TC4-1W+) is included in the gain measurement.
5 4
30 35
3 2
GAIN (dB)
25
1 0 –1 –2 –3 –4 –5 1900
TA = –40°C TA = +25°C
INPUT IP3 (dBm)
20 15 10 5 0 0 1
INPUT IP3
TA = +85°C
NOISE FIGURE
07882-028
2100
2300 2500 2700 RF FREQUENCY (MHz)
2900
3100
2
3 VSET (V)
4
5
6
Figure 28. Power Conversion Gain vs. RF Frequency
5 4 3 2 IPOS 0.30 0.27 0.24 0.21 0.18 GAIN 0.15 0.12 0.09 0.06 0.03 0 0 1 2 3 VSET (V) 4 5 6
07882-029
Figure 31. Input IP3, Noise Figure vs. VSET
60
55
SUPPLY CURRENT (A)
TA = +85°C
INPUT IP2 (dBm)
50
TA = –40°C
GAIN (dB)
1 0 –1 –2 –3 –4 –5
45 TA = +25°C 40
35
07882-032
30 1900
2100
2300 2500 2700 RF FREQUENCY (MHz)
2900
3100
Figure 29. Power Conversion Gain and IPOS vs. VSET
35 30 46 25 44 TA = –40°C 20 15 10 5 0 1900 TA = +85°C 50 TA = +25°C 48
Figure 32. Input IP2 vs. RF Frequency
INPUT IP3 (dBm)
INPUT IP2 (dBm)
42 40 38 36 34
07882-030
32 30 0 1 2 3 VSET (V) 4 5 6
2100
2300 2500 2700 RF FREQUENCY (MHz)
2900
3100
Figure 30. Input IP3 vs. RF Frequency
Figure 33. Input IP2 vs. VSET
Rev. 0 | Page 12 of 32
07882-033
07882-031
ADL5802
15 TA = +25°C 14 TA = +85°C
0 –5 –10
13
LO TO IF LEAKAGE (dBm)
INPUT P1dB (dBm)
–15 –20 –25 –30 –35 –40 TA = +25°C TA = +85°C 2100 2300 2500 2700 2900
07882-037
TA = –40°C 12
11
TA = –40°C
10
07882-034
9
–45 –50 1900
8 1900
2100
2300 2500 2700 RF FREQUENCY (MHz)
2900
3100
3100
LO FREQUENCY (MHz)
Figure 34. Input P1dB vs. RF Frequency
20 18 16 14
NOISE FIGURE (dB)
–30 –31
Figure 37. LO to IF Leakage vs. LO Frequency
TA = +85°C TA = +25°C –32
TA = +85°C
TA = +25°C
LO TO RF LEAKAGE (dBm)
–33 –34 –35 –36 –37 –38
TA = –40°C
12 10 8 6 4
07882-035
TA = –40°C
2 0 1800
–39 –40 1900
2000
2200 2400 2600 RF FREQUENCY (MHz)
2800
3000
2100
2300 2500 2700 LO FREQUENCY (MHz)
2900
3100
Figure 35. SSB Noise Figure vs. RF Frequency
30
–21
Figure 38. LO to RF Leakage vs. LO Frequency
25
RF TO IF OUTPUT ISOLATION (dBc)
–23 –25 –27 –29 –31 –33 –35 1900 TA = +85°C TA = –40°C TA = +25°C
NOISE FIGURE (dB)
20
15
NF, RF 2145MHz, IF 230MHz, BLOCKER 2140MHz
10
0 –60
07882-036
–50
–40
–30
–20
–10
0
10
2100
BLOCKER LEVEL (dBm)
2300 2500 2700 RF FREQUENCY (MHz)
2900
3100
Figure 36. SSB Noise Figure vs. Blocker Level
Figure 39. RF to IF Output Isolation vs. RF Frequency
Rev. 0 | Page 13 of 32
07882-039
5
07882-038
ADL5802
50
CHANNEL-TO-CHANNEL ISOLATION (dB)
48 46 44 42 40 TA = +25°C 38 36 34 32 30 1900
07882-040
TA = –40°C
TA = +85°C
2100
2300 2500 2700 RF FREQUENCY (MHz)
2900
3100
Figure 40. RF Channel Isolation
Rev. 0 | Page 14 of 32
ADL5802
DOWNCONVERTER MODE USING A JOHANSON 3.5 GHZ BALUN
VS = 5 V, TA = 25°C, VSET = 5 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise noted. Insertion loss of input and output baluns (3600BL14M050, TC4-1W+) is included in the gain measurement.
5 4 3 2
GAIN (dB)
20 INPUT IP3 25
1 0 –1 –2
TA = –40°C TA = +25°C
INPUT IP3 (dBm)
15
NOISE FIGURE 10
TA = +85°C –3 –4 –5 2900
07882-041
5
07882-044
0 0 1 2 3 VSET (V) 4 5 6
3100
3300 3500 3700 RF FREQUENCY (MHz)
3900
4100
Figure 41. Power Conversion Gain vs. RF Frequency
5 4 3 2 IPOS 0.30 0.27 0.24
50 48 46
Figure 44. Input IP3, Noise Figure vs. VSET
SUPPLY CURRENT (A)
0.21 0.18 0.15
44
INPUT IP2 (dBm)
TA = –40°C
GAIN (dB)
1 0 GAIN –1 –2 –3 –4 –5 0 1 2 3 VSET (V) 4 5 6
42 40 38 36 34 TA = +85°C TA = +25°C
0.12 0.09 0.06
07882-042
0.03 0
32 30 2900
3100
3300 3500 3700 RF FREQUENCY (MHz)
3900
4100
Figure 42. Power Conversion Gain and IPOS vs. VSET
30 TA = +85°C TA = +25°C 25 TA = –40°C 48 46 44 50
Figure 45. Input IP2 vs. RF Frequency
INPUT IP3 (dBm)
INPUT IP2 (dBm)
20
42 40 38 36 34
15
10
5
07882-043
32 30 0 1 2 3 VSET (V) 4 5 6
0 2900
3100
3300 3500 3700 RF FREQUENCY (MHz)
3900
4100
Figure 43. Input IP3 vs. RF Frequency
Figure 46. Input IP2 vs. VSET
Rev. 0 | Page 15 of 32
07882-046
07882-045
ADL5802
15 TA = +25°C 14 TA = +85°C
–25 –20
13
LO TO IF LEAKAGE (dBm)
INPUT P1dB (dBm)
–30 TA = +25°C –35 TA = –40°C TA = +85°C
12 TA = –40°C 11
–40
10
07882-047
8 2900
3100
3300 3500 3700 RF FREQUENCY (MHz)
3900
4100
–50 2900
3100
3300
3500
3700
3900
4100
LO FREQUENCY (MHz)
Figure 47. Input P1dB vs. RF Frequency
20 18 16
NOISE FIGURE (dB)
Figure 50. LO to IF Leakage vs. LO Frequency
–20 –22
TA = +85°C
–24
LO TO RF LEAKAGE (dBm)
14 12 10 TA = –40°C 8 6 4
07882-048
–26 –28 –30 –32 –34 –36 –38 –40 2900 3100
TA = –40°C
TA = +25°C
TA = +25°C
TA = +85°C
2 0 2700
2900
3100
3300 3500 3700 3900 RF FREQUENCY (MHz)
4100
4300
3300 3500 3700 LO FREQUENCY (MHz)
3900
4100
Figure 48. SSB Noise Figure vs. RF Frequency
45 40 35
NOISE FIGURE (dB)
Figure 51. LO to RF Leakage vs. LO Frequency
–10 –15 –20 –25 –30 –35 –40
07882-052
30 25 20 15 10 5 0 –60
07882-049
NF, RF 3805MHz, IF 300MHz, BLOCKER 3800MHz
RF TO IF OUTPUT ISOLATION (dBc)
TA = –40°C TA = +25°C TA = +85°C
–45 –50 2900
–50
–40
–30
–20
–10
0
10
3100
3300
3500
3700
3900
4100
BLOCKER LEVEL (dBm)
RF FREQUENCY (MHz)
Figure 49. SSB Noise Figure vs. Blocker Level
Figure 52. RF to IF Output Isolation vs. RF Frequency
Rev. 0 | Page 16 of 32
07882-051
07882-050
9
–45
ADL5802
50
CHANNEL-TO-CHANNEL ISOLATION (dB)
48 46 44 42 40 38 36 34 32 30 2900
07882-053
TA = +25°C
TA = –40°C
TA = +85°C
3100
3300 3500 3700 RF FREQUENCY (MHz)
3900
4100
Figure 53. RF Channel Isolation
Rev. 0 | Page 17 of 32
ADL5802
DOWNCONVERTER MODE USING A JOHANSON 5.7 GHZ BALUN
VS = 5 V, TA = 25°C, VSET = 4.8 V, IF = 380 MHz, as measured using a typical circuit schematic with low-side LO, unless otherwise noted. Insertion loss of input and output baluns (5400BL15B050, TC4-1W+) is included in the gain measurement.
25
2
30
20
0 TA = –40°C TA = +85°C
24
–2
15
18
–4 TA = +25°C –6
07882-054
10
NOISE FIGURE
12
5
6
07882-057
07882-059
–8 4900
5100
5300 5500 5700 RF FREQUENCY (MHz)
5900
6100
0 0 1 2 3 VSET (V) 4 5 6
0
Figure 54. Power Conversion Gain vs. RF Frequency
5 4 3 2 0.30 0.27 0.24
60 55 50
Figure 57. Input IP3, Noise Figure vs. VSET
SUPPLY CURRENT (A)
0.21 IPOS 0.18 0.15 0.12 0.09 GAIN 0.06
45
INPUT IP2 (dBm)
TA = +85°C TA = +25°C
GAIN (dB)
1 0 –1 –2 –3 –4 –5 0 1 2
40 35 30 25 20 TA = –40°C
07882-055
0.03 0 3 VSET (V) 4 5 6
15 10 4900
5100
5300 5500 5700 RF FREQUENCY (MHz)
5900
Figure 55. Power Conversion Gain and IPOS vs. VSET
30 TA = –40°C
50
Figure 58. Input IP2 vs. RF Frequency
25
45
INPUT IP3 (dBm)
TA = +85°C
INPUT IP2 (dBm)
20
TA = +25°C
40
15
35
10
30
5
07882-056
25
0 4900
5100
5700 5300 5500 RF FREQUENCY (MHz)
5900
6100
20 1.5
2.0
2.5
3.0
3.5 4.0 VSET (V)
4.5
5.0
5.5
Figure 56. Input IP3 vs. RF Frequency
Figure 59. Input IP2 vs. VSET
Rev. 0 | Page 18 of 32
07882-058
NOISE FIGURE (dB)
IP3
INPUT IP3 (dBm)
GAIN (dB)
ADL5802
16 15 14
INPUT P1dB (dBm)
–10 –15
TA = +25°C 13 12 11 10
07882-060
LO TO IF LEAKAGE (dBm)
TA = +85°C
–20 –25 –30 –35 –40 –45 –50 TA = +85°C
07882-063
TA = –40°C
TA = –40°C TA = +25°C
9 8 4900
–55 –60 4900
5100
5300 5500 5700 RF FREQUENCY (MHz)
5900
6100
5100
5300 5500 5700 LO FREQUENCY (MHz)
5900
6100
Figure 60. Input P1dB vs. RF Frequency
25
Figure 63. LO to IF Leakage vs. LO Frequency
–15 –17
LO TO RF LEAKAGE (dBm)
20
–19 –21 –23 –25 –27 –29 –31 TA = +85°C TA = –40°C TA = +25°C
NOISE FIGURE (dB)
15
10 TA = –40°C TA = +25°C TA = +85°C 5
07882-061
–33 –35 4900
0 4900
5100
5300 5500 5700 RF FREQUENCY (MHz)
5900
6100
5100
5300 5500 5700 LO FREQUENCY (MHz)
5900
6100
Figure 61. SSB Noise Figure vs. RF Frequency
45 40 35
NOISE FIGURE (dB)
Figure 64. LO to RF Leakage vs. LO Frequency
–30 –35 –40 TA = –40°C –45 –50 –55 –60
07882-065
RF TO IF OUTPUT ISOLATION (dBc)
30 25 20 15 10 5 0 –60
07882-062
TA = +25°C
NF, RF 5805MHz, IF 380MHz, BLOCKER 5800MHz
TA = +85°C
–65 –70 4900
–50
–40 –30 –20 BLOCKER LEVEL (dBm)
–10
0
5100
5300
5500
5700
5900
6100
RF FREQUENCY (MHz)
Figure 62. SSB Noise Figure vs. Blocker Level
Figure 65. RF to IF Output Isolation vs. RF Frequency
Rev. 0 | Page 19 of 32
07882-064
ADL5802
45
CHANNEL-TO-CHANNEL ISOLATION (dB)
43 41 39 37 35 33 31 29 27 25 4900 TA = –40°C TA = +25°C TA = +85°C
5100
5300 5500 5700 RF FREQUENCY (MHz)
5900
6100
Figure 66. RF Channel Isolation
07882-066
Rev. 0 | Page 20 of 32
ADL5802
SPUR PERFORMANCE
All spur tables are (N × fRF) − (M × fLO) and were measured using the standard evaluation board (see the Evaluation Board section). Mixer spurious products are measured in decibels relative to the carrier (dBc) from the IF output power level. Data was measured for frequencies less than 6 GHz only. The typical noise floor of the measurement system is −100 dBm.
900 MHz Performance
VS = 5 V, VSET = 4 V, T A = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 900 MHz, fLO = 703 MHz, Z0 = 50 Ω.
0 0 1 2 3 4 5 6 N 7 8 9 10 11 12 13 14 15 −34.3 −49.1 −86.7 −91.8 ≤100 ≤100 1 −35.9 0.0 −69.2 −79.6 ≤100 ≤100 ≤100 ≤100 2 −25.5 −46.3 −68.2 ≤100 −96.4 ≤100 ≤100 ≤100 ≤100 3 −47.3 −19.8 −61.6 −67.3 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 4 −27.4 −64.3 −68.7 −98.0 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 5 −51.5 −30.0 −80.7 −71.0 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 6 −37.5 −75.6 −67.5 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 M 7 −62.1 −45.0 −88.1 −86.3 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 8 −47.5 −67.8 −79.1 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 9 −55.3 −82.6 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 10 11 12 13 14
−91.5 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 −98.4 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100
2090 MHz Performance
VS = 5 V, VSET = 4 V, T A = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 2090 MHz, fLO = 1842 MHz, Z0 = 50 Ω.
M 0 0 1 2 3 4 5 6 N 7 8 9 10 11 12 13 14 15 −26.8 −59.8 1 −43.0 0.0 −71.9 −67.6 2 −23.7 −59.6 −53.8 −97.6 ≤100 3 −52.9 −42.2 −67.5 −59.3 ≤100 ≤100 4 −80.5 −68.2 −92.2 −93.7 ≤100 ≤100 5 6 7 8 9 10 11 12 13 14
−84.1 −79.3 −97.8 −96.1 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
Rev. 0 | Page 21 of 32
ADL5802
2600 MHz Performance
VS = 5 V, VSET = 4.5 V, T A = 25°C, RF power = 0 dBm, LO power = 0 dBm, f RF = 2600 MHz, fLO = 2350 MHz, Z0 = 50 Ω.
M 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 −27.5 −75.5 1 −37.9 0.0 −59.7 −75.0 2 −31.5 −62.6 −52.2 −88.7 ≤100 3 −36.3 −65.8 −56.3 ≤100 ≤100 4 5 6 7 8 9 10 11 12 13 14
−68.8 −86.8 −82.5 ≤100
−90.5 −92.1 −94.4 ≤100
≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100 ≤100
N
≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100
3500 MHz Performance
VS = 5 V, VSET= 5 V, T A = 25°C, RF power = 0 dBm, LO power = 0 dBm, fRF = 3500 MHz, fLO = 3800 MHz, Z0 = 50 Ω.
M 0 0 1 2 3 4 5 6 N 7 8 9 10 11 12 13 14 15 −26.8 −59.8 1 −43.0 0.0 −71.9 −67.6 2 −23.7 −59.6 −53.8 −97.6 ≤100 3 −52.9 −42.2 −67.5 −59.3 ≤100 ≤100 4 −80.5 −68.2 −92.2 −93.7 ≤100 ≤100 5 6 7 8 9 10 11 12 13 14
−84.1 −79.3 −97.8 −96.1 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
≤100 ≤100 ≤100 ≤100 ≤100 ≤100
Rev. 0 | Page 22 of 32
ADL5802
5800 MHz Performance
VS = 5 V, VSET= 4.8 V, T A = 25°C, RF power = −10 dBm, LO power = 0 dBm, f RF = 5800 MHz, fLO = 5600 MHz, Z 0 = 50 Ω.
M 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 −63.6 1 −28.3 0.0 2 −80.5 −48.6 3 4 5 6 7 8 9 10 11 12 13 14
−92.6 −64.2
−98.7 −90.5
−98.3 ≤100
−99.4 −81.6
N
−98.0 −87.2
−95.9 −84.0
−99.5 ≤100
≤100 ≤100
≤100 ≤100
≤100 ≤100
−99.6 ≤100
−99.8 ≤100
Rev. 0 | Page 23 of 32
ADL5802 CIRCUIT DESCRIPTION
The ADL5802 provides two double-balanced active mixers. These mixers are designed for a 50 Ω input impedance and a 200 Ω output impedance. Both are driven from a common local oscillator (LO) amplifier. The RF inputs and LO outputs are differential, providing maximum usable bandwidth at the input and output ports. The LO also operates with a 50 Ω input impedance and can, optionally, be operated differentially or single-ended. The input, output, and LO ports can be operated over an exceptionally wide frequency range. The ADL5802 can be configured as a downconvert mixer or as an upconvert mixer. The ADL5802 can be divided into the following sections: the local oscillator (LO) amplifier and splitter, the RF voltage-tocurrent (V-to-I) converter, the mixer cores, the output loads, and the bias circuit. A simplified block diagram of the device is shown in Figure 67. The LO block generates a pair of differential LO signals to drive two mixer cores. The RF input is converted into current by the V-to-I converters that then feed into the two mixer cores. The internal differential load of the mixers is designed for a wideband 200 Ω output impedance from the mixer. Reference currents to each section are generated by the bias circuit, which can be enabled or disabled using the ENBL pin. A detailed description of each section of the ADL5802 follows.
VPOS RF1+ RF1– GND RF2+ RF2–
24 23 22 21 20 19
RF VOLTAGE TO CURRENT (V-TO-I) CONVERTER
The differential RF input signal is applied to a voltage-to-current converter that converts the differential input voltage to output currents. The V-to-I converter provides a 50 Ω input impedance. The V-to-I section bias current can be adjusted up or down using the VSET pin. Adjusting the current up improves IP3 and P1dB input but degrades SSB NF. Adjusting the current down improves SSB NF but degrades IP3 and P1dB input. The conversion gain remains nearly constant over a wide range of VSET pin settings, allowing the part to be adjusted dynamically without affecting the conversion gain. The current adjustment can be made by connecting a resistor from the VSET pin to the positive supply to increase the bias current or from the VSET pin to ground to decrease the bias current. The VSET pin impedance is approxi-mately 675 Ω in series with two diodes and an internal current source.
MIXER CORES
The ADL5802 has two double-balanced mixers that use high performance SiGe NPN transistors. These mixers are based on the Gilbert cell design of four cross-connected transistors.
MIXER LOAD
Each mixer load is designed to use a pair of 100 Ω resistors connected to the positive supply. This provides a 200 Ω differential output resistance. The mixer output should be pulled to the positive supply externally using a pair of RF chokes or using an output transformer with the center tap connected to the positive supply. It is possible to exclude these components when the mixer core current is low, but both P1dB and IP3 are then reduced. The mixer load output can operate from direct current (dc) up to approximately 500 MHz into a 200 Ω load. For upconversion applications, the mixer load can be matched using off-chip matching components. Transmit operation up to 2 GHz is possible. See the Applications Information section for matching circuit details.
GND GND OP1+ OP1– GND VPOS
1 2 3 4
18 17 16 15 14
GND GND OP2+ OP2– GND VPOS
5 6
ADL5802
IP3 BIAS
13
7
8
9
10
11
12
ENBL GND LOIP LOIN GND VSET
07882-128
Figure 67. ADL5802 Block Diagram
BIAS CIRCUIT
A band gap reference circuit generates the reference currents used by the mixers. The bias circuit can be enabled and disabled using the ENBL pin. If the ENBL pin is grounded or left open, the part is enabled. Pulling the ENBL pin high shuts off the bias circuit and disables the part. However, the ENBL pin does not alter the current in the LO section and, therefore, does not provide a true power-down feature. Certain configurations may require the VSET pin to be connected to the positive supply through a resistor. This will result in an increased mixer core current. Unless this resistor to positive supply is removed, bias current will continue to be supplied to the mixer core.
LO AMPLIFIER AND SPLITTER
The LO input is amplified using a broadband LNA and is then split and followed by separate LO limiting amplifiers. The LNA input impedance is nominally 50 Ω. The LO is designed to accommodate a wide range of LO input power levels. The LO input is conditioned by the series of amplifiers to provide a well controlled and limited LO swing to the mixer core, resulting in excellent IP3. The LO circuit exhibits low additive noise, resulting in an excellent mixer noise figure and output noise under RF blocking. For optimal performance, the LO inputs should be driven differentially but at lower frequencies; singleended drive is acceptable.
Rev. 0 | Page 24 of 32
ADL5802 APPLICATIONS INFORMATION
BASIC CONNECTIONS
The ADL5802 features dual channel mixers with a common local oscillator (LO). The mixer is designed to translate between radio frequencies (RF) and intermediate frequencies (IF). For both upconversion and downconversion applications, RF1+ (Pin 23), RF1− (Pin 22), RF2+ (Pin 20), and RF2− (Pin 19) must be configured as the input interfaces. OP1+ (Pin 3), OP1− (Pin 4), OP2+ (Pin 16), and OP2− (Pin 15) must be configured as the output interfaces. Figure 68 illustrates the basic connections for ADL5802 operation.
RF1 T5 C13 VPOS C11 C8
24 23 22 21 20 19
RF AND LO PORTS
The RF and LO input ports are designed for differential input impedance of approximately 50 Ω. Figure 69 and Figure 70 illustrate the RF and LO interfaces, respectively. It is recommended that each of the RF and LO differential ports be driven through a balun for optimum performance. It is also necessary to accouple both RF and LO ports with the proper size capacitors. Table 4 lists the recommended components for various RF frequency bands. The characterization data is available in the Typical Performance Characteristics section.
RF2 T3 C14 C5 C12
VPOS RF1+ RF1– GND RF2+ RF2–
1 GND 2 GND
GND 18 GND 17 OP2+ 16 VPOS
VPOS IF1P C16 T4
3 OP1+
ADL5802
4 OP1–
C15 T2 IF2P
OP2– 15 GND 14 VPOS 13 C7 C10
5 GND
VPOS C9 C6
6 VPOS
VPOS
ENBL GND LOIP LOIN GND VSET
7 8 9 10 11 12
VSET C2 C3 T1
LO
Figure 68. Basic Connections Schematic
Rev. 0 | Page 25 of 32
07882-101
ADL5802
RF1 T5 C13
23
RF2 T3 C14
22 21
C5
20
C12
19
frequency. A variety of suitable choke inductors is commercially available from manufacturers such as Coilcraft and Murata. An impedance transforming network may be required to transform the final load impedance to 200Ω at the IF outputs.
07882-102
RF1+ RF1– GND RF2+ RF2–
ADL5802
Figure 69. ADL5802 RF Interface
1 GND
VPOS IF1P
2 GND
ADL5802
ENBL GND LOIP LOIN GND
7 8 9 10 11
C16 T4
3 OP1+
ADL5802
4 OP1–
5 GND
C2
C3 T1
GND 18
LO
07882-103
GND 17 OP2+ 16
VPOS
Figure 70. ADL5802 LO Interface
Table 4. Suggested Components for the RF and LO Interfaces RF and LO C2, C3, C5, Frequency T1, T3, T5 C12, C13, C14 900 MHz Mini-Circuits® TC1-1-13M+ 100 pF 1900 MHz Mini-Circuits TC1-1-13M+ 100 pF 2500 MHz 3 pF Johanson Technology 2500BL14M050 3500 MHz 1.5 pF Johanson Technology 3600BL14M050 5500 MHz 3 pF Johanson Technology 5400BL15B050
ADL5802
OP2– 15 GND 14
C15 T2 IF2P
Figure 71. Biasing the IF Port Open-Collector Outputs Using a Center-Tapped Impedance Transformer
VPOS C17
1
GND GND OP1+
IF PORT
The IF port features an open-collector differential output interface. It is necessary to bias the open collector outputs using one of the schemes presented in Figure 71 and Figure 72. Figure 71 shows the use of center-tapped impedance transformers. The turns ratio of the transformer should be selected to provide the desired impedance transformation. In the case of a 50 Ω load impedance, a 4:1 impedance ratio transformer should be used to transform the 50 Ω load into a 200 Ω differential load at the IF output pins. Figure 72 shows a differential IF interface where pull-up choke inductors are used to bias the open-collector outputs. The shunting impedance of the choke inductors used to couple dc current into the mixer core should be large enough at the IF frequency of operation so as not to load down the output current before it reaches the intended load. Additionally, the dc current handling capability of the selected choke inductors must be at least 45 mA. The self-resonant frequency of the selected choke inductors must be higher than the intended IF
ZL
L3 IF1 OUT+ IMPEDANCE TRANSFORMING NETWORK
2
3
ZLOAD = 200Ω
4
ADL5802
OP1– GND
IF1 OUT– L4 C18 VPOS VPOS GND 18 GND 17 OP2+ 16 C4
5
L2 IF2 OUT+ IMPEDANCE TRANSFORMING NETWORK
ADL5802
OP2– 15 GND 14
ZLOAD = 200Ω
L1 C1 IF2 OUT–
07882-104
ZL
VPOS
Figure 72. Biasing the IF Port Open-Collector Outputs Using Pull-Up Choke Inductors
Rev. 0 | Page 26 of 32
07882-105
ADL5802 EVALUATION BOARD
An evaluation board is available for the ADL5802. The standard evaluation board is fabricated using Rogers® RO3003 material. Each of the RF, LO, and IF ports is configured for single-ended signaling via a balun transformer. The schematic for the evaluation board is shown in Figure 73. Table 5 describes the various configuration options for the evaluation board. Layout for the board is shown in Figure 74 and Figure 75.
RF1 T5 C11 VPOS C8 R19
24
RF2 T3 C14
22 21
VPOS C12 VPOS1
19
GND
C13
23
C5
20
VPOS C17
1
VPOS RF1+ RF1– GND RF2+ RF2– GND GND 18 GND 17 OP2+ 16
VPOS C4
L3 IF1P C16 T4 IF1N R3 R21 VPOS C9 C18 R10 R15 L4 R7 R16
2 GND
L2 R14 C15 R6
R2 IF2N T2 IF2P R20 VPOS C10
3
OP1+
ADL5802
4
OP1– GND
OP2– 15 R13 GND 14 VPOS 13 L1 C1 R12 C7
5
6 VPOS
C6
ENBL GND LOIP LOIN GND VSET
7 8 9 10 11 12
VPOS
R9 R11
R4 C2
R5 VSET C3 T1 VPOS R23 R22
07882-001 07882-100
ENBL1 R1
LON
LO
LOP
Figure 73. Evaluation Board Schematic
Table 5. Evaluation Board Configuration Components Function C1, C4, C6, C7, C8, C9, Power supply decoupling. Nominal supply decoupling C10, C11, C17, C18, consists of a 0.01 µF capacitor to ground in parallel with 10 R10, R12, R19, R20, pF capacitors to ground, positioned as close to the device R21 as possible. Series resistors are provided for enhanced supply decoupling using optional ferrite chip inductors. C5, C12, C13, C14, T3, RF Channel 1 and RF Channel 2 input interfaces. Input T5, RF1, RF2 channels are ac-coupled through C5, C12, C13, and C14. T3 and T4 are 1:1 baluns used to interface to the 50 Ω differential inputs. C15, C16, L1, L2, L3, IF Channel 1 and IF Channel 2 output interfaces. The 200 Ω L4, R2, R3, R6, R7, open-collector IF output interfaces are biased through the R13, R14, R15, R16, center taps of T2 and T4 4:1 impedance transformers. C15 R20, R21, T2, T4, IF1, and C16 provide local bypassing with R20 and R21 available IF2 for additional supply bypassing. R6, R7, R13, R14, R15, and R16 are provided for IF filtering and matching options. C2, C3, R4, R5, T1, LO LO interface. C2 and C3 provide ac coupling for the local oscillator input. T1 is a 1:1 balun to allow single-ended interfacing to the differential 50 Ω local oscillator input.
R1, R9, R11, ENBL1 Enable interface. The ADL5802 can be disabled using the 3pin ENBL1 header. The ENBL pin is pulled up to VPOS through R9. R1 is provided as an optional termination for the high impedance enable interface. If desired, the ENBL pin can be driven by an external source through the ENBL SMA connector.
Rev. 0 | Page 27 of 32
Default Conditions C6, C7, C8 = 10 pF (size 0402) C9, C10, C11 = 0.01 µF (size 0402) C1, C4, C17, C18 = open (size 0402) R10, R12, R19, R20, R21 = 0 Ω (size 0402) C5, C12, C13, C14 = 100 pF (size 0402) T3, T5 = TC1-1-13M+ (Mini-Circuits) C15, C16 = 100 pF (size 0402) L1, L2, L3, L4 = open (size 0805) R2, R3, R13, R14, R15, R16, R20, R21 = 0 Ω (size 0402) R6, R7 = open (size 0402) T2, T4 = TC4-1W+ (Mini-Circuits) C2, C3 = 1 nF (size 0402) R4, R5 = open (size 0402) T1 = TC1-1-13M+ (Mini-Circuits) R9 = 10 kΩ (size 0402); R1, R11 = open (size 0402) Or R1 = 10 kΩ (size 0402);R9, R11 = open (size 0402) Or R11 = 10 kΩ (size 0402); R1, R9 = open (size 0402) ENBL1 = 3-pin header and shunt
ADL5802
Components R22, R23, VSET Function VSET bias control. R22 and R23 form an optional resistor divider network between VPOS and GND, allowing for a fixed bias setting. See the Typical Performance Characteristics section to choose the recommended VSET control voltage for the desired frequency band. Exposed paddle. Must be soldered to ground. Default Conditions R22, R23 = open (size 0402)
EPAD (EP)
Figure 74. Evaluation Board Top Layer
07882-106
Figure 75. Evaluation Board Bottom Layer
Rev. 0 | Page 28 of 32
07882-107
ADL5802 OUTLINE DIMENSIONS
4.00 BSC SQ 0.60 MAX 0.60 MAX
19 18 EXPOSED PAD
(BO TTOMVIEW)
PIN 1 INDICATOR
24 1
PIN 1 INDICATOR
TOP VIEW
3.75 BSC SQ
0.50 BSC 0.50 0.40 0.30
2.65 2.50 SQ 2.35
6
13 12
7
0.23 MIN
1.00 0.85 0.80
12° MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
2.50 REF
COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8
Figure 76. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4 mm × 4 mm Body, Very Thin Quad (CP-24-3) Dimensions shown in millimeters
ORDERING GUIDE
Model ADL5802ACPZ-R71 ADL5802-EVALZ1
1
Temperature Range −40°C to +85°C
Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board
Package Option CP-24-3
082908-A
SEATING PLANE
COPLANARITY 0.08
FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET.
Ordering Quantity 1,500 per Reel 1
Z = RoHS Compliant Part.
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ADL5802 NOTES
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ADL5802 NOTES
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ADL5802 NOTES
©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07882-0-11/09(0)
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