5.7 kV rms, Signal Isolated,
Basic CAN FD Transceiver
ADM3050E
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VDD1
VDD2
ADM3050E
CAN
TRANSCEIVER
DIGITAL ISOLATOR
DOMINANT
TIMEOUT
TXD
CANH
RXD
CANL
THERMAL
SHUTDOWN
GND2
GND1
14971-001
5.7 kV rms signal isolated CAN FD transceiver
1.7 V to 5.5 V supply and logic side levels
4.5 V to 5.5 V supply on bus side
ISO 11898-2:2016-compliant CAN FD
Data rates up to 12 Mbps for CAN FD
Low maximum loop propagation delay: 150 ns
Extended common-mode range: ±25 V
Bus fault protection (CANH, CANL): ±40 V
Passes EN 55022, Class B by 6 dB
Safety and regulatory approvals
VDE certificate of conformity, VDE V 0884-10 (pending)
UL: 5700 V rms for 1-minute duration per UL 1577 (pending)
CSA component acceptance 5A at 5.7 kV rms
IEC 60950, IEC 61010 (pending)
High common-mode transient immunity: >75 kV/µs
Industrial operating temperature range: −40°C to +125°C
Figure 1.
APPLICATIONS
CANOpen, DeviceNet, and other CAN bus implementations
Industrial automation
Process control and building control
Transport and infrastructure
GENERAL DESCRIPTION
The ADM3050E is a 5.7 kV rms isolated controller area network
(CAN) physical layer transceiver with a high performance, basic
feature set. The ADM3050E fully meets the CAN flexible data
rate (CAN FD) ISO 11898-2:2016 requirements and is further
capable of supporting data rates as high as 12 Mbps.
The device employs Analog Devices, Inc., iCoupler® technology
to combine a 2-channel isolator and a CAN transceiver into a
single small outline integrated circuit (SOIC) surface-mount
package. The ADM3050E is a fully isolated solution for CAN and
CAN FD applications. The ADM3050E provides isolation
between the CAN controller and physical layer bus. Safety and
regulatory approvals (pending) for a 5.7 kV rms withstand voltage,
an 849 VPEAK working voltage, and a 12.8 kV surge test, ensure
that the ADM3050E meets application isolation requirements.
Rev. B
Low loop propagation delays and the extended common-mode
range of ±25 V support robust communication on longer bus
cables. Dominant timeout functionality protects against bus
lock up in a fault condition, and current limiting and thermal
shutdown features protect against output short circuits. The
CAN bus input and output pins are protected to ±40 V against
accidental connection to a +24 V bus supply. The device is fully
specified over the −40°C to +125°C industrial temperature
range.
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ADM3050E
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 16
Applications ....................................................................................... 1
CAN Transceiver Operation ..................................................... 16
Functional Block Diagram .............................................................. 1
Signal Isolation ........................................................................... 16
General Description ......................................................................... 1
Revision History ............................................................................... 2
Integrated and Certified IEC Electromagnetic Compatibility
(EMC) Solution .......................................................................... 16
Specifications..................................................................................... 3
±40 V Miswire Protection ......................................................... 16
Timing Specifications .................................................................. 5
Dominant Timeout .................................................................... 16
Timing Diagrams.......................................................................... 5
Fail-Safe Features ........................................................................ 16
Insulation and Safety Related Specifications ............................ 6
Thermal Shutdown .................................................................... 16
Package Characteristics ............................................................... 6
Applications Information .............................................................. 17
Regulatory Information ............................................................... 6
Radiated Emissions and PCB Layout ...................................... 17
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics (Pending) ............................................................ 7
PCB Layout ................................................................................. 17
Thermal Analysis ....................................................................... 17
Absolute Maximum Ratings.......................................................... 10
Insulation Lifetime ..................................................................... 17
Thermal Resistance .................................................................... 10
Surface Tracking ......................................................................... 17
ESD Caution ................................................................................ 10
Insulation Wear Out .................................................................. 17
Pin Configurations and Function Descriptions ......................... 11
Calculation and Use of Parameters Example.......................... 18
Operational Truth Table ............................................................ 11
Outline Dimensions ....................................................................... 19
Typical Performance Characteristics ........................................... 12
Ordering Guide .......................................................................... 19
Test Circuits ..................................................................................... 14
Terminology .................................................................................... 15
REVISION HISTORY
9/2019—Rev. A to Rev. B
Added 8-Lead SOIC_IC Package ..................................... Universal
Changes to Table 3 ............................................................................ 6
Added ADM3050EBRWZ Section ................................................. 6
Changes to ADM3050EBRWZ Section ......................................... 6
Added ADM3050EBRIZ Section and Table 6; Renumbered
Sequentially ....................................................................................... 7
Changes to Table 7 ............................................................................ 7
Added Table 8.................................................................................... 8
Change to Figure 4 Caption ............................................................ 9
Added Figure 5; Renumbered Sequentially .................................. 9
Changes to Table 10 ........................................................................ 10
Added Figure 7................................................................................ 11
Added Figure 26 ............................................................................. 17
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 19
12/2018—Rev. 0 to Rev. A
Change to Features Section ..............................................................1
Change to Falling Edge Loop Propagation Delay (TXD to RXD)
Parameter and Rising Edge Loop Propagation Delay (TXD to
RXD) Parameter, Table 2 ..................................................................5
10/2018—Revision 0: Initial Version
Rev. B | Page 2 of 19
Data Sheet
ADM3050E
SPECIFICATIONS
All voltages are relative to their respective ground, 1.7 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise
noted. Typical specifications are at VDD1 = VDD2 = 5 V and TA = 25°C, unless otherwise noted.
Table 1.
Parameter
SUPPLY CURRENT
Bus Side
Recessive State
Dominant State
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
5.3
63
7
75
mA
mA
73
mA
TXD high, load resistance (RL) = 60 Ω
Limited by transmit dominant timeout
(tDT), see the Theory of Operation
section, RL = 60 Ω
Limited by tDT, RL = 60 Ω, 4.75 V ≤ VDD2 ≤
5.25 V
Worst case, see the Theory of Operation
section, RL = 60 Ω
58
60
65
5.5
mA
mA
mA
mA
IDD2
70% Dominant/30% Recessive
1 Mbps
5 Mbps
12 Mbps
Logic Side iCoupler Current
DRIVER
Differential Outputs
Recessive State Voltage
CANH, CANL
Differential Output
Dominant State Voltage
CANH
CANL
Differential Output
Output Symmetry (VDD2 − VCANH to VCANL)
Short-Circuit Current
Absolute
CANH
CANL
Steady State
CANH
CANL
Logic Input TXD
Input Voltage
High
Low
Complementary Metal-Oxide
Semiconductor (CMOS) Logic Input
Currents
RECEIVER
Differential Inputs
Differential Input Voltage Range
Recessive
Dominant
Input Voltage Hysteresis
45
49
58
IDD1
TXD high, low, or switching
See Figure 20
TXD high, RL, and common-mode filter
capacitor (CF) open
VCANL, VCANH
VOD
2.0
−500
3.0
+50
V
mV
VCANH
VCANL
VOD
2.75
0.5
1.5
1.4
1.5
−0.55
4.5
2.0
3.0
3.3
5.0
+0.55
V
V
V
V
V
V
TXD low, CF open
50 Ω ≤ RL ≤ 65 Ω
50 Ω ≤ RL ≤ 65 Ω
50 Ω ≤ RL ≤ 65 Ω
45 Ω ≤ RL ≤ 70
RL = 2240 Ω
RL = 60 Ω, CF = 4.7 nF
RL open
115
115
mA
mA
VCANH = −3 V
VCANL = 18 V
115
115
mA
mA
VCANH = −24 V
VCANL = 24 V
0.35 × VDD1
10
V
V
µA
Input high or low
VSYM
|ISC|
VIH
VIL
|IIH|, |IIL|
0.65 × VDD1
VID
See Figure 21, RXD capacitance (CRXD)
open, −25 V < VCANL, VCANH < +25 V
−1.0
0.9
VHYS
+0.5
5.0
150
Rev. B | Page 3 of 19
V
V
mV
ADM3050E
Parameter
Unpowered Input Leakage Current
Input Resistance
CANH, CANL
Differential
Input Resistance Matching
CANH, CANL Input Capacitance
Differential Input Capacitance
Logic Output (RXD)
Output Voltage
Low
High
Short-Circuit Current
COMMON-MODE TRANSIENT IMMUNITY 1
1
Data Sheet
Symbol
|IIN (OFF)|
Min
RINH, RINL
RDIFF
mR
CINH, CINL
CDIFF
6
20
−0.03
Typ
Max
10
Unit
µA
25
100
+0.03
kΩ
kΩ
35
12
0.2
Test Conditions/Comments
VCANH, VCANL = 5 V, VDD2 = 0 V
mR = 2 × (RINH − RINL)/(RINH + RINL)
pF
pF
VOL
VOH
IOS
VDD1 − 0.2
7
0.4
Input High, Recessive
|CMH|
75
100
kV/µs
Input Low, Dominant
|CML|
75
100
kV/µs
85
V
V
mA
Output impedance (IOUT) = 2 mA
IOUT = −2 mA
Output voltage (VOUT) = GND1 or VDD1
Common-mode voltage (VCM) ≥ 1 kV,
transient magnitude ≥ 800 V
Input voltage (VIN) = VDD1 (TXD) or
CANH/CANL recessive
VIN = 0 V (TXD) or CANH/CANL dominant
|CMH| is the maximum common-mode voltage slew rate that can be sustained while maintaining CANH/CANL recessive or RXD ≥ VDD1 − 0.2 V. |CML| is the maximum
common-mode voltage slew rate that can be sustained while maintaining CANH/CANL dominant or RXD ≤ 0.4 V. The common-mode voltage slew rates apply to both
rising and falling common-mode voltage edges.
Rev. B | Page 4 of 19
Data Sheet
ADM3050E
TIMING SPECIFICATIONS
All voltages are relative to their respective ground, 1.7 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise
noted. Typical specifications are at VDD1 = VDD2 = 5 V and TA = 25°C, unless otherwise noted.
Table 2.
Parameter
DRIVER
Symbol
Min
Maximum Data Rate
Typ
Max
Unit
12
Propagation Delay from TXD to Bus (Recessive to Dominant)
Propagation Delay from TXD to Bus (Dominant to Recessive)
Transmit Dominant Timeout
RECEIVER
tTXD_DOM
tTXD_REC
tDT
Falling Edge Loop Propagation Delay (TXD to RXD)
Rising Edge Loop Propagation Delay (TXD to RXD)
Loop Delay Symmetry (Minimum Recessive Bit Width)
2 Mbps
5 Mbps
8 Mbps
12 Mbps
tLOOP_FALL
tLOOP_RISE
tBIT_RXD
Mbps
35
45
1175
450
160
85
50
60
70
4000
ns
ns
µs
150
150
ns
ns
550
220
140
91.6
ns
ns
ns
ns
TXD low, see Figure 3
See Figure 2 and Figure 22,
tBIT_TXD = 200 ns, RL = 60 Ω,
CL = 100 pF, CRXD = 15 pF
tBIT_TXD = 500 ns
tBIT_TXD = 200 ns
tBIT_TXD = 125 ns
tBIT_TXD = 83.3 ns
TIMING DIAGRAMS
TXD
0.7VDD1
0.3VDD1
VDD1
0.3VDD1
0V
5 × tBIT_TXD
tBIT_TXD
tLOOP_FALL
0.9V
0.5V
tTXD_REC
tBIT_BUS
tTXD_DOM
0.7VDD1
RXD
0.3VDD1
tBIT_RXD
VDD1
0V
tLOOP_RISE
Figure 2. Transceiver Timing Diagram
tDT
14971-103
TXD
VOD
Figure 3. Dominant Timeout, tDT
Rev. B | Page 5 of 19
14971-002
VOD/VID
Test Conditions/Comments
See Figure 2 and Figure 20,
tBIT_TXD = 200 ns, RL = 60 Ω,
CL = 100 pF
ADM3050E
Data Sheet
INSULATION AND SAFETY RELATED SPECIFICATIONS
For additional information, see www.analog.com/icouplersafety.
Table 3.
Parameter
Rated Dielectric Insulation
Voltage
Minimum External Air Gap
(Clearance)
Minimum External Tracking
(Creepage)
Minimum Clearance in the
Plane of the Printed
Circuit Board (PCB)
Clearance
Minimum Internal Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking
Index)
Material Group
Symbol
Value
ADM3050EBRWZ ADM3050EBRIZ
5700
5700
L (I01)
7.8
8.3
L (I02)
7.8
8.3
L (PCB)
8.3
8.3
25.5
25.5
>600
>600
I
I
CTI
Unit
V rms
Test Conditions/Comments
1-minute duration
mm
min
mm
min
mm
min
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Measured from input terminals to output
terminals, shortest distance through air, line of
sight, in the PCB mounting plane
µm
min
V
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material group (DIN VDE 0110, 1/89, Table 1)
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Resistance (Input to Output) 1
Capacitance (Input to Output)1
Input Capacitance 2
1
2
Symbol
RI-O
CI-O
CI
Min
Typ
1013
1.1
4.0
Max
Unit
Ω
pF
pF
Test Conditions/Comments
f = 1 MHz
The device is considered a two-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
ADM3050EBRWZ
See Table 11 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross isolation waveforms
and insulation levels. The ADM3050EBRWZ is pending approval or approved by the organizations listed in Table 5.
Table 5.
UL (Pending)
CSA (Pending)
VDE (Pending)
CQC (Pending)
UL1577 Component
Recognition Program 1
Approved under CSA Component Acceptance
Notice 5A
DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 2
Certified under CQC11471543-2012
Single Protection, 5700 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2:
Reinforced insulation,
849 VPEAK, VIOTM = 8 kVPEAK
GB4943.1-2011
Basic insulation at 780 V rms (1103 VPEAK)
Reinforced insulation at 390 V rms (552 VPEAK)
IEC 60601-1 Edition 3.1:
Basic insulation (1 MOPP), 490 V rms (686 VPEAK)
Reinforced insulation (2 MOPP), 238 V rms
(325 VPEAK)
CSA 61010-1-12 and IEC 61010-1 third edition:
Rev. B | Page 6 of 19
Basic insulation at 780 V
rms (1103 VPEAK)
Reinforced insulation at
390 V rms (552 VPEAK)
Data Sheet
UL (Pending)
ADM3050E
CSA (Pending)
VDE (Pending)
CQC (Pending)
File 2471900-4880-0001
File (pending)
Basic insulation at: 300 V rms mains, 780 V
secondary (1103 VPEAK)
Reinforced insulation at: 300 V rms mains, 390
V secondary (552 VPEAK)
File E214100
1
2
File 205078
In accordance with UL 1577, each ADM3050E is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec.
In accordance with DIN V VDE V 0884-10, each product is proof tested by applying an insulation test voltage ≥ 1592 VPEAK for 1 sec (partial discharge detection limit = 5 pC).
The * marking branded on the component designates DIN V VDE V 0884-10 approval.
ADM3050EBRIZ
See Table 11 and the Insulation Lifetime section for the recommended maximum working voltages for specific cross isolation waveforms
and insulation levels. The ADM3050EBRIZ is pending approval or approved by the organizations listed in Table 6.
Table 6.
UL (Pending)
CSA (Pending)
VDE (Pending)
CQC (Pending)
UL1577 Component
Recognition Program 1
Approved under CSA Component
Acceptance Notice 5A
DIN V VDE V 0884-10
(VDE V 0884-10):2006-12 2
Certified under CQC11471543-2012
Single Protection, 5700 V rms
Isolation Voltage
CSA 60950-1-07+A1+A2 and
IEC 60950-1, second edition, +A1+A2:
Reinforced insulation,
849 VPEAK, VIOTM = 8 kVPEAK
GB4943.1-2011
Basic insulation at 780 V rms (1103 VPEAK)
Basic insulation at 780 V rms
(1103 VPEAK)
Reinforced insulation at
390 V rms (552 VPEAK)
Reinforced insulation at 390 V rms (552 VPEAK)
IEC 60601-1 Edition 3.1:
Basic insulation (1 MOPP), 490 V rms
(686 VPEAK)
Reinforced insulation (2 MOPP), 238 V rms
(325 VPEAK)
CSA 61010-1-12 and IEC 61010-1 third edition:
Basic insulation at: 300 V rms mains, 780 V
secondary (1103 VPEAK)
Reinforced insulation at: 300 V rms mains,
390 V secondary (552 VPEAK)
File E214100
1
2
File 205078
File 2471900-4880-0001
File (pending)
In accordance with UL 1577, each ADM3050E is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec.
In accordance with DIN V VDE V 0884-10, each product is proof tested by applying an insulation test voltage ≥ 1592 VPEAK for 1 sec (partial discharge detection limit = 5 pC).
The * marking branded on the component designates DIN V VDE V 0884-10 approval.
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS (PENDING)
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Protective circuits ensure the maintenance
of the safety data.
Table 7. ADM3050EBRWZ VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Reinforced
Test Conditions/Comments
Symbol
Characteristic
Unit
I to IV
I to IV
I to IV
40/125/21
2
VIORM
Rev. B | Page 7 of 19
849
VPEAK
ADM3050E
Description
Basic, DC Working Voltage
Input to Output Test Voltage, Method B1
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Impulse
Surge Isolation Voltage
Basic
Reinforced
Safety Limiting Values
Maximum Junction Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
Data Sheet
Test Conditions/Comments
See the Absolute Maximum Ratings section and Table 11
for the maximum continuous working voltage for ac bipolar,
ac unipolar, and dc voltages, basic and reinforced insulation,
and 50 year lifetime to 1% failure
VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec,
partial discharge < 5 pC
Symbol
VIORM(DC)
Characteristic
1500
Unit
VDC
Vpd (m)
1592
VPEAK
1274
VPEAK
1019
VPEAK
VIOTM
VIMPULSE
8000
8000
VPEAK
VPEAK
VIOSM
VIOSM
12000
8000
VPEAK
VPEAK
VPEAK
TS
PS
RS
150
2.08
>109
°C
W
Ω
Symbol
Characteristic
Unit
Vpd (m)
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
1.2 µs rise time, 50 µs, 50% fall time in air to the preferred
sequence
VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, and 50% fall time
VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, and 50% fall time
Maximum value allowed in the event of a failure (see
Figure 4)
Test voltage = 500 V
Table 8. ADM3050EBRIZ VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Reinforced
Basic, DC Working Voltage
Input to Output Test Voltage, Method B1
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Impulse
Surge Isolation Voltage
Basic
Reinforced
Safety Limiting Values
Maximum Junction Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
Test Conditions/Comments
I to IV
I to IV
I to IV
40/125/21
2
See the Absolute Maximum Ratings section and Table 11
for the maximum continuous working voltage for ac bipolar,
ac unipolar, and dc voltages, basic and reinforced insulation,
and 50 year lifetime to 1% failure
VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec,
partial discharge < 5 pC
VIORM
VIORM(DC)
849
1500
VPEAK
VDC
Vpd (m)
1592
VPEAK
1274
VPEAK
1019
VPEAK
VIOTM
VIMPULSE
8000
8000
VPEAK
VPEAK
VIOSM
VIOSM
12000
8000
VPEAK
VPEAK
VPEAK
TS
PS
RS
150
1.28
>109
°C
W
Ω
Vpd (m)
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
1.2 µs rise time, 50 µs, 50% fall time in air to the preferred
sequence
VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, and 50% fall time
VPEAK = 12.8 kV, 1.2 µs rise time, 50 µs, and 50% fall time
Maximum value allowed in the event of a failure (see
Figure 4)
Test voltage = 500 V
Rev. B | Page 8 of 19
Data Sheet
ADM3050E
SAFE LIMITING POWER (W)
2.5
2.0
1.5
1.0
0
0
50
100
150
200
AMBIENT TEMPERATURE (°C)
14971-104
0.5
Figure 4. ADM3050EBRWZ Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10 (See the Thermal
Resistance Section for Additional Information)
1.4
SAFE LIMITING POWER (W)
1.2
1.0
0.8
0.6
0.4
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
14971-205
0.2
Figure 5. ADM3050EBRIZ Thermal Derating Curve, Dependence of Safety Limiting Values with Ambient Temperature per DIN V VDE V 0884-10 (See the Thermal
Resistance Section for Additional Information)
Rev. B | Page 9 of 19
ADM3050E
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Pin voltages with respect to GND1/GND2 are on same side,
unless otherwise noted.
Table 9.
Parameter
VDD1/VDD2
Logic Side Input and Output: TXD, RXD
CANH, CANL
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature (TJ)
Electrostatic Discharge (ESD),
IEC 61000-4-2, CANH/CANL
Across Isolation Barrier with Respect
to GND1
Contact Discharge with Respect to
GND2
Air Discharge with Respect to GND2
Human Body Model (HBM), All Pins,
1.5 kΩ, 100 pF
Moisture Sensitivity Level (MSL)
Rating
−0.5 V to +6 V
−0.5 V to VDD1 + 0.5 V
−40 V to +40 V
−40°C to +125°C
−65°C to +150°C
150°C
±8 kV
Thermal performance is directly linked to PCB design and
operating environment. Careful attention to PCB thermal
design is required.
Table 10. Thermal Resistance
Package Type1
RW-16
RI-8-1
1
θJA
60
97
Unit
°C/W
°C/W
The thermocouple is located at the center of the package underside, and the
test was conducted on a 4-layer board with thin traces. See the Thermal
Analysis section for the thermal model definitions.
ESD CAUTION
±8 kV typical
±15 kV
±4 kV
3
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 11. Maximum Continuous Working Voltage 1
Parameter
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation
Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
2
Insulation Rating (20-Year Lifetime) 2
VDE 0884-11 Lifetime Conditions Fulfilled
849 VPEAK
707 VPEAK
Lifetime limited by insulation lifetime per VDE-0884-11
Lifetime limited by insulation lifetime per VDE-0884-11
1697 VPEAK
1275 VPEAK
Lifetime limited by insulation lifetime per VDE-0884-11
Lifetime limited by package creepage per IEC 60664-1
1560 VPEAK
780 VPEAK
Lifetime limited by package creepage per IEC 60664-1
Lifetime limited by package creepage per IEC 60664-1
The maximum continuous working voltage refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for
more details.
Insulation capability without regard to creepage limitations. Working voltage may be limited by the PCB creepage when considering rms voltages for components
soldered to a PCB (assumes Material Group I up to 1250 V rms), or by the SOIC_W package creepage of 7.8 mm, when considering rms voltages for Material Group II.
Rev. B | Page 10 of 19
Data Sheet
ADM3050E
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1
1
16 VDD2
GND1
2
15 GND2
RXD
3
NC
4
NC
5
TXD
6
11 NC
GND1
7
10 GND2
TXD 2
GND1
8
9
RXD 3
14 NC
13 CANH
12 CANL
VDD1 1
GND2
NOTES
1. NC = NO CONNECT. NO INTERNAL CONNECTION TO IC.
GND1 4
8
ADM3050E
VDD2
CANH
TOP VIEW
(Not to Scale) 6 CANL
7
5
GND2
14971-207
TOP VIEW
(Not to Scale)
14971-004
ADM3050E
Figure 7. 8-Lead SOIC_IC Pin Configuration
Figure 6. 16-Lead SOIC_W Pin Configuration
Table 12. Pin Function Descriptions
Pin No.
16-Lead
8-Lead
SOIC_W
SOIC_IC
1
1
2, 7, 8
4
3
3
4, 5, 11, 14
N/A1
6
2
9, 10, 15
5
12
6
13
7
16
8
1
Mnemonic
VDD1
GND1
RXD
NC
TXD
GND2
CANL
CANH
VDD2
Description
Power Supply, Logic Side, 1.7 V to 5.5 V. This pin requires a 0.1 μF decoupling capacitor.
Ground, Logic Side.
Receiver Output Data.
No Connect. No internal connection to IC.
Driver Input Data.
Ground, Bus Side.
CAN Low Input and Output.
CAN High Input and Output.
Power Supply, Bus Side, 4.5 V to 5.5 V. This pin requires a 0.1 μF decoupling capacitor.
N/A means not applicable.
OPERATIONAL TRUTH TABLE
Table 13. Truth Table
VDD1
On
On
Off
On
VDD2
On
On
On
Off
TXD
Low
High
Don’t care
Don’t care
Mode
Normal
Normal
Normal
Transceiver off
RXD
Low
High per bus
Indeterminate
High
Rev. B | Page 11 of 19
CANH/CANL
Dominant (limited by tDT)
Recessive and set by bus
Recessive and set by bus
High-Z
ADM3050E
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
3.5
VDD1
VDD1
VDD1
VDD1
3.1
43
= 5.0V
= 3.3V
= 2.5V
= 1.8V
–35
–15
39
2.7
2.5
2.3
37
35
33
2.1
31
1.9
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
DATA RATE (Mbps)
27
–55
14971-106
0
85
105
125
105
125
105
125
53
VDD2 = 4.5V
VDD2 = 5V
VDD2 = 5.5V
55
51
50
VDD1
VDD1
VDD1
VDD1
= 1.8V
= 2.5V
= 3.3V
= 5.0V
–35
–15
45
40
47
45
35
43
30
41
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
DATA RATE (Mbps)
39
–55
25
5
45
65
85
TEMPERATURE (°C)
Figure 9. Supply Current (IDD2) vs. Data Rate
14971-110
tTXD_REC (ns)
49
14971-107
SUPPLY CURRENT, IDD2 (mA)
65
Figure 11. tTXD_DOM vs. Temperature
60
Figure 12. tTXD_REC vs. Temperature
135
180
170
130
160
VDD1
VDD1
VDD1
VDD1
= 1.8V
= 2.5V
= 3.3V
= 5.0V
125
tLOOP_RISE (ns)
150
140
130
120
110
120
115
110
100
105
80
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
125
Figure 10. Receiver Input Hysteresis vs. Temperature
100
–55
–35
–15
5
25
45
65
85
TEMPERATURE (°C)
Figure 13. tLOOP_RISE vs. Temperature
Rev. B | Page 12 of 19
14971-111
90
14971-108
RECEIVER INPUT HYSTERESIS (mV)
45
TEMPERATURE (°C)
Figure 8. Supply Current (IDD1) vs. Data Rate
25
25
5
14971-109
29
1.7
1.5
VDD1
VDD1
VDD1
VDD1
41
2.9
tTXD_DOM (ns)
SUPPLY CURRENT, IDD1 (mA)
3.3
45
= 1.8V
= 2.5V
= 3.3V
= 5.0V
Data Sheet
ADM3050E
2.8
125
= 1.8V
= 2.5V
= 3.3V
= 5.0V
VDD1
VDD1
VDD1
VDD1
2.6
SUPPLY CURRENT, IDD1 (mA)
tLOOP_FALL (ns)
120
VDD1
VDD1
VDD1
VDD1
115
110
105
= 1.8V
= 2.5V
= 3.3V
= 5.0V
2.4
2.2
2.0
1.8
–35
25
5
–15
45
65
85
105
125
TEMPERATURE (°C)
1.4
–55
14971-112
100
–55
–35
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 17. Supply Current (IDD1) vs. Temperature
Figure 14. tLOOP_FALL vs. Temperature
36.0
2.34
2.32
35.5
2.30
SUPPLY CURRENT, IDD2 (mA)
DIFFERENTIAL OUTPUT VOLTAGE (V)
–15
14971-115
1.6
2.28
2.26
2.24
2.22
2.20
2.18
35.0
34.5
34.0
33.5
33.0
–5
95
45
32.5
–55
14971-113
2.14
–55
TEMPERATURE (°C)
–35
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 15. Differential Output Voltage vs. Temperature, RL = 60 Ω
Figure 18. Supply Current (IDD2) vs. Temperature
2.7
2900
2800
DOMINANT TIMEOUT, tDT (µs)
2.5
2.3
2.1
1.9
2700
2600
2500
2400
2300
1.7
1.5
4.5
4.7
4.9
5.1
SUPPLY VOLTAGE, VDD2 (V)
5.3
5.5
Figure 16. Differential Output Voltage vs. Supply Voltage (VDD2), RL = 60 Ω
Rev. B | Page 13 of 19
2100
–55
–35
–15
5
25
45
65
85
105
TEMPERATURE (°C)
Figure 19. Dominant Timeout (tDT) vs. Temperature
125
14971-117
2200
14971-114
DIFFERENTIAL OUTPUT VOLTAGE (V)
–15
14971-116
2.16
ADM3050E
Data Sheet
TEST CIRCUITS
RL
2
TXD
VOD
VCANH
RL
2
CANH
GND2
VCANL
14971-005
RDIFF
Figure 20. Driver Voltage Measurement
CDIFF
CANL
GND2
14971-008
GND1
CF
Figure 23. RDIFF and CDIFF Measured in Recessive State, Bus Disconnected
RINH
CANH
CINH
RINL
CINL
CANH
VID
CANL
14971-006
GND1
GND2
GND2
Figure 21. Receiver Voltage Measurement
Figure 24. Input Resistance (RINx) and Input Capacitance (CINx) Measured in
Recessive State, Bus Disconnected
CANH
TXD
RL
CL
CANL
RXD
GND2
NOTES
1. 1% TOLERANCE FOR ALL RESISTORS AND CAPACITORS.
14971-007
CRXD
GND1
CANL
14971-009
RXD
CRXD
Figure 22. Switching Characteristics Measurements
Rev. B | Page 14 of 19
Data Sheet
ADM3050E
TERMINOLOGY
tLOOP_RISE
tLOOP_RISE is the propagation delay of a high signal on TXD to the
bus recessive. tOFF_LOOP transitions high on the RXD pin.
IDD1
IDD1 is the current drawn by the VDD1 pin.
IDD2
IDD2 is the current drawn by the VDD1 pin.
VOD and VID
VOD and VID are the differential voltages from the transmitter or
at the receiver on the CANH and CANL pins.
tTXD_DOM
tTXD_DOM is the propagation delay from a low signal on TXD to
transition the bus to a dominant state.
tTXD_REC
tTXD_REC is the propagation delay from a high signal on TXD to
transition the bus to a recessive state.
tLOOP_FALL
tLOOP_FALL is the propagation delay of a low signal on the TXD
pin to the bus dominant. tON_LOOP transitions low on the RXD pin.
tBIT_TXD
tBIT_TXD is the bit time at the TXD pin as transmitted by the CAN
controller. See Figure 2 for level definitions.
tBIT_BUS
tBIT_BUS is the bit time as transmitted by the transceiver to the
bus. When compared with a given tBIT_TXD, a measure of bit
symmetry from the TXD digital isolation channel and CAN
transceiver can be determined. See Figure 2 for level definitions.
tBIT_RXD
tBIT_RXD is the bit time on the RXD output pin, which can be
compared with tBIT_TXD for a round trip measure of pulse width
distortion through the TXD digital isolation channel, the CAN
transceiver, and back through the RXD isolation channel.
Rev. B | Page 15 of 19
ADM3050E
Data Sheet
THEORY OF OPERATION
CAN TRANSCEIVER OPERATION
The ADM3050E facilitates communication between a CAN
controller and the CAN bus. The CAN controller and the
ADM3050E communicate with standard 1.8 V, 2.5 V, 3.3 V
or 5.0 V CMOS levels. The internal transceiver translates the
CMOS levels to and from the CAN bus.
The CAN bus has two states: dominant and recessive. The
recessive state is present on the bus when the differential voltage
between CANH and CANL is less than 0.5 V. In the recessive
state, both the CANH pin and CANL pin are set to high
impedance and are loosely biased to a single-ended voltage of
2.5 V. A dominant state is present on the bus when the differential
voltage between CANH and CANL is greater than 1.5 V. The
transceiver transmits a dominant state by driving the singleended voltage of the CANH line to 3.5 V and the CANL pin to
1.5 V. The recessive and dominant states correspond to CMOS
high and CMOS low, respectively, on the RXD pin and TXD pin.
A dominant state from another node overwrites a recessive state
on the bus. A CAN frame can be set for higher priority by using
a longer string of dominant bits to gain control of the CAN bus
during the arbitration phase. While transmitting, a CAN
transceiver also reads back the state of the bus. When a CAN
controller receives a dominant state while transmitting a
recessive state during arbitration, the CAN controller surrenders
the bus to the node still transmitting the dominant state. The
node that gains control during the arbitration phase reads back
only its own transmission. This interaction between recessive
and dominant states allows competing nodes to negotiate for
control of the bus while avoiding contention between nodes.
Industrial applications can have long cable runs. These long
runs may have differences in local earth potential. Different
sources may also power nodes. The ADM3050E transceiver
has a ±25 V common-mode range (CMR) that exceeds the
ISO11898-2 requirement and further increases the tolerance
to ground variation.
See the AN-1123 Application Note for additional information
on CAN.
SIGNAL ISOLATION
The ADM3050E device provides galvanic signal isolation
implemented on the logic side of the interface. The RXD and
TXD channels are isolated using a low propagation delay on/off
keying (OOK) architecture with iCoupler digital isolation
technology.
The low propagation delay isolation, quick transceiver
conversion speeds, and integrated form factor are critical for
longer cable lengths, higher data speeds, and reducing the total
solution board space. The ADM3050E isolated transceiver
reduces solution board space while increasing data transfer
rates over discrete optocoupler and transceiver solutions.
INTEGRATED AND CERTIFIED IEC ELECTROMAGNETIC
COMPATIBILITY (EMC) SOLUTION
Typically, designers must add protections against harsh operating
environments while also making the product as small as possible.
To reduce the board space and the design efforts needed to meet
system level ESD standards, the ADM3050E isolated transceiver
has brought robust protection circuitry on-chip for the CANH
and CANL lines.
±40 V MISWIRE PROTECTION
High voltage miswire events commonly occur when the system
power supply is connected directly to the CANH and the CANL
bus lines during assembly. Supplies may also be shorted by
accidental damage to the field bus cables while the system is
operating. Accounting for inductive kick and switching effects,
the ADM3050E isolated transceiver CAN bus lines are protected
against these miswire or shorting events in systems with up to
nominal 24 V supplies. The CANH and CANL signal lines can
withstand a continuous supply short with respect to GND2 or
between the CAN bus lines without damage. This level of protection
applies when the device is either powered or unpowered.
DOMINANT TIMEOUT
The ADM3050E features a dominant timeout (tDT in Figure 3). A
TXD line shorted to ground, or malfunctioning CAN controller
are examples of how a single node can indefinitely prevent further
bus traffic. tDT limits how long the dominant state can transmit
to the CAN bus by the transceiver. The TXD function restores
when the line is presented with a logic low.
The tDT minimum also inherently creates a minimum data rate.
Under normal operation, the CAN protocol allows five consecutive
bits of the same polarity before stuffing a bit of opposite polarity
into the transmitting bit sequence. When an error is detected,
the CAN controller purposely violates the bit stuffing rules by
producing six consecutive dominant bits. At any given data rate,
the CAN controller must transmit as many as 11 consecutive
dominant bits to effectively limit the ADM3050E minimum
data rate to 9600 bps.
FAIL-SAFE FEATURES
In cases where the TXD input pin is allowed to float to prevent bus
traffic interruption, the TXD input channel has an internal pull-up
to the VDD1 pin. The pull-up holds the transceiver in the recessive state.
THERMAL SHUTDOWN
The integrated transceiver is designed with thermal shutdown
circuitry to protect the device from excessive power dissipation
during fault conditions. Shorting the driver outputs to a low
impedance source can result in high driver currents. The thermal
sensing circuitry detects the increase in die temperature under this
condition and disables the driver outputs. The circuitry disables the
driver outputs when the die temperature reaches 175°C. The
drivers are enabled after the die has cooled.
Rev. B | Page 16 of 19
Data Sheet
ADM3050E
APPLICATIONS INFORMATION
RADIATED EMISSIONS AND PCB LAYOUT
INSULATION LIFETIME
The ADM3050E isolated CAN transceivers with integrated
dc-to-dc converters pass EN 55022, Class B by 6 dB on a simple
2-layer PCB design. Neither stitching capacitance nor high
voltage surface mount (SMT) safety capacitors are required to
meet this emission level.
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period of time. The rate
of insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation as well as on
the materials and material interfaces.
PCB LAYOUT
The two types of insulation degradation of primary interest are
breakdown along surfaces exposed to the air and insulation
wear out. Surface breakdown is the phenomenon of surface
tracking and is the primary determinant of surface creepage
requirements in system level standards. Insulation wear out
is the phenomenon where charge injection or displacement
currents inside the insulation material cause long-term
insulation degradation.
The ADM3050E isolated CAN transceiver requires no external
interface circuitry for the logic interfaces. Power supply
bypassing is required at the logic input supply (VDD1), and the
shared CAN transceiver and digital isolator supply pin (VDD2).
The recommended bypass capacitor value is 0.1 μF. Note that
low effective series resistance (ESR) bypass capacitors are
required and must be placed as close to the chip pads as possible.
The total lead length between both ends of the capacitor and
the input power supply pin must not exceed 10 mm. Bypassing
between Pin 1, Pin 7, and Pin 8 and between Pin 16, Pin 10, and
Pin 9 must also be considered, unless the ground pair on each
package side is connected in close proximity to the package.
In applications involving high common-mode transients,
minimize board coupling across the isolation barrier. Design
the board layout so that any coupling that does occur equally
affects all pins on a given component side. Failure to ensure this
equal coupling can cause voltage differentials between pins
exceeding the absolute maximum ratings of the device, thereby
leading to latch-up or permanent damage.
ADM3050E
1
VDD1
VDD2
16
2
GND1
GND2
15
3
RXD
NC
14
4
NC
CANH
13
5
NC
CANL
12
6
TXD
NC
11
7
GND1
GND2
10
8
GND1
GND2
9
0.1µF
INSULATION WEAR OUT
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. The working voltage applicable
to tracking is specified in most standards.
Figure 25. Recommended 16-Lead SOIC_W PCB Layout
ADM3050E
1
VDD1
VDD2 8
2
TXD
CANH 7
3
RXD
CANL 6
4
GND1
GND 2 5
0.1µF
14971-226
0.1µF
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working
voltage, the environmental conditions, and the properties of the
insulation material. Safety agencies perform characterization
testing on the surface insulation of components, allowing the
components to be categorized in different material groups.
Lower material group ratings are more resistant to surface
tracking and can therefore provide adequate lifetime with
smaller creepage. The minimum creepage for a given working
voltage and material group is in each system level standard and
is based on the total rms voltage across the isolation, pollution
degree, and material group.
The material group and creepage for the ADM3050E isolator is
listed in Table 3 for both the 8-lead, increased creepage SOIC
package option and the 16-lead, wide body SOIC package option.
14971-010
0.1µF
SURFACE TRACKING
Figure 26. Recommended 8-Lead SOIC_IC PCB Layout
THERMAL ANALYSIS
The ADM3050E device consists of three internal die attached to a
split lead frame. For the purposes of thermal analysis, the die are
treated as a thermal unit, with the highest junction temperature
reflected in the θJA value from Table 10. The θJA value is based on
measurements taken with the devices mounted on a JEDEC
standard, 4-layer board with fine width traces and still air.
Testing and modeling have shown that the primary driver of
long-term degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the
insulation can be broken down into broad categories, such as
dc stress, which causes very little wear out because there is no
displacement current, and an ac component time varying
voltage stress, which causes wear out.
Rev. B | Page 17 of 19
ADM3050E
Data Sheet
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltage. Many practical applications have combinations of 60 Hz
ac and dc across the barrier, as shown in Equation 1. Because
only the ac portion of the stress causes wear out, the equation
can be rearranged to solve for the ac rms voltage, as shown in
Equation 2. For insulation wear out with the polyimide materials
used in these products, the ac rms voltage determines the
product lifetime.
VAC RMS 2 + VDC 2
(1)
VAC RMS = VRMS 2 − VDC 2
(2)
=
VRMS
or
where:
VRMS is the total rms working voltage.
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
=
VRMS
VRMS = 240 2 + 400 2
VRMS = 466 V
This VRMS value is the working voltage used together with the
material group and pollution degree when looking up the creepage
required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. To obtain the ac rms voltage,
use Equation 2.
VAC RMS = VRMS 2 − VDC 2
VAC RMS = 240 V rms
The following example frequently arises in power conversion
applications. Assume that the line voltage on one side of the
isolation is 240 V ac rms and a 400 VDC bus voltage is present on
the other side of the isolation barrier. The isolator material is
polyimide. To establish the critical voltages in determining the
creepage, clearance, and lifetime of a device, see Figure 27 and
the following equations.
In this case, the ac rms voltage is simply the line voltage of
240 V rms. This calculation is more relevant when the waveform is
not sinusoidal. The value is compared to the limits for working
voltage in Table 11 for the expected lifetime, which is less than a
60 Hz sine wave, and is well within the limit for a 50-year
service life.
Note that the dc working voltage limit is set by the creepage of
the package as specified in IEC 60664-1. This value can differ
for specific system level standards.
VAC RMS
VRMS
VDC
TIME
14971-011
VPEAK
VAC RMS 2 + VDC 2
VAC RMS = 466 2 − 400 2
CALCULATION AND USE OF PARAMETERS
EXAMPLE
ISOLATION VOLTAGE
The working voltage across the barrier from Equation 1 is
Figure 27. Critical Voltage Example
Rev. B | Page 18 of 19
Data Sheet
ADM3050E
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
1
10.65 (0.4193)
10.00 (0.3937)
8
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
0.51 (0.0201)
0.31 (0.0122)
8°
0°
1.27 (0.0500)
0.40 (0.0157)
0.33 (0.0130)
0.20 (0.0079)
03-27-2007-B
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 28. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
6.05
5.85
5.65
5
7.60
7.50
7.40
PIN 1
MARK
1
4
2.45
2.35
2.25
0.30
0.20
0.10
COPLANARITY
0.10
10.51
10.31
10.11
2.65
2.50
2.35
1.27 BSC
0.51
0.41
0.31
SEATING
PLANE
0.75
0.50
0.25
1.04
BSC
0.75
0.58
0.40
45°
8°
0°
0.33
0.27
0.20
09-17-2014-B
8
Figure 29. 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Wide Body
(RI-8-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADM3050EBRWZ
ADM3050EBRWZ-RL
ADM3050EBRIZ
ADM3050EBRIZ-RL
EVAL-ADM3050EEBZ
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Standard Small Outline Package [SOIC_W]
16-Lead Standard Small Outline Package [SOIC_W]
8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC]
Evaluation Board
Z = RoHS Compliant Part.
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14971-0-9/19(B)
Rev. B | Page 19 of 19
Package
Option
RW-16
RW-16
RI-8-1
RI-8-1