Flexible Condition Monitoring Platform
ADMW1001
Data Sheet
FEATURES
Embedded FIFO
Multiple diagnostics
Per measurement configuration (sensor type, settling time,
gain, excitation currents, linearization, speed)
Configurable cycle sampling time
Embedded sequencer
Simultaneous 50 Hz and 60 Hz antialiasing rejection
SPI communications interface
Power supply voltage: 3.3 V
Operating temperature range: −40°C to +85°C
Enabled by the MeasureWare ecosystem
Rapid configuration
Upgradeable firmware enabling new features
Complete measurement node (sensor excitation, sensor
measurement, and sensor compensation)
Directly digitizes compensated and uncompensated sensors
Sensors include:
RTD
Thermocouple
Wheatstone bridge
Embedded linearization for 2-/3-wire PT100/1000 RTDs
J, K, T, and custom type thermocouples
Supports custom lookup tables
Supports selected I2C/SPI sensors
2 thermocouple channels
2 universal (4-/6-wire bridge, RTD, ratiometric referencing)
channels
APPLICATIONS
Asset health monitoring
Laboratory instrumentation
Smart agriculture
Supply chain health tracking
Condition profiling
FUNCTIONAL BLOCK DIAGRAM
AVDD
IOVDD
RSENSE_BIAS
RSENSE–
RSENSE+
INTERNAL
REFERENCE
CH1_AIN–
CH1_AIN+
CH1_IEXC
CH1_TC+/IEXC
TC_BIAS
COM_TC–
CH2_TC+/IEXC
CH2_IEXC
CH2_AIN+
CH2_AIN–
DIGITAL
FILTER
CALIBRATION
PGA
24-BIT
Σ-Δ ADC
MEASUREMENT
TIME
CORRECTION/
TRANSLATION
PGA
24-BIT
Σ-Δ ADC
50Hz/60Hz
REJECTION
LOOKUP
TABLE/
POLYNOMIAL
MUX
FIFO
INTERFACE
LOGIC
RESET
WAKE_UP
STATUS
CS0
MISO0
MOSI0
SCLK0
DRDY
CS1
MISO1
MOSI1
SCLK1
CURRENT
SOURCES
CHANNEL
SEQUENCER
ADMW1001
VREF+
VREF–
GND_SW
AGND
DVDD_REG
AVDD_REG
INT_REF
SCL SDA
GPIO0 GPIO1 GPIO2
17325-001
DIAGNOSTICS
Figure 1.
Rev. 0
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ADMW1001
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ADC ............................................................................................. 15
Applications ....................................................................................... 1
Powering the ADMW1001 ....................................................... 15
Functional Block Diagram .............................................................. 1
Interface Logic ............................................................................ 15
Revision History ............................................................................... 2
Channel Sequencer .................................................................... 15
General Description ......................................................................... 3
Digital Filter ................................................................................ 15
Specifications..................................................................................... 4
Reference ..................................................................................... 15
Timing Characteristics ................................................................ 7
Calibration and LUT .................................................................. 15
Sensor Interface Timing Specifications ..................................... 8
PGA and Buffer .......................................................................... 15
Absolute Maximum Ratings.......................................................... 10
Excitation Current Source ......................................................... 15
Thermal Resistance .................................................................... 10
Correction and Translation ....................................................... 16
ESD Caution ................................................................................ 10
Multiplexer .................................................................................. 16
Pin Configuration and Function Descriptions ........................... 11
Outline Dimensions ....................................................................... 17
Typical Performance Characteristics ........................................... 13
Ordering Guide .......................................................................... 17
Theory of Operation ...................................................................... 14
Applications Information .............................................................. 15
REVISION HISTORY
7/2019—Revision 0: Initial Version
Rev. 0 | Page 2 of 17
Data Sheet
ADMW1001
GENERAL DESCRIPTION
The ADMW1001 offers a flexible and versatile IC that directly
connects to a range of sensors, which includes temperature and
humidity sensors. The device has all of the building blocks to
excite, measure, and correct the sensor and generate an output
in sensor related units such as °C, °F, and psi. In conjunction
with the MeasureWare® ecosystem, the ADMW1001 can be
easily configured and optimized for the sensor types selected to
meet the accuracy and measurement times required.
The ADMW1001 is a highly flexible device with a feature set and
sensor library that is designed to evolve over time. As additional
functionality is developed, it becomes available, and it can be
flashed to the device during printed circuit board (PCB)
manufacturing or upgraded in the field through the custom
flash loader tool set.
The ADMW1001 can also be ordered preprogrammed with a
specific revision of the firmware preloaded. Contact Analog
Devices, Inc., for more information.
The ADMW1001 is shipped with a firmware loader and
requires flashing of the most recent version of ADMW1001
firmware to enable the growing list of measurement techniques
and features available with MeasureWare. All firmware revisions
for the ADMW1001 are available through the ADMW1001
product page and the MeasureWare Studio.
The ADMW1001 firmware revision 1.0 directly supports
compensated J–, K–, and T–type thermocouples, and PT100
(platinum RTD, 100 Ω at 0°C) and PT1000 (platinum RTD,
1000 Ω at 0°C) 2-/3-wire resistance temperature detectors
(RTD). Linearization for these sensors is automatically handled
by the ADMW1001. The ADMW1001 also allows the user to
connect custom sensors. In addition to various types of RTDs
and thermocouples, the device can interface to 4-wire bridges,
such as pressure or strain transducers. Lookup tables can be
written to the ADMW1001, enabling fully corrected
measurements for custom sensors. Each revision of the
firmware has an associated user guide, which can be found on
the ADMW1001 product page.
The device has two universal measurement channels that
connect to RTDs, 4-wire bridges, and any custom voltage
output sensor.
The device also has two thermocouple inputs. Thermocouple
inputs are available on CH1_TC+/IEXC and CH2_TC+/IEXC
with a shared COM_TC− pin. The TC_BIAS pin must be used
to bias the thermocouples to midscale.
When a channel is configured as a thermocouple or voltage
input channel, it can also support compensation sensors per
channel, in the form of 2-wire and 3-wire RTDs to be used as
temperature compensation or cold junction compensation.
The ADMW1001 includes two I2C measurement inputs and one
serial peripheral interface (SPI) measurement input. These inputs
are useful for compensated sensors such as pressure, humidity,
and accelerometers. The ADMW1001 measures these sensors
and generates an output in sensor related units.
The ADMW1001 features programmable measurement time,
which enables customization of measurement, speed, and
power consumption. Measurement intervals from seconds to
milliseconds are supported. The ADMW1001 also supports
simultaneous 50 Hz and 60 Hz antialiasing rejection, which is a
key requirement in designs where rejection of interference from
the main power supply is required.
With the ADMW1001 per measurement configuration and onchip measurement sequencer, the user can configure each
measurement being used at one time and input the number of
measurements required from each measurement channel, and
the sequencer automatically steps through the cycle. Via a
choice of interface modes, the measurement results can be
accessed immediately when available. Alternatively, the on-chip
first in, first out (FIFO) can hold the results, and all results can
then be read at one time by the host processor. This
functionality minimizes the workload on the host processor.
Cycle time can be set to determine the interval at which the
cycle is repeated. This is useful in systems such as
environmental monitoring, where measurements are not needed
continuously but at intervals of hours or days. The device enters a
low power state during these intervals, which can extend the
battery life.
Multiple embedded diagnostics assist the user in designing a
robust system. Diagnostics such as open wire detection, shortcircuit detection, and checks on customer-entered lookup
tables ensure that sensors are connected to the inputs and that
the device is configured correctly.
The device operates with a single power supply of 3.3 V. It is
specified for a temperature range of −40°C to +85°C, has a size
of 7 mm × 7 mm, and is a 48-lead LFCSP.
Rev. 0 | Page 3 of 17
ADMW1001
Data Sheet
SPECIFICATIONS
AVDD/IOVDD = 3.3 V, internal 1.2 V reference, all specifications at TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
ADC SPECIFICATIONS
Conversion Rate1
No Missing Codes1
Root Mean Squared Noise and Data
Output Rates
Integral Nonlinearity1
Offset Error2, 3, 4, 5, 6
Offset Error Drift vs. Temperature1, 4, 5
Offset Error Lifetime Stability7
Full-Scale Error1, 4, 5, 6, 8
Full-Scale Error Lifetime Stability7
Gain Error Drift vs. Temperature1, 4, 5
Programmable Gain Amplifier (PGA)
Gain Mismatch Error
Power Supply Rejection1
Absolute Input Voltage Range
Unbuffered Mode
Buffered Mode
Differential Input Voltage Ranges1
Common-Mode Voltage (VCM)1
Test Conditions/Comments
ADC0 and ADC1
Min
Typ
Max
Unit
976
Hz
Bits
10
1
20
4
+30
+50
70
μV
μV
μV
μV
ppm of FSR
ppm of FSR
ppm of FSR
ppm of FSR
μV
μV
μV
μV
μV/°C
nV/°C
nV/°C
μV/1000 Hr
μV
μV
μV/1000 Hr
±3
±6
±0.15
ppm/°C
ppm/°C
%
5
24
fADC ≤ 250 Hz
Gain = 1, ADC speed = 5 Hz
Gain = 8, ADC speed = 5 Hz
Gain = 1, ADC speed = 122 Hz
Gain = 8, ADC speed = 122 Hz
Gain = 1
Gain = 8
Gain = 2, 4, or 16
Gain = 32, 64, or 128
Chop off
Chop on, gain = 1
Chop on, gain = 8
Chop on. gain ≥ 16
Chop off, gain ≤ 4
Chop off, gain ≥ 8
Chop on
Gain = 128
Gain = 1
Gain = 8
Gain = 128
External reference
Gain = 1, 2, 4, 8, or 16
Gain = 32, 64, or 128
−30
−50
−10
−2
±10
±15
±20
±230/gain
±1.0
+10
+2
±1.0
1/gain
230
10
1
−500
−500
+500
+500
External reference
Chop on, ADC input = 0.25 V, gain = 4
Chop off, ADC input = 7.8 mV, gain = 128
Chop off, ADC input = 1 V, gain = 1
95
80
90
Available for all gain settings G = 1 to 128
AGND
AGND + 0.1
AVDD
AVDD − 0.1
V
V
AGND
±VREF
±500
±250
±125
±62.5
AVDD
V
mV
mV
mV
mV
V
Gain = 1
Gain = 2
Gain = 4
Gain = 8
Gain = 16
Ideally, VCM = ((AIN+) + (AIN−))/2, gain = 2
to 128, input current varies with VCM
Rev. 0 | Page 4 of 17
dB
dB
dB
Data Sheet
Parameter
Input Current
Buffered Mode
Unbuffered Mode
Average Input Current Drift1
Buffered Mode
Unbuffered Mode
Common-Mode Rejection, DC1
Common-Mode Rejection,
Simultaneous 50 Hz and 60 Hz
Antialiasing Rejection1
Normal Mode Rejection,
50 Hz and 60 Hz1
GROUND SWITCH
On Resistance (RON)
Allowable Current1
VOLTAGE REFERENCE
Internal VREF
Initial Accuracy
Reference Temperature Coefficient
(TC)1, 9
Power Supply Rejection1
EXTERNAL REFERENCE INPUTS
Input Range
Buffered Mode
Unbuffered Mode
Input Current
Buffered Mode
Unbuffered Mode
Normal Mode Rejection1
Common-Mode Rejection1
Reference Detect Levels1
EXCITATION CURRENT SOURCES
Output Current
Initial Tolerance at 25°C1
Accuracy
Drift1
Initial Current Matching at 25°C1
Drift Matching1
Load Regulation
ADMW1001
Test Conditions/Comments
Min
Typ
Max
Unit
Gain 1, 8
Gain 2, 4, ≥16
Input current varies with input voltage
−20
+2
2
860
+20
nA
nA
nA/V
CH1_AIN+, CH1_TC+/IEXC, CH2_IEXC,
RSENSE+
RSENSE−, CH1_IEXC, CH2_AIN−, COM_TC−
CH1_AIN−, CH2_TC+/IEXC, CH2_AIN+
On ADC input
ADC gain = 1, AVDD < 2 V
ADC gain = 1, AVDD > 2 V
ADC gain = 2 to 128
50 Hz and 60 Hz ± 1 Hz, fADC = 8.24 Hz
65
80
80
±5
pA/°C
±9
±15
±250
pA/°C
pA/°C
pA/V/°C
100
100
dB
dB
dB
ADC gain = 1
ADC gain = 2 to 128
On ADC input
97
90
dB
dB
50 Hz and 60 Hz ± 1 Hz, fADC = 8.24 Hz,
chop on, fADC = 50 Hz, chop off
60
80
3.7
10
20 kΩ resistor off, direct short to ground
VREF = ADC internal reference
dB
19
20
Ω
mA
+0.1
+15
V
%
ppm/°C
1.2
Measured at TA = 25°C
Minimum differential voltage between
VREF+ and VREF− pins is 400 mV
−0.1
−15
±5
82
90
AGND + 0.1
0
−20
85
Available from each current source, value is
programmable from 10 μA to 1 mA
Excitation output current (IOUT) ≥ 50 μA
10 μA setting
250 μA setting
Using an internal reference resistor
Matching between both current sources
AVDD1 = 3.3 V
Rev. 0 | Page 5 of 17
+10
500
80
100
400
10
dB
AVDD − 0.1
AVDD
V
V
+27
nA
nA/V
dB
dB
mV
1000
μA
±5
8
200
100
±0.5
50
0.2
15
300
400
%
μA
μA
ppm/°C
%
ppm/°C
%/V
ADMW1001
Parameter
Output Compliance1
POWER-ON RESET (POR)
POR Trip Level
Timeout from POR1
DIGITAL INPUTS
Input Leakage Current
Logic 1
Logic 0
Input Leakage Current
Logic 1
Logic 0
Input Capacitance1
Logic Input Voltage
Low, VINL
High, VINH
Logic Output Voltage
High, Voltage Output High (VOH)
Low, Voltage Output Low (VOL)
START-UP TIME1
After Reset Event
Wake-Up Time
POWER REQUIREMENTS
Power Supply Voltages, Supply
Voltage (VDD)
Power Consumption
Supply Current (IDD) (Active
Mode)
IDD (Hibernation)
Data Sheet
Test Conditions/Comments
IOUT = 10 μA to 210 μA
IOUT > 210 μA
Min
AGND − 0.03
AGND − 0.03
Voltage at IOVDD pin
Power-on level
Power-down level
All digital inputs
Digital inputs except for the RESET
Voltage input high (VINH) = IOVDD or VINH =
1.8 V
Internal pull-up disabled
Voltage input low (VINL) = 0 V
Internal pull-up disabled
RESET
Typ
Max
AVDD − 0.85
AVDD − 1.1
1.65
1.65
50
V
V
ms
140
μA
1
160
10
nA
μA
nA
140
160
10
μA
μA
pF
0.2 × IOVDD
0.7 × IOVDD
Current Source (ISOURCE) = 1 mA
Current Sink (ISINK) = 1 mA
Unit
V
V
IOVDD − 0.4
0.4
V
V
V
V
Time to first sample
100
50
ms
μs
AVDD, IOVDD
3.3
V
5
6
15
1
These numbers are not production tested but are guaranteed by design and/or characterization data at production release.
Tested at gain = 4 after initial offset calibration.
3
Measured with a short-circuit of the analog input pins. A system zero-scale calibration removes this error.
4
A recalibration at any temperature removes these errors.
5
These numbers do not include internal reference temperature drift.
6
Factory calibrated at gain = 1.
7
The long-term stability specification is noncumulative. The drift in subsequent 1000 hour periods is significantly lower than in the first 1000 hour period.
8
System calibration at a specific gain removes the error at this gain.
9
Measured using the box method.
2
Rev. 0 | Page 6 of 17
mA
μA
Data Sheet
ADMW1001
TIMING CHARACTERISTICS
SPI Master Interface Timing Specifications
Table 2. SPI Slave Mode Timing
Parameter
tCS0
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tSFS
t12
Min
62.5
125
125
Typ
Max
49.1
20.2
10.1
12
12
12
12
35.5
35.5
35.5
35.5
0
60
Slave SPI interface operates in Mode 0. Clock polarity (CPOL) = clock phase (CPHA) = 0.
CS0
tSFS
tCS0
SCLK0
(POLARITY = 0)
tSL
tDAV
tDF
MSB
MISO0
MOSI0
tSR
tDR
tSF
BIT 6 TO BIT 1
MSB IN
LSB
BIT 6 TO BIT 1
LSB IN
17325-002
tSH
tDSU
tDHD
Figure 2. SPI Slave Mode Timing
t12
MOSI0
MISO0
WRITE
WRITE
t12
t12
READ
READ
DRDY
17325-003
1
Description
CS0 to SCLK0 edge
SCLK0 low pulse width1
SCLK0 high pulse width1
Data output valid after SCLK0 edge
Data input setup time before SCLK0 edge
Data input hold time after SCLK0 edge
Data output fall time
Data output rise time
SCLK0 rise time
SCLK0 fall time
CS0 high after SCLK0 edge
CS0 low to CS0 high time
SCLK0
Figure 3. Delay Between Consecutive Serial Operations
Rev. 0 | Page 7 of 17
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
ADMW1001
Data Sheet
SENSOR INTERFACE TIMING SPECIFICATIONS
SPI Timing Specifications
Table 3. SPI Master Mode Timing
Parameter
tSL
tSH
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
Min
62.5
Typ
500
500
0
Max
12
12
12
12
35.5
35.5
35.5
35.5
35.5
((SPIDIV + 1) × tUCLK)/2
58.7
16
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SPIDIV = 8 MHz/SPI_CLK_SPEED. There are 16 SPI_CLK_SPEED options available for slave devices from 8 MHz to 244 Hz.
CS1
1/2 SCLK1
CYCLE
3/4 SCLK1
CYCLE
tCS1
tSFS
SCLK1
(POLARITY = 0)1
tSH
tSL
tSR
tSF
SCLK1
(POLARITY = 1)
tDAV
tDF
MOSI1
tDR
MSB
MISO1
BIT 6 TO BIT 1
MSB IN
LSB
BIT 6 TO BIT 1
LSB IN
17325-004
tDSU
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 1)
1 SCLK1 CYCLE
1 SCLK1 CYCLE
CS1
tCS1
tSFS
SCLK1
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK1
(POLARITY = 1)
tDAV
tDOSU
MOSI1
MISO1
tDF
MSB
MSB IN
tDR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
LSB IN
17325-005
1
Description
SCLK1 low pulse width1
SCLK1 high pulse width1
Data output valid after SCLK1 edge
Data output setup time before SCLK1 edge1
Data input setup time before SCLK1 edge
Data input hold time after SCLK1 edge
Data output fall time
Data output rise time
SCLK1 rise time
SCLK1 fall time
tDSU
tDHD
Figure 5. SPI Master Mode Timing (Phase Mode = 0)
Rev. 0 | Page 8 of 17
Data Sheet
ADMW1001
I2C Sensor Timing Specifications
The capacitive load for each I2C bus line (CB) is 400 pF maximum as per the I2C bus specifications. I2C timing is guaranteed by design but
is not production tested.
Table 4. I2C Timing in Fast Mode (400 kHz)
Parameter
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
tSUP
Description
Serial clock (SCL) low pulse width
SCL high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCL and serial data (SDA)
Fall time for both SCL and SDA
Pulse width of suppressed spike
Min
1300
600
600
100
0
600
600
1.3
20 + 0.1 CB
20 + 0.1 CB
0
Max
Min
4.7
4.0
4.7
250
0
4.0
4.0
4.7
Max
Unit
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
300
300
50
Table 5. I2C Timing in Standard Mode (100 kHz)
Parameter
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
Description
SCL low pulse width
SCL high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both SCL and SDA
Fall time for both SCL and SDA
tBUF
Unit
μs
ns
μs
ns
μs
μs
μs
μs
μs
ns
1
300
tSUP
tR
MSB
tDSU
LSB
tSHD
P
S
tF
tDHD
tR
tRSU
tH
1
SCL (I)
MSB
tDSU
tDHD
tPSU
ACK
8
tL
9
tSUP
STOP
START
CONDITION CONDITION
1
S(R)
REPEATED
START
Figure 6. I2C-Compatible Interface Timing
Rev. 0 | Page 9 of 17
tF
17325-006
SDA (I/O)
ADMW1001
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
THERMAL RESISTANCE
Table 6.
Thermal performance is directly linked to PCB design and
operating environment. Close attention to PCB thermal design
is required.
Parameter
AVDD to AGND
IOVDD to AGND
Digital Input Voltage to DGND
Digital Output Voltage to DGND
Analog Inputs to AGND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
Electrostatic Discharge (ESD) Rating, All Pins
Human Body Model (HBM)
Field-Induced Charged Device Model
(FICDM)
Peak Solder Reflow Temperature
Tin-Lead (SnPb) Assemblies (10 sec to
30 sec)
Pb-Free Assemblies (20 sec to 40 sec)
Rating
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−40°C to +85°C
−65°C to +150°C
150°C
Table 7. Thermal Resistance
Package Type
CP-48-4
ESD CAUTION
±2 kV
±850 V
240°C
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 10 of 17
θJA
27
θJC
9.5
Unit
°C/W
Data Sheet
ADMW1001
48
47
46
45
44
43
42
41
40
39
38
37
DNC
DNC
SCL
CS0
MOSI0
SCLK0
MISO0
DRDY
WAKE_UP
GPIO2
STATUS
IOVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADMW1001
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
DNC
DNC
GPIO1
GPIO0
CS1
MOSI1
SCLK1
MISO1
TC_BIAS
COM_TC–
CH2_AIN–
CH2_AIN+
NOTES
1. DNC = DO NOT CONNECT.
2. EXPOSED PAD. THE LFCSP HAS AN EXPOSED PAD THAT MUST BE SOLDERED
TO A METAL PLATE ON THE PCB AND TO DGND.
17325-007
GND_SW
VREF+
VREF–
AGND
AVDD
AVDD_REG
RSENSE_BIAS
INT_REF
DNC
CH1_TC+/IEXC
CH2_TC+/IEXC
CH2_IEXC
13
14
15
16
17
18
19
20
21
22
23
24
RESET 1
SDA 2
DNC 3
DNC 4
DNC 5
IOVDD 6
DVDD_REG 7
RSENSE– 8
RSENSE+ 9
CH1_AIN– 10
CH1_AIN+ 11
CH1_IEXC 12
Figure 7. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1
2
Mnemonic
RESET
SDA
3
4
5
6
7
8
DNC
DNC
DNC
IOVDD
DVDD_REG
RSENSE−
9
RSENSE+
10
11
12
CH1_AIN−
CH1_AIN+
CH1_IEXC
13
14
15
16
17
18
GND_SW
VREF+
VREF−
AGND
AVDD
AVDD_REG
19
20
21
22
RSENSE_BIAS
INT_REF
DNC
CH1_TC+/IEXC
23
CH2_TC+/IEXC
Description
Device Reset Pin. When this pin is taken low, the ADMW1001 is reset to the default state.
Serial Data for I2C Sensor Interface. This serial clock is used in conjunction with the SCL pin to transfer data
between the ADMW1001 and an I2C sensor connected to this port. The port accommodates up to two I2C sensors.
Do Not Connect.
Do Not Connect.
Do Not Connect.
Digital System Supply Pin. This pin must be connected to AGND via a 0.1 μF capacitor.
Digital Regulator Supply. This pin must be connected to AGND via a 470 nF capacitor and to Pin 18, AVDD_REG.
Sense Resistor Negative Input. This pin is used for differential readings of an externally supplied reference resistor
(RSENSE). This input must be biased to AGND + 100 mV for accurate measurements. Connect to RSENSE_BIAS.
Sense Resistor Positive Input. This pin is used for differential readings of RSENSE. Connect a low temperature
coefficient resistor (recommended 1 kΩ, 10 ppm) between RSENSE+ and RSENSE− for RTD measurements.
Universal Channel 1 Analog Input 1−.
Universal Channel 1 Analog Input 1+.
Universal Channel 1 Current Excitation Output. This pin can be configured as the output pin for the excitation
current source.
Sensor Power Switch to Analog Ground Reference. This pin automatically cycles with measurement sequence.
External Reference Positive Input. An external reference can be applied between the VREF+ pin and VREF− pin.
External Reference Negative Input. An external reference can be applied between the VREF+ pin and VREF− pin.
Analog System Ground Reference Pin.
Analog System Supply Pin. This pin must be connected to AGND via a 0.1 μF capacitor. Connect to a 3.3 V supply.
Internal Analog Regulator Supply Output. This pin must be connected to AGND via a 470 nF capacitor and to
Pin 7, DVDD_REG.
Bias Voltage Output. Connect to RSENSE−.
Internal Reference. This pin must be connected to ground via a 470 nF decoupling capacitor.
Do Not Connect.
Universal Channel 1 Thermocouple Input and Current Excitation Output. This pin can be configured as the
output pin for the excitation current source or an input to the ADC.
Universal Channel 2 Thermocouple Input and Current Excitation Output. This pin can be configured as the
output pin for the excitation current source or an input to the ADC.
Rev. 0 | Page 11 of 17
ADMW1001
Pin No.
24
Mnemonic
CH2_IEXC
25
26
27
CH2_AIN+
CH2_AIN−
COM_TC−
28
TC_BIAS
29
30
MISO1
SCLK1
31
32
MOSI1
CS1
33
34
35
36
37
38
GPIO0
GPIO1
DNC
DNC
IOVDD
STATUS
39
40
GPIO2
WAKE_UP
41
DRDY
42
43
MISO0
SCLK0
44
45
MOSI0
CS0
46
SCL
47
48
DNC
DNC
Exposed Pad
Data Sheet
Description
Universal Channel 2 Current Excitation Output. This pin can be configured as the output pin for the excitation
current source. This pin can also be configured as an input to the ADC.
Universal Channel 2 Analog Input 1+.
Universal Channel 2 Analog Input 1−.
Common Thermocouple Input. This pin can be used for thermocouple measurement with CH1_TC+/IEXC and
CH2_TC+/IEXC simultaneously.
Analog Voltage Bias Pin. This pin is used to bias COM_TC− to midscale for TC measurements. Connect to COM_TC−
when performing TC measurements.
SPI Master In/Slave Out. Serial data is transmitted from the SPI sensor to the ADMW1001 on this pin.
SPI Serial Clock Output. This pin supplies the serial clock for data transfers between the ADMW1001 and an
external SPI sensor that can be connected to the SPI interface. The serial clock can be continuous with all data
transmitted in a continuous train of pulses. Alternatively, the serial clock can be a noncontinuous clock with the
information transmitted in smaller batches of data.
SPI Master Out/Slave In. Serial data is transmitted from the ADMW1001 to the SPI sensor on this pin.
SPI Chip Select Output. This is an active low logic output that selects the digital SPI sensor. CS1 is used as a
frame synchronization signal when communicating with the digital sensor.
GPIO Pin. Tie to ground or do not connect if unused.
GPIO Pin. Tie to ground or do not connect if unused.
Do Not Connect.
Do Not Connect.
Digital System Supply Pin. This pin must be connected to AGND via a 0.1 μF capacitor.
Status Pin. This pin indicates if an error or alert has occurred. This pin goes high if the error bit in the status
register is set or if the alert bit is set. The error bit is set if any of the diagnostics included in the ADMW1001
report an error, and the alert bit is set if the threshold values have been exceeded for any sensor setup.
GPIO Pin. Tie to ground or do not connect if unused.
WAKE_UP Pin. This pin is required to wake the device up from hibernation mode if enabled. Hibernation mode
can be enabled through an SPI command. This pin is active low.
Data Ready Digital Output. DRDY is a data ready pin, going high to indicate the completion of a sensor measurement.
The functionality of this pin is programmable. DRDY can be programmed to go high on the completion of each
individual measurement, when a cycle is complete, or when the FIFO is full. If the measurement results are not
read before new measurement data is available, the pin goes high before the next update occurs. The DRDY
rising edge can also be used as an interrupt to a processor, indicating that valid measurement data is available.
SPI Master In/Slave Out. Serial data is transmitted from the ADMW1001 to the host processor on this pin.
SPI Serial Clock Input. This pin accepts the serial clock for data transfers between the ADMW1001 and the host
processor. The serial clock can be continuous with all data transmitted in a continuous train of pulses. Alternatively,
the serial clock can be a noncontinuous clock with the information transmitted in smaller batches of data.
SPI Master Out/Slave In. Serial data is transmitted from the host processor to the ADMW1001 on this pin.
SPI Chip Select Input. This is an active low logic input that selects the serial interface of the ADMW1001. CS0 is
used as a frame synchronization signal when communicating with the ADMW1001.
Serial Clock for I2C Sensor Interface. This serial clock is used in conjunction with the SDA pin to transfer data
between the ADMW1001 and an I2C sensor connected to this port. The port accommodates up to two I2C
sensors.
Do Not Connect.
Do Not Connect.
Exposed Pad. The LFCSP has an exposed pad that must be soldered to a metal plate on the PCB and to AGND.
Rev. 0 | Page 12 of 17
Data Sheet
ADMW1001
30
IP
IN
IP – IN
20
10
0
–10
–30
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
COMMON-MODE VOLTAGE (V)
17325-008
–20
Figure 8. Input Current vs. Common-Mode Voltage (VCM), Gain = 4,
ADC Input = 250 mV, AVDD = 3.6 V, TA = 25°C, VCM = ((AIN+) + (AIN−))/2
5
4
2
1
0
–1
–2
–3
IP
IN
IP – IN
–4
–5
0
0.5
1.0
1.5
2.0
2.5
COMMON-MODE VOLTAGE (V)
3.0
3.5
17325-009
INPUT CURRENT (nA)
3
Figure 9. Input Current vs. Common-Mode Voltage (VCM), Gain = 128,
ADC Input = 7.8125 mV, AVDD = 3.6 V, TA = 25°C, VCM = ((AIN+) + (AIN−))/2
25
20
15
10
5
0
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOLTAGE APPLIED TO DIGITAL PIN (V)
17325-012
INPUT CURRENT (nA)
40
30
Figure 10. Digital Input Pin Pull-Up Resistance Value vs. Voltage Applied
to Digital Pin, TA = 25°C, IOVDD = 3.4 V
60
50
40
30
20
10
0
0
0.5
1.0
1.5
VOLTAGE APPLIED TO DIGITAL PIN (V)
2.0
17325-013
50
DIGITAL INPUT PIN PULL-UP RESISTANCE VALUE (kΩ)
60
DIGITAL INPUT PIN PULL-UP RESISTANCE VALUE (kΩ)
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 11. Digital Input Pin Pull-Up Resistance Value vs. Voltage Applied
to Digital Pin, TA = 25°C, IOVDD = 1.8 V
Rev. 0 | Page 13 of 17
ADMW1001
Data Sheet
THEORY OF OPERATION
Figure 12 shows the ADMW1001 configured for two RTDs and
two thermocouples on the analog channels. A precision 1 kΩ
resistor is required as a ratiometric reference for measuring
RTDs on the universal channels. The value of this resistor can
be programmed into the reference resistor register for greater
precision. In this measurement setup, the RTD temperature
measurements can be used as cold junction compensation
measurements for the thermocouple channels. Optional analog
filters can be placed on the analog inputs as antialiasing filters
to remove unwanted out of band noise.
Information on firmware flashing and links to the firmware
repository can be obtained from the MeasureWare Studio. Each
firmware revision is accompanied with a user guide revision
detailing sensor compatibility, device configuration, and best
practices for the ADMW1001. For information on the features,
functionality, and performance of each firmware revision, go to
the MeasureWare Studio for the firmware user guide.
For rapid development, visit the MeasureWare Designer to
develop a configuration file that can be used with the
MeasureWare Lab or exported to a C++ header file that can be
used with the ADMW1001 C++ API, which is available in the
MeasureWare Studio.
I2C SENSOR INTERFACE
CH1_AIN–
8
RSENSE–
33
GPIO0
10
34
GPIO1
CH1_AIN+
29
MISO1
11
30
MOSI1
CH1_IEXC
31
SCLK1
12
32
CS1
RESET
46
SCL
1
SPI SENSOR INTERFACE
2
SDA
RESET
GPIO2 39
RTD
DVDD
STATUS 38
IOVDD 37
0.1µF
1kΩ
9
RSENSE+
19
RSENSE_BIAS
26
CH2_AIN–
25
CH2_AIN+
24
CH2_IEXC
22
CH1_TC+/IEXC
MOSI0 44
28
TC_BIAS
SCLK0 43
27
COM_TC–
MISO0 42
23
CH2_TC+/IEXC
DRDY 41
14
VREF+
15
VREF–
13
GND_SW
DGND
ADMW1001
RTD
WAKE_UP
AVDD
DVDD_REG
16
AVDD_REG
20
AVDD
CS0 45
AGND
17
18
7
SPI HOST INTERFACE
DVDD
IOVDD 6
0.1µF
DGND
0.1µF
0.47µF
0.47µF
5V
ADP1720ARMZ-3.3
1µF
DGND
DVDD
AVDD
1.6Ω
OUT
IN
EN
4.7µF
4.7µF
0.1µF
GND
AGND
DGND
Figure 12. Typical Connection Diagram
Rev. 0 | Page 14 of 17
AGND AGND
17325-014
THERMOCOUPLE
WAKE_UP 40
INT_REF
THERMOCOUPLE
Data Sheet
ADMW1001
APPLICATIONS INFORMATION
The ADMW1001 is ideally suited to precision sensor
measurement applications. The benefit of the ADMW1001 is
rapid configuration for defined measurement types. The blocks
of the ADMW1001 are explained in more detail in this section.
ADC
The ADMW1001 features two 24-bit simultaneous sampling Σ-Δ
ADCs. Each ADC is connected to a separate input buffer, PGA,
and digital filter. The ADC can use the internal reference or
external references from the AVDD supply of the VREF+ and
VREF− input pins. ADC conversions can be configured from
5 SPS to 1 kSPS.
POWERING THE ADMW1001
Powering the ADMW1001 requires a 3.3 V dc supply. A precision
low dropout regulator (LDO) is recommended with filtering
between the analog and digital power inputs to reduce noise
coupling into the sensitive analog front end. The AVDD_REG pin
and DVDD_REG pin are shorted together and connected to a
common decoupling capacitor.
INTERFACE LOGIC
The logic interface that is used for communication and
configuration of the ADMW1001 is accomplished using the
host SPI interface. A data ready signal is issued by the DRDY pin
every time a new conversion is complete and can be used to
interrupt a host microcontroller.
The WAKE_UP signal is active low and requires a pull-up to
AVDD or direct connection to a host controller pin. When the
device is placed in hibernation mode, only a high to low
transition on the WAKE_UP signal can put the device back into
full power mode.
CHANNEL SEQUENCER
The ADMW1001 features a smart channel sequencer. The
sequencer creates a measurement cycle from all the enabled
channels. The cycle can be programmed to repeatedly sample at
programmed intervals in continuous mode, or every time a
convert command is issued in single cycle mode.
A 2 kb FIFO allows samples to be buffered on the ADMW1001,
which reduces the burden on host processors and allows bulk
ready back of samples.
DIGITAL FILTER
The ADMW1001 supports a range of sample rates from as slow
as 5 SPS to 1 kSPS. However, there is a noise vs. speed trade-off,
and the default values for each sensor are chosen to have the
best performance in a wide range of environmental noise
conditions. Only a subset of the speed options filter 50 Hz and
60 Hz power line frequency interference.
Lower output data rates offer lower noise measurements and
also tune the filter notch. Nine speed modes have been defined
for optimized speed and noise.
REFERENCE
The internal reference is a 1.2 V precision reference. The initial
tolerance is ±0.1% with a typical drift of 100 ppm/°C. The
internal reference is selected by default for all measurement
types. The AVDD supply can also be switched internally to the
reference supply to enable a large dynamic range when the
input buffers are disabled. External referencing can also be
selected using the VREF+ and VREF− input pins. This can be
used for precision measurement where ratiometric referencing
is required.
CALIBRATION AND LUT
The ADMW1001 has a series of calibration features, including
per sensor offset and gain configuration options. These values
can be stored in the configuration and are loaded on power-up.
The ADMW1001 has sensor lookup tables (LUT), which can be
used for 4-wire bridge applications and custom sensor
configuration.
PGA AND BUFFER
The PGA on the analog front end allows the analog signals to
be amplified in gain stages of 1× to 128×. For thermocouple
measurement, a gain of 8× is recommended to achieve the best
range and accuracy results. For RTD, a gain of 1× is recommended
when a value of 1 kΩ is selected for the ratiometric resistors.
The analog input voltage range is constricted when the PGA is
enabled. See the Specifications section for more information on
analog input ranges.
A separate analog buffer can be enabled or disabled on the front
end. For low impendence sensors or buffered sensors, the
ADMW1001 analog input buffer can be disabled. When the
buffer is disabled, the analog input range is extended to AVDD.
EXCITATION CURRENT SOURCE
The excitation current sources can be used to excite RTDs and
other custom sensors. For 2-wire and 3-wire RTD measurement,
the CH1_IEXC pin and CH2_IEXC pin are used as the primary
excitation source. For 3-wire RTD measurements, the
CH1_TC+/IEXC pin and CH2_TC+/IEXC pin are also used as
current sources to remove the error introduced from lead
resistance. Current source options are 10 μA, 50 μA, 100 μA,
250 μA, 500 μA, and 1000 μA.
Rev. 0 | Page 15 of 17
ADMW1001
Data Sheet
CORRECTION AND TRANSLATION
MULTIPLEXER
The ADMW1001 allows the selection of specific defined
measurement types, such as K–, J–, and T–type thermocouples
and PT100 and PT1000 RTDs. The ADMW1001 completes the
sampling sequence required for each measurement type and
applies the translation from ADC bits to temperature in °C or
°F. The thermocouple table and RTD polynomials are stored
internally, but custom tables can be loaded through the LUT.
The multiplexer (MUX) is used to switch in front-end signals to
the ADC buffers automatically, depending on the measurement
type selected.
Rev. 0 | Page 16 of 17
Data Sheet
ADMW1001
OUTLINE DIMENSIONS
7.10
7.00 SQ
6.90
PIN 1
INDICATOR
AREA
DETAIL A
(JEDEC 95)
0.30
0.23
0.18
37
36
48
1
0.50
BSC
P IN 1
IN D IC AT O R AR E A OP T IO N S
(SEE DETAIL A)
5.20
5.10 SQ
5.00
EXPOSED
PAD
12
0.80
0.75
0.70
END VIEW
PKG-004509
SEATING
PLANE
0.45
0.40
0.35
24
13
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.20 MIN
5.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4
10-10-2018-C
TOP VIEW
Figure 13. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADMW1001BCPZ
ADMW1001BCPZ-RL7
EV-ProMW1001ARDZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP]
48-Lead Lead Frame Chip Scale Package [LFCSP]
ADMW1001 Prototype Development Kit
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17325-0-7/19(0)
Rev. 0 | Page 17 of 17
Package Option
CP-48-4
CP-48-4
Ordering Quantity
260
750
1
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