Constant Frequency Current-Mode
Step-Down DC-to-DC Controller in TSOT
ADP1864
Data Sheet
FEATURES
GENERAL DESCRIPTION
Wide input voltage range: 3.15 V to 14 V
Wide output voltage range: 0.8 V to input voltage
Pin-to-pin compatible with LTC1772, LTC3801
Up to 94% efficiency
0.8 V ± 1.25% reference accuracy over temperature
Internal soft start
100% duty cycle for low dropout voltage
Current-mode operation for good line and load
transient response
7 μA shutdown supply current
235 μA quiescent supply current
Short-circuit and overvoltage protection
Small 6-lead TSOT package
Supported by ADIsimPower™ design tool
The ADP1864 is a compact, inexpensive, constant-frequency,
current-mode, step-down dc-to-dc controller. The ADP1864
drives a P-channel MOSFET that regulates an output voltage as
low as 0.8 V with ±1.25% accuracy, for up to 5 A load currents,
from input voltages as high as 14 V.
The ADP1864 provides system flexibility by allowing accurate
setting of the current limit with an external resistor, and the
output voltage is easily adjustable using two external resistors.
The ADP1864 includes an internal soft start to allow quick
power-up while preventing input inrush current. Additional
safety features include short-circuit protection, output overvoltage
protection, and input undervoltage protection. Current-mode
control provides fast and stable load transient performance,
while the 580 kHz operating frequency allows a small inductor
to be used in the system. To further the life of a battery source,
the controller turns on the external P-channel MOSFET 100%
of the duty cycle during dropout.
APPLICATIONS
Wireless devices
1- to 3-cell Li-Ion battery-powered applications
Set-top boxes
Processor core power supplies
Hard disk drives
The ADP1864 operates over the −40°C to +125°C temperature
range and is available in a small, low profile, 6-lead TSOT package.
TYPICAL APPLICATIONS DIAGRAM
25kΩ
1
470pF
COMP
68pF
80.6kΩ
PGATE 6
2
GND
3
FB
VIN = 3.15V TO 14V
0.03Ω
ADP1864
10µF
IN 5
5µH
CS 4
2.5V, 2.0A
47µF
05562-001
174kΩ
Figure 1.
Rev. C
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ADP1864
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Soft Start .........................................................................................9
Applications ....................................................................................... 1
Applications Information .............................................................. 10
General Description ......................................................................... 1
Duty Cycle ................................................................................... 10
Typical Applications Diagram ........................................................ 1
Ripple Current ............................................................................ 10
Revision History ............................................................................... 2
Sense Resistor.............................................................................. 10
Specifications..................................................................................... 3
Inductor Value ............................................................................ 10
Absolute Maximum Ratings ............................................................ 4
MOSFET ...................................................................................... 11
ESD Caution .................................................................................. 4
Diode............................................................................................ 11
Pin Configuration and Function Descriptions ............................. 5
Input Capacitor ........................................................................... 11
Typical Performance Characteristics ............................................. 6
Output Capacitor........................................................................ 11
Theory of Operation ........................................................................ 8
Feedback Resistors ..................................................................... 11
Loop Startup .................................................................................. 8
Layout Considerations ................................................................... 12
Short-Circuit Protection .............................................................. 9
Example Applications Circuits ..................................................... 13
Undervoltage Lockout (UVLO) ................................................. 9
Outline Dimensions ....................................................................... 14
Overvoltage Lockout Protection (OVP).................................... 9
Ordering Guide .......................................................................... 14
REVISION HISTORY
8/12—Rev. B to Rev. C
Change to Features Section ............................................................. 1
Added ADIsimPower Design Tool Section ................................. 10
Updated Outline Dimensions ....................................................... 14
Changes to Ordering Guide .......................................................... 14
4/08—Rev. A to Rev. B
Change General Description Section............................................. 1
Deleted Figure 2 ................................................................................ 1
Change to FB Regulation Voltage Parameter................................ 3
Change to MOSFET Section ......................................................... 11
Changes to Ordering Guide .......................................................... 14
2/07—Rev 0. to Rev. A
Updated Format .................................................................. Universal
Changes to Figure 1 .......................................................................... 1
Changes to General Description .................................................... 2
Changes to Specifications ................................................................ 3
Change to Figure 13 ......................................................................... 8
Replaced Layout Considerations Section .................................... 12
Replaced Example Applications Circuits Section ...................... 13
10/05—Revision 0: Initial Version
Rev. C | Page 2 of 16
Data Sheet
ADP1864
SPECIFICATIONS
VIN = 5 V, TJ = 25°C, unless otherwise noted.
Table 1.
Parameter
POWER SUPPLY
Input Voltage
Quiescent Current
Shutdown Supply Current
Undervoltage Lockout Threshold
VIN
IQ
ISD
VUVLO
ERROR AMPLIFIER
FB Input Current
IFB
Amplifier Transconductance
COMP Startup Threshold
COMP Shutdown Threshold
COMP Start-Up Current Source
FB Regulation Voltage
Overvoltage Protection Threshold
Overvoltage Protection Hysteresis
CURRENT SENSE
Peak Current Sense Voltage
Current Sense Gain
OUTPUT REGULATION
Line Regulation 1
Load Regulation 2
OSCILLATOR
Oscillator Frequency
FB Frequency Foldback Threshold
GATE DRIVE
Gate Rise Time
Gate Fall Time
Minimum On Time
SOFT START POWER-ON TIME
1
2
Symbol
VOVP
Conditions
Min
Typ
Max
Unit
235
7
2.90
3.00
14
360
15
3.01
3.15
V
μA
μA
V
V
+20
+40
nA
nA
mmho
V
V
μA
V
V
mV
3.15
VIN = 3.15 V to 14 V, PGATE = IN
VIN = 3.15 V to 14 V, COMP = GND
VIN falling, TJ = −40°C to +125°C
VIN rising, TJ = −40°C to +125°C
2.75
2.85
VFB = 0.8 V, TJ = 25°C
VFB = 0.8 V, TJ = −40°C to +125°C
VFB = 0.8 V, ICOMP = ±5 μA
VIN = 3.15 V to 14 V, TJ = −40°C to +125°C
VIN = 3.15 V to 14 V, TJ = −40°C to +125°C
COMP = GND
VIN = 3.15 V to 14 V, TJ = −40°C to +125°C
Measured at FB, TJ = −40°C to +125°C
−20
−40
TJ = −40°C to +125°C
VIN = 3.15 V to 14 V, TJ = −40°C to +125°C
VCS to VCOMP
90
70
0.55
0.15
0.25
0.790
0.87
VIN = 3.15 V to 14 V, VFB/VIN
VFB/VCOMP
VFB = 0.8 V, TJ = −40°C to +125°C
VFB = 0 V
CGATE = 3 nF
CGATE = 3 nF
PGATE minimum low duration
500
−2
−2
0.24
0.67
0.3
0.6
0.8
0.885
50
0.80
0.55
0.95
0.810
0.9
125
125
12
mV
mV
V/V
0.12
−2
mV/V
mV/V
580
190
0.35
50
40
190
1.1
650
kHz
kHz
V
ns
ns
ns
ms
Line regulation is measured using the application circuit in Figure 1. Line regulation is specified as the change in the FB voltage resulting from a 1 V change in
the IN voltage.
Load regulation is measured using the application circuit in Figure 1. Load regulation is specified as the change in the FB voltage resulting from a 1 V change in the
COMP voltage. The COMP voltage range is typically 0.9 V to 2.3 V for the minimum to maximum load current condition.
Rev. C | Page 3 of 16
ADP1864
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
IN to GND
CS, PGATE to GND
FB, COMP to GND
θJA 2-Layer (SEMI Standard Board)
θJA 4-Layer (JEDEC Standard Board)
Operating Junction Temperature Range
Storage Temperature Range
Lead Temperature
Rework Temperature (J-STD-020B)
Peak Reflow Temperature,
(20 sec to 40 sec, J-STD-020B)
Rating
−0.3 V to +16 V
−0.3 V to (VIN + 0.3 V)
−0.3 V to +6 V
315°C/W
186°C/W
−40°C to +125°C
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
260°C
260°C
Rev. C | Page 4 of 16
Data Sheet
ADP1864
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
COMP 1
6
PGATE
ADP1864
5
TOP VIEW
(Not to Scale)
FB 3
4
IN
CS
05562-003
GND 2
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
COMP
2
GND
3
FB
4
CS
5
IN
6
PGATE
Description
Regulator Compensation Node. COMP is the output of the internal transconductance error amplifier. Connect a
series RC from COMP to GND to compensate for the control loop. Add an extra high frequency capacitor between
COMP and GND to further reduce switching jitter. The value of this is typically one-tenth of the main compensation
capacitor. Pulling the COMP pin below 0.3 V disables the ADP1864 and turns off the external PFET.
Analog Ground. Directly connect the compensation and feedback networks to GND, preferably with a small analog
GND plane. Connect GND to the power ground (PGND) plane with a narrow track at a single point close to the GND
pin. See the Layout Considerations section for more information.
Feedback Input. Connect a resistive voltage divider from the output voltage to FB to set the output voltage. The
regulation feedback voltage is 0.8 V. Place the feedback resistors as close as possible to the FB pin.
Current Sense Input. CS is the negative input of the current sense amplifier. It provides the current feedback signal
used to terminate the PWM on time. Place a current sense resistor between IN and CS to set the current limit. The
current limit threshold is typically 125 mV.
Power Input. IN is the power supply to the ADP1864 and the positive input of the current sense amplifier. Connect
IN to the positive side of the input voltage source. Bypass IN to PGND with a 10 μF or larger capacitor as close as possible
to the ADP1864. For additional high frequency noise reduction, add a 0.1 μF capacitor to PGND at the IN pin.
Gate Drive Output. PGATE drives the gate of the external P-channel MOSFET. Connect PGATE to the gate of the
external MOSFET.
Rev. C | Page 5 of 16
ADP1864
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.810
0.8
VIN = 5V
0.805
COMP RISING
0.6
COMP (V)
0.5
0.800
0.4
COMP FALLING
0.3
0.795
0.1
–20
0
20
40
60
80
100
0
–40
120
05562-007
0.790
–40
0.2
05562-004
REFERENCE VOLTAGE (V)
0.7
–20
0
20
TEMPERATURE (°C)
40
60
80
100
120
TEMPERATURE (°C)
Figure 3. Reference Voltage vs. Temperature
Figure 6. COMP Shutdown Threshold vs. Temperature
2.52
600
VIN = 5V
2.50
2.48
580
VOUT (V)
570
2.46
2.44
560
05562-005
550
–40
2.42
–20
0
20
40
60
80
100
05562-008
FREQUENCY (kHz)
590
2.40
0
120
0.5
1.0
1.5
2.0
2.5
3.5
3.0
LOAD (A)
TEMPERATURE (°C)
Figure 4. Normalized Oscillator Frequency vs. Temperature
Figure 7. Typical Load Regulation (VIN = 5 V; See Figure 1)
2.520
3.10
3.05
2.515
3.00
UVLO RISING
VOUT (V)
2.90
UVLO FALLING
2.85
2.505
2.80
05562-006
2.75
2.70
–40
2.510
–20
0
20
40
60
80
100
05562-009
VIN (V)
2.95
2.500
3
120
5
7
9
11
13
VIN (V)
TEMPERATURE (°C)
Figure 5. UVLO Voltage vs. Temperature (VIN Rising and VIN Falling)
Figure 8. Typical Line Regulation vs. Input Voltage (See Figure 19)
Rev. C | Page 6 of 16
Data Sheet
ADP1864
650
12
TEMPERATURE = 25°C
630
11
620
610
FREQUENCY (kHz)
10
VIN = 16V
9
8
VIN = 5V
7
590
580
570
560
550
530
VIN = 3.15V
5
–40
–20
0
20
40
60
80
100
520
510
500
3
120
VIN = 16V
VIN = 12V
VIN = 7V
270
250
VIN = 5V
VIN = 4V
230
VIN = 3.1V
05562-011
210
190
–40
–20
0
20
40
60
7
9
11
Figure 11. Oscillator Frequency vs. Input Voltage
Figure 9. Shutdown Supply Current vs. Temperature
290
5
VIN (V)
TEMPERATURE (°C)
310
05562-012
6
VIN = 4V
IQ (µA)
600
540
05562-010
SHUTDOWN SUPPLY CURRENT (µA)
640
80
100
120
TEMPERATURE (°C)
Figure 10. Quiescent Current vs. Temperature
Rev. C | Page 7 of 16
13
ADP1864
Data Sheet
THEORY OF OPERATION
positive input to the error amplifier is driven by a 0.8 V band
gap reference. An increase in the load current causes a small
drop in the feedback voltage, in turn causing an increase in the
COMP voltage and, therefore, the duty cycle. The resulting
increase in the on time of the FET provides the additional
current required by the load.
The ADP1864 is a constant frequency (580 kHz), current-mode
buck controller. PGATE drives the gate of the external P-channel
FET. The duty cycle of the external FET dictates the output
voltage and the current supplied to the load.
The peak inductor current is measured across the external sense
resistor, while the system output voltage is fed back through an
external resistor divider to the FB pin.
LOOP STARTUP
Pulling the COMP pin to GND disables the ADP1864. When
the COMP pin is released from GND, an internal 0.6 μA current
source charges the external compensation capacitor on the
COMP node. Once the COMP voltage has charged to 0.67 V,
the internal control blocks are enabled and COMP is pulled up
to its minimum normal operating voltage (0.9 V). As the voltage at
COMP continues to increase, the on time of the external FET
increases to supply the required inductor current. The loop
stabilizes completely once the COMP voltage is sufficiently high
to support the load current. The regulation voltage at FB is 0.8 V.
At the start of every oscillator cycle, PGATE turns on the
external FET, causing the inductor current, and therefore the
current sense amplifier voltage, to increase. The inductor
current increases until the current amplifier voltage equals
the voltage at the COMP pin. This resets the internal flip-flop,
causing PGATE to go high and turning off the external FET.
The inductor current decreases until the beginning of the next
oscillator period.
The voltage at the COMP node is the output of the internal
error amplifier. The negative input of the error amplifier is the
output voltage scaled by an external resistive divider, and the
VIN = 3.15V TO 14V
IN
5
4
CS
15mV
VREF
0.8V
VREF
RSI
R
Q
S
SLOPE
COMP
UVLO
VIN
ICMP
OSC
UVLO,
SWITCHING
LOGIC AND
BLANKING
CIRCUIT
S
6
G
PGATE
GND
FREQUENCY
FOLDBACK
2
VIN
D
2.5V
2A
OVP
0.35V
VREF
+
80mV
SHORT-CIRCUIT
DETECT
EAMP
0.6µA
VREF
0.8V
FB
3
VIN
0.3V
SHDN
0.3V SHDN
CMP
UV
COMP
UVLO
1
05562-013
0.8V
ADP1864
Figure 12. Functional Block Diagram
Rev. C | Page 8 of 16
Data Sheet
ADP1864
SHORT-CIRCUIT PROTECTION
OVERVOLTAGE LOCKOUT PROTECTION (OVP)
If there is a short across the output load, the voltage at the
feedback pin (FB) drops rapidly. When the FB voltage drops
below 0.35 V, the ADP1864 reduces the oscillator frequency
to 190 kHz. The increase in the oscillator period allows the
inductor additional time to discharge, preventing the output
current from running away. Once the output short is removed
and the feedback voltage increases above the 0.35 V threshold,
the oscillator frequency returns to 580 kHz.
The ADP1864 provides an overvoltage protection feature to
protect the system against output short circuits to a higher
voltage supply. If the feedback voltage increases to 0.885 V,
PGATE is held high, turning the external FET off. The FET
continues to be held high until the voltage at FB decreases to
0.84 V, at which time the ADP1864 resumes normal operation.
UNDERVOLTAGE LOCKOUT (UVLO)
To prevent erratic operation when the input voltage drops
below the minimum acceptable voltage, the ADP1864 has an
undervoltage lockout (UVLO) feature. If the input voltage
drops below 2.90 V, PGATE is pulled high and the ADP1864
continues to draw its typical quiescent current. Current consumption continues to drop toward the shutdown current as input
voltage is reduced. The ADP1864 is re-enabled and begins
switching once the IN voltage is increased above the UVLO
rising threshold (3.0 V).
SOFT START
The ADP1864 includes a soft start feature that limits the rate of
increase in the inductor current once the part is enabled. Soft
start is activated when the input voltage is increased above the
UVLO threshold or COMP is released from GND. Soft start
limits the inrush current at the input and limits the output
voltage overshoot. The soft start control slope is set internally.
Rev. C | Page 9 of 16
ADP1864
Data Sheet
APPLICATIONS INFORMATION
ADIsimPower DESIGN TOOL
RSENSE ( MIN ) =
0.95
To determine the worst-case inductor ripple current, output
voltage ripple, and slope compensation factor, establish the
system maximum and minimum duty cycle. The duty cycle is
calculated by the equation
Duty Cycle (DC ) =
0.85
0.75
0.65
0.55
05562-014
0.45
0.35
0
0.1
0.2
0.3
(1)
VIN + VD
(4)
1.05
DUTY CYCLE
VOUT + VD
SF × PCSV
∆I
I LOAD ( MAX ) + ( PEAK )
2
where SF is the slope factor correction ratio, taken from
Figure 13, at the system maximum duty cycle (minimum
input voltage).
SLOPE FACTOR (SF)
The ADP1864 is supported by ADIsimPower design tool set.
ADIsimPower is a collection of tools that produce complete
power designs optimized for a specific design goal. The tools
enable the user to generate a full schematic, bill of materials,
and calculate performance in minutes. ADIsimPower can
optimize designs for cost, area, efficiency, and parts count
while taking into consideration the operating conditions and
limitations of the IC and all real external components. For
more information about ADIsimPower design tools, refer to
www.analog.com/ADIsimPower. The tool set is available from
this website, and users can also request an unpopulated board
through the tool.
0.4
0.5
0.6
0.7
0.8
0.9
1.0
DUTY CYCLE
Figure 13. Slope Factor (SF) vs. Duty Cycle
where VD is the diode forward drop.
INDUCTOR VALUE
A typical Schottky diode has a forward voltage drop of 0.5 V.
The inductor value choice is important because it dictates the
inductor ripple and, therefore, the voltage ripple at the output.
When operating the part at >40% duty cycle, keep the inductor
value low enough for the slope compensation to remain
effective.
RIPPLE CURRENT
Choose the peak-to-peak inductor ripple current between 20%
and 40% of the maximum load current at the system’s highest
input voltage. A good starting point for a design is to pick the
peak-to-peak ripple current at 30% of the load current.
ΔI(PEAK) = 0.3 × ILOAD(MAX)
(2)
The inductor ripple current is inversely related to the
inductor value.
SENSE RESISTOR
Choose the sense resistor value to provide the desired current
limit. The internal current comparator measures the peak
current (sum of load current and positive inductor ripple
current) and compares it against the current limit threshold.
The current sense resistor value is calculated by the equation
RSENSE ( MIN ) =
PCSV
∆I
I LOAD ( MAX ) + ( PEAK )
2
(3)
where PCSV is the peak current sense voltage, typically 0.125 V.
To ensure the design provides the required output load current
over all system conditions, consider the variation in PCSV over
temperature (see the Specifications section) as well as increases
in ripple current due to inductor tolerance.
If the system is being operated with >40% duty cycle, incorporate the slope compensation factor into the calculation.
∆I ( PEAK ) =
(V
IN
− VOUT )
L× f
V
+ VD
× OUT
V +V
D
IN
(5)
where f is the oscillator frequency.
Smaller inductor values are usually less expensive, but increase
the ripple current and the output voltage ripple. Too large an
inductor value results in added expenses and can impede effective
load transient responses at >40% duty cycle because it reduces
the effect of slope compensation.
Start with the highest input voltage, and assuming the ripple
current is 30% of the maximum load current,
L=
(VIN − VOUT )
V
+ VD
× OUT
0.3 × I LOAD ( MAX ) × f VIN + VD
(6)
From this starting point, modify the inductance to obtain
the right balance of size, cost, and output voltage ripple, while
maintaining the inductor ripple current between 20% and 40%
of the maximum load current.
Rev. C | Page 10 of 16
Data Sheet
ADP1864
MOSFET
INPUT CAPACITOR
Choose the external P-channel MOSFET based on the following:
threshold voltage (VT), maximum voltage and current ratings,
RDS(ON), and gate charge.
The minimum operating voltage of the ADP1864 is 3.15 V.
Choose a MOSFET with a VT that is at least 1 V lower than
the minimum input supply voltage used in the application.
The input capacitor provides a low impedance path for the
pulsed current drawn by the external P-channel FET. Choose
an input capacitor whose impedance at the switching frequency
is lower than the impedance of the voltage source (VIN). The
preferred input capacitor is a 10 μF ceramic capacitor due to
its low ESR and low impedance.
Ensure that the maximum ratings for MOSFET VSG and VSD are
a few volts greater than the maximum input voltage used with
the ADP1864.
For all types of capacitors, make sure the ripple current rating
of the capacitor is greater than half of the maximum output
load current.
Estimate the rms current in the MOSFET under continuous
conduction mode by
Where space is limited, multiple capacitors can be placed in
parallel to meet the rms current requirement. Place the input
capacitor as close as possible to the IN pin of the ADP1864.
VOUT + V D
× I LOAD
V IN + V D
(7)
OUTPUT CAPACITOR
The ESR and capacitance value of the output capacitor
determine the amount of output voltage ripple.
Derate the MOSFET current by at least 20% to account for
inductor ripple and changes in the diode voltage.
1
∆V ≅ ∆I ×
+ ESR
C OUT
8× f ×C
OUT
The MOSFET power dissipation is the sum of the conducted
and switching losses:
PDFET(COND) = (IFET(rms))2 × (1 + T) × RDS(ON)
(8)
where T = 0.005/°C × TJ (FET) − 25°C.
Ensure the maximum power dissipation calculated is significantly
less than the maximum rating of the MOSFET.
where f is the oscillator frequency (typically 580 kHz).
Because the output capacitance is typically >40 μF, the ESR
dominates the voltage ripple. Ensure the output capacitor
ripple rating is greater than the maximum inductor ripple.
DIODE
The diode carries the inductor current during the off time of
the external FET. The average current of the diode is, therefore,
dependent on the duty cycle of the controller as well as the
output load current.
I DIODE ( AV )
V
+ VD
= 1 − OUT
VIN + VD
× I LOAD
(9)
(10)
I rms ≅
(V
+ VD ) × (VIN − VOUT )
1
× OUT
L × f × VIN
2× 3
(11)
POSCAP™ capacitors from Sanyo offer a good size, ESR, ripple,
and current capability trade-off.
FEEDBACK RESISTORS
The feedback resistors ratio sets the output voltage of the system.
where VD is the diode forward drop.
ADP1864
A typical Schottky diode has a forward drop voltage of 0.5 V.
R2
3
A Schottky diode is recommended for best efficiency because it
has a low forward drop and faster switching speed than junction
diodes. If a junction diode is used it must be an ultrafast recovery
diode. The low forward drop reduces power losses during the
FET off time, and fast switching speed reduces the switching
losses during PFET transitions.
FB
R1
VOUT
05562-015
I FET (rms ) =
Figure 14. Two Feedback Resistors Used to Set Output Voltage
0.8 V = VOUT ×
R1 = R2 ×
(VOUT
R2
R1 + R 2
− 0.8)
0.8
(12)
(13)
Choose 80.6 kΩ for R2. Using higher values for R2 results in
reduced output voltage accuracy, and lower values cause an
increased voltage divider current, thus increasing quiescent
current consumption.
Rev. C | Page 11 of 16
ADP1864
Data Sheet
LAYOUT CONSIDERATIONS
R2
1
All noisy nodes (P-channel drain, power diode cathode, and
inductor terminal) are located along the bottom portion of the
evaluation board on the top layer (see Figure 16). A substantial
amount of copper has been allocated for this area with ample
track spacing to minimize coupling (crosstalk) effects during
switching.
The FB tap is isolated and runs from the RTOP, along the upper
right portion of the board on the bottom layer (see Figure 17)
to minimize EMI pickups emitted from the power components
along the bottom portion of the evaluation board’s top layer (see
Figure 16). Sufficient track spacing is placed from the main
power ground plane located near the center of the board to
effectively decouple this track.
There are two ground planes on the top layer: the analog
ground plane is on the left and the power ground plane on
the right. An analog ground pickup point projects down to
the bottom layer and through a single narrow and isolated
track (see Figure 17).
IN 5
VIN
CE1
RS
RTOP
3 FB
CS 4
RBOTTOM
U1
D1
L1
PGND
CE2
VOUT
05562-016
GND
Figure 15. Application Circuit Showing High Current Paths (in Bold)
ISOLATED POWER GROUND PLANE. USE A SUBSTANTIAL
AMOUNT OF COPPER TO BEST ACCOMMODATE
THIS HIGH CURRENT PATH. ALSO PROVIDES AID
FOR POWER DISSIPATION.
CE1
CE2
C1 RS
R2
VOUT
C2
D1
L1
RBOTTOM
RTOP
U1
FB TAP
ANALOG
GROUND TAP
NOISY POWER PLANE IS LOCATED ON THIS
SIDE OF THE BOARD TO ACCOMODATE SPIKY
NODES AND MINIMIZE EMI EFFECTS TO THE
REST OF THE SYSTEM.
05562-020
All analog components are grouped together on the left side
of the evaluation board (left side of the ADP1864 DUT, see
Figure 16), including compensation and FB components. All
power components are located on the right side of the board
(MOSFET, inductor, input bypass capacitors, output capacitors,
and power diode).
PGATE 6
ADP1864
2
Keep the PGND connections for the diode, input capacitor(s),
and output capacitor(s) as close together as possible on a wide
PGND plane. Connect the PGND and GND planes at a single
point with a narrow trace close to the ADP1864 GND connection.
Ensure the feedback resistors are placed as close as possible
to the FB pin to prevent stray pickup. To prevent extra noise
pickup on the FB line, do not allow the feedback trace from
the output voltage to FB to pass right beside the drain of the
external PFET. Add an extra copper plane at the connection of
the FET drain and the cathode of the diode to help dissipate the
heat generated by losses in those components.
COMP
C1
C2
Figure 16. Top Layer of an Example Layout for an ADP1864 Application
1
2
3
1 FB TAP FROM OUTPUT TO R
TOP. TRACE SHOULD BE AWAY FROM
POWER COMPONENTS TO MINIMIZE EMI PICKUP.
TRACE FOR GATE CONNECTION OF THE PFET. ROUTING OF
THIS CONNECTION AWAY FROM THE CATHODE OF D1 AND DRAIN OF
PFET IS TO ENSURE THAT NOISE DOES NOT COUPLE INTO THIS TRACK.
2 ISOLATED
3 ISOLATED
TRACK FOR CONNECTING AGND TO PGND. THIS HELPS
MINIMIZE STRAY PARASITIC EFFECTS TOWARDS THE ANALOG
COMPONENTS (FB AND COMPENSATION COMPONENTS).
05562-021
Layout is important with all switching regulators, but is particularly important for high switching frequencies. Ensure all high
current paths are as wide as possible to minimize track inductance, which causes spiking and electromagnetic interference
(EMI). These paths are shown in bold in Figure 15. Place the
current sense resistor and the input capacitor(s) as close to the
IN pin as possible.
Figure 17. Bottom Layer of an Example Layout of an ADP1864 Application
The P-channel gate should have an isolated trace (bottom layer)
tying back to Pin 6 of the DUT by via connections.
Rev. C | Page 12 of 16
Data Sheet
ADP1864
EXAMPLE APPLICATIONS CIRCUITS
25kΩ
1
470pF
COMP
PGATE 6
ADP1864
68pF
2
GND
VIN = 4.5V TO 5.5V
0.03Ω
10µF
IN 5
3.3µH
80.6kΩ
3 FB
CS 4
3.3V, 2.0A
47µF
255kΩ
05562-018
RSENSE LRC-LR1206-01-R030-F
MOSFET FAIRCHILD SEMI FDC638P
INDUCTOR TOKO FDV0630-3R3M
DIODE SYNSEMI SK22
CIN LMK325BJ106KN
COUT SANYO POSCAP 6TPB47M
Figure 18. Application Circuit for VOUT = 3.3 V, 2 A Load
1
470pF
COMP
68pF
80.6kΩ
PGATE 6
2
GND
3
FB
VIN = 3.15V TO 14V
0.03Ω
ADP1864
10µF
IN 5
5µH
CS 4
2.5V, 2.0A
47µF
174kΩ
RSENSE LRC-LR1206-01-R030-F
MOSFET FAIRCHILD SEMI FDC658P
INDUCTOR SUMIDA CDRH6D38-5R0
DIODE VISHAY SSB43L
CIN LMK325BJ106KN
COUT SANYO POSCAP 6TPB47M
Figure 19. Application Circuit for VOUT = 2.5 V, 2 A Load
Rev. C | Page 13 of 16
05562-019
25kΩ
ADP1864
Data Sheet
OUTLINE DIMENSIONS
2.90 BSC
6
5
4
2.80 BSC
1.60 BSC
1
2
PIN 1
INDICATOR
3
0.95 BSC
1.90
BSC
*1.00 MAX
SEATING
PLANE
0.10 MAX
0.50
0.30
0.20
0.08
8°
4°
0°
0.60
0.45
0.30
*COMPLIANT TO JEDEC STANDARDS MO-193-AA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
102808-A
*0.90
0.87
0.84
Figure 20. 6-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADP1864AUJZ-R7
ADP1864-EVAL
ADP1864-EVALZ
1
2
Temperature Range
−40°C to +125°C
Package Description
6-Lead Thin Small Outline Transistor Package [TSOT]
Evaluation Board
Evaluation Board
Z = RoHS Compliant Part.
VOUT = 2.5 V (variable), ILOAD = 0 A to 3 A, VIN = 3.15 V to 14 V.
Rev. C | Page 14 of 16
Package Option
UJ-6
Branding
P0N
Data Sheet
ADP1864
NOTES
Rev. C | Page 15 of 16
ADP1864
Data Sheet
NOTES
©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05562-0-8/12(C)
Rev. C | Page 16 of 16
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