ADP5080CB-1-EVALZ

FEATURES FUNCTIONAL BLOCK DIAGRAM Wide input voltage range: 4.0 V to 15 V High efficiency architecture Up to 2 MHz switching frequency 6 synchronous rectification dc-to-dc converters Channel 1 buck regulator: 3 A maximum Channel 2 buck regulator: 1.15 A maximum Channel 3 buck regulator: 1.5 A maximum Channel 4 buck regulator: 0.8 A maximum Channel 5 buck regulator: 2 A maximum Channel 6 configurable buck or buck boost regulator 2 A maximum for buck regulator configuration 1.5 A maximum for buck boost regulator configuration Channel 7 high voltage, high performance LDO regulator: 30 mA maximum 2 low quiescent current keep-alive LDO regulators LDO1 regulator: 400 mA maximum LDO2 regulator: 300 mA maximum Control circuit Charge pump for internal switching driver power supply I2C-programmable output levels and power sequencing Package: 72-ball, 4.5 mm × 4.0 mm × 0.6 mm WLCSP (0.5 mm pitch) SCL SDA ENABLE I2C INTERFACE CONTROL LOGIC OSCILLATOR VOLTAGE REFERENCE FAULT CHARGE PUMP 4V TO 15V LDO1 4V TO 15V CH1 BUCK REGULATOR 5.0V TO 5.5V, 400mA LDO2 4V TO 15V CH 3 BUCK REGULATOR CH 5 BUCK REGULATOR 5V TO 25V 1.8V TO 3.55V/ADJ, 0.8A 3.0V TO 5.0V, 2A CH 6 BUCK BOOST REGULATOR 4V TO 15V 1.0V TO 3.3V, 1.15A 1.2V TO 1.8V/ADJ, 1.5A CH 4 BUCK REGULATOR 4V TO 15V 4V TO 15V 0.80V TO 1.20V, 3A CH2 BUCK REGULATOR 4V TO 15V 3V TO 3.3V, 300mA CH7 LDO REGULATOR 3.5V TO 5.5V/ADJ BUCK ONLY: 2A BUCK BOOST: 1.5A 5V TO 12V, 30mA 11639-001 Data Sheet High Efficiency Integrated Power Solution for Multicell Lithium Ion Applications ADP5080 Figure 1. APPLICATIONS DSLR cameras Non-reflex (mirrorless) cameras Portable instrumentation GENERAL DESCRIPTION The ADP5080 is a fully integrated, high efficiency power solution for multicell lithium ion battery applications. The device can connect directly to the battery, which eliminates the need for preregulators and, therefore, increases the battery life of the system. The ADP5080 integrates two keep-alive LDO regulators, five synchronous buck regulators, a configurable four-switch buck boost regulator, and a high voltage LDO regulator. The ADP5080 is a highly integrated power solution that incorporates all power MOSFETs, feedback loop compensation, voltage setting resistor dividers, and discharge switches, as well as a charge pump to generate a global bootstrap voltage. Rev. A All these features help to minimize the number of external components and PCB space required, providing significant advantages for portable applications. The switching frequency is selectable on each channel from 750 kHz to 2 MHz. Key functions for power applications, such as soft start, selectable preset output voltage, and flexible power-up and power-down sequences, are provided on chip and are programmable via the I2C interface with fused factory defaults. The ADP5080 is available in a 72-ball WLCSP 0.5 mm pitch package. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADP5080 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Channel 7: High Voltage LDO Regulator ............................... 29 Applications ....................................................................................... 1 Charge Pump .............................................................................. 29 Functional Block Diagram .............................................................. 1 Enabling and Disabling the Output Channels........................ 30 General Description ......................................................................... 1 Power-Good Function ............................................................... 31 Revision History ............................................................................... 2 Fault Function ............................................................................. 31 Specifications..................................................................................... 3 Undervoltage Protection (UVP) .............................................. 32 Housekeeping Block Specifications ........................................... 4 Overvoltage Protection (OVP) ................................................. 33 DC-to-DC Converter Block Specifications .............................. 5 Applications Information .............................................................. 34 Linear Regulator Block Specifications ....................................... 7 I C Interface Timing Specifications ........................................... 8 Component Selection for the Buck and Buck Boost Regulators .................................................................................... 34 Absolute Maximum Ratings............................................................ 9 Component Selection for the LDO Regulators ...................... 36 Thermal Resistance ...................................................................... 9 PCB Layout Recommendations ............................................... 36 2 ESD Caution .................................................................................. 9 Thermal Considerations............................................................ 37 Pin Configuration and Function Descriptions ........................... 10 I C Interface .................................................................................... 38 Typical Performance Characteristics ........................................... 12 SDA and SCL Pins ...................................................................... 38 Application Circuit ......................................................................... 18 I2C Address .................................................................................. 38 Theory of Operation ...................................................................... 19 Self-Clearing Register Bits......................................................... 38 UVLO and POR .......................................................................... 19 I2C Interface Timing Diagrams ................................................ 38 Discharge Switch ........................................................................ 19 Control Register Information ....................................................... 40 Keep-Alive LDO Regulators ..................................................... 19 Control Register Map ................................................................ 40 DC-to-DC Converter Channels ............................................... 22 Control Register Details ............................................................ 41 Light Load and Other Modes of Operation for the DC-to-DC Converter Channels .................................. 27 Factory Default Options ................................................................ 61 Switching Clock .......................................................................... 28 Ordering Guide .......................................................................... 63 2 Outline Dimensions ....................................................................... 63 Soft Start Function ..................................................................... 29 REVISION HISTORY 4/14—Revision A: Initial Version Rev. A | Page 2 of 64 Data Sheet ADP5080 SPECIFICATIONS TJ = 25°C, VVBATT = 7.2 V, VVREG1 = VVDRx = 5 V, VVREG2 = VVDDIO = 3.3 V, unless otherwise noted. Table 1. Parameter INPUT SUPPLY VOLTAGE RANGE VBATT Symbol Min VVBATT VILDO7 VDDIO QUIESCENT CURRENT Operating Quiescent Current VDDIO Standby Current VVILDO7 VVDDIO UNDERVOLTAGE LOCKOUT UVLO Rising Threshold UVLO Falling Threshold VBATT UVLO Threshold Reset Threshold OSCILLATOR CIRCUIT Switching Frequency UVLO VUVLO (R) VUVLO (F) VUVLO (BATT) VUVLO (POR) SYNC Pin, Input Clock Frequency Range Minimum On Pulse Width Minimum Off Pulse Width High Logic Low Logic LOGIC INPUTS EN Pin High Level Threshold Low Level Threshold EN34 Pin High Level Threshold Low Level Threshold SCL and SDA Pins High Level Threshold Low Level Threshold LOGIC OUTPUTS SDA Pin Low Level Output Voltage Typ Max Unit Test Conditions/Comments 4.0 15 V Applies to PVIN1, PVIN2, PVIN3, PVIN4, PVIN5, and PVIN6 5 1.6 25 3.6 V V 8 0.2 12 1.25 11 mA µA µA mA All channels on, nonswitching VVDDIO = VSCL = VSDA = 3.3 V Includes LDO1 and LDO2, EN low All channels off, EN high, SEL_FSW = 1, FREQ_CP = 01 3.45 3.7 3.45 3.3 2.4 3.85 3.55 V V V V At PVIN1 At PVIN1 At VBATT, falling At VREG2, falling fSW 1.98 1.48 2.0 1.5 2.02 1.52 MHz MHz ROSC = 100 kΩ, SEL_FSW = 0 ROSC = 100 kΩ, SEL_FSW = 1 fSYNC tSYNC_MIN_ON tSYNC_MIN_OFF VH (SYNC) VL (SYNC) 0.5 100 100 2.0 MHz ns ns V V ROSC = 100 kΩ VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C 2.15 V V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C 1.25 V V VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C VVREG2 = 3.3 V, −25°C ≤ TJ ≤ +85°C 0.75 × VVDDIO V V VVDDIO = 3.3 V, −25°C ≤ TJ ≤ +85°C VVDDIO = 3.3 V, −25°C ≤ TJ ≤ +85°C 0.4 V 3.0 mA sink current, −25°C ≤ TJ ≤ +85°C VSDA = 3.3 V IQ (VIN) IQ (VDDIO_OP) IQ (VBATT_STNBY1) IQ (VBATT_STNBY2) 20 0.8 × VVREG2 0.3 × VVREG2 VIH (EN) VIL (EN) 1.45 VIH (EN34) VIL (EN34) 0.70 VIH (I2C) VIL (I2C) 0.3 × VVDDIO VOL (SDA) Leakage Current CLKO Pin High Level Output Voltage ILEAK (SDA) Low Level Output Voltage VOL (CLKO) 0.4 V FAULT Pin Low Level Output Voltage VOL (FAULT) 0.4 V Leakage Current VOH (CLKO) ILEAK (FAULT) 10 nA VVREG2 − 0.4 V 10 Rev. A | Page 3 of 64 nA 3.0 mA sink current, −25°C ≤ TJ ≤ +85°C 3.0 mA sink current, −25°C ≤ TJ ≤ +85°C 3.0 mA source current, −25°C ≤ TJ ≤ +85°C VFAULT = 3.3 V ADP5080 Parameter POWER GOOD Rising Threshold Falling Threshold OVERVOLTAGE/UNDERVOLTAGE OVP Threshold UVP Threshold THERMAL SHUTDOWN Rising Threshold Hysteresis Data Sheet Symbol Min VPGOOD (R) VPGOOD (F) VOVP VUVP TSD TTSD TTSD_HYS Typ Max 83 79 48 125 65 137 165 15 Unit Test Conditions/Comments % % Measured at VOUT Measured at VOUT % % Measured at VOUT Measured at VOUT °C °C HOUSEKEEPING BLOCK SPECIFICATIONS TJ = 25°C, VVBATT = 7.2 V, VVREG1 = VVDRx = 5 V, VVREG2 = VVDDIO = 3.3 V, unless otherwise noted. Table 2. Parameter LDO1 Output Voltage (VREG1 Pin) Fixed Voltage Range, 1 Bit Voltage Accuracy Load Regulation Line Regulation Current-Limit Threshold Dropout Voltage Input Select Switch On Resistance COUT Discharge Switch On Resistance LDO2 Output Voltage (VREG2 Pin) Fixed Voltage Range, 2 Bits Voltage Accuracy Load Regulation Current-Limit Threshold Input Select Switch On Resistance COUT Discharge Switch On Resistance CHARGE PUMP C+ Switch On Resistance Low-Side High-Side C− Switch On Resistance High-Side Low-Side Shunt Switch On Resistance Charge Pump Start-Up Threshold Symbol Min VVREG1 VVREG1 (DEFAULT) ∆VVREG1/IVREG1 ∆VVREG1/VVBATT ILDO1_ILIM 5.0 −2 Max Unit Test Conditions/Comments 5.5 +2 RDSON_VISW1 3.5 0.03 550 0.15 795 V % %/A %/V mA V mΩ VVBATT = VVREG1 + 0.5 V, IVREG1 = 10 mA VVBATT = VVREG1 + 0.5 V, IVREG1 = 10 mA IVREG1 = 4 mA to 95 mA VVBATT = (VVREG1 + 0.5 V) to 15 V VVREG1 = 90% of nominal IVREG1 = 100 mA, VVREG1 = 5 V VVISW1 = 5 V RDIS_LDO1 1 kΩ VVREG1 = 1 V 5.5 400 1409 V % %/A mA mΩ IVREG2 = 10 mA IVREG2 = 10 mA IVREG2 = 4 mA to 95 mA VVREG2 = 90% of nominal VVISW2 = 3.3 V RDIS_LDO2 12 Ω VVREG2 = 1 V RDSON_C+SW1 RDSON_C+SW2 1.1 1.0 Ω Ω Source, PVINCP to C+ Sink, C+ to BSTCP RDSON_C−SW1 RDSON_C−SW2 RDSON_CP CPSTART 1.0 785 3.3 4.0 Ω mΩ Ω V Source, VDR5 to C− Sink, C− to PGND5 BSTCP to PVINCP, EN low At VBATT VVREG2 VVREG2 (DEFAULT) ∆VVREG2/IVREG2 ILDO2_ILIM RDSON_VISW2 390 Typ 3.0 −2 290 3.3 +2 Rev. A | Page 4 of 64 Data Sheet ADP5080 DC-TO-DC CONVERTER BLOCK SPECIFICATIONS TJ = 25°C, VVBATT = 7.2 V, VVREG1 = VVDRx = 5 V, VVREG2 = VVDDIO = 3.3 V, unless otherwise noted. Table 3. Parameter CHANNEL 1 SYNC BUCK REGULATOR Channel 1 Output Voltage (FB1 Pin) Fixed Voltage Range, 5 Bits Symbol Min VFB1 0.89 0.80 −0.8 Typ Max Unit Test Conditions/Comments 1.20 1.11 +0.8 V V % REDUCE_VOUT1 = 0 REDUCE_VOUT1 = 1 +1.3 Feedback Voltage Accuracy at Default VID Code VFB1 (DEFAULT) Load Regulation ∆VFB1/ILOAD1 0.15 % %/A ∆VFB1/VPVIN1 0.004 %/V −25°C ≤ TJ ≤ +85°C ILOAD1 = 20 mA to 2 A, AUTO-PSM1 = 0 VPVIN1 = 5 V to 15 V, ILOAD = 1 A RDSON_1AH RDSON_1AL 250 130 mΩ mΩ ID = 100 mA ID = 100 mA RDSON_1BH RDSON_1BL 175 95 mΩ mΩ ID = 100 mA, GATE_SCAL1 = 0 ID = 100 mA 4.0 115 0 4 125 A ns % ms Ω Valley current, −25°C ≤ TJ ≤ +85°C −1.3 Line Regulation SW1A Pin High-Side Power FET On Resistance Low-Side Power FET On Resistance SW1B Pin High-Side Power FET On Resistance Low-Side Power FET On Resistance SW1A and SW1B Pins Switch Current Limit Minimum Off Time Minimum Duty Cycle Soft Start Time COUT Discharge Switch On Resistance CHANNEL 2 SYNC BUCK REGULATOR Channel 2 Output Voltage (FB2 Pin) Fixed Voltage Range, 4 Bits Feedback Voltage Accuracy at Default VID Code ICL1 tOFF1 (MIN) DMIN1 tSS1 RDIS1 3.1 VFB2 VFB2 (DEFAULT) 1.0 −0.8 −1.3 Load Regulation Line Regulation SW2 Pins High-Side Power FET On Resistance Low-Side Power FET On Resistance Switch Current Limit Minimum Off Time Minimum Duty Cycle Soft Start Time COUT Discharge Switch On Resistance CHANNEL 3 SYNC BUCK REGULATOR Channel 3 Output Voltage (FB3 Pin) Fixed Voltage Range, 3 Bits Minimum Adjustable Voltage Feedback Voltage Accuracy at Default VID Code 3.3 +0.8 V % +1.3 ∆VFB2/ILOAD2 0.25 % %/A ∆VFB2/VPVIN2 0.004 %/V RDSON_2H RDSON_2L ICL2 tOFF2 (MIN) DMIN2 tSS2 RDIS2 235 165 1.8 100 0 4 125 mΩ mΩ A ns % ms Ω VFB3 1.2 1.2 1.8 0.8 VFB3 (DEFAULT) −0.8 +0.8 −1.3 +1.3 V V % Load Regulation ∆VFB3/ILOAD3 0.17 % %/A Line Regulation ∆VFB3/VPVIN3 0.003 %/V Rev. A | Page 5 of 64 SS1 = 10 VFB1 = 1 V −25°C ≤ TJ ≤ +85°C ILOAD2 = 10 mA to 1.0 A, AUTO-PSM2 = 0 VPVIN2 = 5 V to 15 V, ILOAD2 = 500 mA ID = 100 mA ID = 100 mA Valley current, −25°C ≤ TJ ≤ +85°C SS2 = 10 VFB2 = 1 V VID3 = 111 −25°C ≤ TJ ≤ +85°C ILOAD3 = 15 mA to 1.5 A, AUTO-PSM3 = 0 VPVIN3 = 5 V to 15 V, ILOAD3 = 700 mA ADP5080 Parameter SW3 Pins High-Side Power FET On Resistance Low-Side Power FET On Resistance Switch Current Limit Minimum Off Time Minimum Duty Cycle Soft Start Time COUT Discharge Switch On Resistance CHANNEL 4 SYNC BUCK REGULATOR Channel 4 Output Voltage (FB4 Pin) Fixed Voltage Range, 3 Bits Minimum Adjustable Voltage Feedback Voltage Accuracy at Default VID Code Data Sheet Symbol RDSON_3H RDSON_3L ICL3 tOFF3 (MIN) DMIN3 tSS3 RDIS3 VFB4 Min 2.05 Typ 155 100 2.8 90 0 4 125 1.8 3.55 0.8 VFB4 (DEFAULT) −1 +1 −2 Load Regulation Line Regulation SW4 Pin High-Side Power FET On Resistance Low-Side Power FET On Resistance Switch Current Limit Minimum On Time Maximum Duty Cycle Soft Start Time COUT Discharge Switch On Resistance CHANNEL 5 SYNC BUCK REGULATOR Channel 5 Output Voltage (FB5 Pin) Fixed Voltage Range, 3 Bits Feedback Voltage Accuracy at Default VID Code Line Regulation SW5 Pins High-Side Power FET On Resistance Low-Side Power FET On Resistance Switch Current Limit Minimum On Time Maximum Duty Cycle Soft Start Time COUT Discharge Switch On Resistance CHANNEL 6 BUCK BOOST REGULATOR Channel 6 Output Voltage (FB6 Pin) Fixed Voltage Range, 4 Bits Minimum Adjustable Voltage Accuracy at Default VID Code Test Conditions/Comments mΩ mΩ A ns % ms Ω ID = 100 mA ID = 100 mA Valley current, −25°C ≤ TJ ≤ +85°C V V % 0.10 % %/A ∆VFB4/VPVIN4 0.003 %/V RDSON_4H RDSON_4L ICL4 tON4 (MIN) DMAX4 tSS4 RDIS4 350 345 1.4 75 100 4 125 mΩ mΩ A ns % ms Ω VFB5 VFB5 (DEFAULT) +2 Unit ∆VFB4/ILOAD4 0.96 3.0 −1 −2 Load Regulation Max 5.0 +1 V % +2 ∆VFB5/ILOAD5 0.05 % %/A ∆VFB5/VPVIN5 0.001 %/V RDSON_5H RDSON_5L ICL5 tON5 (MIN) DMAX5 tSS5 RDIS5 200 120 3 75 100 4 125 mΩ mΩ A ns % ms Ω VFB6 2.4 3.5 5.5 Load Regulation ∆VVOUT6/ILOAD6 0.05 V V % % %/A Line Regulation ∆VVOUT6/ VPVIN6 0.001 %/V 0.8 VVOUT6 (DEFAULT) −1 −2 +1 +2 Rev. A | Page 6 of 64 SS3 = 10 VFB3 = 1 V VID4 = 111 −25°C ≤ TJ ≤ +85°C ILOAD4 = 10 mA to 800 mA, AUTO-PSM4 = 0 VPVIN4 = 5 V to 15 V, ILOAD4 = 400 mA ID = 100 mA ID = 100 mA Peak current, −25°C ≤ TJ ≤ +85°C SS4 = 10 VFB4 = 1 V −25°C ≤ TJ ≤ +85°C ILOAD5 = 20 mA to 2 A, AUTO-PSM5 = 0 VPVIN5 = 5 V to 15 V, ILOAD5 = 1 A ID = 100 mA ID = 100 mA Peak current, −25°C ≤ TJ ≤ +85°C SS5 = 10 VFB5 = 1 V VID6 = 1111 −25°C ≤ TJ ≤ +85°C Buck boost configuration, ILOAD6 = 15 mA to 1.5 A, AUTO-PSM6 = 0 VPVIN6 = 5 V to 15 V, ILOAD6 = 700 mA Data Sheet ADP5080 Parameter SW6A Pins Low-Side Power FET On Resistance High-Side Power FET On Resistance High-Side Switch Current Limit Minimum On Time SW6B Pins Low-Side Power FET On Resistance High-Side Power FET On Resistance Boost Minimum Duty Cycle Soft Start Time COUT Discharge Switch On Resistance Symbol Min RDSON_6AL RDSON_6AH ICL6A tON6 (MIN) Typ 3.2 RDSON_6BL RDSON_6BH DMIN6B tSS6 RDIS6 Max Unit Test Conditions/Comments 95 60 4.4 80 mΩ mΩ A ns ID = 100 mA, VVDR6 = 5 V ID = 100 mA, VVDR6 = 5 V Peak current, −25°C ≤ TJ ≤ +85°C SW6A high-side on time 50 55 0 4 110 mΩ mΩ % ms Ω ID = 100 mA ID = 100 mA SW6B low-side duty cycle SS6 = 10 VVOUT6 = 1 V LINEAR REGULATOR BLOCK SPECIFICATIONS TJ = 25°C, VVBATT = 7.2 V, VVREG1 = VVDRx = 5 V, VVREG2 = VVDDIO = 3.3 V, unless otherwise noted. Table 4. Parameter CHANNEL 7 LDO REGULATOR Channel 7 Output Voltage Voltage Accuracy 1 Symbol Min VVOLDO7 VVOLDO7 (DEFAULT) 5 −1.5 −2.5 Typ Max Unit Test Conditions/Comments 12 +1.5 +2.5 V % % VVILDO7 = VVOLDO7 + 0.5 V VVILDO7 = VVOLDO7 + 0.5 V, ILOAD7 = 1 mA VVILDO7 = VVOLDO7 + 0.5 V, ILOAD7 = 1 mA, −25°C ≤ TJ ≤ +85°C VVILDO7 = VVOLDO7 + 0.5 V, ILOAD7 = 1 mA to 20 mA VVILDO7 = (VVOLDO7 + 0.5 V) to 25 V, ILOAD7 = 1 mA VVOLDO7 programmed to 12 V, IVOLDO7 = 10 mA VVOLDO7 = 95% of nominal SS7 = 1 VVOLDO7 = 1 V Load Regulation ∆VVOLDO7/ILOAD7 0.005 %/mA Line Regulation ∆VVOLDO7/VVILDO7 0.007 %/V Dropout Voltage1 VDROP 75 mV Current Limit Soft Start Time COUT Discharge Switch On Resistance ICL7 tSS7 RDIS7 50 4 1 mA ms kΩ 30 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. Rev. A | Page 7 of 64 ADP5080 Data Sheet I2C INTERFACE TIMING SPECIFICATIONS TJ = 25°C, VVBATT = 7.2 V, VVDRx = 5 V, VVREG2 = VVDDIO = 3.3 V, unless otherwise noted. Table 5. Parameter fSCL tHIGH tLOW tSU,DAT tHD,DAT tSU,STA tHD,STA tBUF tSU,STO tR tF tSP CB 2 Min Typ Max 400 0.6 1.3 100 0 0.6 0.6 1.3 0.6 20 + 0.1 × CB2 20 + 0.1 × CB2 0 Unit kHz µs µs ns µs µs µs µs µs ns ns ns pF 0.9 300 300 50 400 Description SCL clock frequency SCL high time SCL low time Data setup time Data hold time 1 Setup time for repeated start Hold time for start or repeated start Bus free time between a stop condition and a start condition Setup time for a stop condition Rise time of SCL and SDA Fall time of SCL and SDA Pulse width of suppressed spike Capacitive load for each bus line A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH minimum of the SCL signal) to bridge the undefined region of the SCL falling edge. 2 CB is the total capacitance of one bus line in picofarads (pF). 1 Timing Diagram SDA tLOW tF tR tF tHD,STA tSU,DAT tSP tBUF tR SCL tHD,DAT tHIGH tSU,STA Sr tSU,STO P S 11639-002 S S = START CONDITION Sr = REPEATED START CONDITION P = STOP CONDITION Figure 2. I2C Interface Timing Diagram Rev. A | Page 8 of 64 Data Sheet ADP5080 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter VBATT to GND VDDIO to GND VISW1 to GND VISW2 to GND VREG1 to GND VREG2 to GND EN to GND EN34 to GND FAULT to GND BSTCP to PVINCP BSTCP to GND C+ to PVINCP C− to PGND5 PVINx to PGNDx VDRx to PGNDx BST16, BST23, BST45 to PVINx FB1, FB2, FB3 to GND FB4, FB5, FB6 to GND VOUT6 to PGND6 SW1A, SW1B to PGND1 SW2 to PGND2 SW3 to PGND3 SW4 to PGND4 SW5 to PGND5 SW6A to PGND6 SW6B to PGND6 PGNDx to GND VILDO7 to GND VOLDO7 to GND FREQ to GND SYNC to GND CLKO to GND SCL to GND SDA to GND Storage Temperature Range Operating Ambient Temperature Range Operating Junction Temperature Range Rating −0.3 V to +18 V −0.3 V to +4.0 V −0.3 V to +6.5 V −0.3 V to +4.0 V −0.3 V to +6.5 V −0.3 V to +4.0 V −0.3 V to +18 V −0.3 V to +6.5 V −0.3 V to +4.0 V −0.3 V to +6.5 V −0.3 V to +23 V −0.3 V to (VVDR5 + 0.3 V) −0.3 V to (VVDR5 + 0.3 V) −0.3 V to +18 V −0.3 V to +6.5 V −0.3 V to +6.5 V −0.3 V to +4.0 V −0.3 V to +6.5 V −0.3 V to +6.5 V −2.0 V to +18 V −2.0 V to +18 V −2.0 V to +18 V −2.0 V to +18 V −2.0 V to +18 V −2.0 V to +18 V −0.5 V to (VVOUT6 + 2.0 V) or +6.5 V, whichever is lower −0.3 V to +0.3 V −0.3 V to +28 V −0.3 V to +18 V −0.3 V to (VVREG2 + 0.3 V) −0.3 V to +4.0 V −0.3 V to (VVREG2 + 0.3 V) −0.3 V to +4.0 V −0.3 V to +4.0 V −65°C to +150°C −25°C to +85°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for worst-case conditions; that is, a device soldered in a circuit board for surface-mount packages. Note that actual θJA depends on the application environment. Table 7. Thermal Resistance PCB Type1 1S0P 2S2P 1 2 θJA2 60.6 26.9 θJB2 7.3 4.5 Unit °C/W °C/W PCB type conforms to JEDEC JESD51-9 standard. 1.25 W power dissipation with zero airflow. ESD CAUTION −25°C to +125°C Rev. A | Page 9 of 64 ADP5080 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS BALL A1 CORNER 1 2 3 4 5 6 7 8 9 VOUT6 VOUT6 VISW1 VISW2 PVINCP C+ PGND5 SW5 PVIN5 SW6B SW6B VREG1 VREG2 VOLDO7 C– PGND5 SW5 PVIN5 PGND6 PGND6 VBATT EN34 VILDO7 BSTCP VDR5 BST45 PVIN4 SW6A SW6A VDR6 FB6 GND SYNC FB5 FB4 SW4 PVIN6 PVIN6 BST16 SDA SCL GND CLKO VDR34 PGND4 PVIN1 PVIN1 FB1 EN VDDIO FREQ FB3 PGND3 PGND3 SW1A SW1B VDR12 FB2 GND FAULT GND SW3 SW3 PGND1 PGND1 PGND2 SW2 SW2 PVIN2 BST23 PVIN3 PVIN3 A B C D E F G TOP VIEW (BALL SIDE DOWN) Not to Scale 11639-003 H Figure 3. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1A 2A 3A Mnemonic VOUT6 VOUT6 VISW1 4A VISW2 5A 6A 7A 8A 9A 1B 2B 3B 4B 5B 6B 7B 8B 9B 1C 2C 3C 4C 5C 6C 7C 8C PVINCP C+ PGND5 SW5 PVIN5 SW6B SW6B VREG1 VREG2 VOLDO7 C− PGND5 SW5 PVIN5 PGND6 PGND6 VBATT EN34 VILDO7 BSTCP VDR5 BST45 Description Output Voltage for Channel 6. Output Voltage for Channel 6. Input for an External Regulator Output. A 5.0 V to 5.5 V regulator connected to the VISW1 pin can take over from LDO1 to supply the internal circuit of the ADP5080 and the VREG1 load. If this pin is not used, connect it to GND. Input for an External Regulator Output. A 3.0 V to 3.3 V regulator connected to the VISW2 pin can take over from LDO2 to supply the internal circuit of the ADP5080 and the VREG2 load. If this pin is not used, connect it to GND. Input Power Supply for the Charge Pump. Flying Capacitor Terminal for the Charge Pump. Power Ground for Channel 5. Switching Node for Channel 5. Input Power Supply for Channel 5. Secondary Side Boost Switching Node for Channel 6. Secondary Side Boost Switching Node for Channel 6. Output Voltage for LDO1. Output Voltage for LDO2. Output Voltage for Channel 7. Leave this pin open if not used. Flying Capacitor Terminal for the Charge Pump. Power Ground for Channel 5. Switching Node for Channel 5. Input Power Supply for Channel 5. Power Ground for Channel 6. Power Ground for Channel 6. Power Supply Input for the Internal Circuits. Connect this pin to the battery. Independent Enable Input for Channel 3 and Channel 4. If this pin is not used, connect it to GND. Input Power Supply for Channel 7. If this pin is not used, connect it to VBATT. Output Voltage for Charge Pump. Low-Side FET Driver Power Supply for Channel 5. Connect this pin to VREG1. High-Side FET Driver Power Supply for Channel 4 and Channel 5. Rev. A | Page 10 of 64 Data Sheet Pin No. 9C 1D 2D 3D 4D 5D 6D 7D 8D 9D 1E 2E 3E 4E 5E 6E 7E Mnemonic PVIN4 SW6A SW6A VDR6 FB6 GND SYNC FB5 FB4 SW4 PVIN6 PVIN6 BST16 SDA SCL GND CLKO 8E 9E 1F 2F 3F 4F 5F 6F VDR34 PGND4 PVIN1 PVIN1 FB1 EN VDDIO FREQ 7F 8F 9F 1G 2G 3G 4G 5G 6G 7G 8G 9G 1H 2H 3H 4H 5H 6H 7H 8H 9H FB3 PGND3 PGND3 SW1A SW1B VDR12 FB2 GND FAULT GND SW3 SW3 PGND1 PGND1 PGND2 SW2 SW2 PVIN2 BST23 PVIN3 PVIN3 ADP5080 Description Input Power Supply for Channel 4. Primary Side Switching Node for Channel 6. Primary Side Switching Node for Channel 6. Low-Side FET Driver Power Supply for Channel 6. Connect this pin to VREG1. Feedback Node for Channel 6. Ground. All GND pins must be connected. External Clock Input (CMOS Input Port). If this pin is not used, connect it to GND. Feedback Node for Channel 5. Feedback Node for Channel 4. Switching Node for Channel 4. Input Power Supply for Channel 6. Input Power Supply for Channel 6. High-Side FET Driver Power Supply for Channel 1 and Channel 6. Data Input/Output for I2C Interface. Open-drain I/O port. Clock Input for I2C Interface. For start-up requirements, see the I2C Interface section. Ground. All GND pins must be connected. Clock Output (CMOS Output Port). CLKO replicates the Channel 1 switching clock. This output is not available when the SYNC pin is driven by an external clock. If this pin is not used, leave it open. Low-Side FET Driver Power Supply for Channel 3 and Channel 4. Connect this pin to VREG1. Power Ground for Channel 4. Input Power Supply for Channel 1. Input Power Supply for Channel 1. Feedback Node for Channel 1. Enable Control Input. Supply Voltage for I2C Interface. Typically, this pin is connected externally to VREG2 or to the host I/O voltage. Frequency Pin for the Internal Oscillator. To select the internal clock source oscillator, connect an external 100 kΩ resistor from the FREQ pin to GND. Feedback Node for Channel 3. Power Ground for Channel 3. Power Ground for Channel 3. Switching Node for Channel 1. Switching Node for Channel 1. Low-Side FET Driver Power Supply for Channel 1 and Channel 2. Connect this pin to VREG1. Feedback Node for Channel 2. Ground. All GND pins must be connected. Fault Status Output Pin. This open-drain output port goes low when a fault occurs. Leave open if not used. Ground. All GND pins must be connected. Switching Node for Channel 3. Switching Node for Channel 3. Power Ground for Channel 1. Power Ground for Channel 1. Power Ground for Channel 2. Switching Node for Channel 2. Switching Node for Channel 2. Input Power Supply for Channel 2. High-Side FET Driver Power Supply for Channel 2 and Channel 3. Input Power Supply for Channel 3. Input Power Supply for Channel 3. Rev. A | Page 11 of 64 ADP5080 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS 100 100 90 90 80 AUTO PSM 80 AUTO PSM 70 VIN = 4.5V VIN = 7.2V VIN = 12.6V 50 40 FPWM 40 30 20 20 10 10 100 OUTPUT CURRENT (mA) 1000 VIN = 4.5V VIN = 7.2V VIN = 12.6V 50 30 0 10 FPWM 60 0 10 Figure 4. Channel 1 Efficiency, VOUT = 1.1 V 100 OUTPUT CURRENT (mA) 1000 11639-007 EFFICIENCY (%) 60 11639-004 EFFICIENCY (%) 70 Figure 7. Channel 4 Efficiency, VOUT = 3.3 V 100 100 90 90 AUTO PSM 80 80 AUTO PSM 70 VIN = 4.5V VIN = 7.2V VIN = 12.6V 50 FPWM 40 FPWM 60 40 30 30 20 20 10 10 0 10 1000 100 OUTPUT CURRENT (mA) VIN = 4.5V VIN = 7.2V VIN = 12.6V 50 0 10 100 OUTPUT CURRENT (mA) 1000 11639-008 EFFICIENCY (%) 60 11639-005 EFFICIENCY (%) 70 Figure 8. Channel 5 Efficiency, VOUT = 3.3 V Figure 5. Channel 2 Efficiency, VOUT = 1.2 V 100 100 90 90 AUTO PSM 80 70 70 60 FPWM VIN = 4.5V VIN = 7.2V VIN = 12.6V 50 40 60 FPWM 40 30 30 20 20 10 10 0 10 100 OUTPUT CURRENT (mA) 1000 VIN = 4.5V VIN = 7.2V VIN = 12.6V 50 0 10 100 OUTPUT CURRENT (mA) Figure 9. Channel 6 Efficiency, VOUT = 5 V Figure 6. Channel 3 Efficiency, VOUT = 1.8 V Rev. A | Page 12 of 64 1000 11639-009 EFFICIENCY (%) 80 11639-006 EFFICIENCY (%) AUTO PSM Data Sheet ADP5080 3.315 1.110 VIN = 4.5V VIN = 7.2V VIN = 12.6V 3.310 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.105 1.100 VIN = 4.5V VIN = 7.2V VIN = 12.6V 3.305 3.300 3.295 1.095 1 10 100 OUTPUT CURRENT (mA) 3.285 0.1 11639-010 1.090 0.1 1000 1000 3.320 1.210 VIN = 4.5V VIN = 7.2V VIN = 12.6V 3.315 1.206 OUTPUT VOLTAGE (V) 3.310 OUTPUT VOLTAGE (V) 10 100 OUTPUT CURRENT (mA) Figure 13. Channel 4 Load Regulation Figure 10. Channel 1 Load Regulation 1.208 1 11639-013 3.290 1.204 1.202 1.200 1.198 1.196 VIN = 4.5V VIN = 7.2V VIN = 12.6V 3.305 3.300 3.295 3.290 1.194 1 10 100 OUTPUT CURRENT (mA) 1000 3.280 0.1 11639-011 1.190 0.1 Figure 11. Channel 2 Load Regulation 10 100 OUTPUT CURRENT (mA) 1000 Figure 14. Channel 5 Load Regulation 5.020 1.810 VIN = 4.5V VIN = 7.2V VIN = 12.6V 5.015 1.805 VIN = 4.5V VIN = 7.2V VIN = 12.6V OUTPUT VOLTAGE (V) 5.010 1.800 1.795 5.005 5.000 4.995 4.990 1.790 0.1 1 10 100 OUTPUT CURRENT (mA) 1000 Figure 12. Channel 3 Load Regulation 4.980 0.1 1 10 100 OUTPUT CURRENT (mA) Figure 15. Channel 6 Load Regulation Rev. A | Page 13 of 64 1000 11639-015 4.985 11639-012 OUTPUT VOLTAGE (V) 1 11639-014 3.285 1.192 ADP5080 Data Sheet 12.05 12.04 OUTPUT VOLTAGE (V) 12.03 2 12.02 12.01 12.00 11.99 11.98 11.97 1 OUTPUT CURRENT (mA) 10 B 20.0M CH2 20.0mV W CH4 500mA 50Ω BW 250M 11639-016 11.95 0.1 200µs/DIV 20.0MS/s 11639-018 4 11.96 Figure 19. Channel 1 Load Transient, VOUT = 1.1 V, FPWM Mode Figure 16. Channel 7 Load Regulation, VILDO7 = 16 V 5.100 5.050 2 5.025 5.000 4.975 4.950 4.925 1 10 100 OUTPUT CURRENT (mA) B 20.0M CH2 20.0mV W CH4 300mA 50Ω BW 20.0M 11639-017 4.900 0.1 4 200µs/DIV 10.0MS/s 11639-127 VREG1 OUTPUT VOLTAGE (V) 5.075 Figure 20. Channel 1 Load Transient, VOUT = 1.1 V, Auto PSM Mode Figure 17. VREG1 Load Regulation 3.400 3.350 2 3.325 3.300 3.275 3.250 3.225 1 10 OUTPUT CURRENT (mA) 100 B 20.0M CH2 20.0mV W CH4 300mA 50Ω BW 250M 200µs/DIV 20.0MS/s 11639-019 3.200 0.1 4 11639-118 VREG2 OUTPUT VOLTAGE (V) 3.375 Figure 21. Channel 2 Load Transient, VOUT = 1.2 V, FPWM Mode Figure 18. VREG2 Load Regulation Rev. A | Page 14 of 64 ADP5080 2 4 4 20.0MS/s CH2 20mV CH4 200mA Figure 22. Channel 2 Load Transient, VOUT = 1.2 V, Auto PSM Mode 4 4 20.0MS/s 11639-020 2 200µs/DIV B 20.0M CH2 50.0mV W CH4 100mA 50Ω BW 20.0M Figure 23. Channel 3 Load Transient, VOUT = 1.8 V, FPWM Mode 4 4 20.0MS/s 11639-129 2 200µs/DIV 5.0MS/s 200µs/DIV 20.0MS/s Figure 26. Channel 4 Load Transient, VOUT = 3.3 V, Auto PSM Mode 2 B 20.0M CH2 50.0mV W CH4 200mA 50Ω BW 20.0M 200µs/DIV Figure 25. Channel 4 Load Transient, VOUT = 3.3 V, FPWM Mode 2 B 20.0M CH2 40.0mV W CH4 400mA 50Ω BW 250M B 20.0M W 50Ω BW 250M 11639-130 200µs/DIV B 20.0M CH2 50.0mV W CH4 500mA 50Ω BW 250M Figure 24. Channel 3 Load Transient, VOUT = 1.8 V, Auto PSM Mode 200µs/DIV 20.0MS/s 11639-022 B 20.0M CH2 20.0mV W CH4 200mA 50Ω BW 20.0M 11639-128 2 11639-021 Data Sheet Figure 27. Channel 5 Load Transient, VOUT = 3.3 V, FPWM Mode Rev. A | Page 15 of 64 Data Sheet 2 4 4 200µs/DIV 20.0MS/s CH2 100mV CH4 100mA Figure 28. Channel 5 Load Transient, VOUT = 3.3 V, Auto PSM Mode 4 4 20.0MS/s 11639-023 2 200µs/DIV CH2 20mV CH4 100mA Figure 29. Channel 6 Load Transient, VOUT = 5 V, FPWM Mode 200µs/DIV 20.0MS/s 11639-132 4 B 20.0M W 50Ω BW 20.0M 20.0MS/s B 20.0M W 50Ω BW 250M 200µs/DIV 20.0MS/s Figure 32. VREG2 Load Transient, VREG2 = 3.3 V 2 CH2 100mV CH4 300mA 200µs/DIV Figure 31. VREG1 Load Transient, VREG1 = 5 V 2 B 20.0M CH2 70.0mV W CH4 400mA 50Ω BW 1.0G B 20.0M W 50Ω BW 250M Figure 30. Channel 6 Load Transient, VOUT = 5 V, Auto PSM Mode Rev. A | Page 16 of 64 11639-126 B 20.0M CH2 50.0mV W CH4 300mA 50Ω BW 20.0M 11639-131 2 11639-125 ADP5080 Data Sheet ADP5080 CH7 R3 R4 3 2 CH7 CH5 CH5 R1 CH6 R4 CH6 CH4 CH4 1 CH3 2 R2 1 CH2 CH1 3 CH3 CH2 R3 R2 EN CH1 1.0V CH2 2.0V CH3 5.0V CH4 5.0V EN 4 1MΩ 1MΩ 1MΩ 1MΩ R1 R2 R3 R4 1.0V 1.0ms 1.0V 5.0V 2.0V CH1 5.0V CH2 3.0V CH3 1.0V CH4 5.0V Figure 33. Startup 1MΩ 1MΩ 1MΩ 1MΩ R1 R2 R3 R4 5.0V 2.0ms 1.0V 700mV 3.0V Figure 34. Shutdown Rev. A | Page 17 of 64 11639-027 4 CH1 11639-026 R1 ADP5080 Data Sheet APPLICATION CIRCUIT EN I2C INTERFACE SDA KEY CONTROLLER/ SUB-CPU 4.7µF VREG2 VISW2 VREG1 VISW1 VBATT GND VDDIO SCL 4.7µF 10µF LDO1 (KEEP-ALIVE) POWER SWITCH 3.3V VBATT 1µF VDDIO VDDIO VREG2 TO VDRx 5.0V VDDIO EN34 OUTPUT ENABLE LOGIC LDO2 (KEEP-ALIVE) VREG2 UVLO UVLO FAULT POR FAULT PVIN1 VBATT BSTCP PVIN1 PGND1 BST16 SW1A SW1B VOUT1 PGND1 PGND1 FB1 VDR12 VREG1 PVIN2 POWER FAULT DETECTION CHANNEL 1 BUCK REGULATOR BST23 CHANNEL 2 BUCK REGULATOR GATE SCALING (VDR12) DISCHARGE SWITCH SOFT COMP START DISCHARGE SWITCH SOFT COMP START DAC BSTCP PGND2 SW2 VOUT2 SW2 PGND2 FB2 DAC PVIN3 VBATT VBATT PVIN4 VBATT PVIN3 PGND3 VOUT3 POWER SEQUENCE SW3 SW3 PGND3 CHANNEL 3 BUCK REGULATOR PGND3 FB3 VDR34 VREG1 DISCHARGE SWITCH SOFT COMP START DISCHARGE SWITCH (BST23) (VDR34) DAC PGND4 BST45 CHANNEL 4 BUCK REGULATOR SOFT COMP START DAC BSTCP SW4 VOUT4 PGND4 FB4 PVIN5 PVIN6 VBATT PGND6 (BST16) PGND6 VOUT6 VOUT6 PGND6 VDR5 CHANNEL 5 BUCK REGULATOR CHANNEL 6 BUCK/ BUCK BOOST REGULATOR VREG1 SOFT COMP START SW6B FB6 VOUT5 SW5 DAC PGND5 FB5 FREQ PGND6 VDR6 SW5 PGND5 DISCHARGE SWITCH SW6B VREG1 PGND5 SW6A SW6A VOUT6 VBATT PVIN5 (BST45) PVIN6 OSCILLATOR SOFT COMP START CLKO 100kΩ OPTIONAL SYNC DISCHARGE SWITCH DAC BSTCP C+ VBATT CHANNEL 7 HV LDO PVINCP C+ PVINCP VOLDO7 CHARGE PUMP 12V GND GND C– GND Figure 35. Typical Application Circuit Rev. A | Page 18 of 64 11639-028 BSTx VILDO7 BSTCP Data Sheet ADP5080 THEORY OF OPERATION The ADP5080 is a fully integrated, high efficiency power solution for multicell lithium ion battery applications. The device can connect directly to the battery, which eliminates the need for preregulators and increases the battery life of the system. The ADP5080 integrates two keep-alive LDO regulators, five synchronous buck regulators, one configurable buck boost regulator, and one high voltage LDO regulator. An integrated charge pump provides the switch driver power supply. Along with the integrated power FETs and drivers, integrated compensation, soft start, and FB dividers contribute to minimize the number of external components and the PCB layout space, providing significant advantages for portable applications. Factory programming sets the default values for the output voltages, fault behavior, switching frequency, start-up time, and other functions. These values can also be programmed via the I2C interface. The ADP5080 features a built-in sequencer that provides automatic startup and shutdown timing based on these settings. UVLO AND POR The undervoltage lockout (UVLO) and power-on reset (POR) functions prevent abnormal behavior and force a smooth shutdown when input voltages fall below the minimum required levels. The ADP5080 incorporates UVLO on VBATT, PVIN1, and VDR12; it incorporates POR on VREG2. The thresholds are low enough to ensure normal operation down to 4 V at VBATT with ample hysteresis to avoid chattering. Undervoltage Lockout (UVLO) If the PVIN1 voltage of Channel 1 falls below the UVLO threshold (VUVLO (F)), all channels, as well as the charge pump, are turned off. However, LDO1 and LDO2 remain operational. As the input voltage rises, the regulator channels do not restart automatically. EN must be toggled after a UVLO event to restart channels in sequencer mode or manual mode. For more information about enabling channels using sequencer mode and manual mode, see the Enabling and Disabling the Output Channels section. The VDRx pins provide the gate drive voltage to the internal power FETs. If the VDR12 voltage falls below 2.9 V (typical), all channels except LDO1 and LDO2 shut down to prevent malfunction of the power FETs. As with a PVIN UVLO event, EN must be toggled to restart channel operation. Power-On Reset (POR) If the VBATT voltage falls below its UVLO threshold (VUVLO (BATT)), all channels, including LDO1 and LDO2, are shut down. This event forces a power-on reset. VREG2 is the voltage supply for the internal digital circuit blocks. If the VREG2 voltage falls below the power-on reset threshold (VUVLO (POR)) of 2.4 V typical, the ADP5080 shuts down, and all registers are reset to their default values. DISCHARGE SWITCH The ADP5080 integrates discharge switches for Channel 1 to Channel 7. These switches help to discharge the output capacitors quickly when a channel is turned off. The discharge switches are turned on when the EN signal goes low or when a channel is manually turned off via I2C control, provided that the discharge function was enabled by setting the DSCGx_ON bit (x is 1 to 7) in Register 1. The default values for the discharge switches are factory fuse programmed. KEEP-ALIVE LDO REGULATORS The keep-alive LDO linear regulators (LDO1 and LDO2) are kept alive as long as a valid supply voltage is applied to the VBATT pin. The LDO regulators are used to power the internal control block of the ADP5080 so that the device is ready for the enable (EN) signal. The outputs of LDO1 and LDO2 are also available via the VREG1 and VREG2 pins for external circuits that are also kept alive during system standby. When VBATT initially rises above the UVLO threshold, LDO1 begins operation, followed by LDO2. When all UVLO thresholds are cleared, the ADP5080 is in standby mode and ready to be enabled. If an external voltage is used to drive VDDIO, VDDIO can be on before VBATT; otherwise, LDO2 provides power to VDDIO via the VREG2 output. Rev. A | Page 19 of 64 ADP5080 Data Sheet LDO1 The use of an external regulator connected to the VISW1 pin is intended to achieve better system power efficiency by allowing a switching power supply to take over the LDO1 linear regulator when the system is powered up to operation. If the VISW1 input is not used, tie it to GND. The VISW1 input is not active until EN is high. LDO1 regulates the supply voltage applied to the VBATT pin to either 5.0 V or 5.5 V and is capable of providing up to 400 mA. LDO1 internally supplies LDO2, as well as external circuits, including the VDRx pins supplied through the VREG1 pin. The LDO1 output is enabled when the VBATT pin voltage rises above the UVLO threshold and is disabled when the VBATT pin voltage falls below the UVLO threshold. Current Limit for LDO1 LDO1 is rated to a maximum load current of 400 mA. Above this level, the current-limit feature limits the current to protect the device. VISW1 Input A 5.0 V to 5.5 V regulator connected to the VISW1 pin can take over from LDO1 to supply the internal circuit of the ADP5080 and the VREG1 load. To enable this feature, set the SEL_INP_LDO1 bit (Bit 0 in Register 33) high after the VISW1 pin voltage settles above 4.7 V. The VISW1 input has an independent current-limit circuit with a typical threshold of 500 mA. If this overcurrent threshold is exceeded, the VISW1 input is immediately disconnected and LDO1 takes over to supply the VREG1 current. After the VISW1 input is turned off due to a current-limit event, it can be reset only by toggling the EN pin. If the VISW1 pin voltage falls below 4.5 V, LDO1 resumes control automatically. However, if the VISW1 source is disabled, it is recommended that the SEL_INP_LDO1 bit be reset to 0 before turning off the VISW1 pin source. Discharge Switch for LDO1 A discharge switch at the VREG1 pin turns on during low VBATT pin voltage (3.5 V ± 0.1 V hysteresis), removing the charge of the external capacitor via a 1 kΩ resistor. VOLTAGE DETECTION VISW1 OVERCURRENT PROTECTION 5.0V TO 5.5V CURRENT DETECTION OVERCURRENT PROTECTION VBATT VREG1 5.0V OR 5.5V DISCHARGE SWITCH AGND TO INTERNAL CIRCUITS VREF 11639-029 LDO1 Figure 36. VREG1, LDO1, and VISW1 Rev. A | Page 20 of 64 Data Sheet ADP5080 LDO2 is not used, tie it to GND. The VISW2 input is not active until EN is high. LDO2 regulates the internally routed VREG2 pin voltage to 3 V, 3.15 V, 3.2 V, or 3.3 V and is capable of providing up to 300 mA. LDO2 internally supplies the control block of the ADP5080, as well as external circuits supplied through the VREG2 pin. Because the VISW2 input supplies VREG2 with no regulation, the maximum voltage that can be applied to VISW2 is 3.3 V. The VISW2 input has a relatively high resistance compared to the LDO2 path. As a result, VISW2 regulation may not be sufficient when used to supply heavier loads. The LDO2 output is enabled when the VBATT pin voltage rises above the UVLO threshold and is disabled when the VBATT pin voltage falls below the UVLO threshold. Current Limit for LDO2 LDO2 is rated to a maximum load current of 300 mA. Above this level, the current-limit feature limits the current to protect the device. VISW2 Input A 3.0 V to 3.3 V regulator connected to the VISW2 pin can take over from LDO2 to supply the internal circuit of the ADP5080 and the VREG2 load. To enable this feature, set the SEL_INP_LDO2 bit (Bit 4 in Register 33) high after the VISW2 pin voltage settles above 2.7 V. The VISW2 input has an independent current-limit circuit with a typical threshold of 300 mA. If this overcurrent threshold is exceeded, the VISW2 input is immediately disconnected and LDO2 takes over to supply the VREG2 current. After the VISW2 input is turned off due to a current-limit event, it can be reset only by toggling the EN pin. If the VISW2 pin voltage falls below 2.55 V, LDO2 resumes control automatically. However, if the VISW2 source is disabled, it is recommended that the SEL_INP_LDO2 bit be reset to 0 before turning off the VISW2 pin source. Discharge Switch for LDO2 A discharge switch at the VREG2 pin turns on during low VBATT pin voltage (3.5 V ± 0.1 V hysteresis), removing the residual charge of the external capacitor via a 12 Ω resistor. The use of an external regulator connected to the VISW2 pin is intended to achieve better system power efficiency by allowing a switching power supply to take over the LDO2 linear regulator when the system is powered up to operation. If the VISW2 input VOLTAGE DETECTION VISW2 OVERCURRENT PROTECTION 3.0V TO 3.3V CURRENT DETECTION OVERCURRENT PROTECTION VREG2 3.0V TO 3.3V DISCHARGE SWITCH FROM VREG1 OUTPUT 5.0V TO 5.5V AGND TO INTERNAL CIRCUITS VREF 11639-030 LDO2 Figure 37. VREG2, LDO2, and VISW2 Rev. A | Page 21 of 64 ADP5080 Data Sheet DC-TO-DC CONVERTER CHANNELS The ADP5080 integrates five buck regulators and a configurable buck only/buck boost regulator. These regulators can be configured for various functions including auto PSM, auto DCM, DVS, and gate scaling. Each function is included only in the channels where it is most effective (see Table 9). Channel 1, Channel 2, and Channel 3: Buck Regulators with Flex-Mode Architecture Channel 1, Channel 2, and Channel 3 feature Flex-Mode™ current mode control, which eliminates minimum on time requirements and allows duty cycles as low as 0%. Flex-Mode uses a unique adaptive control architecture that maintains stable operation over a wide range of application conditions. With Flex-Mode control, very high step-down ratios can be achieved while maintaining high efficiency and excellent transient performance. If the input voltage falls below this level, the output voltage droops below its nominal value. Current-Limit Protection, Channel 1 to Channel 3 Channel 1, Channel 2, and Channel 3 use valley mode current limit (see Figure 38). In valley mode current-limit protection, inductor current is sensed during the low-side on cycle, immediately before the high-side FET turns on. If the inductor current is above the current-limit threshold at this point, the next switching pulse is skipped. CURRENT SENSING POINT INDUCTOR CURRENT VALLEY CURRENTLIMIT THRESHOLD Selecting the Output Voltage, Channel 1 to Channel 3 The output voltage of Channel 1, Channel 2, or Channel 3 is selected from one of the preset values available in the VIDx bits, where x is 1, 2, or 3 (see Table 39 and Table 41). The default output voltage value is factory fuse programmed. Channel 3 has an adjustable mode option that can be selected using the VID3 bits. When the adjustable output voltage mode is selected, the output voltage is set by an external feedback resistor divider. Select resistor values such that the desired output voltage is divided down to 0.8 V and the paralleled resistance seen from the dividing node does not exceed 25 kΩ (see the Setting the Output Voltage (Adjustable Mode Channels) section). Channel 1 can also be used in adjustable output mode by setting the VID1 bits to 0.8 V and using external feedback resistors with values less than 1 kΩ. When using the adjustable mode for Channel 1 or Channel 3, be aware of the minimum off time restriction, which may limit the range of available output voltages. Channel 1, Channel 2, and Channel 3 are designed for very low duty cycle operation. However, at very high duty cycle, these channels have a limited range due to the minimum off time restriction (see Table 3). The minimum input voltage capability for a given output voltage can be determined using the following equation: 11639-031 SKIPPED CYCLE SW NODE Figure 38. Valley Mode Current Limit Switching does not resume until the current falls below the limit threshold. This behavior creates an inherent frequency foldback feature, which makes valley mode current-limit protection very robust against runaway inductor current. Because this type of current limit senses current before switching, it is also relatively immune to switching noise. Table 3 provides the valley current threshold specifications. The actual load current-limit threshold varies with inductor value, frequency, and input and output voltage. When the current-limit threshold is exceeded, load current is not allowed to increase further. Therefore, as the load impedance is reduced, the current limit forces the output voltage to fall. The falling output voltage in turn toggles the PWRGx, UVx, and FAULT error flags. In the extreme event of an output voltage short circuit, the UVP function protects the device against excessive current during the on cycle (see the Undervoltage Protection (UVP) section). VIN_MIN = VOUT/(1 − tOFF_MIN × fSW) Table 9. DC-to-DC Converter Specifications and Functions Channel 1 2 3 4 5 6 1 Regulator Type Buck Buck Buck Buck Buck Buck or buck boost VIN Range (V) 4 to 15 4 to 15 4 to 15 4 to 15 4 to 15 4 to 15 VOUT Range (V) 0.8 to 1.2 1 1.0 to 3.3 1.2 to 1.8 1.8 to 3.55 3.0 to 5.0 3.5 to 5.5 Adjustable Mode (V) 0.8 to 1.2 N/A 0.8 to 3.6 1.0 to 5.0 N/A 1.0 to 5.0 Channel 1 has two available voltage ranges. Rev. A | Page 22 of 64 IOUT (A) 3 1.15 1.5 0.8 2 2 (buck) 1.5 (buck boost) Auto PSM Yes Yes Yes Yes Yes Yes Auto DCM N/A N/A N/A N/A Yes Yes DVS Yes Yes N/A N/A N/A N/A Gate Scaling Yes N/A N/A N/A N/A N/A Data Sheet ADP5080 Discharge Switch, Channel 1 to Channel 3 DVSx_INTVAL Each channel incorporates a discharge switch. For Channel 1 and Channel 2, the discharge switch is located at the FB1 and FB2 pins, respectively; for Channel 3, the discharge switch is located at the SW3 pin. The discharge switch can be turned on when the corresponding channel output is turned off, removing the residual charge of the external capacitor via a 125 Ω resistor. The discharge switch can be enabled by setting the appropriate DSCGx_ON bit in Register 1. VID (PREV – 1) OUTPUT VOLTAGE VID (PREV) Figure 39. DVS Operation The output voltage for Channel 1 is programmed using the VID1 bits in Register 12; the output voltage for Channel 2 is programmed using the VID2 bits in Register 13. When the DVS function is enabled, the voltage transition takes place according to the steps set by the VID1 or VID2 bits (see Table 39 and Table 41). The transition time from one step to the next is specified by the interval programmed in Register 17 using the DVSx_INTVAL bits (where x is 1 or 2). The DVS function is enabled by setting the EN_DVSx bit in Register 17. Gate Scaling (Channel 1 Only) Channel 1 features a gate scaling function, which improves efficiency in light load conditions. When enabled by setting the GATE_SCAL1 bit in Register 32, gate scaling halves the size of the Channel 1 switching FETs, reducing the gate charge-up current—which is a non-negligible loss element in light load conditions—while allowing increased RDSON, whose effect is less significant in these conditions. When gate scaling is enabled, only SW1A is used for the Channel 1 switch node because it is assumed that the load current is light. For Channel 2, DVS operation is limited to an output voltage range of 1.0 V to 1.25 V. When Channel 1 or Channel 2 is configured for DVS operation, toggling EN low does not immediately reset the VID code to its initial state. Instead Channel 1 or Channel 2 returns to its configured output voltage according to the steps set by the VID1 or VID2 bits (see Table 39 and Table 41, respectively). Dynamic Voltage Scaling (DVS) Function Channel 1 and Channel 2 incorporate a dynamic voltage scaling (DVS) function. DVS provides a stair-step transition in output voltage when the preset value for the output voltage is reprogrammed on the fly (see Figure 39). BSTx BSTCP ADP5080 SOFT START VDRx PWM COMPARATOR R RS LATCH CLOCK S OVP UVP OCP SHOOT-THROUGH PROTECTION PVINx VREG1 PGNDx 4V TO 15V PGNDx SWx OUTPUT VOLTAGE PGNDx PGNDx ZERO CROSS COMPARATOR PSM LOGIC ON PERIOD SLOPE GENERATION ERROR AMP PGND CURRENT SENSE AMP OCP OUTPUT VOLTAGE CURRENT LIMIT FBx FB3 VREF 0.8V FB1 FB2 SW3 POWER-GOOD COMPARATOR DISCHARGE SWITCH Figure 40. Buck Regulator Block Diagram: Channel 1, Channel 2, and Channel 3 Rev. A | Page 23 of 64 EXTERNAL VOLTAGE DIVIDER (CH3 ADJ MODE ONLY) 11639-033 SEQUENCER 11639-032 VID (NEW) ADP5080 Data Sheet Channel 4 and Channel 5: Current Mode Buck Regulators seen from the dividing node does not exceed 25 kΩ (see the Setting the Output Voltage (Adjustable Mode Channels) section). When using the adjustable mode for Channel 4, be aware of the minimum on time restriction, which may limit the range of available output voltages. Channel 4 and Channel 5 are internally compensated current mode control buck regulators (see Figure 41). Combined with the integrated charge pump, these channels are designed to operate at high duty cycles up to 100%. Channel 4 and Channel 5 are designed for very high duty cycle operation. However, at very low duty cycle, these channels have a limited range due to the minimum on time restriction (75 ns typical) inherent in current mode control. The maximum input voltage capability for a given output voltage can be determined using the following equation: Selecting the Output Voltage, Channel 4 and Channel 5 The output voltage of Channel 4 or Channel 5 is selected from one of the preset values available in the VIDx bits, where x is 4 or 5 (see Table 43). The default output voltage value is factory fuse programmed. Channel 4 has an adjustable mode option that can be selected using the VID4 bits. When the adjustable output voltage mode is selected, the output voltage is set by an external feedback resistor divider. Select resistor values such that the desired output voltage is divided down to 0.8 V and the paralleled resistance VIN_MAX = VOUT/(tON_MIN × fSW) If the input voltage rises above this level, the output voltage continues to be regulated; however, switching pulses are skipped, which may increase output voltage ripple. BSTx ADP5080 VDRx OCP SOFT START R SLOPE COMPENSATION RS LATCH S CLOCK OVP UVP OCP SHOOT-THROUGH PROTECTION PWM COMPARATOR CURRENT LIMIT VREG1 PGNDx CURRENT SENSE AMP PVINx 4V TO 15V PGNDx SWx OUTPUT VOLTAGE PGNDx PGNDx ZERO CROSS COMPARATOR PSM LOGIC PGND ERROR AMP OUTPUT VOLTAGE FBx SW4 FB5 POWER-GOOD COMPARATOR VREF DISCHARGE SWITCH Figure 41. Buck Regulator Block Diagram: Channel 4 and Channel 5 Rev. A | Page 24 of 64 FB4 0.8V EXTERNAL VOLTAGE DIVIDER (CH4 ADJ MODE ONLY) 11639-034 SEQUENCER BSTCP Data Sheet ADP5080 Current-Limit Protection, Channel 4 and Channel 5 Buck Boost Configuration Channel 4 and Channel 5 have integrated cycle-by-cycle currentlimit protection. In this type of current-limit protection, inductor current is sensed throughout the high-side on cycle. If the inductor current rises above the current-limit threshold during this time, the switching pulse is immediately terminated until the next cycle. This behavior causes the duty cycle to decrease, which in turn causes the output voltage to fall. The falling output voltage then toggles the PWRGx, UVx, and FAULT error flags. Because there is substantial parasitic noise at the rising edge of the high-side switch, some blanking time is required to prevent false current-limit triggering. This required blanking time determines the minimum on time of the channel. For the buck boost configuration, set the BUCK6_ONLY bit (Bit 4 in Register 30) to 0. The default value of this bit is factory fuse programmed. For the buck boost configuration, connect the inductor between the SW6A and SW6B pins (see Figure 42). Make sure that no capacitor is connected to the SW6B pin. Unlike valley mode current-limit protection, peak mode currentlimit protection has no inherent frequency foldback. In extreme conditions such as a short circuit or inductor saturation, peak mode current limit is susceptible to runaway inductor current. To prevent this, the ADP5080 provides frequency foldback on Channel 4, Channel 5, and Channel 6. When the output voltage falls below approximately 80% of its nominal value, the switching frequency is halved. The frequency is halved again if the output voltage falls below approximately 40% of its nominal value. The frequency foldback feature allows more time for inductor current to decay, eliminating the possibility of current runaway. When the input voltage is close to the output voltage, Channel 6 operates in buck boost mode with all four power FETs switching. This four-switch mode of operation ensures a smooth transition and excellent regulation, regardless of input voltage conditions. Table 3 provides the peak current-limit threshold specifications. The actual load current-limit threshold varies with inductor value, frequency, and input and output voltage. Discharge Switch, Channel 4 and Channel 5 Each channel incorporates a discharge switch. For Channel 4, the discharge switch is located at the SW4 pin; for Channel 5, the discharge switch is located at the FB5 pin. The discharge switch can be turned on when the corresponding channel output is turned off, removing the residual charge of the external capacitor via a 125 Ω resistor. The discharge switch can be enabled by setting the appropriate DSCGx_ON bit in Register 1. Channel 6: Buck or Buck Boost Regulator Channel 6 is a current mode control, four-switch buck boost regulator that can be configured as a buck only regulator. In a system in which the input voltage never falls below the Channel 6 output, using the buck only configuration reduces the losses caused by the switching FETs of the boost side. The buck only configuration yields better power efficiency, as well as lower output ripple and noise. Buck Only Configuration For the buck only configuration, set the BUCK6_ONLY bit (Bit 4 in Register 30) to 1. The default value of this bit is factory fuse programmed. When Channel 6 is configured for buck only mode, connect the inductor between the SW6A and VOUT6 pins, leaving the SW6B pin open (see Figure 42). This configuration bypasses the boost side switching FET. In buck boost operation, Channel 6 automatically switches between the buck and boost modes as the input voltage varies.   In buck mode, the primary FETs (SW6A) switch with the SW6B high-side FET operating at 100% duty cycle. In boost mode, all four FETs are typically switching, although the primary high-side FET is capable of a 100% duty cycle. The BOOST6_VTH bits (Bits[1:0] in Register 30) set the input voltage threshold for the boost FETs to start switching. A lower threshold provides higher efficiency because the region where all four switches are in operation is smaller. The lowest setting for these bits (11) sets an input voltage threshold that is still high enough to prevent dropout in most cases. However, under heavy load current at the lowest threshold setting, the buck side may reach a 100% duty cycle and some output droop may occur. The second lowest setting for these bits (00) is recommended for heavy load applications. The default value of these bits is factory fuse programmed. Selecting the Output Voltage, Channel 6 The output voltage of Channel 6 is selected from one of the preset values available in the VID6 bits (see Table 45). The default output voltage value is factory fuse programmed. Channel 6 has an adjustable mode option that can be selected using the VID6 bits. When the adjustable output voltage mode is selected, the output voltage is set by an external feedback resistor divider. Select resistor values such that the desired output voltage is divided down to 0.8 V while the paralleled resistance seen from the dividing node does not exceed 25 kΩ (see the Setting the Output Voltage (Adjustable Mode Channels) section). Because Channel 6 can operate in boost mode, there is no practical output voltage limitation other than the maximum rating. When using the adjustable output voltage in buck only mode, be aware of the minimum on time restriction, which may limit the range of available output voltages. The minimum on time limitation is essentially the same as for Channel 4 and Channel 5 (see the Selecting the Output Voltage, Channel 4 and Channel 5 section). Rev. A | Page 25 of 64 ADP5080 Data Sheet Current-Limit Protection, Channel 6 Discharge Switch, Channel 6 Like Channel 4 and Channel 5, Channel 6 has integrated cycleby-cycle current-limit protection. In this type of current-limit protection, inductor current is sensed throughout the high-side on cycle. The Channel 6 current limit is sensed on the primary high-side FET (SW6A). For more information, see the CurrentLimit Protection, Channel 4 and Channel 5 section. Each channel incorporates a discharge switch. For Channel 6, the discharge switch is located at the VOUT6 pin. The discharge switch can be turned on when the Channel 6 output is turned off, removing the residual charge of the external capacitor via a 110 Ω resistor. The discharge switch can be enabled by setting the DSCG6_ON bit in Register 1. BUCK BOOST CONFIGURATION VREG1 PGND6 VDR6 SW6A SW6B CURRENT SENSE AND LIMIT ADP5080 PVIN6 4V TO 15V OCP VOUT6 3.5V TO 5.5V PGND6 BSTCP PGND6 VOUT6 CONTROL LOGIC CONTROL LOGIC PGND6 PGND6 PSM LOGIC ZERO CROSS COMPARATOR CLOCK Q RS LATCH FB6 OVP UVP OCP R SLOPE COMPENSATION DISCHARGE SWITCH S PWM COMPARATOR VOUT6 SEQUENCER ERROR AMP CLOCK FB6 POWER-GOOD COMPARATOR 0.8V SOFT START VREF EXTERNAL VOLTAGE DIVIDER (ADJ MODE ONLY) PGND6 PGND6 BUCK ONLY CONFIGURATION SW6A OPEN SW6B VOUT6 ADP5080 3.5V TO 5.5V PGND6 VOUT6 FB6 0.8V FB6 EXTERNAL VOLTAGE DIVIDER (ADJ MODE ONLY) Figure 42. Channel 6 Buck or Buck Boost Regulator Block Diagram Rev. A | Page 26 of 64 11639-035 BST16 Data Sheet ADP5080 LIGHT LOAD AND OTHER MODES OF OPERATION FOR THE DC-TO-DC CONVERTER CHANNELS AUTO PSM Each dc-to-dc converter channel in the ADP5080 has two or three options to handle light load conditions, whereas asynchronous dc-to-dc converters simply transition to discontinuous conduction mode (DCM). Although light load modes provide higher efficiency and longer battery life, they are also associated with increased ripple and noise. This trade-off requires the user to select the option that best suits the application, usually on a channel by channel basis (see Table 9). The modes of operation are illustrated in Figure 43, which shows the inductor current and the switch node in auto PSM, auto DCM, and FPWM modes. AUTO DCM 11639-036 FPWM Figure 43. Auto PSM, Auto DCM, and FPWM Operation (Switch Node and Inductor Current Shown, Dashed Line Indicates 0 A) Slew Rate Adjustment Each channel has a slew rate adjustment option, which is set using the ADJ_SRx bit (where x is 1 to 6) in the OPT_SR_ADJ register (Register 31). When the ADJ_SRx bit is set, the switch node slew rate for the channel is reduced, which in turn reduces high frequency spike noise. Enabling this feature reduces the efficiency of the channel, however, due to increased switching losses. For this reason, use the slew rate adjustment feature only when low output noise is critical. 100 90 80 EFFICIENCY (%) 70 Forced PWM (FPWM) Mode Auto DCM 50 40 AUTO PSM AUTO DCM FPWM 30 20 10 0 0.01 0.1 1 OUTPUT CURRENT (A) Figure 44. Efficiency of Auto PSM, Auto DCM, and FPWM Operation Selecting Light Load Switching Modes Each dc-to-dc converter channel can be configured with its own light load switching mode using the AUTO-PSMx bits in Register 28 and, for Channel 5 and Channel 6, the DCM56 bit in Register 32 (see Table 10 and Table 11). Automatic discontinuous conduction mode (auto DCM) is available on Channel 5 and Channel 6. Auto DCM turns off the low-side switching FET when the inductor current falls to zero during the tOFF period, preventing negative current from flowing through the low-side FET. This operation is equivalent to that of traditional flywheel diode-based PWM regulators. Auto DCM has higher efficiency than FPWM mode because negative inductor current is not allowed, but rather is recirculated to the input side. At very light loads in auto DCM, some pulse skipping occurs and, therefore, switching is not at a constant frequency. Table 10. Light Load Switching Modes, Channel 1 to Channel 4 Auto PSM Table 11. Light Load Switching Modes, Channel 5 and Channel 6 Automatic power save mode (auto PSM) is similar to auto DCM, except that it intentionally turns on the high-side FET with a fixed period (approximately 80% of nominal tON). This operation forces the regulator to skip a number of PWM cycles. Compared to auto DCM, auto PSM skips a larger number of cycles and begins skipping cycles at a higher load current. Auto PSM reduces switching losses dramatically and improves efficiency, as shown in Figure 44. However, in light load conditions, larger output voltage ripple can be expected. 11639-037 Forced pulse-width modulation (FPWM) mode maintains PWM operation despite light load conditions, allowing negative current to flow from the inductor through the low-side switching FET. This mode is also referred to as continuous conduction mode (CCM). The FPWM option has the lowest efficiency, but may be selected when constant frequency and low ripple are absolutely required, regardless of load. 60 AUTO-PSMx Bit 0 1 AUTO-PSMx Bit 0 1 1 1 X = don’t care. Rev. A | Page 27 of 64 Light Load Switching Mode FPWM Auto PSM DCM56 Bit X1 0 1 Light Load Switching Mode FPWM Auto PSM Auto DCM ADP5080 Data Sheet SWITCHING CLOCK Selecting the External Resistor The ADP5080 integrates a highly accurate switching clock for the dc-to-dc converters and the charge pump. As shown in Figure 45, the internal clock can also be bypassed and the system synchronized to an external clock. When the internal clock source is used, the switching frequency for each dc-to-dc converter and the charge pump can be configured. An external 100 kΩ resistor from the FREQ pin to GND is required for the internal clock source oscillator. To obtain an accurate clock frequency, select a high precision resistor with a low temperature coefficient. A 1 nF bypass capacitor is also recommended at the FREQ pin. PHASEx FREQx Each dc-to-dc converter can be configured to use the inverted phase of the master clock by setting the PHASEx bit (where x is 1 to 6) in Register 20. Setting channels out of phase with each other helps reduce rms current stress on the input capacitors and spreads switching energy over two cycles. Phase shifting reduces possible interference in a system due to propagated switching noise on the input rail. EN_CLKO SYNC DETECTOR CLKO 1/2 CH1 SYNC CH2 SEL_FSW CH3 When any channel is operated at 1/2 × fSW, the higher frequency channel must be set out of phase to have any effect on the apparent phase of the lower frequency channel (see Figure 46). CH4 CLOCK SOURCE 2.0MHz (0) OR 1.5MHz (1) Phase Shifting CH5 FREQ 1 CH6 ROSC 100kΩ 1/2 1 2 MASTER CLOCK CHARGE PUMP 1/8 IN PHASE FREQ_CP[1] 2MHz 11639-039 FREQ_CP[0] SYNC DETECTOR 2 3 3 3 OUT OF PHASE Figure 45. Switching Clock Distribution External Synchronization Mode Selecting the Internal Clock Frequency If the SYNC pin is tied high or low, the device uses the internal clock. The internal oscillator generates a master clock at either 2.0 MHz or 1.5 MHz, as specified by the SEL_FSW bit in Register 18. The internal clock is active when EN is high. The master clock is divided down by half so that each dc-to-dc converter can select 1× or 1/2× the master clock frequency. The frequency of each channel is set using the FREQx bit (where x is 1 to 6) in Register 18. For example, if the master clock is set to 1.5 MHz, Channel 1 through Channel 6 can be configured to operate at 750 kHz or 1.5 MHz, but not at 1 MHz or 2 MHz. For the charge pump, the FREQ_CP bits set the switching frequency (see the Charge Pump Switching Frequency section). IN PHASE 1MHz OUT OF PHASE 11639-038 When an external clock is present at the SYNC pin, all dc-to-dc converters and the charge pump automatically use it as their master switching clock; the FREQx bit settings in Register 18 are ignored. When using external synchronization mode, ensure that the external clock is already stable before the EN signal is asserted to avoid unexpected behavior in the converters. When an external clock is used, the clock must operate within the specifications listed in Table 1. Figure 46. Switching Phase Relationships Any channel at 1 × fSW has the expected, set phase relationship to the master clock. However, when a channel operates at 1/2 × fSW, it always appears to be in phase with the master clock and with any in-phase channel at 1 × fSW. This relationship is illustrated by the lines labeled 1 and 2 in Figure 46; regardless of the phase setting, Line 1 or Line 2 is always aligned to the rising edge. To set a channel operating at 1/2 × fSW out of phase, the highest frequency channel must be set out of phase. Referring to the lines labeled 3 in Figure 46, the channel operating at 1/2 × fSW is now out of phase with the channel operating at 1 × fSW, regardless of the phase setting. CLKO Pin The clock output (CLKO) pin can output the internal switching clock used for Channel 1. The output is enabled by setting the EN_CLKO bit in Register 19 to 1. The CLKO output stays low when external clocking is used or when the EN_CLKO bit is set to 0. Rev. A | Page 28 of 64 Data Sheet ADP5080 SOFT START FUNCTION OUTPUT VVBATT + VVDR5 To provide controlled output voltage ramping on startup, the ADP5080 incorporates soft start control for each dc-to-dc converter. The ramp-up period to reach the target voltage can be set to 1 ms, 2 ms, 4 ms, or 8 ms using the SSx bit (where x is 1 to 6) in Register 2 or Register 3. The default soft start values are factory fuse programmed. It is not recommended that the ADP5080 be started up into a full load condition. BSTCP BSTx COUT 1µF VBATT PVINCP C+ CFLY 1µF CHANNEL 7: HIGH VOLTAGE LDO REGULATOR C– The ADP5080 integrates a high voltage LDO linear regulator, which allows input voltages up to 25 V (see Figure 47). The LDO regulator outputs one of four preset regulated voltages and is capable of providing up to 30 mA. SEQUENCER AGND 11639-041 PGND5 ADP5080 Figure 48. Charge Pump for BSTx Supply The charge pump requires a minimum VBATT voltage to start up. In some cases, the start-up threshold, which is 4 V typical, may be higher than the rising UVLO threshold. POWER-GOOD COMPARATOR PROGRAMMABLE SOFT START UP TO 25V VDR5 CLOCK VOLDO7 5V TO 12V VILDO7 CURRENT DETECTION If the BSTCP voltage drops approximately 2.5 V below the nominal value, the ADP5080 shuts down to prevent abnormal switching. An OVP or UVP fault is not indicated in this case. AGND Charge Pump Switching Frequency CURRENT LIMIT VREF DISCHARGE SWITCH 11639-040 UVP Figure 47. High Voltage LDO (Channel 7) Selecting the Output Voltage, Channel 7 The output voltage of Channel 7 is selected from one of the preset values (12 V, 9 V, 6 V, or 5 V) using the VID7 bits in Register 16. The default value is factory fuse programmed. Discharge Switch, Channel 7 Each channel incorporates a discharge switch. For Channel 7, the discharge switch is located at the VOLDO7 pin. The discharge switch can be turned on when Channel 7 is turned off, removing the residual charge of the external capacitor via an internal 1 kΩ resistor. The discharge switch can be enabled by setting the DSCG7_ON bit in Register 1. CHARGE PUMP The ADP5080 includes an integrated charge pump, which provides power to the high-side switching NMOS FET driver (see Figure 48). The charge pump raises the voltage applied to the PVINCP pin by the VDR5 pin voltage, making the voltage available at the BSTCP pin. In a typical application, the PVINCP pin is supplied by the battery (VBATT), and the VDR5 pin is supplied by VREG1 (5 V or 5.5 V). Thus, the output voltage at the BSTCP pin is VBATT + 5 V or 5.5 V, which is ideal for driving the high-side FET driver supply pin for each channel, BSTx. The internal clock source generates either 2.0 MHz or 1.5 MHz, as set by the SEL_FSW bit in Register 18. This master frequency is further divided by 1/2, 1/4, 1/8, or 1/16 by the FREQ_CP bits in Register 19 (see Table 53). If the master clock frequency is set to 2.0 MHz, the charge pump switching clock frequency can be 1.0 MHz, 500 kHz, 250 kHz, or 125 kHz. If the master frequency is set to 1.5 MHz, the charge pump switching clock frequency can be 750 kHz, 375 kHz, 188 kHz, or 94 kHz. Typically, a setting of 1/4 in 1.5 MHz operation or 1/8 in 2 MHz operation is recommended for the best efficiency. Lower settings may not provide enough boost voltage when all channels are operating at load. If an external clock is used, the charge pump frequency can be set to 1/4 or 1/8 of the external frequency using the FREQ_CP bits. Charge pump efficiency is slightly affected by the duty cycle of the external clock; a 50% duty cycle is the optimal point of operation. Capacitor Selection A 1 µF capacitor is used for each charge pump capacitor (CFLY and COUT; see Figure 48). The voltage rating of these capacitors must be adequate for the charge-up voltage, that is, the PVINCP pin voltage across CFLY and the VDR5 pin voltage across COUT. Protection Diode It is strongly recommended that a protection diode be mounted as shown in Figure 48 to avoid problems during power-up while the BSTCP voltage is charging. Use a Schottky diode that can withstand a 1 A peak current. Rev. A | Page 29 of 64 ADP5080 Data Sheet Using the Charge Pump as the Channel 7 Input Supply Note that Figure 50 shows the logical states of each channel; it does not show soft start and discharge ramps. The disable delay time for all channels can be increased to four times its configured value by setting the DIS_DLY_EXTEND bit in Register 35. The charge pump can also be used to generate a high voltage for the Channel 7 input. This configuration is enabled by adding the circuit shown in Figure 49 in parallel with the BSTx generating circuit shown in Figure 48. When all channels controlled by the sequencer are turned on, each channel can be manually turned off or on using the CHx_ON bit (x is 1 to 7) in Register 48. When the CHx_ON bit is used to turn a channel on or off, the enable state of the channel changes immediately, regardless of the settings of the EN_DLYx and DIS_DLYx bits. BSTCP 1µF C+ PVINCP 11639-042 VILDO7 VPVINCP + 2VVDR5 When using the sequencer mode, note the following: Figure 49. Charge Pump Used as a High Voltage Supply for Channel 7 • The circuit shown in Figure 49 generates VILDO7 with the voltage VPVINCP + 2 × VVDR5. In a typical application, this voltage is equivalent to VVBATT + 10 V to 11 V (PVINCP = VBATT; VDR5 = VREG1 = 5.5 V or 5 V). ENABLING AND DISABLING THE OUTPUT CHANNELS • Each channel (Channel 1 to Channel 7) can be turned on and off using the sequencer mode or the manual mode. A channel configured for sequencer mode is automatically turned on and off by assertion and deassertion of the EN pin, with individually programmed delay times. A channel configured for manual mode does not automatically start when EN goes high, but can be turned on or off via I2C control, as required. A channel that is controlled by the sequencer cannot be turned off manually until after the sequencer turns on all the channels that it controls and the soft start period has ended. This ready state can be identified by reading the PWRGx bits (x is 1 to 7) in Register 24. After the EN pin is asserted, writing to the VIDx bits is forbidden while the internal sequencer is in operation to prevent unexpected behavior. The internal sequencer is in operation from the assertion of the EN pin until the PWRGx bits in Register 24 go high. Manual Mode When the MODE_ENx bit (x is 1 to 7) is cleared in Register 29, the specified channel turns on and off under I2C control. All channels that are not configured for sequencer mode can be manually turned on or off using the CHx_ON bits (x is 1 to 7) in the PCTRL register (Register 48). Writing 1 to the CHx_ON bit enables the channel only when the EN pin is logic high. Sequencer Mode When the MODE_ENx bit (x is 1 to 7) is set in Register 29, the specified channel turns on and off under the control of the internal sequencer, which is triggered by the EN pin (see Figure 50). When the EN pin is taken low, all channels configured for manual mode turn off immediately, and all the CHx_ON bits are reset to 0. While the EN pin is low, any data written to or read from the CHx_ON bits is not valid. When the EN pin goes high, each channel controlled by the sequencer begins a soft start after the delay time specified by the EN_DLYx bits (see Table 23, Table 25, Table 27, and Table 29). Similarly, when the EN pin goes low, the channel turns off after the delay time specified by the DIS_DLYx bits (see Table 31, Table 33, Table 35, and Table 37). EN OFF CHANNEL 2 OFF CHANNEL 3 OFF CHANNEL 4 OFF CHANNEL 5 OFF CHANNEL 6 OFF CHANNEL 7 OFF tEN_DLY2 tEN_DLY3 ON ON ON tEN_DLY4 ON tEN_DLY5 ON tEN_DLY6 tEN_DLY7 ON ON tDIS_DLY1 tDIS_DLY2 tDIS_DLY3 tDIS_DLY4 tDIS_DLY5 tDIS_DLY6 tDIS_DLY7 Figure 50. Example Power-Up/Power-Down Sequence Using Sequencer Mode Rev. A | Page 30 of 64 11639-043 tEN_DLY1 CHANNEL 1 Data Sheet ADP5080 EN Function POWER-GOOD FUNCTION The EN pin has an internal pull-down resistor that holds the ADP5080 in standby mode until the pin is actively pulled high. The EN function does not take effect until the device is ready for operation, that is, until all the following conditions are met: The power-good status of each channel (PWRGx bit) can be read back from the PWRG register (Register 24). A value of 1 for the PWRGx bit indicates that the regulated output voltage of Channel x is within 85% to 125% of its nominal value. When the regulated output voltage of a channel falls below this level, the PWRGx bit is set to 0. As shown in Figure 51, hysteresis is applied to both the upper and lower boundaries to minimize power-good chattering. VOUT 125% 123% CHx OUTPUT 85% 82% If any of these conditions are not met during operation, the ADP5080 shuts down, as described in the UVLO and POR section. PWRGx (x = 1 TO 7) 11639-044     VBATT pin voltage (VUVLO (BATT)) is above 3.3 V. VREG1 pin voltage is within the specified range. VREG2 pin voltage (VUVLO (POR)) is within the specified range. Device is not in thermal shutdown. Internal oscillator is stable (typically 250 μs). PVIN1 pin voltage (VUVLO (R)) is above 3.7 V. VDR12 pin voltage is above 2.95 V. EN34 Function Figure 51. Power-Good Status Bit The EN34 pin allows Channel 3, Channel 4, or both channels to be independently enabled and disabled using the EN34 pin. This functionality can be enabled on either or both channels using the DIS_EN34_CHx bits (x is 3 or 4) in Register 35. When the DIS_EN34_CHx bit is set low, the channel is not turned on until both the EN and EN34 pins are high. If Channel 3 or Channel 4 is in sequencer mode, EN34 must be high before EN goes high to maintain the enable delay timing on the channels (see the Sequencer Mode section). If EN is high when the EN34 pin is taken high, Channel 3 or Channel 4 is immediately enabled or disabled, regardless of whether the channel is configured for manual mode or sequencer mode. FAULT FUNCTION The FAULT pin is an open-drain output that indicates the logical OR status of the PWRGx bits for all channels. When any PWRGx bit = 0, the FAULT pin goes low. As shown in Figure 52, FAULT has approximately 70 ms of blanking time after EN is asserted to allow for the enable delay and soft start times. After the blanking period, a PWRGx low bit causes FAULT to go low immediately. FAULT remains low until the EN pin is toggled or power is cycled. If an OVP or UVP condition at startup forces a shutdown before the FAULT blanking period ends, FAULT does not go low. VBATT When the DIS_EN34_CHx bit is set high, Channel 3 or Channel 4 is enabled and disabled in the same way as all the other channels in the device, and the EN34 pin has no effect on the operation of the channel. EN ΣPWRGx Regardless of the state of the DIS_EN34_CHx bits, disabling Channel 3 and Channel 4 does not cause FAULT to go low (see the Fault Function section). This means that the power-good flags for Channel 3 and Channel 4 do not need to be masked. FAULT goes low only when Channel 3 or Channel 4 is enabled using the CH3_ON or CH4_ON bit and the PWRG3 or PWRG4 bit subsequently goes low. TIMEOUT COUNTER 70ms RESET RESET FAULT Figure 52. FAULT Function If a channel is not enabled manually or via the sequencer, the PWRGx bit remains low. This forces FAULT low unless the channel is masked by the MASK_PWRGx bit in Register 25. This does not apply to Channel 3 and Channel 4, as described in the EN34 Function section. Rev. A | Page 31 of 64 11639-045    ADP5080 Data Sheet EN MASK_PWRG1 PWRG1 MASK_PWRG2 PWRG2 PWRG3 MASK_PWRG3 TIMEOUT LOGIC CH3_ON FAULT MASK_PWRG4 1 PWRG4 1 1 0 CH4_ON MASK_PWRG5 Q D 0 0 PWRG5 R MASK_PWRG6 VBATT_UVLO 11639-046 PWRG6 MASK_PWRG7 PWRG7 Figure 53. Fault Function Logic Diagram Table 12. Channel 5 Standalone Undervoltage Detection Option 1 Output All channels shut down All channels shut down All channels shut down All channels are operational All channels shut down All channels shut down Channel 5 shuts down; all other channels are operational All channels are operational UNDERVOLTAGE PROTECTION (UVP) VOUT The ADP5080 incorporates undervoltage protection (UVP) on Channel 1 to Channel 7. When the output of any channel falls below 65% of the specified voltage, UVP shuts down all seven channels by internally resetting the CHx_ON bits in Register 48. Channel 5 can be configured for standalone undervoltage protection (see the Channel 5 Standalone Undervoltage Detection Option section). 65% SHUTDOWN TIME Δt < UV_DLY Δt = UV_DLY CHx_ON (x = 1 TO 7) UVP Detection Delay Undervoltage detection includes a debounce delay, which is configured in Register 23 (see Table 57). The undervoltage condition is recognized only after it continues for the period specified by the UV_DLY bits in Register 23 (see Figure 54). Setting the UV_DLY bits to 11 disables UVP. 11639-047 SEL_IND_UV5 Bit 0 Undervoltage Detected Any Channel Other Than Channel 5 Channel 5 Yes Yes Yes No No Yes No No Yes Yes Yes No No Yes No No UVx (x = 1 TO 7) Figure 54. Undervoltage Detection Delay Channel 5 Standalone Undervoltage Detection Option If desired, undervoltage protection on Channel 5 can be isolated from UVP on all the other channels. When the SEL_IND_UV5 bit is set high in Register 34, an undervoltage condition on Channel 5 causes only Channel 5 to be shut down (see Table 12). If this option is selected, the UV_DLY5 bits in Register 34 can be used to set a UVP detection delay for Channel 5 only. Rev. A | Page 32 of 64 Data Sheet ADP5080 Recovering from UVP Recovering from OVP After the cause of the undervoltage condition is removed, the outputs can be recovered by toggling EN from low to high. If standalone Channel 5 undervoltage shutdown is enabled (by setting the SEL_IND_UV5 bit in Register 34), Channel 5 can be recovered by setting the CH5_ON bit in Register 48 to 1. After the cause of the overvoltage condition is removed, the outputs can be recovered by toggling EN from low to high. The overvoltage status of a channel is stored in the OVPST register (Register 27) after shutdown and can be read back from the OVx bit in Register 27. The OVx bit is cleared by writing a 1 to it. The undervoltage status of a channel is stored in the UVPST register (Register 26) after shutdown and can be read back from the UVx bit in Register 26. The UVx bit is cleared by writing a 1 to it. SHUTDOWN VOUT 125% OVERVOLTAGE PROTECTION (OVP) The ADP5080 incorporates overvoltage protection (OVP) on Channel 1 to Channel 6. When the output of any of these channels rises above 125% of the specified voltage, OVP shuts down all six channels by internally resetting the CHx_ON bits in Register 48. TIME Δt < OV_DLY Δt = OV_DLY CHx_ON (x = 1 TO 6) Overvoltage detection includes a debounce delay, which is configured in Register 23 (see Table 57). The overvoltage condition is recognized only after it continues for the period specified by the OV_DLY bits in Register 23 (see Figure 55). Setting the OV_DLY bits to 11 disables OVP. Rev. A | Page 33 of 64 11639-048 OVP Detection Delay OVx (x = 1 TO 6) Figure 55. Overvoltage Detection Delay ADP5080 Data Sheet APPLICATIONS INFORMATION This section provides component and PCB layout guidelines to ensure optimal device performance, efficiency, stability, and minimal switching noise and crosstalk. COMPONENT SELECTION FOR THE BUCK AND BUCK BOOST REGULATORS Setting the Output Voltage (Adjustable Mode Channels) Channel 3, Channel 4, and Channel 6 can be configured for an adjustable output voltage. Table 9 provides the adjustable output voltage range for these channels. When any of these channels is configured for adjustable mode, connect a resistor divider to the FBx pin between VOUT and GND, as shown in Figure 56. VOUT Note that ripple current varies with input voltage. The typical input voltage can be used to determine the inductor value. However, to avoid inductor saturation and current limit, also calculate the inductor value with the worst-case input voltage (VIN max). The maximum rated current of the selected inductor (both rms current and saturation current) must be greater than the peak inductor current (IPEAK) at the maximum load current. If the rating of the inductor is not sufficient, the inductor may saturate due to inductor value degradation, causing it to reach the current limit, even in a lower load condition than expected. The peak current can be estimated using Equation 3. IPEAK = ILOAD + (IRIPPLE/2) RFB_TOP If the 30% ripple guideline is followed, typical peak current is simplified as follows: FBx IPEAK = (ILOAD + 0.15) × ILOAD = 1.15 × ILOAD 11639-052 RFB_BOT The resistor values can be calculated as follows, where 0.8 V is the typical FB voltage, and 20 kΩ is a good typical value for RFB_BOT. (V OUT (4) Another important specification to consider is the parasitic series resistance in the inductor: dc resistance (DCR). A larger DCR decreases efficiency, but a larger size inductor typically has lower DCR. Therefore, the trade-off between available space on the PCB and device performance must be considered carefully. Figure 56. Feedback Resistors for Adjustable Output R FB _ TOP = (3) − 0.8 V ) × R FB _ BOT 0. 8 V Note that changing the output voltage often requires a change to the inductor (L) and output capacitor (COUT) values. After the VOUT value is selected, calculate and test the L and COUT values (see the Selecting the Inductor section and the Selecting the Output Capacitor section). Selecting the Inductor Equation 1 to Equation 4 apply to the buck regulators. Although Channel 6 is a buck boost regulator, the inductor value can be determined using the buck regulator mode of operation given that the available step-up ratio in boost mode is relatively small (4 V at the PVIN6 pin to 5.5 V at the VOUT6 pin) compared to the available step-down ratio. Therefore, an inductor value selected for buck regulator mode typically works equally well in boost regulator mode. (1) Table 13 lists recommended inductor values for a range of voltages and frequencies. The values provided are based on a wide operating range and assume the maximum load current for each channel. In the actual application, larger or smaller values may be more appropriate. In general, the inductor value can be increased or decreased by one standard value from the recommended 30% ripple guideline. A larger inductance provides higher efficiency, whereas smaller values results in better transient response and a smaller footprint. Note that inductor values much smaller or larger than the ones recommended in Table 13 may cause control loop instability. In general, the recommended ripple current is 30% of the maximum load current. Therefore, Equation 1 can be rewritten as follows: It is also important to note that because the current-limit protection monitors peak or valley current, the selected inductance affects the load current level at which current limit is triggered. The required inductor value can be determined by the input and output voltages, the switching frequency, and the ripple current, as shown in Equation 1. L= VIN − VOUT I RIPPLE × 1 f SW × VOUT VIN where: L is the inductor value. fSW is the switching frequency. IRIPPLE is a peak-to-peak value for the ripple current. L= VIN − VOUT 0.3 × I LOAD × 1 f SW × VOUT VIN (2) Rev. A | Page 34 of 64 Data Sheet ADP5080 Table 13. Suggested Inductors Channel 1 VOUT (V)