ADRF6703ACPZ-R7

1550 MHz to 2650 MHz Quadrature Modulator with 2100 MHz to 2600 MHz Frac-N PLL and Integrated VCO ADRF6703 Data Sheet The integrated fractional-N PLL/synthesizer generates a 2× fLO input to the IQ modulator. The phase detector together with an external loop filter is used to control the VCO output. The VCO output is applied to a quadrature divider. To reduce spurious components, a sigma-delta (Σ-Δ) modulator controls the programmable PLL divider. FEATURES IQ modulator with integrated fractional-N PLL RF output frequency range: 1550 MHz to 2650 MHz Internal LO frequency range: 2100 MHz to 2600 MHz Output P1dB: 14.2 dBm @ 2140 MHz Output IP3: 33.2 dBm @ 2140 MHz Noise floor: −159.6 dBm/Hz @ 2140 MHz Baseband bandwidth: 750 MHz (3 dB) SPI serial interface for PLL programming Integrated LDOs and LO buffer Power supply: 5 V/240 mA 40-lead 6 mm × 6 mm LFCSP The IQ modulator has wideband differential I and Q inputs, which support baseband as well as complex IF architectures. The single-ended modulator output is designed to drive a 50 Ω load impedance and can be disabled. The ADRF6703 is fabricated using an advanced silicongermanium BiCMOS process. It is available in a 40-lead, exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP package. Performance is specified from −40°C to +85°C. A lead-free evaluation board is available. Table 1. APPLICATIONS Cellular communications systems GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA, LTE Broadband wireless access systems Satellite modems Part No. ADRF6701 GENERAL DESCRIPTION The ADRF6703 provides a quadrature modulator and synthesizer solution within a small 6 mm × 6 mm footprint while requiring minimal external components. Internal LO Range 750 MHz 1150 MHz 1550 MHz 2150 MHz 2100 MHz 2600 MHz 2500 MHz 290 MHz ADRF6702 ADRF6703 The ADRF6703 is designed for RF outputs from 1550 MHz to 2650 MHz. The low phase noise VCO and high performance quadrature modulator make the ADRF6703 suitable for next generation communication systems requiring high signal dynamic range and linearity. The integration of the IQ modulator, PLL, and VCO provides for significant board savings and reduces the BOM and design complexity. ADRF6704 ±3 dB RFOUT Balun Range 400 MHz 1250 MHz 1200 MHz 2400 MHz 1550 MHz 2650 MHz 2050 MHz 3000 MHz FUNCTIONAL BLOCK DIAGRAM VCC7 VCC6 VCC5 VCC4 VCC3 VCC2 VCC1 34 29 27 22 17 10 1 ADRF6703 LOSEL 36 LON 37 LOP 38 BUFFER CLK 13 SPI INTERFACE LE 14 MODULUS 2:1 MUX INTEGER REG THIRD-ORDER FRACTIONAL INTERPOLATOR ×2 REFIN 6 ÷2 N COUNTER 21 TO 123 MUX TEMP SENSOR ÷4 MUXOUT 8 4 7 11 15 20 21 23 25 28 30 31 35 GND ÷2 0/90 CHARGE PUMP 250µA, 500µA (DEFAULT), 750µA, 1000µA – PHASE + FREQUENCY DETECTOR 24 5 NC RSET NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. DECL2 2 DECL1 18 QP VCO CORE PRESCALER ÷2 9 19 QN 32 IN 33 IP 3 39 16 26 CP VTUNE ENOP RFOUT 08570-001 FRACTION REG DATA 12 40 DECL3 DIVIDER ÷2 BUFFER Figure 1. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. ADRF6703 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Device Programming and Register Sequencing..................... 19 Applications ....................................................................................... 1 Register Summary .......................................................................... 20 General Description ......................................................................... 1 Register Description....................................................................... 21 Functional Block Diagram .............................................................. 1 Register 0—Integer Divide Control (Default: 0x0001C0) .... 21 Revision History ............................................................................... 2 Register 1—Modulus Divide Control (Default: 0x003001) .. 22 Specifications..................................................................................... 3 Register 2—Fractional Divide Control (Default: 0x001802) 22 Timing Characteristics ................................................................ 6 Register 3—Σ-Δ Modulator Dither Control (Default: 0x10000B) .................................................................................... 23 Absolute Maximum Ratings............................................................ 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 16 Register 4—PLL Charge Pump, PFD, and Reference Path Control (Default: 0x0AA7E4)................................................... 24 Register 5—LO Path and Modulator Control (Default: 0x0000D5) ................................................................................... 26 PLL + VCO .................................................................................. 16 Register 6—VCO Control and VCO Enable (Default: 0x1E2106) .................................................................................... 27 Basic Connections for Operation ............................................. 16 Register 7—External VCO Enable ........................................... 27 External LO ................................................................................. 16 Characterization Setups ................................................................. 28 Loop Filter ................................................................................... 17 Evaluation Board ............................................................................ 30 DAC-to-IQ Modulator Interfacing .......................................... 18 Evaluation Board Control Software ......................................... 30 Adding a Swing-Limiting Resistor ........................................... 18 Outline Dimensions ....................................................................... 35 IQ Filtering .................................................................................. 19 Ordering Guide .......................................................................... 35 Baseband Bandwidth ................................................................. 19 REVISION HISTORY 10/11—Rev. A to Rev. B Changes to Table 1 ............................................................................ 1 6/11—Rev. 0 to Rev. A Changes to Figure 1 .......................................................................... 1 Changes to Figure 5 ........................................................................ 10 Changes to Figure 17 and Figure 18 ............................................. 12 6/11—Revision 0: Initial Version Rev. B | Page 2 of 36 Data Sheet ADRF6703 SPECIFICATIONS VS = 5 V; TA = 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q frequency (fBB) = 1 MHz; fPFD = 38.4 MHz; fREF = 153.6 MHz at +4 dBm Re:50 Ω (1 V p-p); 130 kHz loop filter, unless otherwise noted. Table 2. Parameter Test Conditions/Comments Min OPERATING FREQUENCY RANGE IQ modulator (±3 dB RF output range) PLL LO range RFOUT pin Baseband VIQ = 1 V p-p differential RF output divided by baseband input voltage 1550 2100 RF OUTPUT = 2140 MHz Nominal Output Power IQ Modulator Voltage Gain OP1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 Noise Floor POUT − P (fLO ± (2 × fBB)) POUT − P (fLO ± (3 × fBB)) f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset RF OUTPUT = 2300 MHz Nominal Output Power IQ Modulator Voltage Gain OP1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 Noise Floor RFOUT pin Baseband VIQ = 1 V p-p differential RF output divided by baseband input voltage RF OUTPUT = 2600 MHz Nominal Output Power IQ Modulator Voltage Gain OP1dB Carrier Feedthrough Sideband Suppression Quadrature Error I/Q Amplitude Balance Second Harmonic Third Harmonic Output IP2 Output IP3 Noise Floor SYNTHESIZER SPECIFICATIONS Internal LO Range Figure of Merit (FOM) 1 RFOUT pin Baseband VIQ = 1 V p-p differential RF output divided by baseband input voltage POUT − P (fLO ± (2 × fBB)) POUT − P (fLO ± (3 × fBB)) f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset POUT − P (fLO ± (2 × fBB)) POUT − P (fLO ± (3 × fBB)) f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone f1BB = 3.5 MHz, f2BB = 4.5 MHz, POUT ≈ −2 dBm per tone) I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset Synthesizer specifications referenced to the modulator output Typ Unit 2650 2600 MHz MHz 4.95 0.95 14.2 −44.1 −52.3 +0.0/−0.6 0.04 −63.0 −52.0 70.1 33.2 −159.6 dBm dB dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz 4.48 0.48 13.5 −46.0 −44.0 −0.25/−0.98 0.06 −67.0 −53.0 68.6 32.7 −159.7 dBm dB dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz 2.75 −1.25 11.8 −46.8 −35.3 0.56/2.3 0.06 −63.0 −51.0 62.0 29.2 −161.7 dBm dB dBm dBm dBc Degrees dB dBc dBc dBm dBm dBm/Hz 2100 2600 −222.0 Rev. B | Page 3 of 36 Max MHz dBc/Hz/Hz ADRF6703 Data Sheet Parameter Test Conditions/Comments REFERENCE CHARACTERISTICS REFIN Input Frequency REFIN Input Capacitance Phase Detector Frequency MUXOUT Output Level REFIN, MUXOUT pins Min 12 PHASE NOISE (FREQUENCY = 2140 MHz, fPFD = 38.4 MHz) Integrated Phase Noise Reference Spurs PHASE NOISE (FREQUENCY = Max Unit 160 MHz pF MHz V V % 4 20 Low (lock detect output selected) High (lock detect output selected) 40 0.25 2.7 MUXOUT Duty Cycle CHARGE PUMP Charge Pump Current Output Compliance Range Typ 50 Programmable to 250 µA, 500 µA, 750 µA, 1000 µA 500 1 2.8 µA V Closed loop operation (see Figure 35 for loop filter design) 10 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 1 kHz to 10 MHz integration bandwidth fPFD/2 fPFD fPFD × 2 fPFD × 3 fPFD × 4 Closed loop operation (see Figure 35 for loop filter design) −105.3 −103.1 −127.9 −149.7 0.29 −110 −102.0 −87.2 −90.4 −98.4 dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms dBc dBc dBc dBc dBc 10 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 1 kHz to 10 MHz integration bandwidth fPFD/2 fPFD fPFD × 2 fPFD × 3 fPFD × 4 Closed loop operation (see Figure 35 for loop filter design) −103.5 −102.2 −128.4 −149.5 0.295 −110.7 −102.3 −85.5 −92.4 −101.1 dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms dBc dBc dBc dBc dBc 10 kHz offset 100 kHz offset 1 MHz offset 10 MHz offset 1 kHz to 10 MHz integration bandwidth fPFD/2 fPFD fPFD × 2 fPFD × 3 fPFD × 4 Measured at RFOUT, frequency = 2140 MHz Second harmonic Third harmonic LOP, LON Divide by 2 circuit in LO path enabled Divide by 2 circuit in LO path disabled 2× LO or 1× LO mode, into a 50 Ω load, LO buffer enabled Externally applied 2× LO, PLL disabled Externally applied 2× LO, PLL disabled −98.8 −100.2 −129.2 −151.0 0.37 −110.6 −106.5 −88.6 −92.4 −102.5 dBc/Hz dBc/Hz dBc/Hz dBc/Hz °rms dBc dBc dBc dBc dBc −41 −65 dBc dBc 2300 MHz, fPFD = 38.4 MHz) Integrated Phase Noise Reference Spurs PHASE NOISE (FREQUENCY = 2600 MHz, fPFD = 38.4 MHz) Integrated Phase Noise Reference Spurs RF OUTPUT HARMONICS LO INPUT/OUTPUT Output Frequency Range LO Output Level at 2140 MHz LO Input Level LO Input Impedance Rev. B | Page 4 of 36 2100 4200 2600 5200 0.1 0 50 MHz MHz dBm dBm Ω Data Sheet ADRF6703 Parameter Test Conditions/Comments BASEBAND INPUTS I and Q Input DC Bias Level Bandwidth IP, IN, QP, QN pins Differential Input Impedance Differential Input Capacitance LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN TEMPERATURE SENSOR Output Voltage Temperature Coefficient POWER SUPPLIES Voltage Range Supply Current 1 2 Min Typ Max Unit 400 500 600 mV POUT ≈ −7 dBm, RF flatness of IQ modulator output calibrated out 0.5 dB 3 dB Frequency = 1 MHz 2 Frequency = 1 MHz2 CLK, DATA, LE, ENOP, LOSEL 350 750 945 1 1.4 0 MHz MHz Ω pF 3.3 0.7 0.1 5 VPTAT voltage measured at MUXOUT TA = 25°C, RL ≥10 kΩ (LO buffer disabled) TA = −40°C to +85°C, RL ≥10 kΩ VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7 1.624 3.65 4.75 Normal Tx mode (PLL and IQMOD enabled, LO buffer disabled) Tx mode using external LO input (internal VCO/PLL disabled) Tx mode with LO buffer enabled Power-down mode 5 240 134 290 22 V V µA pF V mV/°C 5.25 V mA mA mA µA The figure of merit (FOM) is computed as phase noise (dBc/Hz) – 10log10(fPFD) – 20log10(fLO/fPFD). The FOM was measured across the full LO range, with fREF = 80 MHz, fREF power = 10 dBm (500 V/μs slew rate) with a 40 MHz fPFD. The FOM was computed at 50 kHz offset. Refer to Figure 40 for plot of input impedance over frequency. Rev. B | Page 5 of 36 ADRF6703 Data Sheet TIMING CHARACTERISTICS Table 3. Parameter t1 t2 t3 t4 t5 t6 t7 Limit 20 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments LE to CLK setup time DATA to CLK setup time DATA to CLK hold time CLK high duration CLK low duration CLK to LE setup time LE pulse width t4 t5 CLK t3 t2 DATA DB23 (MSB) DB22 DB2 (CONTROL BIT C3) DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t7 t1 08570-002 t6 LE Figure 2. Timing Diagram Rev. B | Page 6 of 36 Data Sheet ADRF6703 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage (VCC1 to VCC7) Digital I/O, CLK, DATA, LE LOP, LON IP, IN, QP, QN REFIN θJA (Exposed Paddle Soldered Down)1 Maximum Junction Temperature Operating Temperature Range Storage Temperature Range 1 Rating 5.5 V −0.3 V to +3.6 V 18 dBm −0.5 V to +1.5 V −0.3 V to +3.6 V 35°C/W 150°C −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Per JDEC standard JESD 51-2. Rev. B | Page 7 of 36 ADRF6703 Data Sheet 40 39 38 37 36 35 34 33 32 31 DECL3 VTUNE LOP LON LOSEL GND VCC7 IP IN GND PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR ADRF6703 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 GND VCC6 GND VCC5 RFOUT GND NC GND VCC4 GND NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. 2. THE EXPOSED PADDLE SHOULD BE SOLDERED TO A LOW IMPEDANCE GROUND PLANE. 08570-003 GND DATA CLK LE GND ENOP VCC3 QP QN GND 11 12 13 14 15 16 17 18 19 20 VCC1 1 DECL1 2 CP 3 GND 4 RSET 5 REFIN 6 GND 7 MUXOUT 8 DECL2 9 VCC2 10 Figure 3. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1, 10, 17, 22, 27, 29, 34 2 Mnemonic VCC1, VCC2, VCC3, VCC4, VCC5, VCC6, VCC7 DECL1 3 CP 4, 7, 11, 15, 20, 21, 23, 25, 28, 30, 31, 35 24 5 GND NC RSET Description Power Supply Pins. The power supply voltage range is 4.75 V to 5.25 V. Drive all of these pins from the same power supply voltage. Decouple each pin with 100 pF and 0.1 µF capacitors located close to the pin. Decoupling Node for Internal 3.3 V LDO. Decouple this pin with 100 pF and 0.1 µF capacitors located close to the pin. Charge Pump Output Pin. Connect VTUNE to this pin through the loop filter. If an external VCO is being used, connect the output of the loop filter to the VCO’s voltage control pin. The PLL control loop should then be closed by routing the VCO’s frequency output back into the ADRF6703 through the LON and LOP pins. Ground. Connect these pins to a low impedance ground plane. Do not connect to this pin. Charge Pump Current. The nominal charge pump current can be set to 250 µA, 500 µA, 750 µA, or 1000 µA using DB10 and DB11 of Register 4 and by setting DB18 to 0 (CP reference source). In this mode, no external RSET is required. If DB18 is set to 1, the four nominal charge pump currents (INOMINAL) can be externally tweaked according to the following equation:  217.4 × I CP R SET =   I NOMINAL 6 REFIN 8 MUXOUT 9 DECL2 12 DATA   − 37.8 Ω   where ICP is the base charge pump current in microamps. For further details on the charge pump current, see the Register 4—PLL Charge Pump, PFD, and Reference Path Control section. Reference Input. The nominal input level is 1 V p-p. Input range is 12 MHz to 160 MHz. This pin has high input impedance and should be ac-coupled. If REFIN is being driven by laboratory test equipment, the pin should be externally terminated with a 50 Ω resistor (place the ac-coupling capacitor between the pin and the resistor). When driven from an 50 Ω RF signal generator, the recommended input level is 4 dBm. Multiplexer Output. This output allows a digital lock detect signal, a voltage proportional to absolute temperature (VPTAT), or a buffered, frequency-scaled reference signal to be accessed externally. The output is selected by programming DB21 to DB23 in Register 4. Decoupling Node for 2.5 V LDO. Connect 100 pF, 0.1 µF, and 10 µF capacitors between this pin and ground. Serial Data Input. The serial data input is loaded MSB first with the three LSBs being the control bits. Rev. B | Page 8 of 36 Data Sheet ADRF6703 Pin No. 13 Mnemonic CLK 14 LE 16 18, 19, 32, 33 ENOP QP, QN, IN, IP 26 RFOUT 36 LOSEL 37, 38 LON, LOP 39 VTUNE 40 DECL3 EP Description Serial Clock Input. This serial clock input is used to clock in the serial data to the registers. The data is latched into the 24-bit shift register on the CLK rising edge. Maximum clock frequency is 20 MHz. Latch Enable. When the LE input pin goes high, the data stored in the shift registers is loaded into one of the six registers, the relevant latch being selected by the first three control bits of the 24-bit word. Modulator Output Enable/Disable. See Table 6. Modulator Baseband Inputs. Differential in-phase and quadrature baseband inputs. These inputs should be dc-biased to 0.5 V. RF Output. Single-ended, 50 Ω internally biased RF output. RFOUT must be ac-coupled to its load. LO Select. This digital input pin determines whether the LOP and LON pins operate as inputs or outputs. This pin should not be left floating. LOP and LON become inputs if the LOSEL pin is set low and the LDRV bit of Register 5 is set low. External LO drive must be a 2× LO. In addition to setting LOSEL and LDRV low and providing an external 2× LO, the LXL bit of Register 5 (DB4) must be set to 1 to direct the external LO to the IQ modulator. LON and LOP become outputs when LOSEL is high or if the LDRV bit of Register 5 (DB3) is set to 1. A 1× LO or 2× LO output can be selected by setting the LDIV bit of Register 5 (DB5) to 1 or 0 respectively (see Table 7). Local Oscillator Input/Output. The internally generated 1× LO or 2× LO is available on these pins. When internal LO generation is disabled, an external 1× LO or 2× LO can be applied to these pins. VCO Control Voltage Input. This pin is driven by the output of the loop filter. Nominal input voltage range on this pin is 1.3 V to 2.5 V. If the external VCO mode is activated, this pin can be left open. Decoupling Node for VCO LDO. Connect a 100 pF capacitor and a 10 µF capacitor between this pin and ground. Exposed Paddle. The exposed paddle should be soldered to a low impedance ground plane. Table 6. Enabling RFOUT ENOP X1 0 1 1 Register 5 Bit DB6 0 X1 1 RFOUT Disabled Disabled Enabled X = don’t care. Table 7. LO Port Configuration 1, 2 LON/LOP Function LOSEL Register 5 Bit DB5(LDIV) Register 5 Bit DB4(LXL) Register 5 Bit DB3 (LDRV) Input (2× LO) Output (Disabled) Output (1× LO) Output (1× LO) Output (1× LO) Output (2× LO) Output (2× LO) Output (2× LO) 0 0 0 1 1 0 1 1 X X 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 1 2 X = don’t care. LOSEL should not be left floating. Rev. B | Page 9 of 36 ADRF6703 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS VS = 5 V; TA = 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q frequency (fBB) = 1 MHz; fPFD = 38.4 MHz; fREF = 153.6 MHz at +4 dBm Re:50 Ω (1 V p-p); 130 kHz loop filter, unless otherwise noted. 10 TA = –40°C TA = +25°C TA = +85°C 9 8 SSB OUTPUT POWER (dBm) 7 6 5 4 3 7 6 5 4 3 2 1 1 0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 08570-104 2 LO FREQUENCY (MHz) Figure 4. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown Figure 7. Single Sideband (SSB) Output Power (POUT) vs. LO Frequency (fLO) and Power Supply; Multiple Devices Shown 20 VS = 5.25V VS = 5.00V VS = 4.75V VS = 5.25V VS = 5.00V VS = 4.75V 19 1dB OUTPUT COMPRESSION (dBm) 18 17 16 15 14 13 12 18 17 16 15 14 13 12 11 10 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 10 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) 08570-105 11 LO FREQUENCY (MHz) Figure 5. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown 0 Figure 8. SSB Output 1dB Compression Point (OP1dB) vs. LO Frequency (fLO) and Power Supply 20 0 16 –10 CARRIER FEEDTHROUGH (dBm) 12 8 –40 4 –50 0 –60 –4 –70 –8 SECOND-ORDER DISTORTION (dBc) –80 –90 –100 0.1 SECOND-ORDER DISTORTION (dBc), THIRD-ORDER DISTORTION (dBc), CARRIER FEEDTHROUGH (dBm), SIDEBAND SUPPRESSION (dBc) –30 SSB OUTPUT POWER (dBm) –12 SIDEBAND SUPPRESSION (dBc) 1 BASEBAND INPUT VOLTAGE (V p-p Differential) –20 –30 –20 10 Figure 6. SSB Output Power, Second- and Third-Order Distortion, Carrier Feedthrough and Sideband Suppression vs. Baseband Differential Input Voltage (fOUT = 2140 MHz) SSB OUTPUT POWER (dBm) CARRIER FEEDTHROUGH (dBm) –40 10 5 0 –50 –5 –60 –70 SECOND-ORDER DISTORTION (dBc) –10 –80 –90 –16 –100 0.1 08570-106 –20 SSB OUTPUT POWER (dBm) SECOND-ORDER DISTORTION (dBc), THIRD-ORDER DISTORTION (dBc), CARRIER FEEDTHROUGH (dBm), SIDEBAND SUPPRESSION (dBc) –10 15 THIRD-ORDER DISTORTION (dBc) THIRD-ORDER DISTORTION (dBc) SIDEBAND SUPPRESSION (dBc) 1 BASEBAND INPUT VOLTAGE (V p-p Differential) –15 –20 10 Figure 9. SSB Output Power, Second- and Third-Order Distortion, Carrier Feedthrough and Sideband Suppression vs. Baseband Differential Input Voltage (fOUT = 2600 MHz) Rev. B | Page 10 of 36 08570-109 19 08570-108 20 SSB OUTPUT POWER (dBm) SSB OUTPUT POWER (dBm) 8 LO FREQUENCY (MHz) 1dB OUTPUT COMPRESSION (dBm) VS = 5.25V VS = 5.00V VS = 4.75V 9 08570-107 10 Data Sheet ADRF6703 0 –20 –30 –40 –50 –60 –20 –30 –40 –50 –60 –70 –70 –80 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 – 80 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) Figure 10. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown LO FREQUENCY (MHz) Figure 13. Carrier Feedthrough vs. LO Frequency (fLO) and Temperature After Nulling at 25°C; Multiple Devices Shown 0 UNDESIRED SIDEBAND NULLED (dBc) –20 –30 –40 –50 –60 –70 –90 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) Figure 11. Sideband Suppression vs. LO Frequency (fLO) and Temperature; Multiple Devices Shown –20 –30 –40 –50 –60 –70 –80 LO FREQUENCY (MHz) Figure 14. Sideband Suppression vs. LO Frequency (fLO) and Temperature After Nulling at 25°C; Multiple Devices Shown 80 –20 75 –25 THIRD-ORDER DISTORTION (dBc), SECOND-ORDER DISTORTION (dBc) 70 65 OIP2 60 55 50 45 OIP3 40 35 30 25 15 –30 –35 –40 –45 LO FREQUENCY (MHz) Figure 12. OIP3 and OIP2 vs. LO Frequency (fLO) and Temperature (POUT ≈ −2 dBm per Tone); Multiple Devices Shown TA = –40°C TA = +25°C TA = +85°C THIRD-ORDER DISTORTION –50 –55 –60 –65 –70 –75 10 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 SECOND-ORDER DISTORTION –80 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 08570-112 20 TA = –40°C TA = +25°C TA = +85°C TA = –40°C TA = +25°C TA = +85°C –90 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 08570-111 –80 –10 LO FREQUENCY (MHz) 08570-115 UNDESIRED SIDEBAND (dBc) –10 TA = –40°C TA = +25°C TA = +85°C 08570-114 0 OUTPUT IP3 AND IP2 (dBm) TA = –40°C TA = +25°C TA = +85°C 08570-113 CARRIER FEEDTHROUGH (dBm) –10 08570-110 CARRIER FEEDTHROUGH (dBm) –10 0 TA = –40°C TA = +25°C TA = +85°C Figure 15. Second- and Third-Order Distortion vs. LO Frequency (fLO) and Temperature Rev. B | Page 11 of 36 Data Sheet 1.0 0 TA = –40°C TA = +25°C TA = +85°C INTEGRATED PHASE NOISE (°rms) –40 –50 –60 –70 –80 0.9 2.5kHz LOOP FILTER 130kHz LOOP FILTER 0.7 0.6 0.5 0.4 0.3 0.2 0.1 10k 100k 1M 10M 100M OFFSET FREQUENCY (Hz) 0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) 0 –10 –80 –50 –60 –70 PHASE NOISE, 100kHz OFFSET (dBc/Hz) TA = –40°C TA = +25°C TA = +85°C –20 –30 –40 2.5kHz LOOP FILTER –80 –90 –100 –110 –120 –130 –140 130kHz LOOP FILTER –150 –160 1 10 100 1000 10000 100000 OFFSET FREQUENCY (kHz) –100 OFFSET = 100kHz –110 TA = –40°C TA = +25°C TA = +85°C –120 –130 OFFSET = 5MHz –140 LO FREQUENCY (MHz) Figure 20. Phase Noise vs. LO Frequency at 1 kHz, 100 kHz, and 5 MHz Offsets PHASE NOISE , 1MHz OFFSET (dBc/Hz) 2.5kHz LOOP FILTER 130kHz LOOP FILTER 10 OFFSET = 1kHz –80 TA = –40°C TA = +25°C TA = +85°C 1 –90 –150 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 100 1000 OFFSET FREQUENCY (kHz) 10000 100000 08570-118 PHASE NOISE, LO FREQUENCY = 2600MHz (dBc/Hz) Figure 17. Phase Noise vs. Offset Frequency and Temperature, fLO = 2300 MHz 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 Figure 19. Integrated Phase Noise vs. LO Frequency 08570-117 PHASE NOISE, LO FREQUENCY = 2300MHz (dBc/Hz) Figure 16. Phase Noise vs. Offset Frequency and Temperature, fLO = 2140 MHz 08570-119 –140 –150 –160 1k TA = –40°C TA = +25°C TA = +85°C 08570-120 –90 –100 –110 –120 –130 0.8 Figure 18. Phase Noise vs. Offset Frequency and Temperature, fLO = 2600 MHz –90 TA = –40°C TA = +25°C TA = +85°C OFFSET = 10kHz –100 –110 –120 OFFSET = 1MHz –130 –140 –150 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) 08570-121 –10 –20 –30 08570-116 PHASE NOISE, LO FREQUENCY = 2140MHz (dBc/Hz) ADRF6703 Figure 21. Phase Noise vs. LO Frequency at 10 kHz and 1 MHz Offsets Rev. B | Page 12 of 36 Data Sheet ADRF6703 –70 –70 TA = –40°C TA = +25°C TA = +85°C 2 × PFD FREQUENCY 4 × PFD FREQUENCY –75 –80 SPUR LEVEL (dBc) SPUR LEVEL (dBc) –80 TA = –40°C TA = +25°C TA = +85°C 2 × PFD FREQUENCY 4 × PFD FREQUENCY –90 –100 –85 –90 –95 –100 –105 –110 –110 –120 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 –120 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) Figure 22. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD) at Modulator Output LO FREQUENCY (MHz) Figure 25. PLL Reference Spurs vs. LO Frequency (2× PFD and 4× PFD) at LO Output –70 –70 TA = –40°C TA = +25°C TA = +85°C 1 × PFD FREQUENCY 3 × PFD FREQUENCY –80 –80 –85 –85 –90 –95 –100 –105 –90 –95 –100 –105 0.5 ×, 2 × PFD FREQUENCY –115 0.5 × PFD FREQUENCY 08570-123 –120 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) Figure 23. PLL Reference Spurs vs. LO Frequency (0.5× PFD, 1× PFD, and 3× PFD) at Modulator Output LO FREQUENCY (MHz) 08570-126 –115 –120 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 Figure 26. PLL Reference Spurs vs. LO Frequency (0.5× PFD, 2× PFD, and 3× PFD) at LO Output 0 2.8 TA = –40°C TA = +25°C TA = +85°C –20 LO = 2594.13MHz LO = 2138.95MHz LO = 2306.26MHz –40 2.2 2.0 1.8 1.6 –60 –80 –100 –120 –140 1.2 –160 1.0 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 –180 1k LO FREQUENCY (MHz) Figure 24. VTUNE vs. LO Frequency and Temperature 08570-124 1.4 10k 100k FREQUENCY (Hz) 1M 10M 08570-127 PHASE NOISE (dBc/Hz) 2.4 VTUNE (V) 3 × PFD FREQUENCY –110 –110 2.6 TA = –40°C TA = +25°C TA = +85°C –75 SPUR LEVEL (dBc) SPUR LEVEL (dBc) –75 08570-125 08570-122 –115 Figure 27. Open-Loop VCO Phase Noise at 2138.95 MHz, 2306.26 MHz, and 2594.13 MHz Rev. B | Page 13 of 36 Data Sheet 2140MHz 2300MHz 2600MHz 80 70 60 50 40 30 20 0 –164 –163 –162 –161 –160 –159 –158 –157 NOISE FLOOR (dBm/Hz) 08570-128 10 –20 –30 –40 –50 –60 SSB OUTPUT POWER –70 –80 LO FEEDTHROUGH –90 –100 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 LO FREQUENCY (MHz) Figure 30. SSB Output Power and LO Feedthrough with RF Output Disabled 15 2.0 10 1.9 1.8 5 1.7 VPTAT (V) 0 –5 –10 1.6 1.5 1.4 1.3 –15 1.2 –20 1.1 –25 0 50 100 150 200 250 TIME (µs) 300 08570-129 FREQUENCUY DEVIATION FROM 2410MHz (MHz) Figure 28. IQ Modulator Noise Floor Cumulative Distributions at 2140 MHz, 2300 MHz, and 2600 MHz 0 –10 1.0 –40 –15 10 35 60 TEMPERATURE (°C) Figure 31. VPTAT Voltage vs. Temperature Figure 29. Frequency Deviation from LO Frequency at LO = 2.41 GHz to 2.4 GHz vs. Lock Time Rev. B | Page 14 of 36 85 08570-131 CUMULATIVE PERCENTAGE (%) 90 08570-130 100 SSB OUTPUT POWER AND LO FEEDTHROUGH (dBm) ADRF6703 Data Sheet ADRF6703 0 –1 RETURN LOSS (dB) –2 –3 –4 –5 RF OUT –6 –7 2 LO INPUT 2600MHz –8 1 2100MHz 08570-132 LO FREQUENCY (MHz) Figure 32. Input Return Loss of LO Input (LON, LOP Driven Through MABA007159 1:1 Balun) and Output Return Loss of RFOUT vs. Frequency 300 SUPPLY CURRENT (mA) 280 TA = –40°C TA = +25°C TA = +85°C 260 240 220 200 LO FREQUENCY (MHz) 08570-133 180 160 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 08570-134 –9 –10 2100 2150 2200 2250 2300 2350 2400 2450 2500 2550 2600 Figure 33. Power Supply Current vs. Frequency and Temperature (PLL and IQMOD Enabled, LO Buffer Disabled) Rev. B | Page 15 of 36 Figure 34. Smith Chart Representation of RF Output ADRF6703 Data Sheet THEORY OF OPERATION The ADRF6703 integrates a high performance IQ modulator with a state of the art fractional-N PLL. The ADRF6703 also integrates a low noise VCO. The programmable SPI port allows the user to control the fractional-N PLL functions and the modulator optimization functions. This includes the capability to operate with an externally applied LO or VCO. The quadrature modulator core within the ADRF6703 is a part of the next generation of industry-leading modulators from Analog Devices, Inc. The baseband inputs are converted to currents and then mixed to RF using high performance NPN transistors. The mixer output currents are transformed to a single-ended RF output using an integrated RF transformer balun. The high performance active mixer core, coupled with the low-loss RF transformer balun results in an exceptional OIP3 and OP1dB, with a very low output noise floor for excellent dynamic range. The use of a passive transformer balun rather than an active output stage leads to an improvement in OIP3 with no sacrifice in noise floor. At 2140 MHz the ADRF6703 typically provides an output P1dB of 14.2 dBm, OIP3 of 33.2 dBm, and an output noise floor of −159.6 dBm/Hz. Typical image rejection under these conditions is −52.3 dBc with no additional I and Q gain compensation. PLL + VCO The fractional divide function of the PLL allows the frequency multiplication value from REFIN to the LOP/LON outputs to be a fractional value rather than restricted to an integer as in traditional PLLs. In operation, this multiplication value is INT + (FRAC/MOD) where INT is the integer value, FRAC is the fractional value, and MOD is the modulus value, all of which are programmable via the SPI port. In previous fractional-N PLL designs, the fractional multiplication was achieved by periodically changing the fractional value in a deterministic way. The downside of this was often spurious components close to the fundamental signal. In the ADRF6703, a sigma delta modulator is used to distribute the fractional value randomly, thus significantly reducing the spurious content due to the fractional function. BASIC CONNECTIONS FOR OPERATION Figure 35 shows the basic connections for operating the ADRF6703 as they are implemented on the device’s evaluation board. The seven power supply pins should be individually decoupled using 100 pF and 0.1 µF capacitors located as close as possible to the pins. A single 10 µF capacitor is also recommended. The three internal decoupling nodes (labeled DECL3, DECL2, and DECL1) should be individually decoupled with capacitors as shown in Figure 35. The four I and Q inputs should be driven with a bias level of 500 mV. These inputs are generally dc-coupled to the outputs of a dual DAC (see the DAC-to-IQ Modulator Interfacing and IQ Filtering sections for more information). A 1 V p-p (0.353 V rms) differential sine wave on the I and Q inputs results in a single sideband output power of 4.95 dBm (at 2140 MHz) at the RFOUT pin (this pin should be ac-coupled as shown in Figure 35). This corresponds to an IQ modulator voltage gain of 0.95 dB. The reference frequency for the PLL (typically 1 V p-p between 12 MHz and 160 MHz) should be applied to the REFIN pin, which should be ac-coupled. If the REFIN pin is being driven from a 50 Ω source (for example, a lab signal generator), the pin should be terminated with 50 Ω as shown in Figure 35 (an RF drive level of +4 dBm should be applied). Multiples or fractions of the REFIN signal can be brought back off-chip at the multiplexer output pin (MUXOUT). A lock-detect signal and an analog voltage proportional to the ambient temperature can also be brought out on this pin by setting the appropriate bits on (DB21-DB23) in Register 4 (see the Register Description section). EXTERNAL LO The internally generated local oscillator (LO) signal can be brought off-chip as either a 1× LO or a 2× LO (via pins LOP and LON) by asserting the LOSEL pin and making the appropriate internal register settings. The LO output must be disabled whenever the RF output of the IQ modulator is disabled. The LOP and LON pins can also be used to apply an external LO. This can be used to bypass the internal PLL/VCO or if operation using an external VCO is desired. To turn off the PLL Register 6, Bits[20:17] must be zero. Rev. B | Page 16 of 36 Data Sheet ADRF6703 VCC VDD R20 0Ω (0402) R47 10kΩ (0402) C7 0.1µF (0402) C27 0.1µF (0402) C25 0.1µF (0402) C23 0.1µF (0402) C20 0.1µF (0402) C19 0.1µF (0402) C9 0.1µF (0402) C8 100pF (0402) C26 100pF (0402) C24 100pF (0402) C22 100pF (0402) C21 100pF (0402) C18 100pF (0402) C10 100pF (0402) VDD VDD VDD VDD VDD VDD LE (USB) DATA (USB) CLK (USB) DECL2 R40 10kΩ (0402) C16 100pF (0402) C17 0.1µF (0402) C42 10µF (0603) DECL1 C12 100pF (0402) C11 0.1µF (0402) C41 OPEN (0603) LOSEL SPI INTERFACE LON 5 1 4 3 MABA-007159 C5 100pF (0402) C29 100pF (0402) REF_IN DIVIDER ÷2 C6 100pF LOP (0402) REFIN R73 49.9Ω (0402) SEE TEXT REFOUT OPEN FRACTION REG MODULUS 2:1 MUX INTEGER REG ADRF6703 QP THIRD-ORDER FRACTIONAL INTERPOLATOR ×2 ÷2 N COUNTER 21 TO 123 MUX ÷4 TEMP SENSOR MUXOUT PRESCALER ÷2 NC R2 R37 OPEN 0Ω (0402) (0402) GND CP TEST POINT (OPEN) R38 OPEN (0402) C14 22pF (0603) RSET IP CP VTUNE DECL3 R10 3kΩ (0603) C15 2.7nF (1206) C13 6.8pF (0603) C2 OPEN (0402) IN R3 OPEN (0402) IP RFOUT OPEN R62 0Ω (0402) VTUNE OPEN C40 22pF (0603) QP QN IN R9 10kΩ R65 10kΩ (0402) (0402) C3 100pF (0402) RFOUT R63 OPEN (0402) R12 0Ω (0402) R11 OPEN (0402) C43 10µF (0603) QN R23 OPEN (0402) ÷2 0/90 CHARGE PUM P 250µA, 500µA (DEFAULT), 750µA, 1000µA – PHASE + FREQUENCY DETECTOR R16 OPEN (0402) VCO CORE C1 100pF (0402) 08570-023 EXT LO LE S1 S2 DATA R39 10kΩ (0402) C28 10µF (3216) CLK VCC R43 10kΩ (0402) ENOP VCC RED +5V NOTES 1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN. Figure 35. Basic Connections for Operation (Loop Filter Set to 130 kHz) LOOP FILTER Table 8. Recommended Loop Filter Components The loop filter is connected between the CP and VTUNE pins. The return for the loop filter components should be to Pin 40 (DECL3). The loop filter design in Figure 35 results in a 3 dB loop bandwidth of 130 kHz. The ADRF6703 closed loop phase noise was also characterized using a 2.5 kHz loop filter design. The recommended components for both filter designs are shown in Table 8. For assistance in designing loop filters with other characteristics, download the most recent revision of ADIsimPLL™ from www.analog.com/adisimpll. Operation with an external VCO is possible. In this case, the return for the loop filter components is ground (assuming a ground reference on the external VCO tuning input). The output of the loop filter is connected to the external VCO’s tuning pin. The output of the VCO is brought back into the device on the LOP and LON pins (using a balun if necessary). Component C14 R10 C15 R9 C13 R65 C40 R37 R11 R12 Rev. B | Page 17 of 36 130 kHz Loop Filter 22 pF 3 kΩ 2.7 nF 10 kΩ 6.8 pF 10 kΩ 22 pF 0Ω Open 0Ω 2.5 kHz Loop Filter 0.1 µF 68 Ω 4.7 µF 270 Ω 47 nF 0Ω Open 0Ω Open 0Ω ADRF6703 Data Sheet AD9122 The ADRF6703 is designed to interface with minimal components to members of the Analog Devices, Inc., family of TxDACs®. These dual-channel differential current output DACs provide an output current swing from 0 mA to 20 mA. The interface described in this section can be used with any DAC that has a similar output. An example of an interface using the AD9122 TxDAC is shown in Figure 36. The baseband inputs of the ADRF6703 require a dc bias of 500 mV. The average output current on each of the outputs of the AD9122 is 10 mA. Therefore, a single 50 Ω resistor to ground from each of the DAC outputs results in an average current of 10 mA flowing through each of the resistors, thus producing the desired 500 mV dc bias for the inputs to the ADRF6703. ADRF6703 OUT1_P IN RBIP 50Ω RBIN 50Ω IP OUT1_N OUT2_N QN OUT2_P 08570-033 RBQN 50Ω RBQP 50Ω QP Figure 36. Interface Between the AD9122 and ADRF6703 with 50 Ω Resistors to Ground to Establish the 500 mV DC Bias for the ADRF6703 Baseband Inputs The AD9122 output currents have a swing that ranges from 0 mA to 20 mA. With the 50 Ω resistors in place, the ac voltage swing going into the ADRF6703 baseband inputs ranges from 0 V to 1 V (with the DAC running at 0 dBFS). So the resulting drive signal from each differential pair is 2 V p-p differential with a 500 mV dc bias. OUT1_P IP RBIP 50Ω RSL1 (SEE TEXT) RBIN 50Ω IN OUT1_N OUT2_N OUT2_P QN RBQN 50Ω RBQP 50Ω RSL2 (SEE TEXT) QP Figure 37. AC Voltage Swing Reduction Through the Introduction of a Shunt Resistor Between the Differential Pair The value of this ac voltage swing limiting resistor(RSL as shown in Figure 37) is chosen based on the desired ac voltage swing and IQ modulator output power. Figure 38 shows the relationship between the swing-limiting resistor and the peak-to-peak ac swing that it produces when 50 Ω bias-setting resistors are used. A higher value of swing-limiting resistor will increase the output power of the ADRF6703 and signal-to-noise ratio (SNR) at the cost if higher intermodulation distortion. For most applications, the optimum value for this resistor will be between 100 Ω and 300 Ω. When setting the size of the swing-limiting resistor, the input impedance of the I and Q inputs should be taken into account. The I and Q inputs have a differential input resistance of 920 Ω. As a result, the effective value of the swing-limiting resistance is 920 Ω in parallel with the chosen swing-limiting resistor. For example, if a swing-limiting resistance of 200 Ω is desired (based on Figure 37), the value of RSL should be set such that 200 Ω = (920 × RSL)/(920 + RSL) resulting in a value for RSL of 255 Ω. 2.0 1.8 The voltage swing for a given DAC output current can be reduced by adding a third resistor to the interface. This resistor is placed in the shunt across each differential pair, as shown in Figure 37. It has the effect of reducing the ac swing without changing the dc bias already established by the 50 Ω resistors. DIFFERENTIAL SWING (V p-p) ADDING A SWING-LIMITING RESISTOR 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 10 100 1000 RSL (Ω) 10000 08570-235 AD9122 ADRF6703 08570-034 DAC-TO-IQ MODULATOR INTERFACING Figure 38. Relationship Between the AC Swing-Limiting Resistor and the Peak-to-Peak Voltage Swing with 50 Ω Bias-Setting Resistors Rev. B | Page 18 of 36 Data Sheet ADRF6703 IQ FILTERING BASEBAND BANDWIDTH Figure 39 shows the frequency response of the ADRF6703’s baseband inputs. This plot shows 0.5 dB and 3 dB bandwidths of 350 MHz and 750 MHz respectively. Any flatness variations across frequency at the ADRF6703 RF output have been calibrated out of this measurement. 2 0 RESISTANCE 700 0.6 600 0.4 500 0.2 0 100 200 300 400 CAPACITANCE (pF) 0.8 800 400 0 500 BASEBAND FREQUENCY (MHz) Figure 40. Differential Baseband Input R and Input C Equivalents (Shunt R, Shunt C) DEVICE PROGRAMMING AND REGISTER SEQUENCING The device is programmed via a 3-pin SPI port. The timing requirements for the SPI port are shown in Table 3 and Figure 2. Eight programmable registers, each with 24 bits, control the operation of the device. The register functions are listed in Table 9. The eight registers should initially be programmed in reverse order, starting with Register 7 and finishing with Register 0. Once all eight registers have been initially programmed, any of the registers can be updated without any attention to sequencing. Software is available on the ADRF6703 product page at www.analog.com that allows programming of the evaluation board from a PC running Windows® XP or Windows Vista. –2 –4 To operate correctly under Windows XP, Version 3.5 of Microsoft .NET must be installed. To run the software on a Windows 7 PC, XP emulation mode must be used (using Virtual PC). –6 –8 100 BB FREQUENCY (MHz) 1000 08570-234 BASEBAND FREQUENCY RESPONSE (dBc) 4 CAPACITANCE 08570-141 Unless a swing-limiting resistor of 100 Ω is chosen, the filter must be designed to support different source and load impedances. In addition, the differential input capacitance of the I and Q inputs (1 pF) should be factored into the filter design. Modern filter design tools allow for the simulation and design of filters with differing source and load impedances as well as inclusion of reactive load components. 1.0 900 RESISTANCE (Ω) An antialiasing filter must be placed between the DAC and modulator to filter out Nyquist images and broadband DAC noise. The interface for setting up the biasing and ac swing discussed in the Adding a Swing-Limiting Resistor section, lends itself well to the introduction of such a filter. The filter can be inserted between the dc bias setting resistors and the ac swing-limiting resistor. Doing so establishes the input and output impedances for the filter. –10 10 1.2 1000 Figure 39. Baseband Bandwidth Rev. B | Page 19 of 36 ADRF6703 Data Sheet REGISTER SUMMARY Table 9. Register Functions Register Register 0 Register 1 Register 2 Register 3 Register 4 Register 5 Register 6 Register 7 Function Integer divide control (for the PLL) Modulus divide control (for the PLL) Fractional divide control (for the PLL) Σ-Δ modulator dither control PLL charge pump, PFD, and reference path control LO path and modulator control VCO control and VCO enable External VCO enable Rev. B | Page 20 of 36 Data Sheet ADRF6703 REGISTER DESCRIPTION Integer Divide Ratio REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0) The integer divide ratio bits are used to set the integer value in Equation 2. The INT, FRAC, and MOD values make it possible to generate output frequencies that are spaced by fractions of the PFD frequency. The VCO frequency (fVCO) equation is With Register 0, Bits[2:0] set to 000, the on-chip integer divide control register is programmed as shown in Figure 41. Divide Mode fVCO = 2 × fPFD × (INT + (FRAC/MOD)) Divide mode determines whether fractional mode or integer mode is used. In integer mode, the RF VCO output frequency (fVCO) is calculated by where: INT is the preset integer divide ratio value (24 to 119 in fractional mode). MOD is the preset fractional modulus (1 to 2047). FRAC is the preset fractional divider ratio value (0 to MOD − 1). (1) where: fVCO is the output frequency of the internal VCO. fPFD is the frequency of operation of the phase-frequency detector. INT is the integer divide ratio value (21 to 123 in integer mode). RESERVED DIVIDE MODE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DM ID6 ID5 ID4 ID3 ID2 ID1 ID0 C3(0) C2(0) C1(0) 0 0 0 0 0 0 0 0 0 0 0 0 0 DM DIVIDE MODE INTEGER DIVIDE RATIO 0 FRACTIONAL (DEFAULT) 1 INTEGER CONTROL BITS DB1 ID6 ID5 ID4 ID3 ID2 ID1 ID0 INTEGER DIVIDE RATIO 0 0 1 0 1 0 1 21 (INTEGER MODE ONLY) 0 0 1 0 1 1 0 22 (INTEGER MODE ONLY) 0 0 1 0 1 1 1 23 (INTEGER MODE ONLY) 0 0 1 1 0 0 0 24 ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 0 1 1 1 0 0 0 56 (DEFAULT) ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... ... 1 1 1 0 1 1 1 119 1 1 1 1 0 0 0 120 (INTEGER MODE ONLY) 1 1 1 1 0 0 1 121 (INTEGER MODE ONLY) 1 1 1 1 0 1 0 122 (INTEGER MODE ONLY) 1 1 1 1 0 1 1 123 (INTEGER MODE ONLY) Figure 41. Register 0—Integer Divide Control Register Map Rev. B | Page 21 of 36 DB0 08570-014 fVCO = 2 × fPFD × (INT) (2) ADRF6703 Data Sheet REGISTER 1—MODULUS DIVIDE CONTROL (DEFAULT: 0x003001) REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802) With Register 1, Bits[2:0] set to 001, the on-chip modulus divide control register is programmed as shown in Figure 42. With Register 2, Bits[2:0] set to 010, the on-chip fractional divide control register is programmed as shown in Figure 43. Modulus Value Fractional Value The modulus value is the preset fractional modulus ranging from 1 to 2047. The FRAC value is the preset fractional modulus ranging from 0 to