ADRV9008BBCZ-2

Integrated Dual RF Transmitters and Observation Receiver ADRV9008-2 Data Sheet FEATURES Dual transmitters Dual input shared observation receiver Maximum tunable transmitter synthesis bandwidth: 450 MHz Maximum observation receiver bandwidth: 450 MHz Fully integrated fractional-N RF synthesizers Fully integrated clock synthesizer Multichip phase synchronization for RF LO and baseband clocks JESD204B datapath interface Tuning range (center frequency): 75 MHz to 6000 MHz APPLICATIONS 2G/3G/4G/5G macrocell base stations Active antenna systems Massive multiple input, multiple output (MIMO) Phased array radars Electronic warfare Military communications Portable test equipment GENERAL DESCRIPTION The ADRV9008-2 is a highly integrated, RF agile transmit subsystem offering dual-channel transmitters, an observation path receiver, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption required by 2G/3G/4G/5G macrocell base stations, and active antenna applications. The transmitters use an innovative direct conversion modulator that achieves multicarrier macrocell base station quality performance and low power. In 3G/4G mode, the maximum transmitter large signal bandwidth is 200 MHz. In multicarrier Rev. 0 global system for mobile communications (MC GSM) mode, which has higher inband spurious-free dynamic range (SFDR), the maximum large signal bandwidth is 75 MHz. The observation path consists of a wide bandwidth direct conversion receiver with state of the art dynamic range. The complete receive subsystem includes dc offset correction, quadrature correction, and digital filtering, thus eliminating the need for these functions in the digital baseband. Several auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose inputs/outputs (GPIOs) for power amplifier (PA) and radio frequency (RF) front-end control are also integrated. The fully integrated phase-locked loops (PLLs) provide high performance, low power fractional-N RF frequency synthesis for the transmitter and receiver sections. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. Special precautions have been taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated. The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter in the widest bandwidth mode and two lanes for the observation path receiver in the widest bandwidth mode. The core of the ADRV9008-2 can be powered directly from 1.3 V regulators and 1.8 V regulators and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9008-2 is packaged in a 12 mm × 12 mm 196-ball chip scale ball grid array (CSP_BGA). Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADRV9008-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 69 Applications ....................................................................................... 1 Transmitter .................................................................................. 69 General Description ......................................................................... 1 Observation Receiver ................................................................. 69 Revision History ............................................................................... 2 Clock Input.................................................................................. 69 Functional Block Diagram .............................................................. 3 Synthesizers ................................................................................. 69 Specifications..................................................................................... 4 Serial Peripheral Interface (SPI) ............................................... 69 Current and Power Consumption Specifications................... 13 JTAG Boundary Scan ................................................................. 69 Timing Diagrams........................................................................ 14 Power Supply Sequence ............................................................. 69 Absolute Maximum Ratings.......................................................... 15 GPIO_x Pins ............................................................................... 70 Reflow Profile .............................................................................. 15 Auxiliary Converters .................................................................. 70 Thermal Management ............................................................... 15 JESD204B Data Interface .......................................................... 70 Thermal Resistance .................................................................... 15 Applications Information .............................................................. 71 ESD Caution ................................................................................ 15 PCB Layout and Power Supply Recommendations ............... 71 Pin Configuration and Function Descriptions ........................... 16 PCB Material and Stackup Selection ....................................... 71 Typical Performance Characteristics ........................................... 23 Fanout and Trace Space Guidelines ......................................... 73 75 MHz to 525 MHz Band ........................................................ 23 Component Placement and Routing Guidelines ................... 74 650 MHz to 3000 MHz Band .................................................... 36 RF and JESD204B Transmission Line Layout ........................ 79 3400 MHz to 4800 MHz Band .................................................. 47 Isolation Techniques Used on the ADRV9008-2W/PCBZ ... 83 5100 MHz to 5900 MHz Band .................................................. 57 RF Port Interface Information .................................................. 85 Transmitter Output Impedance ................................................ 67 Outline Dimensions ....................................................................... 95 Observation Receiver Input Impedance .................................. 67 Ordering Guide .......................................................................... 95 Terminology .................................................................................... 68 REVISION HISTORY 9/2018—Revision 0: Initial Version Rev. 0 | Page 2 of 95 Data Sheet ADRV9008-2 FUNCTIONAL BLOCK DIAGRAM ADRV9008-2 ORX1 ORX2 ORX1_IN– ORX2_IN+ ADC LPF ORX2_IN– ADC DIGITAL PROCESSING LPF RF_EXT_LO_I/O+ RF_EXT_LO_I/O– TX1_OUT+ ARM Cortex-M3 RF LO SYNTHESIZER TX1 TX2 TX1_OUT– TX2_OUT+ DAC LPF TX2_OUT– DECIMATION pFIR AGC DC OFFSET QEC LOCAL OSCILLATOR LEAKAGE JESD204B DAC SYNCIN0± SYNCIN1± SERDOUT0± SERDOUT1± SERDOUT2± SERDOUT3± SERDIN0± SERDIN1± SERDIN2± SERDIN3± SYNCOUT0± SYNCOUT1± SYSREFIN± GP_INTERRUPT ORXx_ENABLE TXx_ENABLE RESET SCLK CS SDO SDIO LPF GPIOs, AUXILIARY ADCs, AND AUXILIARY DACs GPIO_3p3_x GPIO_x AUXADC_x Figure 1. Rev. 0 | Page 3 of 95 CLOCK GENERATION REF_CLK_IN+ REF_CLK_IN– 16833-001 ORX1_IN+ ADRV9008-2 Data Sheet SPECIFICATIONS Electrical characteristics at VDDA1P31 = 1.3 V, VDDD1P3_DIG = 1.3 V, VDDA1P8_TX = 1.8 V, TJ = full operating temperature range. Local oscillator frequency (fLO) = 1800 MHz, unless otherwise noted. The specifications in Table 1 are not de-embedded. Refer to the Typical Performance Characteristics section for input/output circuit path loss. The device configuration profile for the 75 MHz to 525 MHz frequency range is as follows: transmitter = 50 MHz/100 MHz bandwidth (inphase quadrature (IQ) rate = 122.88 MHz), observation receiver = 100 MHz bandwidth (IQ rate = 122.88 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz. Unless otherwise specified, the device configuration for all other frequency ranges is as follows: transmitter = 200 MHz/450 MHz bandwidth (IQ rate = 491.52 MHz), observation receiver = 450 MHz bandwidth (IQ rate = 491.52 MHz), JESD204B rate = 9.8304 GSPS, and device clock = 245.76 MHz. Table 1. Parameter TRANSMITTERS Center Frequency Transmitter (Tx) Synthesis Bandwidth (BW) Transmitter Large Signal Bandwidth (3G/4G) Transmitter Large Signal Bandwidth (MC GSM) Peak-to-Peak Gain Deviation Symbol Min Typ 75 Max Unit 6000 450 MHz MHz 200 MHz 75 MHz 1.0 dB Gain Slope ±0.1 dB Deviation from Linear Phase Transmitter Attenuation Power Control Range 1 Degrees Transmitter Attenuation Power Control Resolution Transmitter Attenuation Integral Nonlinearity Transmitter Attenuation Differential Nonlinearity Transmitter Attenuation Serial Peripheral Interface 2 (SPI 2) Timing Time from CS Going High to Change in Transmitter Attenuation Time Between Consecutive Microattenuation Steps Time Required to Reach Final Attenuation Value Maximum Attenuation Overshoot During Transition 0 32 dB Test Conditions/Comments Low intermediate frequency (IF) mode 450 MHz bandwidth, compensated by programmable finite impulse response (FIR) filter Any 20 MHz bandwidth span, compensated by programmable FIR filter 450 MHz bandwidth Signal-to-noise ratio (SNR) maintained for attenuation between 0 dB and 20 dB 0.05 dB INL 0.1 dB For any 4 dB step DNL ±0.04 dB Monotonic See Figure 4 tSCH 19.5 24 ns tACH 6.5 8.1 ns A large change in attenuation can be broken up into a series of smaller attenuation changes 800 ns Time required to complete the change in attenuation from start attenuation to final attenuation value +0.5 dB tDCH −1.0 Rev. 0 | Page 4 of 95 Data Sheet Parameter Change in Attenuation per Microstep Maximum Attenuation Change when CS Goes High Adjacent Channel Leakage Ratio (ACLR) (LTE) ADRV9008-2 Symbol Min Typ Max 0.5 32 Unit dB dB 20 MHz LTE at −12 dBFS −67 −64 −60 dB dB dB −147 −148 −149 −150.5 dBm/Hz dBm/Hz dBm/Hz dBm/Hz −147 −153 −154 −155.5 dBm/Hz dBm/Hz dBm/Hz dBm/Hz 75 MHz < f ≤ 2800 MHz 2800 MHz < f ≤ 4800 MHz 4800 MHz < f ≤ 6000 MHz 0 dB attenuation, in band noise falls 1 dB for each dB of attenuation for attenuation between 0 dB and 20 dB 75 MHz < f ≤ 600 MHz 600 MHz < f ≤ 3000 MHz 3000 MHz < f ≤ 4800 MHz 4800 MHz < f ≤ 6000 MHz 0 dB attenuation, 3 × bandwidth/2 offset 75 MHz < f ≤ 600 MHz 600 MHz < f ≤ 3000 MHz 3000 MHz < f ≤ 4800 MHz 4800 MHz < f ≤ 6000 MHz −95 −80 85 dBc dBc dB 75 MHz < f ≤ 600 MHz 75 70 65 56 dB dB dB dB 600 MHz < f ≤ 2800 MHz 2800 MHz < f ≤ 4800 MHz 4800 MHz < f ≤ 5700 MHz 5700 MHz < f ≤ 6000 MHz In Band Noise Floor Out of Band Noise Floor Interpolation Images MC GSM Mode 3G/4G Mode Transmitter to Transmitter Isolation Image Rejection Within Large Signal Bandwidth Beyond Large Signal Bandwidth 70 65 62 60 40 dB dB dB dB dB 9 7 6 4.5 dBm dBm dBm dBm 29 27 23 dBm dBm dBm Maximum Output Power Third-Order Output Intermodulation Intercept Point Test Conditions/Comments OIP3 Rev. 0 | Page 5 of 95 Quadrature error correction (QEC) active 75 MHz < f ≤ 600 MHz 600 MHz < f ≤ 4000 MHz 4000 MHz < f ≤ 4800 MHz 4800 MHz < f ≤ 6000 MHz Assumes that distortion power density is 25 dB below desired power density 0 dBFS, continuous wave (CW) tone into 50 Ω load, 0 dB transmitter attenuation 75 MHz < f ≤ 600 MHz 600 MHz < f ≤ 3000 MHz 3000 MHz < f ≤ 4800 MHz 4800 MHz < f ≤ 6000 MHz 0 dB transmitter attenuation 75 MHz < f ≤ 600 MHz 600 MHz < f ≤ 4000 MHz 4000 MHz < f ≤ 6000 MHz ADRV9008-2 Parameter Third-Order Intermodulation Data Sheet Symbol IM3 Min Typ −70 Max Unit dBc Carrier Leakage Carrier Offset from Local Oscillator (LO) Carrier on LO Error Vector Magnitude (Third Generation Partnership Project (3GPP) Test Signals) 75 MHz LO2 1900 MHz LO 3800 MHz LO 5900 MHz LO Output Impedance OBSERVATION RECEIVER Center Frequency Gain Range −84 dBFS −82 −80 −71 dBFS dBFS dBFS 600 MHz < f ≤ 4800 MHz 4800 MHz < f ≤ 6000 MHz 0.5 0.7 0.7 1.1 50 % % % % Ω 300 kHz RF PLL loop bandwidth 50 kHz RF PLL loop bandwidth 300 kHz RF PLL loop bandwidth 300 kHz RF PLL loop bandwidth Differential (see Figure 265) EVM ZOUT ORx 30 MHz dB Analog Gain Step 0.5 dB Peak-to-Peak Gain Deviation Gain Slope 1 dB ±0.1 dB Deviation from Linear Phase Observation Receiver Bandwidth Observation Receiver Alias Band Rejection Maximum Useable Input Level 1 Degrees Integrated Noise Test Conditions/Comments 2 × GSMK carriers, ΣPOUT = −12 dBFS rms The two carriers can be placed anywhere within the transmitter band such that the IM3 products fall within the transmitter band or within 10 MHz of the band edges With LO leakage correction active, 0 dB attenuation, scales decibel for decibel with attenuation, measured in 1 MHz bandwidth, resolution bandwidth, and video bandwidth = 100 kHz, rms detector, 100 trace average 75 MHz < f ≤ 600 MHz 75 6000 450 60 MHz dB Due to digital filters dBm dBm dBm dBFS dBFS 0 dB attenuation, increases decibel for decibel with attenuation, continuous wave corresponds to −1 dBFS at ADC 75 MHz < f ≤ 3000 MHz 3000 MHz < f ≤ 4800 MHz 4800 MHz < f ≤ 6000 MHz 450 MHz integration bandwidth 491.52 MHz integration bandwidth PHIGH −11 −9.5 −8 −58.5 −57.5 Rev. 0 | Page 6 of 95 Third-order input intermodulation intercept point (IIP3) improves decibel for decibel for the first 18 dB of gain attenuation, QEC performance optimized for 0 dB to 6 dB of attenuation only For attenuator steps from 0 dB to 6 dB 450 MHz bandwidth, compensated by programmable FIR filter Any 20 MHz bandwidth span, compensated by programmable FIR filter 450 MHz RF bandwidth Data Sheet Parameter Second-Order Input Intermodulation Intercept Point Third-Order Input Intermodulation Intercept Point Narrow Band ADRV9008-2 Symbol IIP2 Fifth-Order Intermodulation Product (1800 MHz) Seventh-Order Intermodulation Product (1800 MHz) Spurious-Free Dynamic Range Harmonic Distortion Second-Order Harmonic Distortion Product Third-Order Harmonic Distortion Product Image Rejection Within Large Signal Bandwidth Outside Large Signal Bandwidth Typ 62 Max Unit dBm 62 dBm 4 dBm 11 dBm 12 12 11 7 7 6 dBm dBm dBm dBm dBm dBm IM5 −70 −67 −62 −80 dBc dBc dBc dBc IM7 −80 dBc SFDR 70 dB HD2 −80 dBc −80 dBc −70 dBc −60 dBc 65 dB 55 dB Test Conditions/Comments Maximum observation receiver gain, (PHIGH – 14) dB per tone (see the Terminology section), 75 MHz < f ≤ 600 MHz Maximum observation receiver gain, (PHIGH – 8) dB per tone (see the Terminology section), 600 MHz < f ≤ 3000 MHz IIP3 Wide Band Third-Order Intermodulation Product Min IM3 HD3 Rev. 0 | Page 7 of 95 75 MHz < f ≤ 300 MHz, (PHIGH − 14) dB per tone 300 MHz < f ≤ 600 MHz, (PHIGH − 14) dB per tone IM3 product < 130 MHz at baseband, (PHIGH − 8) dB per tone 600 MHz < f ≤ 3000 MHz 3000 MHz < f ≤ 4800 MHz 4800 MHz < f ≤ 6000 MHz 600 MHz < f ≤ 3000 MHz 3000 MHz < f ≤ 4800 MHz 4800 MHz < f ≤ 6000 MHz IM3 product < 130 MHz at baseband, two tones, each at (PHIGH − 12) dB 600 MHz < f ≤ 3000 MHz 3000 MHz < f ≤ 4800 MHz 4800 MHz < f ≤ 6000 MHz IM5 product < 50 MHz at baseband, two tones, each at (PHIGH − 12) dB, 600 MHz < f ≤ 6000 MHz IM7 product < 50 MHz at baseband, two tones, each at (PHIGH − 12) dB, 600 MHz < f ≤ 6000 MHz Non IMx related spurs, does not include HDx, (PHIGH − 9) dB input signal, 600 MHz < f ≤ 6000 MHz (PHIGH − 11) dB input signal (PHIGH – 11) dB input signal, 75 MHz < f ≤ 600 MHz (PHIGH – 9) dB input signal, 600 MHz < f ≤ 6000 MHz In band HD falls within ±100 MHz Out of band HD falls within ±225 MHz In band HD falls within ±100 MHz Out of band HD falls within ±225 MHz QEC active ADRV9008-2 Parameter Input Impedance Isolation Transmitter 1 (Tx1) to Observation Receiver 1 (ORx1) and Transmitter 2 (Tx2) to Observation Receiver 2 (ORx2) Data Sheet Unit Ω Test Conditions/Comments Differential (see Figure 266) 100 dB 75 MHz < f ≤ 600 MHz 65 55 105 dB dB dB 600 MHz < f ≤ 5300 MHz 5300 MHz < f ≤ 6000 MHz 75 MHz < f ≤ 600 MHz 65 55 dB dB 600 MHz < f ≤ 5300 MHz 5300 MHz < f ≤ 6000 MHz 2.3 Hz −85 dBc 0.014 °rms 1900 MHz LO 0.2 °rms 3800 MHz LO 5900 MHz LO Spot Phase Noise 75 MHz LO 10 kHz Offset 100 kHz Offset 1 MHz Offset 10 MHz Offset 1900 MHz LO 100 kHz Offset 200 kHz Offset 400 kHz Offset 600 kHz Offset 800 kHz Offset 1.2 MHz Offset 1.8 MHz Offset 6 MHz Offset 10 MHz Offset 3800 MHz LO 100 kHz Offset 1.2 MHz Offset 10 MHz Offset 5900 MHz LO 100 kHz Offset 1.2 MHz Offset 10 MHz Offset LO PHASE SYNCHRONIZATION Phase Deviation 0.36 0.54 °rms °rms 1.5 GHz to 2.8 GHz, 76.8 MHz phase frequency detector (PFD) frequency Excludes integer boundary spurs 2 kHz to 18 MHz Narrow PLL loop bandwidth (50 kHz) Narrow PLL loop bandwidth (50 kHz) Wide PLL loop bandwidth (300 kHz) Wide PLL loop bandwidth (300 kHz) −126.5 −132.8 −150.1 −150.7 dBc/Hz dBc/Hz dBc/Hz dBc/Hz −100 −115 −120 −129 −132 −135 −140 −150 −153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz −104 −125 −145 dBc/Hz dBc/Hz dBc/Hz −99 −119.7 −135.4 dBc/Hz dBc/Hz dBc/Hz 1.6 ps/°C Tx1 to ORx 2 and Tx2 to ORx 1 LO SYNTHESIZER LO Frequency Step LO Spur Integrated Phase Noise 75 MHz LO Symbol Min Typ 100 Max Narrow PLL loop bandwidth Narrow PLL loop bandwidth Wide PLL loop bandwidth Wide PLL loop bandwidth Rev. 0 | Page 8 of 95 Change in LO delay per temperature change Data Sheet Parameter EXTERNAL LO INPUT Input Frequency Input Signal Power ADRV9008-2 Symbol Min fEXTLO 300 Test Conditions/Comments 8000 MHz 12 3 dBm dBm 6 dBm Input frequency must be 2× the desired LO frequency 50 Ω matching at the source fEXTLO ≤ 2 GHz, add 0.5 dBm/GHz above 2 GHz fEXTLO = 8 GHz To ensure adequate QEC VDD_ INTERFACE × 0.8 0 ps dB % dBc 0.4 °rms −109 −129 −149 dBc/Hz dBc/Hz dBc/Hz 10 0.3 DAC Resolution Output Voltage Minimum Maximum Low Level Unit 3.6 1 2 −50 AUXILIARY CONVERTERS ADC Resolution Input Voltage Minimum Maximum Output Drive Capability DIGITAL SPECIFICATIONS (CMOS)—SDIO, SDO, SCLK, CS GPIO_x, TXx_ENABLE, ORXx_ENABLE Logic Inputs Input Voltage High Level Max 0 External LO Input Signal Differential Phase Error Amplitude Error Duty Cycle Error Even-Order Harmonics CLOCK SYNTHESIZER Integrated Phase Noise 1966.08 MHz LO Spot Phase Noise 1966.08 MHz LO 100 kHz Offset 1 MHz Offset 10 MHz Offset REFERENCE CLOCK (REF_CLK_IN±) Frequency Range Signal Level Typ 1000 2.0 MHz V p-p 1 kHz to 100 MHz PLL optimized for close in phase noise AC-coupled, common-mode voltage (VCM) = 618 mV, for best spurious performance, use 300 kHz, Spectrum Analyzer Limits Far Out Noise Rev. 0 | Page 66 of 95 Data Sheet ADRV9008-2 TRANSMITTER OUTPUT IMPEDANCE TX PORT SIMULATED IMPEDANCE: SEDZ M21 FREQUENCY = 100.0MHz S (1,1) = 0.143 / –7.865 IMPEDANCE = 66.439 – j2.654 M27 M22 FREQUENCY = 300.0MHz S (1,1) = 0.141 / –25.589 IMPEDANCE = 64.063 – j7.987 M29 M26 S (1,1) M23 FREQUENCY = 500.0MHz S (1,1) = 0.145 / –42.661 IMPEDANCE = 60.623 – j12.201 M26 FREQUENCY = 3.000GHz S (1,1) = 0.368 / 150.626 IMPEDANCE = 24.355 + j10.153 M28 M25 M27 FREQUENCY = 4.000GHz S (1,1) = 0.484 / –107.379 IMPEDANCE = 25.118 + j30.329 M28 FREQUENCY = 5.000GHz S (1,1) = 0.569 / 70.352 IMPEDANCE = 35.932 + j56.936 M21 M22 M23 M24 M29 FREQUENCY = 6.000GHz S (1,1) = 0.614 / 36.074 IMPEDANCE = 81.032 + j94.014 M24 FREQUENCY = 1.000GHz S (1,1) = 0.164 / –84.046 IMPEDANCE = 49.000 – j16.447 16833-002 M25 FREQUENCY = 2.000GHz S (1,1) = 0.247 / 155.186 IMPEDANCE = 31.131 – j6.860 FREQUENCY (0Hz TO 6.000GHz) Figure 265. Transmitter Output Impedance Series Equivalent Differential Impedance (SEDZ) OBSERVATION RECEIVER INPUT IMPEDANCE ORX PORT SIMULATED IMPEDANCE: SEDZ M20 FREQUENCY = 3.000GHz S (1,1) = 0.104 / –66.720 IMPEDANCE = 53.262 – j10.292 M15 FREQUENCY = 100.0MHz S (1,1) = 0.391 / –1.848 IMPEDANCE = 114.099 – j3.397 M23 M16 FREQUENCY = 300.0MHz S (1,1) = 0.389 / –5.601 IMPEDANCE = 112.639 – j10.091 M21 M21 FREQUENCY = 4.000GHz S (1,1) = 0.116 / –104.276 IMPEDANCE = 46.060 + j10.522 M21 S (1,1) M17 FREQUENCY = 500.0MHz S (1,1) = 0.385 / –9.396 IMPEDANCE = 109.556 – j16.156 M22 M20 M19 M15 M16 M17 M18 M22 FREQUENCY = 5.000GHz S (1,1) = 0.342 / 75.761 IMPEDANCE = 46.551 + j34.914 M23 FREQUENCY = 6.000GHz S (1,1) = 0.525 / 53.007 IMPEDANCE = 56.249 + j65.146 M18 FREQUENCY = 1.000GHz S (1,1) = 0.362 / –19.087 IMPEDANCE = 97.259 – j26.513 FREQUENCY (0Hz TO 6.000GHz) Figure 266. Observation Receiver Input Impedance SEDZ Rev. 0 | Page 67 of 95 16833-003 FREQUENCY = 2.000GHz S (1,1) = 0.267 / –39.928 IMPEDANCE = 70.189 – j25.940 ADRV9008-2 Data Sheet TERMINOLOGY Large Signal Bandwidth Large signal bandwidth, otherwise known as instantaneous bandwidth or signal bandwidth, is the bandwidth over which there are large signals. For example, for Band 42 LTE, the large signal bandwidth is 200 MHz. Occupied Bandwidth Occupied bandwidth is the total bandwidth of the active signals. For example, three 20 MHz carriers have a 60 MHz occupied bandwidth, regardless of where the carriers are placed within the large signal bandwidth. Synthesis Bandwidth Synthesis bandwidth is the bandwidth over which digital predistortion (DPD) linearization is transmitted. Synthesis bandwidth is the 1 dB bandwidth of the transmitter. The power density of the signal outside the occupied bandwidth is assumed to be 25 dB below the signal in the occupied bandwidth, which also assumes that the unlinearized power amplifier (PA) achieves 25 dB ACLR. Observation Bandwidth Observation bandwidth is the 1 dB bandwidth of the observation receiver. With the observation receiver sharing the transmitter LO, the observation receiver sees similar power densities, such as those in the occupied bandwidth and synthesis bandwidth of the transmitter. Backoff Backoff is the difference (in dB) between full scale and the rms signal power. PHIGH PHIGH is the largest signal that can be applied without overloading the ADC for the observation receiver input. This input level results in slightly less than full scale at the digital output because of the nature of the continuous time Σ-Δ ADCs, which, for example, exhibit a soft overload in contrast to the hard clipping of pipeline ADCs. Rev. 0 | Page 68 of 95 Data Sheet ADRV9008-2 THEORY OF OPERATION The ADRV9008-2 is a highly integrated RF transmitter subsystem capable of configuration for a wide range of applications. The device integrates all RF, mixed-signal, and digital blocks necessary to provide all transmitter traffic and DPD observation receiver functions in a single device. Programmability allows the transmitter to be adapted for use in many time division duplexes (TDDs) and 2G/3G/4G/5G cellular standards. The ADRV9008-2 contains four high speed serial interface links for the transmitter chain, and four high speed links for the observation receiver chain. The links are JESD204B, Subclass 1 compliant. The ADRV9008-2 also provides tracking correction of dc offset QEC errors, and transmitter LO leakage to maintain high performance under varying temperatures and input signal conditions. The device also includes test modes that allow system designers to debug designs during prototyping and to optimize radio configurations. TRANSMITTER The ADRV9008-2 transmitter section consists of two identical and independently controlled channels that provide all digital processing, mixed-signal, and RF blocks necessary to implement a direct conversion system while sharing a common frequency synthesizer. The digital data from the JESD204B lanes pass through a fully programmable, 128-tap FIR filter with variable interpolation rates. The FIR output is sent to a series of interpolation filters that provide additional filtering and interpolation prior to reaching the DAC. Each 14-bit DAC has an adjustable sample rate. When converted to baseband analog signals, the inphase (I) and quadrature (Q) signals are filtered to remove sampling artifacts and are fed to the upconversion mixers. Each transmitter chain provides a wide attenuation adjustment range with fine granularity to optimize SNR. OBSERVATION RECEIVER The ADRV9008-2 contains an independent DPD observation receiver front end. The observation receiver shares the common frequency synthesizer with the transmitter. The observation receiver is a direct conversion system that contains a programmable attenuator stage, followed by matched I and Q mixers, baseband filters, and ADCs. The continuous time Σ-Δ ADCs have inherent antialiasing that reduces the RF filtering requirement. The ADC outputs can be conditioned further by a series of decimation filters and a programmable FIR filter with additional decimation settings. The sample rate of each digital filter block is adjustable by changing decimation factors to produce the desired output data rate. CLOCK INPUT The ADRV9008-2 requires a differential clock connected to the REF_CLK_IN_± pins. The frequency of the clock input must be between 10 MHz and 1000 MHz and must have very low phase noise because this signal generates the RF LO and internal sampling clocks. SYNTHESIZERS RF PLL The ADRV9008-2 contains a fractional-N PLL to generate the RF LO for the signal paths. The PLL incorporates an internal VCO and loop filter, requiring no external components. The LOs on multiple chips can be phase synchronized to support active antenna systems and beamforming applications. Clock PLL The ADRV9008-2 contains a PLL synthesizer that generates all the baseband related clock signals and serialization/deserialization (SERDES) clocks. This PLL is programmed based on the data rate and sample rate requirements of the system. SERIAL PERIPHERAL INTERFACE (SPI) The ADRV9008-2 uses an SPI interface to communicate with the baseband processor (BBP). This interface can be configured as a 4-wire interface with dedicated receiver and transmitter ports, or it can be configured as a 3-wire interface with a bidirectional data communications port. This bus allows the BBP to set all device control parameters using a simple address data serial bus protocol. Write commands follow a 24-bit format. The first five bits set the bus direction and the number of bytes to transfer. The next 11 bits set the address where data is written. The final 8 bits are the data to be transferred to the specific register address. Read commands follow a similar format with the exception that the first 16 bits are transferred on the SDIO pin and the final eight bits are read from the ADRV9008-2, either on the SDO pin in 4-wire mode or on the SDIO pin in 3-wire mode. JTAG BOUNDARY SCAN The ADRV9008-2 provides support for JTAG boundary scan. Five dual function pins are associated with the JTAG interface. Use these pins, listed in Table 5, to access the on-chip test access port. To enable the JTAG functionality, set the GPIO_3 pin through the GPIO_0 pin to 1001, and then pull the TEST pin high. POWER SUPPLY SEQUENCE The ADRV9008-2 requires a specific power-up sequence to avoid undesired power-up currents. In the optimal power-up sequence, the VDDD1P3_DIG and the VDDA1P3 supplies (VDDA1P3 includes all 1.3 V domains) power up first and at the same time. If these supplies cannot be powered up simultaneously, the VDDD1P3_DIG supply must power up first. Power up the Rev. 0 | Page 69 of 95 ADRV9008-2 Data Sheet VDDA_3P3, VDDA1P8_BB, VDDA1P8_TX, VDDA1P3_DES, and VDDA1P3_SER supplies after the 1.3 V supplies. The VDD_INTERFACE supply can be powered up at any time. Note that no device damage occurs if this sequence is not followed. However, failure to follow this sequence may result in higher than expected power-up currents. It is also recommended to toggle the RESET signal after power stabilizes, prior to configuration. The power-down sequence is not critical. If a power-down sequence is followed, remove the VDDD1P3_DIG supply last to avoid any back biasing of the digital control lines. GPIO_x PINS The ADRV9008-2 provides 19, 1.8 V to 2.5 V GPIO signals that can be configured for numerous functions. When configured as outputs, certain pins can provide real-time signal information to the BBP, allowing the BBP to determine observation receiver performance. A pointer register selects the information that is output to these pins. Signals used for manual gain mode, calibration flags, state machine states, and various observation receiver parameters are among the outputs that can be monitored on these pins. Additionally, certain pins can be configured as inputs and used for various functions, such as setting the observation receiver gain in real time. Twelve 3.3 V GPIO_x pins are also included on the device. These pins provide control signals to external components. AUXILIARY CONVERTERS AUXADC_x The ADRV9008-2 contains an auxiliary ADC that is multiplexed to four input pins (AUXADC_x). The auxiliary ADC is 12 bits with an input voltage range of 0.05 V to VDDA_3P3 − 0.05 V. When enabled, the auxiliary ADC is free running. The SPI reads provide the last value latched at the ADC output. The auxiliary ADC can also be multiplexed to a built in, diode-based temperature sensor. Auxiliary DAC x The ADRV9008-2 contains 10 identical auxiliary DACs (auxiliary DAC x) that can be used for bias or other system functionality. The auxiliary DACs are 10 bits, have an output voltage range of approximately 0.7 V to VDDA_3P3 − 0.3 V, and have an output drive of 10 mA. JESD204B DATA INTERFACE The digital data interface for the ADRV9008-2 uses JEDEC JESD204B Subclass 1. The serial interface operates at speeds of up to 12.288 Gbps. The benefits of the JESD204B interface include a reduction in required board area for data interface routing, resulting in smaller total system size. Four high speed serial lanes are provided for the transmitter, and four high speed lanes are provided for the observation receiver. The ADRV9008-2 supports single-lane or dual-lane interfaces as well as fixed and floating point data formats for observation receiver data. Table 6. Observation Path Interface Rates Bandwidth (MHz) 200 200 250 450 450 Output Rate (MSPS) 245.76 307.2 307.2 491.52 491.52 JESD204B Lane Rate Number of (Mbps) Lanes 9830.4 1 12288 1 12288 1 9830.4 2 4915.2 4 Table 7. Transmitter Interface Rates (Other Output Rates, Bandwidth, and JESD204B Lanes Also Supported) TRANSMIT HALF-BAND FILTER 2 1, 2 I/Q DAC TRANSMIT HALF-BAND FILTER 1 1, 2 TRANSMIT FIR FILTER (INTERPOLATION 1, 2, 4) Dual-Channel Operation JESD204B Lane JESD204B Number Rate (Mbps) of Lanes 9830.4 2 12288 2 12288 2 9830.4 4 QUADRATURE CORRECTION DIGITAL GAIN JESD204B 16833-309 Bandwidth (MHz) 200 200 250 450 Single-Channel Operation JESD204B Lane JESD204B Number Rate (Mbps) of Lanes 9830.4 1 12288 1 12288 1 9830.4 2 Input Rate (MSPS) 245.76 307.2 307.2 491.52 Figure 267. Transmitter Datapath Filter Implementation RECEIVE HALF-BAND 3 RECEIVE HALF-BAND 2 RECEIVE HALF-BAND 1 FIR (DEC 1, 2, 4) DC CORRECTION DIG GAIN JESD204B 16833-311 ADC Figure 268. Observation Receiver Datapath Filter Implementation Rev. 0 | Page 70 of 95 Data Sheet ADRV9008-2 APPLICATIONS INFORMATION PCB LAYOUT AND POWER SUPPLY RECOMMENDATIONS Overview The ADRV9008-2 device is a highly integrated RF agile transceiver with significant signal conditioning integrated on one chip. Due to the increased complexity of the device and its high pin count, careful PCB layout is important to get the optimal performance. This data sheet provides a checklist of issues to look for and guidelines on how to optimize the PCB to mitigate performance issues. The goal of this data sheet is to help achieve the optimal performance from the ADRV9008-2 while reducing board layout effort. This data sheet assumes that the reader is an experienced analog and RF engineer with an understanding of RF PCB layout and RF transmission lines. This data sheet discusses the following issues and provides guidelines for system designers to achieve the optimal performance for the ADRV9008-2: • • • • • • • PCB material and stack up selection Fanout and trace space layout guidelines Component placement and routing guidelines RF and JESD204B transmission line layout Isolation techniques used on the ADRV9008-2W/PCBZ Power management considerations Unused pin instructions 13 are crucial to maintaining the RF signal integrity and, ultimately, the ADRV9008-2 performance. Layer 3 and Layer 12 are used to route power supply domains. To keep the RF section of the ADRV9008-2 isolated from the fast transients of the digital section, the JESD204B interface lines are routed on Layer 5 and Layer 10. Those layers have impedance control set to a 100 Ω differential. The remaining digital lines from the ADRV9008-2 are routed on Inner Layer 7 and Inner Layer 8. RF traces on the outer layers must be a controlled impedance to get the best performance from the device. The inner layers on this board use 0.5 ounce copper or 1 ounce copper. The outer layers use 1.5 ounce copper so that the RF traces are less prone to pealing. Ground planes on this board are full copper floods with no splits except for vias, through-hole components, and isolation structures. The ground planes must route entirely to the edge of the PCB under the Surface-Mount Type A (SMA) connectors to maintain signal launch integrity. Power planes can be pulled back from the board edge to decrease the risk of shorting from the board edge. Figure 269 shows the PCB stackup used for the ADRV90082W/PCBZ. Table 8 and Table 9 list the single-ended and differential impedence for the stackup shown in Figure 269. The dielectric material used on the top and the bottom layers is 8 mil Rogers 4350B. The remaining dielectric layers are FR4-370 HR. The board design uses the Rogers laminate for the top and the bottom layers for the low loss tangent at high frequencies. The ground planes under the Rogers laminate (Layer 2 and Layer 13) are the reference planes for the transmission lines routed on the outer surfaces. These layers are solid copper planes without any splits under the RF traces. Layer 2 and Layer Rev. 0 | Page 71 of 95 16833-434 PCB MATERIAL AND STACKUP SELECTION Figure 269. ADRV9008-2W/PCBZ Trace Impedance and Stackup ADRV9008-2 Data Sheet Table 8. Evaluation Board Single-Ended Impedance and Stackup1 Layer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 Board Copper % N/A 65 50 65 50 65 50 50 65 50 65 50 65 Starting Copper (oz.) 0.5 1 0.5 1 0.5 1 0.5 0.5 1 0.5 0.5 1 1 0.5 Finished Copper (oz.) 1.71 1 1 1 0.5 1 0.5 0.5 1 1 1 1 1 1.64 Single-Ended Impedance 50 Ω ±10% N/A N/A N/A 50 Ω ±10% N/A 50 Ω ±10% 50 Ω ±10% N/A 50 Ω ±10% N/A N/A N/A 50 Ω ±10% Designed Trace SingleEnded (inches) 0.0155 N/A N/A N/A 0.0045 N/A 0.0049 0.0049 N/A 0.0045 N/A N/A N/A 0.0155 Finished Trace SingleEnded (inches) 0.0135 N/A N/A N/A 0.0042 N/A 0.0039 0.0039 N/A 0.0039 N/A N/A N/A 0.0135 Calculated Impedance (Ω) 49.97 N/A N/A N/A 49.79 N/A 50.05 50.05 N/A 49.88 N/A N/A N/A 49.97 SingleEnded Reference Layers 2 N/A N/A N/A 4, 6 N/A 6, 9 6, 9 N/A 9, 11 N/A N/A N/A 13 N/A means not applicable. Table 9. Evaluation Board Differential Impedance and Stackup1 Layer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 Differential Impedance 100 Ω ± 10% 50 Ω ± 10% N/A N/A N/A 100 Ω ±10% N/A 100 Ω ±10% 100 Ω ±10% N/A 100 Ω ±10% N/A N/A N/A N/A 100 Ω ±10% 50 Ω ±10% Designed Trace (inches) 0.008 0.0032 N/A N/A N/A 0.0036 N/A 0.0036 0.0038 N/A 0.0036 N/A N/A N/A N/A 0.008 0.032 Designed Gap Differential (inches) 0.006 0.004 0.0064 0.0064 0.0062 0.0064 0.006 Finished Trace (inches) 0.007 0.0304 N/A N/A N/A 0.0034 N/A 0.0034 0.0034 N/A 0.003 N/A N/A N/A N/A 0.007 0.004 N/A means not applicable. Rev. 0 | Page 72 of 95 Finished Gap Differential (inches) 0.007 0.0056 0.0065 0.0066 0.0066 0.007 0.007 Calculated Impedance (Ω) 99.55 50.11 N/A N/A N/A 99.95 N/A 100.51 100.51 N/A 100.80 N/A N/A N/A N/A 99.55 50.11 Differential Reference Layers 2 2 N/A N/A N/A 4, 6 N/A 6, 9 6, 9 N/A 9, 11 N/A N/A N/A N/A 13 13 Data Sheet ADRV9008-2 FANOUT AND TRACE SPACE GUIDELINES The ADRV9008-2 device uses a 196-ball chip scale package ball grid array (CSP_BGA), 12 × 12 mm package. The pitch between the pins is 0.8 mm. This small pitch makes it impractical to route all signals on a single layer. RF pins are placed on the outer edges of the ADRV9008-2 package. The location of the pins helps route the critical signals without a fanout via. Each digital signal is routed from the BGA pad using a 4.5 mil trace. The trace is connected to the BGA using a via in the pad structure. The signals are buried in the inner layers of the board for routing to other parts of the system. The JESD204B interface signals are routed on two signal layers that use impedance control (Layer 5 and Layer 10). The spacing between the BGA pads is 17.5 mil. After the signal is on the inner layers, a 3.6 mil trace (50 Ω) connects the JESD204B signal to the field programmable gate array (FPGA) mezzanine card (FMC) connector. The recommended BGA land pad size is 15 mil. Figure 270 shows the fanout scheme of the ADRV9008-2W/PCBZ. As mentioned before, the ADRV9008-2W/PCBZ uses a via in the pad technique. This routing approach can be used for the ADRV9008-2 if there are no issues with manufacturing capabilities. 4.5mil TRACE AIR GAP = 17.5mil JESD204B INTERFACE TRACE WIDTH = 3.6mil PAD SIZE = 15mil 16833-435 VIA SIZE = 14mil Figure 270. Trace Fanout Scheme on the ADRV9008-2W/PCBZ (PCB Layer Top and Layer 5 Enabled) Rev. 0 | Page 73 of 95 ADRV9008-2 Data Sheet COMPONENT PLACEMENT AND ROUTING GUIDELINES The observation receiver and transmitter baluns and the matching circuits affect the overall RF performance of the ADRV9008-2 transceiver. Make every effort to optimize the component selection and placement to avoid performance degradation. The RF Routing Guidelines section describes proper matching circuit placement and routing in more detail. Refer to the RF Port Interface Information section for more information. The ADRV9008-2 transceiver requires few external components to function, but those that are used require careful placement and routing to optimize performance. This section provides a checklist for properly placing and routing critical signals and components. Signals with Highest Routing Priority To achieve the desired level of isolation between RF signal paths, use the technique described in the Isolation Techniques Used on the ADRV9008-2W/PCBZ section in customer designs. RF lines and JESD204B interface signals are the signals that are most critical and must be routed with the highest priority. Figure 271 shows the general directions in which each of the signals must be routed so that they can be properly isolated from noisy signals. In cases in which ADRV9008-2 is used, install a 10 µF capacitor near the transmitter balun(s) VDDA1P8_TX dc feed(s) for RF transmitter outputs. This acts as a reservoir for the transmitter supply current. The Transmitter Balun DC Feed Supplies section discusses more details about the transmitter output power supply configuration. VSSA ORX2_IN+ ORX2_IN– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA ORX1_IN+ ORX1_IN– VSSA VDDA1P3_ RX_RF VSSA VSSA VSSA VSSA VSSA RF_EXT_ LO_I/O– RF_EXT_ LO_I/O+ VSSA VSSA VSSA VSSA VSSA VSSA GPIO_3p3_0 GPIO_3p3_3 VDDA1P3_ RX_TX VSSA VDDA1P3_ RF_VCO_LDO VDDA1P3_ RF_VCO_LDO VDDA1P3_ RF_LO VSSA VDDA1P3_ AUX_VCO_ LDO VSSA VDDA_3P3 GPIO_3p3_9 RBIAS GPIO_3p3_1 GPIO_3p3_4 VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA1P1_ AUX_VCO VSSA VSSA GPIO_3p3_8 GPIO_3p3_10 GPIO_3p3_2 GPIO_3p3_5 GPIO_3p3_6 VDDA1P8_BB VDDA1P3_BB VSSA REF_CLK_IN+ REF_CLK_IN– VSSA AUX_ SYNTH_OUT AUXADC_3 VDDA1P8_TX GPIO_3p3_7 GPIO_3p3_11 VSSA VSSA AUXADC_0 AUXADC_1 VSSA VSSA VSSA VSSA VSSA VSSA AUXADC_2 VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA1P3_ CLOCK_ SYNTH VSSA VDDA1P3_ RF_SYNTH VDDA1P3_ AUX_SYNTH RF_SYNTH_ VTUNE VSSA VSSA VSSA VSSA VSSA TX2_OUT– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA TX1_OUT+ TX2_OUT+ VSSA GPIO_18 RESET GP_ INTERRUPT TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA TX1_OUT– VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CS GPIO_14 GPIO_9 VSSA VSSA VSSA VSSA SYNCIN1– SYNCIN1+ GPIO_6 GPIO_7 VSSD VDDD1P3_ DIG VDDD1P3_ DIG VSSD GPIO_15 GPIO_8 SYNCOUT1– SYNCOUT1+ VDDA1P1_ CLOCK_VCO VSSA SYNCIN0– SYNCIN0+ ORX1_ ENABLE TX1_ ENABLE ORX2_ ENABLE TX2_ ENABLE VSSA GPIO_17 GPIO_16 VDD_ INTERFACE SYNCOUT0– SYNCOUT0+ VDDA1P3_ CLOCK_ VCO_ LDO VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA VDDA1P3_ SER VDDA1P3_ DES SERDIN1– SERDIN1+ SERDIN0– SERDIN0+ VSSA VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+ VDDA1P3_ SER VDDA1P3_ DES VSSA SERDIN3– SERDIN3+ SERDIN2– SERDIN2+ 16833-436 AUX_SYNTH_ VTUNE VDDA1P1_ RF_VCO Figure 271. RF Input/Output, REF_CLK_IN±, and JESD204B Signal Routing Guidelines Rev. 0 | Page 74 of 95 Data Sheet ADRV9008-2 Figure 272 shows placement for ac coupling capacitors and a 100 Ω termination resistor near the ADRV9008-2 REF_CLK_IN± pins. Shield the traces with ground flooding that is surrounded with vias staggered along the edge of the trace pair. The trace pair creates a shielded channel that shields the reference clock from any interference from other signals. Refer to the ADRV90082W/PCBZ layout, including board support files included with the evaluation board software, for exact details. Routing Guidelines section outlines recommendations for JESD204B interface routing. Provide appropriate isolation between interface differential pairs. The Isolation Between JESD204B Lines section provides guidelines for optimizing isolation. The RF_EXT_LO_I/O− pin (B7) and the RF_EXT_LO_I/O+ pin (B8) on the ADRV9008-2 are internally dc biased. If an external LO is used, connect it via ac coupling capacitors. Route the JESD204B interface at the beginning of the PCB design and with the same priority as the RF signals. The RF AC COUPLING CAPS 100ΩTERMINATION RESISTOR 16833-439 TO ADRV9008-2 BGA BALLS Figure 272. REF_CLK_IN± Routing Recommendation Rev. 0 | Page 75 of 95 ADRV9008-2 Data Sheet Signals with Second Routing Priority When the recommendation is to use a trace to connect power to a particular domain, ensure that this trace is surrounded by ground. Figure 273 shows an example of such traces routed on the ADRV9008-2W/PCBZ on Layer 12. Each trace is separated from any other signal by the ground plane and vias. Separating the traces from other signals is essential to providing necessary isolation between the ADRV9008-2 power domains. 16833-440 Power supply quality has direct impact on overall system performance. To achieve optimal performance, users should follow recommendations regarding ADRV9008-2 power supply routing. The following recommendations outline how to route different power domains that can be connected together directly and that can be tied to the same supply, but are separated by a 0 Ω placeholder resistor or ferrite bead (FB). Figure 273. Layout Example of Power Supply Domains Routed with Ground Shielding (Layer 12 to Power) Rev. 0 | Page 76 of 95 Data Sheet ADRV9008-2 capacitors are placed. The recommendation is to connect a ferrite bead between a power plane and the ADRV9008-2 at a distance away from the device The ferrite bead and the resevoir capacitor provide stable voltage to the ADRV9008-2 during operation by isolating the pin or pins that the network is connected to from the power plane. Then, shield that trace with ground and provide power to the power pins on the ADRV9008-2. Place a 100 nF capacitor near the power supply pin with the ground side of the bypass capacitor placed so that ground currents flow away from other power pins and the bypass capacitors. Each power supply pin requires a 0.1 µF bypass capacitor near the pin at a minimum. Place the ground side of the bypass capacitor so that ground currents flow away from other power pins and the bypass capacitors. For the domains shown in Figure 274, like the domains powered through a 0 Ω placeholder resistor or ferrite bead, place the 0 Ω placeholder resistors or ferrite beads further away from the device. Space 0 Ω placeholder resistors or ferrite beads apart from each other to ensure the electric fields on the ferrite beads do not influence each other. Figure 275 shows an example of how the ferrite beads, reservoir capacitors, and decoupling TRACE THROUGH 0.1Ω RESISTOR TO AP TRACE THROUGH 0Ω RES. TO 1.3V ANALOG PLANE (AP) MAINTAIN LOWEST POSSIBLE IMPEDANCE TRACE THROUGH 0Ω TO AP TRACE THROUGH 0Ω TO 1.8V PLANE TRACE THROUGH 0Ω TO AP TRACE THROUGH 0Ω TO AP TRACE THROUGH 1Ω RESISTOR TO AP TRACE THROUGH 0Ω TO AP VSSA ORX2_IN+ ORX2_IN– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA ORX1_IN+ ORX1_IN– VSSA VDDA1P3_ RX_RF VSSA VSSA VSSA VSSA VSSA RF_EXT_ LO_I/O– RF_EXT_ LO_I/O+ VSSA VSSA VSSA VSSA VSSA VSSA GPIO_3p3_0 GPIO_3p3_3 VDDA1P3_ RX_TX VSSA VDDA1P3_ RF_VCO_LDO VDDA1P3_ RF_VCO_LDO VDDA1P3_ RF_LO VSSA VDDA1P3_ AUX_VCO_ LDO VSSA VDDA_3P3 GPIO_3p3_9 RBIAS GPIO_3p3_1 GPIO_3p3_4 VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA1P1_ AUX_VCO VSSA VSSA GPIO_3p3_8 GPIO_3p3_10 GPIO_3p3_2 GPIO_3p3_5 GPIO_3p3_6 VDDA1P8_BB VDDA1P3_BB VSSA REF_CLK_IN+ REF_CLK_IN– VSSA AUX_ SYNTH_OUT AUXADC_3 VDDA1P8_TX GPIO_3p3_7 GPIO_3p3_11 VSSA VSSA AUXADC_0 AUXADC_1 VSSA VSSA VSSA VSSA VSSA VSSA AUXADC_2 VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA1P3_ CLOCK_ SYNTH VSSA VDDA1P3_ RF_SYNTH VDDA1P3_ AUX_SYNTH RF_SYNTH_ VTUNE VSSA VSSA VSSA VSSA VSSA TX2_OUT– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA TX1_OUT+ TX2_OUT+ VSSA GPIO_18 RESET GP_ INTERRUPT TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA TX1_OUT– VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CS GPIO_14 GPIO_9 VSSA VSSA VSSA VSSA SYNCIN1– SYNCIN1+ GPIO_6 GPIO_7 VSSD VDDD1P3_ DIG VDDD1P3_ DIG VSSD GPIO_15 GPIO_8 SYNCOUT1– SYNCOUT1+ VDDA1P1_ CLOCK_VCO VSSA SYNCIN0– SYNCIN0+ ORX1_ ENABLE TX1_ ENABLE ORX2_ ENABLE TX2_ ENABLE VSSA GPIO_17 GPIO_16 VDD_ INTERFACE SYNCOUT0– SYNCOUT0+ TRACE THROUGH FB TO INTERFACE SUPPLY VDDA1P3_ CLOCK_ VCO_ LDO VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA VDDA1P3_ SER VDDA1P3_ DES SERDIN1– SERDIN1+ SERDIN0– SERDIN0+ VSSA TRACE THROUGH 0Ω TO 1.3V JESD204B SUPPLY VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+ VDDA1P3_ SER VDDA1P3_ DES VSSA SERDIN3– SERDIN3+ SERDIN2– SERDIN2+ AUX_SYNTH_ VTUNE VDDA1P1_ RF_VCO TRACE THROUGH FB TO 3.3V PLANE TRACE THROUGH 0Ω TO 1.8V PLANE TRACE THROUGH 0Ω TO AP WIDE TRACE TO 1.3V DIGITAL SUPPLY HIGH CURRENT TRACE THROUGH FB TO 1.3V JESD204B SUPPLY Figure 274. Power Supply Domains Interconnection Guidelines Rev. 0 | Page 77 of 95 16833-441 TRACE THROUGH 0Ω TO AP TRACE THROUGH 0Ω TO AP ADRV9008-2 Data Sheet 0Ω RESISTOR PLACEHOLDERS FOR FERRITE BEADS RESERVOIR CAPACITORS DUT 1µ + 100nF bypass CAPS ORIENTED SUCH THAT CURRENTS FLOW AWAY FROM OTHER POWER PINS PLACEHOLDERS FOR FERRITE BEADS 16833-444 0Ω RESISTOR Figure 275. Placement Example of 0 Ω Resistor Placeholders for Ferrite Beads, Reservoir and Bypass Capacitors on the ADRV9008-2W/PCBZ (Layer 12 to Power Layer and Bottom Layer) Rev. 0 | Page 78 of 95 Data Sheet ADRV9008-2 Signals with Lowest Routing Priority When routing analog signals such as GPIO_3p3_x/Auxiliary DAC x or AUXADC_x, it is recommended to route them away from the digital section (Row H through Row P). Do not cross the analog section of the ADRV9008-2 highlighted by a reddotted line in Figure 276 by any digital signal routing. As a last step while designing the PCB layout, route signals shown in Figure 276. The following list outlines the recommended order of signal routing: 2. 3. 4. Use ceramic 1 µF bypass capacitors at the VDDA1P1_RF_ VCO, VDDA1P1_AUX_VCO, and VDDA1P1_CLOCK_ VCO pins. Place them as close as possible to the ADRV9008-2 device with the ground side of the bypass capacitor placed so that ground currents flow away from other power pins and the bypass capacitors, if at all possible. Connect a 14.3 kΩ resistor to the RBIAS pin (C14). This resistor must have a 1% tolerance. Pull the TEST pin (J6) to ground for normal operation. The device has support for JTAG boundary scan, and this pin is used to access that function. Refer to the JTAG Boundary Scan section for JTAG boundary scan information. Pull the RESET pin (J4) high with a 10 kΩ resistor to VDD_INTERFACE for normal operation. To reset the device, drive the RESET pin low. When routing digital signals from rows H and below, it is important to route them away from the analog section (Row A through Row G). Do not cross the analog section of the ADRV9008-2 highlighted by a red-dotted line in Figure 276 by any digital signal routing. RF AND JESD204B TRANSMISSION LINE LAYOUT RF Routing Guidelines The ADRV9008-2W/PCBZ use microstrip type lines for observation receiver and transmitter RF traces. In general, Analog Devices, Inc. does not recommend using vias to route RF traces unless a direct line route is not possible. VSSA ORX2_IN+ ORX2_IN– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA ORX1_IN+ ORX1_IN– VSSA VDDA1P3_ RX_RF VSSA VSSA VSSA VSSA VSSA RF_EXT_ LO_I/O– RF_EXT_ LO_I/O+ VSSA VSSA VSSA VSSA VSSA VSSA GPIO_3p3_0 GPIO_3p3_3 VDDA1P3_ RX_TX VSSA VDDA1P3_ RF_VCO_LDO VDDA1P3_ RF_VCO_LDO VDDA1P3_ RF_LO VSSA VDDA1P3_ AUX_VCO_ LDO VSSA VDDA_3P3 GPIO_3p3_9 RBIAS GPIO_3p3_1 GPIO_3p3_4 VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA1P1_ AUX_VCO VSSA VSSA GPIO_3p3_8 GPIO_3p3_10 GPIO_3p3_2 GPIO_3p3_5 GPIO_3p3_6 VDDA1P8_BB VDDA1P3_BB VSSA REF_CLK_IN+ REF_CLK_IN– VSSA AUX_ SYNTH_OUT AUXADC_3 VDDA1P8_TX GPIO_3p3_7 GPIO_3p3_11 VSSA VSSA AUXADC_0 AUXADC_1 VSSA VSSA VSSA VSSA VSSA VSSA AUXADC_2 VSSA VSSA VSSA VSSA VSSA VSSA VSSA VDDA1P3_ CLOCK_ SYNTH VSSA VDDA1P3_ RF_SYNTH VDDA1P3_ AUX_SYNTH RF_SYNTH_ VTUNE VSSA VSSA VSSA VSSA VSSA TX2_OUT– VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA VSSA GPIO_12 GPIO_11 VSSA TX1_OUT+ TX2_OUT+ VSSA GPIO_18 RESET GP_ INTERRUPT TEST GPIO_2 GPIO_1 SDIO SDO GPIO_13 GPIO_10 VSSA TX1_OUT– VSSA VSSA SYSREF_IN+ SYSREF_IN– GPIO_5 GPIO_4 GPIO_3 GPIO_0 SCLK CS GPIO_14 GPIO_9 VSSA VSSA VSSA VSSA SYNCIN1– SYNCIN1+ GPIO_6 GPIO_7 VSSD VDDD1P3_ DIG VDDD1P3_ DIG VSSD GPIO_15 GPIO_8 SYNCOUT1– SYNCOUT1+ VDDA1P1_ CLOCK_VCO VSSA SYNCIN0– SYNCIN0+ ORX1_ ENABLE TX1_ ENABLE ORX2_ ENABLE TX2_ ENABLE VSSA GPIO_17 GPIO_16 VDD_ INTERFACE SYNCOUT0– SYNCOUT0+ VDDA1P3_ CLOCK_ VCO_ LDO VSSA SERDOUT3– SERDOUT3+ SERDOUT2– SERDOUT2+ VSSA VDDA1P3_ SER VDDA1P3_ DES SERDIN1– SERDIN1+ SERDIN0– SERDIN0+ VSSA VSSA VSSA SERDOUT1– SERDOUT1+ SERDOUT0– SERDOUT0+ VDDA1P3_ SER VDDA1P3_ DES VSSA SERDIN3– SERDIN3+ SERDIN2– SERDIN2+ 1µF CAPACITOR 1µF CAPACITOR 1µF CAPACITOR AUX_SYNTH_ VTUNE VDDA1P1_ RF_VCO 14.3kΩ RESISTOR ALL DIGITAL GPIO SIGNALS ROUTED BELOW THE RED LINE 16833-445 1. Figure 276. Auxiliary ADC, Analog, and Digital GPIO Signals Routing Guidelines Rev. 0 | Page 79 of 95 ADRV9008-2 Data Sheet Differential lines from the balun to the observation receiver and transmitter pins need to be as short as possible. Make the length of the single-ended transmission line also short to minimize the effects of parasitic coupling. It is important to note that these traces are the most critical when optimizing performance and are, therefore, routed before any other routing. These traces have the highest priority if trade-offs are needed. Figure 277 and Figure 278 show pi matching networks on the single-ended side of the baluns. The observation receiver front end is dc biased internally, so the differential side of the balun is ac-coupled. The system designer can optimize the RF performance with a proper selection of the balun, matching components, and ac coupling capacitors. The external LO traces and the REF_CLK_IN± traces may require matching components as well to ensure optimal performance. Figure 277. Pi Network Matching Components Available on Transmitter Outputs 16833-449 Refer to the RF Port Interface Information section for more information on RF matching recommendations for the device. 16833-448 All the RF signals mentioned previously must have a solid ground reference under each trace. Do not run any of the critical traces over a section of the reference plane that is discontinuous. The ground flood on the reference layer must extend all the way to the edge of the board. This flood length ensures signal integrity for the SMA launch when an edge launch connector is used. Figure 278. Pi Network Matching Components Available on Observation Receiver Inputs Rev. 0 | Page 80 of 95 Data Sheet ADRV9008-2 Transmitter Balun DC Feed Supplies Each transmitter requires approximately 200 mA supplied through an external connection. On the ADRV9008-2 and ADRV9009 evaluation boards, bias voltages are supplied at the dc feed of the baluns. Layout of both boards allows the use of external chokes to provide a 1.8 V power domain to the ADRV9008-2 outputs. This configuration is useful in scenarios where a balun used at the transmitter output is not capable of conducting the current necessary for the transmitter outputs to operate. To reduce switching transients when attenuation settings change, power the balun dc feed or transmitter output chokes directly by the 1.8 V plane. Design the geometry of the 1.8 V plane so that each balun supply or each set of two chokes is isolated from the other. This geometry can affect tansmitter to transmitter isolation. Figure 279 shows the layout configuration used on the ADRV9008-2W/PCBZ. 16833-450 Tx OUTPUT / BALUN 1.8V SUPPLY FEED Figure 279. Transmitter Power Supply Planes (VDDA1P8_TX) on the ADRV9008-2W/PCBZ Rev. 0 | Page 81 of 95 ADRV9008-2 Data Sheet Both the positive and negative transmitter pins must be biased with 1.8 V. This biasing is accomplished on the evaluation board through dc capacitors chokes and decoupling capacitors, as shown in Figure 280. Match both chokes and their layout to avoid potential current spikes. A difference in parameters between both chokes can cause unwanted emission at transmitter outputs. Place the decoupling capacitors that are near the transmitter balun as close as possible to the dc feed of the balun or the ground pin. Make orientation of the capacitor perpendicular to the device so that the return current forms as small a loop as possible with the ground pins surrounding the transmitter input. A combination network of capacitors is used to provide a wideband and low impedance ground path and helps to eliminate transmitter spectrum spurs and dampens the transients. TX OUTPUT Route the differential pairs on a single plane using a solid ground plane as a reference on the layers above and/or below these traces. All JESD204B lane traces must be impedance controlled to achieve 50 Ω to ground. It is recommended that the differential pair be coplanar and loosely coupled. An example of a typical configuration is a 5 mil trace width and 15 mil edge to edge spacing, with the trace width maximized as shown in Figure 281. Match trace widths with pin and ball widths while maintaining impedance control. If possible, use 1 oz. copper trace widths of at least 8 mil (200 µm). The coupling capacitor pad size must match JESD204B lane trace widths If trace width does not match pad size, use a smooth transition between different widths. The pad area for all connector and passive component choices must be minimized due to a capacitive plate effect that leads to problems with signal integrity. DC FEED CHOKES Reference planes for impedance controlled signals must not be segmented or broken for the entire length of a trace. DECOUPLING CAPACITORS 1.8V TX POWER DOMAIN FEED BALUN Routing Recommendations The REF_CLK_IN± signal trace and the SYSREF signal trace are impedance controlled for characteristic impedence (ZO) = 50 Ω. CONDUCTING RESISTORS Stripline Transmission Lines vs. Microstrip Transmission Lines Stripline transmission lines have less singal loss and emit less electromagnetic interference than microstrip transmission lines. However, stripline transmission lines require the use of vias that add line inductance, increasing the difficulty of controlling the impedance. BALUN DECOUPLING CAPACITORS 16833-451 Microstrip transmission lines are easier to implement if the component placement and density allow routing on the top layer. Microstrip transmission lines make controlling the impedance easier. Figure 280. Transmitter DC Chokes and Balun Feed Supply JESD204B Trace Routing Recommendations The ADRV9008-2 transceiver uses the JESD204B, high speed serial interface. To ensure optimal performance of this interface, keep the differential traces as short as possible by placing the ADRV9008-2 as close as possible to the FPGA or BBP, and route the traces directly between the devices. Use a PCB material with a low dielectric constant (< 4) to minimize loss. For distances greater than 6 inches, use a premium PCB material, such as RO4350B or RO4003C. If the top layer of the PCB is used by other circuits or signals, or if the advantages of stripline transmission lines are more desirable over the advantages of microstrip transmission lines, follow these recommendations: • • • • Minimize the number of vias. Use blind vias where possible to eliminate via stub effects, and use micro vias to minimize via inductance. When using standard vias, use a maximum via length to minimize the stub size. For example, on an 8-layer board, use Layer 7 for the stripline pair. Place a pair of ground vias in close proximity to each via pair to minimize the impedance discontinuity. Route the JESD204B lines on the top side of the board as a differential 100 Ω pair (microstrip). For the ADRV90082W/PCBZ, the JESD204B differential signals are routed on inner layers of the board (Layer 5 and Layer 10) as differential Rev. 0 | Page 82 of 95 Data Sheet ADRV9008-2 100 Ω pairs (stripline). To minimize potential coupling, these signals are placed on an inner layer using a via embedded in the component footprint pad where the ball connects to the PCB. The ac coupling capacitors (100 nF) on these signals are placed near the connector and away from the chip to minimize coupling. The JESD204B interface can operate at frequencies of up to 12 GHz. Ensure that signal integrity from the chip to the connector is maintained. ISOLATION TECHNIQUES USED ON THE ADRV9008-2W/PCBZ To meet these isolation goals with significant margin, isolation structures are introduced. Figure 282 shows the isolation structures used on the ADRV90082W/PCBZ. These structures consist of a combination of slots and square apertures. These structures are present on every copper layer of the PCB stack. The advantage of using square apertures is that signals can be routed between the openings without affecting the isolation benefits of the array of apertures. When using these isolation structures, make sure to place ground vias around the slots and apertures. Isolation Goals Significant isolation challenges were overcome in designing the ADRV9008-2W/PCBZ. The following isolation requirements are used to accurately evaluate the ADRV9008-2 transceiver performance: Transmitter to transmitter, 75 dB out to 6 GHz Transmitter to observation receiver, 65 dB out to 6 GHz Tx DIFF A Tx DIFF B TIGHTLY COUPLED DIFFERENTIAL Tx LINES Tx DIFF A Tx DIFF B LOOSELY COUPLED DIFFERENTIAL Tx LINES 16833-452 Figure 281. Routing JESD204B, Differential A and Differential B Correspond to Differential Positive Signals or Negative Signals (One Differential Pair) 16833-453 • • Figure 282. Isolation Structures on the ADRV9008-2W/PCBZ Rev. 0 | Page 83 of 95 Data Sheet 16833-454 ADRV9008-2 Figure 283. Current Steering Vias Placed Next to Isolation Structures Figure 283 outlines the methodology used on the ADRV90082W/PCBZ. When using slots, ground vias must be placed at the ends of the slots and along the sides of the slots. When using square apertures, at least one single ground via must be placed adjacent to each square. These vias must be through-hole vias from the top to the bottom layer. The function of these vias is to steer return current to the ground planes near the apertures. For accurate slot spacing and square apertures layout, use simulation software when designing a PCB for the ADRV9008-2 transceiver. Spacing between square apertures must be no more than 1/10 of a wavelength. Calculate the wavelength using Equation 1: 300 Wavelength (m) = Frequency (MHz) × E (1) R where ER is the dielectric constant of the isolator material. For RO4003C material, microstrip structure (+ air) ER = 2.8. For FR4370HR material, stripline structure ER = 4.1. For example, if the maximum RF signal frequency is 6 GHz, and ER = 2.8 for RO4003C material, microstrip structure (+ air), the minimum wavelength is approximately 29.8 mm. To follow the 1/10 wavelength spacing rule, square aperture spacing must be 2.98 mm or less. Isolation Between JESD204B Lines The JESD204B interface uses eight line pairs that can operate at speeds of up to 12 GHz. When configuring the PCB layout, ensure these lines are routed according to the rules outlined in the JESD204B Trace Routing Recommendations section. In addition, use isolation techniques to prevent crosstalk between different JESD204B lane pairs. Figure 284 shows a technique used on the ADRV9008-2W/PCBZ that involves via fencing. Placing ground vias around each JESD204B pair provides isolation and decreases crosstalk. The spacing between vias is 1.2 mm. Figure 284 shows the rule provided in Equation 1 JESD204B lines are routed on Layer 5 and Layer 10 so that the lines use stripline structures. The dielectric material used in the inner layers of the ADRV9008-2W/PCBZ PCB is FR4-370HR. For accurate spacing of the JESD204B fencing vias, use layout simulation software. Input the following data into Equation 1 to calculate the wavelength and square aperture spacing: • • The maximum JESD204B signal frequency is approximately 12 GHz. For FR4-370HR material, stripline structure, ER = 4.1, the minimum wavelength is approximately 12.4 mm. To follow the 1/10 wavelength spacing rule, spacing between vias must be 1.24 mm or less. The minimum spacing recommendation according to transmission line theory is 1/4 wavelength. Rev. 0 | Page 84 of 95 ADRV9008-2 16833-455 Data Sheet 1.24mm Figure 284. Via Fencing Around JESD204B Lines, PCB Layer 10 RF PORT INTERFACE INFORMATION RF Port Impedance Data This section details the RF transmitter and observation receiver interfaces for optimal device performance. This section also includes data for the anticipated ADRV9008-2 RF port impedance values and examples of impedance matching networks used in the evaluation platform. This section also provides information on board layout techniques and balun selection guidelines. This section provides the port impedance data for all transmitters and observation receivers in the ADRV9008-2 integrated transceiver. Please note the following: The ADRV9008-2 is a highly integrated transceiver with transmit and observation (DPD) receive signal chains. External impedance matching networks are required on transmitter and observation receiver ports to achieve performance levels indicated on the data sheet. • • • • Analog Devices recommends the use of simulation tools in the design and optimization of impedance matching networks. To achieve the closest match between computer simulated results and measured results, accurate models of the board environment, surface-mount device (SMD) components (including baluns and filters), and ADRV9008-2 port impedances are required. Rev. 0 | Page 85 of 95 ZO is defined as 50 Ω. The ADRV9008-2 ball pads are the reference plane for this data. Single-ended mode port impedance data is not available. However, a rough assessment is possible by taking the differential mode port impedance data and dividing both the real and imaginary components by 2. Contact Analog Devices applications engineering for the impedance data in Touchstone format. ADRV9008-2 Data Sheet 1.0 2.0 0.5 M28 M27 M29 0.2 5.0 M26 S91,1) m21 FREQUENCY = 100MHz S(1,1) = 0.143/–7.865 IMPEDANCE = 66.439 – j2.654 m22 FREQUENCY = 300MHz S(1,1) = 0.141/–25.589 IMPEDANCE = 64.063 – j7.987 m23 FREQUENCY = 500MHz S(1,1) = 0.145/–42.661 IMPEDANCE = 60.623 – j12.201 m24 FREQUENCY = 1GHz S(1,1) = 0.164/–84.046 IMPEDANCE = 49.000 + j16.447 m25 FREQUENCY = 2GHz S(1,1) = 0.247/–155.186 IMPEDANCE = 31.131 – j6.860 0 M25 M21 M22 M24 M23 –0.2 –5.0 –0.5 m26 FREQUENCY = 3GHz S(1,1) = 0.368/150.626 IMPEDANCE = 24.355 + j10.153 m27 FREQUENCY = 4GHz S(1,1) = 0.484/107.379 IMPEDANCE = 25.118 + j30.329 m28 FREQUENCY = 5GHz S(1,1) = 0.569/70.352 IMPEDANCE = 35.932 + j56.936 m29 FREQUENCY = 6GHz S(1,1) = 0.614/36.074 IMPEDANCE = 81.032 + j94.014 –2.0 16833-458 –1.0 FREQUENCY (0.000Hz TO 6.000Hz) Figure 285. Transmitter 1 and Transmitter 2 SEDZ and Parallel Equivalent Differential Impedance (PEDZ) Data 1.0 2.0 0.5 0.2 M23 5.0 M22 M21 0 M20 M19 M15 M16 M17 M18 –0.2 –5.0 –0.5 m20 FREQUENCY = 3GHz S(1,1) = 0.104/–66.720 IMPEDANCE = 53.262 – j10.292 m21 FREQUENCY = 4GHz S(1,1) = 0.116/104.276 IMPEDANCE = 46.060 + j10.522 m22 FREQUENCY = 5GHz S(1,1) = 0.342/75.761 IMPEDANCE = 46.551 + j34.914 m23 FREQUENCY = 6GHz S(1,1) = 0.525/53.007 IMPEDANCE = 56.249 + j65.146 –2.0 –1.0 FREQUENCY (0Hz TO 6GHz) Figure 286. Observation Receiver 1 and Observation Receiver 2 SEDZ and PEDZ Data Rev. 0 | Page 86 of 95 16833-460 S(1,1) m15 FREQUENCY = 100MHz S(1,1) = 0.391/–1.848 IMPEDANCE = 114.099 – j3.397 m16 FREQUENCY = 300MHz S(1,1) = 0.389/–5.601 IMPEDANCE = 112.639 – j10.091 m17 FREQUENCY = 500MHz S(1,1) = 0.385/–9.396 IMPEDANCE = 109.556 – j16.156 m18 FREQUENCY = 1GHz S(1,1) = 0.362–19.087 IMPEDANCE = 97.259 – j26.513 m19 FREQUENCY = 2GHz S(1,1) = 0.267/–39.928 IMPEDANCE = 70.789 – j25.940 Data Sheet ADRV9008-2 1.0 2.0 m6 FREQUENCY = 12GHz S(1,1) = 0.757/46.679 IMPEDANCE = 40.002 – j103.036 900 350 M5 R_PEDZ L_OR_C_PE X_STATUS 300 M6 5.0 250 R_PEDZ M4 M1 M2 M3 800 m7 FREQUENCY = 5GHz L_OR_C_PE = 1.336 m8 FREQUENCY = 5GHz R_PEDZ = 31.172 m9 FREQUENCY = 5GHz X_STATUS = 1 200 150 700 600 500 400 L_OR_C_PE X_STATUS 0.5 m1 FREQUENCY = 100MHz S(1,1) = 0.018/–149.643 IMPEDANCE = 48.491 – j0.866 0.2 m2 FREQUENCY = 750MHz S(1,1) = 0.074/–123.043 IMPEDANCE = 45.753 – j5.744 m3 FREQUENCY = 1.5GHz 0 S(1,1) = 0.147/–138.745 IMPEDANCE = 39.362 – j7.804 m4 FREQUENCY = 3GHz S(1,1) = 0.292/–175.424 IMPEDANCE = 27.426 – j1.397 –0.2 m5 FREQUENCY = 6GHz S(1,1) = 0.538/123.271 IMPEDANCE = 18.885 – j23.935 300 –5.0 100 200 50 –0.5 100 0 0 –2.0 0 2 12 10 8 6 4 FREQUENCY (GHz) 16833-461 –1.0 FREQUENCY (100MHz TO 12GHz) Figure 287. RF_EXT_LO_I/O± SEDZ and PEDZ Data 1.0 2.0 1.0 13E+5 R_PEDZ L_OR_C_PE X_STATUS 1.2E+5 5.0 R_PEDZ 0.8 m7 FREQUENCY = 1GHz L_OR_C_PE = 0.389 m8 FREQUENCY = 1GHz R_PEDZ = 4.761E4 m9 FREQUENCY = 1GHz X_STATUS = 0 1.1E+5 1.0E+5 M1 M2 M3 M4 M5 0.9 9.0E+4 8.0E+4 0.7 0.6 0.5 0.4 7.0E+4 0.3 –5.0 –0.5 –2.0 L_OR_C_PE X_STATUS 0.5 m1 FREQUENCY = 100MHz S(1,1) = 0.999/–1.396 IMPEDANCE = 159.977 – j4.099E3 0.2 m2 FREQUENCY = 250MHz S(1,1) = 0.999/–3.480 IMPEDANCE = 30.567 – j1.645E3 m3 FREQUENCY = 500MHz 0 S(1,1) = 0.999/–6.952 IMPEDANCE = 9.723 – j823.070 m4 FREQUENCY = 750MHz S(1,1) = 0.998/–10.431 IMPEDANCE = 5.273 – j547.733 –0.2 m5 FREQUENCY = 1GHz S(1,1) = 0.999/–13.925 IMPEDANCE = 3.521 – j409.400 6.0E+4 0.2 5.0E+4 0.1 4.0E+4 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 1.1 –1.0 FREQUENCY (0.000Hz TO 1.100GHz) Figure 288. REF_CLK_IN± SEDZ and PEDZ Data, On Average, the Real Part of the Parallel Equivalent Differential Impedance (RP) = ~ 70 kΩ Rev. 0 | Page 87 of 95 16833-462 FREQUENCY (GHz) ADRV9008-2 Data Sheet Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File Analog Devices supplies the port impedance as an .s1p file that can be downloaded from the ADRV9008-2 product page. This format allows simple interfacing to the ADS by using the DataAccessComponent. In Figure 289, Term 1 is the singleended input or output, and Term 2 is the differential input or output RF port on the device. The pi on the single-ended side and the differential pi configuration on the differential side allow maximum flexibility in designing matching circuits. The pi configuration is suggested for all design layouts because the pi configuration can step the impedance up or down as needed with appropriate component population. The mechanics of setting up a simulation for impedance measurement and impedance matching is as follows: 1. 2. 3. 4. Transmitter Bias and Port Interface This section considers the dc biasing of the ADRV9008-2 transmitter outputs and how to interface to each transmitter port. The ADRV9008-2 transmitters operate over a range of frequencies. At full output power, each differential output side draws approximately 100 mA of dc bias current. The transmitter outputs are dc biased to a 1.8 V supply voltage using either RF chokes (wire wound inductors) or a transformer center tap connection. Careful design of the dc bias network is required to ensure optimal RF performance levels. When designing the dc bias network, select components with low dc resistance to minimize the voltage drop across the series parasitic resistance element with either of the suggested dc bias schemes suggested in Figure 290. The RDCR resistors indicate the parasitic elements. As the impedance of the parasitics increases, the voltage drop (ΔV) across the parasitic element increases, which causes the transmitter RF performance (PO,1dB, PO,MAX, and so on) to degrade. The choke inductance (LC) must be at least 3× times higher than the load impedance at the lowest desired frequency so that it does not degrade the output power (see Table 10). 16833-463 5. The DataAccessComponent block reads the RF port .s1p file. This file is the device RF port reflection coefficient. The two equations convert the RF port reflection coefficient to a complex impedance. The result is the RX_SEDZ variable. The RF port calculated complex impedance (RX_SEDZ) is used to define the Term 2 impedance. Term 2 is used in a differential mode, and Term 1 is used in a single-ended mode. Setting up the simulation this way allows one to measure the input reflection (S11), output reflection (S22), and through reflection (S21) of the three-port system without complex math operations within the display page. For the highest accuracy, electromagnetic momentum (EM) modelling result of the PCB artwork, S11, S22, and S21 of the matching components and balun must be used in the simulations. Figure 289. Simulation Setup in ADS with SEDZ .s1p Files and DataAccessComponent Table 10. Sample Wire Wound DC Bias Choke Resistance vs. Size vs. Inductance Inductance (nH) 100 200 300 400 500 600 Resistance (Size: 0603) (Ω) 0.10 0.15 0.16 0.28 0.45 0.52 Rev. 0 | Page 88 of 95 Resistance (Size: 1206) (Ω) 0.08 0.10 0.12 0.14 0.15 0.20 Data Sheet ADRV9008-2 The recommended dc bias network is shown in Figure 291. This network has fewer parasitics and fewer total components. 1.8V Figure 291. RF DC Bias Configurations Showing Parasitic Losses Due to Center Tapped Transformers TX1_OUT+/ TX2_OUT+ 1.8V Tx1 OR Tx2 OUTPUT STAGE Figure 292. RF Transmitter Interface Configurations 1.8V If a transmitter balun that requires a set of external dc bias chokes is selected, careful planning is required. It is necessary to find the optimum compromise between the choke physical size, choke dc resistance, and the balun low frequency insertion loss. In commercially available dc bias chokes, resistance decreases as size increases. As choke inductance increases, resistance increases. It is undesirable to use physically small chokes with high inductance because small chokes exhibit the greatest resistance. For example, the voltage drop of a 500 nH, 0603 choke at 100 mA is roughly 50 mV. CB TX1_OUT+/ TX2_OUT+ IBIAS = ~100mA Tx1 OR Tx2 VBIAS = 1.8 – ΔV OUTPUT STAGE VBIAS = 1.8 – ΔV TX1_OUT–/ TX2_OUT– IBIAS = ~100mA LC CC 1.8V OUTPUT STAGE CC 1.8V TX1_OUT–/ TX2_OUT– Figure 293. RF Transmitter Interface Configurations 1.8V CB LC TX1_OUT+/ TX2_OUT+ LC 1.8V Tx1 OR Tx2 OUTPUT STAGE 1.8V TX1_OUT–/ TX2_OUT– Figure 294. RF Transmitter Interface Configurations 1.8V CB TX1_OUT+/ TX2_OUT+ LC 1.8V LC CC Tx1 OR Tx2 OUTPUT STAGE – RDCR ΔV + 1.8V CC DRIVER AMPLIFIER TX1_OUT–/ TX2_OUT– Figure 295. RF Transmitter Interface Configurations 1.8V 16833-464 TX1_OUT+/ TX2_OUT+ LC LC Tx1 OR Tx2 VDC = 1.8V – RDCR ΔV + LC 16833-467 In Figure 292, the center tapped transformer passes the bias voltage directly to the transmitter outputs. In Figure 293, RF chokes bias the differential transmitter output lines. Additional coupling capacitors (CC) are added in the creation of a transmission line balun. In Figure 294, RF chokes are used to bias the differential transmitter output lines and connect to a transformer. In Figure 295, RF chokes bias the differential output lines that are ac-coupled to the input of a driver amplifier. CB CB TX1_OUT–/ TX2_OUT– Figure 290. RF DC Bias Configurations Showing Parasitic Losses Due to Wire Wound Chokes Rev. 0 | Page 89 of 95 16833-469 • – ΔV + 16833-468 • RDCR IBIAS = ~100mA CB TX1_OUT–/ TX2_OUT– 16833-465 OUTPUT STAGE Descriptions of the transmitter port interface schemes are as follows: • RDCR Tx1 OR Tx2 The recommended RF transmitter interface is shown in Figure 290 to Figure 295, featuring a center tapped balun. This configuration offers the lowest component count of the options presented. • – ΔV + IBIAS = ~100mA 16833-466 Figure 292 through Figure 295 identify four basic differential transmitter output configurations. Except in cases in which impedance is already matched, impedence matching networks (balun single-ended port) are required to achieve optimum device performance. In applications in which the transmitter is not connected to another circuit that requires or can tolerate dc bias on the transmitter outputs, the transmitter outputs must be ac-coupled because of the dc bias voltage applied to the differential output lines of the transmitter. TX1_OUT+/ TX2_OUT+ Data Sheet General Observation Receiver Path Interface ORX1_IN– The ADRV9008-2 has two observation, or DPD, receivers (Observation Receiver 1 and Observation Receiver 2). The observation receivers can support up to 450 MHz bandwidth. The observation receiver channels are designed for differential use. OBSERVATION RECEIVER INPUT STAGE ORX1_IN+ (MIXER OR LNA) Figure 296. Differential Observation Receiver Interface Using a Transformer CC CC ORX1_IN– ORX1_IN+ OBSERVATION RECEIVER INPUT STAGE (MIXER OR LNA) 16833-471 The ADRV9008-2 differential signals of the observation receivers interface to an integrated mixer. The mixer input pins have a dc bias of approximately 0.7 V and may need to be ac-coupled, depending on the common-mode voltage level of the external circuit. 16833-470 ADRV9008-2 Important considerations for the observation receiver port interface are as follows: Figure 297. Differential Observation Receiver Interface Using a Transmission Line Balun • Impedance Matching Network Example • • • The device to be interfaced (filter, balun, transmit/receive (T/R) switch, external low noise amplifier (LNA), external PA, and so on). The observation receiver maximum safe input power is 23 dBm (peak). The observation receiver optimum dc bias voltage is 0.7 V bias to ground. The board design (reference planes, transmission lines, impedance matching, and so on). Figure 296 and Figure 297 show possible differential observation receiver port interface circuits. The options in Figure 296 and Figure 297 are valid for all observation receiver inputs operating in differential mode, although only the Observation Receiver 1 signal names are indicated. Impedance matching may be necessary to obtain the performance levels. Given wide RF bandwidth applications, SMD balun devices function well. Decent loss and differential balance are available in a relatively small (0603, 0805) package. Impedance matching networks are required to achieve the ADRV9008-2 data sheet performance levels. This section provides a description of matching network topologies and components used on the ADRV9008-2W/PCBZ. Device models, board models, and balun and SMD component models are required to build an accurate system level simulation. The board layout model can be obtained from an EM simulator. The balun and SMD component models can be obtained from the device vendors or built locally. Contact Analog Devices applications engineering for ADRV9008-2 modeling details. The impedance matching network provided in this section is not evaluated in terms of mean time to failure (MTTF) in high volume production. Consult with component vendors for longterm reliability concerns. Consult with balun vendors to determine appropriate conditions for dc biasing. Figure 299 and Figure 300 show that in a generic port impedance matching network, the shunt or series elements may be a resistor, inductor, or capacitor. Rev. 0 | Page 90 of 95 Data Sheet ADRV9008-2 ORX+ ORX IN 16833-472 ORX– Figure 298. Impedance Matching Topology Rev. 0 | Page 91 of 95 ADRV9008-2 Data Sheet RF OUTPUT 1 VDCA1P8_TX C307 0.1µF AGND L323 L307 43nH DNI TX1_OUT+ R307 C323 DNI AGND TX1_BAL+ 0Ω 5 C339 DNI C338 DNI R308 TX1_OUT– T302 TCM1-83X+ 4 2 L325 DNI RFO_1 18pF J303 1 R309 C312 DNI 0Ω C314 DNI 5 4 3 2 TX1_BAL– 0Ω L308 43nH C337 3 C325 DNI AGND NC 1 6 C344 AGND AGND 51pF AGND C345 VDCA1P8_TX C308 75pF 0.1µF C346 AGND 10pF C347 AGND 27pF RF OUTPUT 2 VDDA1P8_TX C315 0.1µF AGND L327 L315 43nH DNI TX2_OUT+ R310 C327 DNI AGND TX2_BAL+ 0Ω 5 C342 DNI C341 DNI R311 TX2_OUT– T303 TCM1-83X+ 4 2 L329 DNI RFO_2 18pF J304 1 R312 C320 DNI 0Ω C322 DNI 5 4 3 2 TX2_BAL– 0Ω L316 43nH C336 3 NC 1 6 C348 C329 DNI AGND AGND AGND 10pF AGND C349 C316 27pF 0.1µF C350 AGND 51pF C351 AGND 75pF Figure 299. Transmitter 1 and Transmitter 2 Generic Matching Network Topology Rev. 0 | Page 92 of 95 16833-401 VDDA1P8_TX Data Sheet ADRV9008-2 ORX1 J203 1 ORX1_UNBAL R216 0Ω 2 3 4 5 C250 3 T205 TCM1-83X+ 2 18pF 5 0Ω C217 DNI C215 DNI C218 DNI NC AGND ORX1_IN– R219 ORX1_BAL– 4 C221 DNI 6 1 AGND ORX1_IN+ R220 AGND C244 10pF DNI 0Ω ORX1_BAL+ C245 27pF AGND J204 1 R223 ORX2_UNBAL 0Ω 2 3 4 5 C251 3 2 18pF C222 DNI T207 TCM1-83X+ 5 0Ω 4 C224 DNI AGND C228 DNI C225 DNI NC 6 1 AGND AGND R227 C247 27pF C246 10pF DNI ORX2_BAL+ ORX2_IN+ 0Ω AGND Figure 300. Observation Receiver 1 and Observation Receiver 2 Generic Matching Network Topology Rev. 0 | Page 93 of 95 ORX2_IN– R226 ORX2_BAL– 16833-402 ORX2 ADRV9008-2 Data Sheet Table 11 and Table 12 show the selected balun and component values used for the matching network sets. Refer to the ADRV9008-2 schematics for a wideband matching example that operates across the entire device frequency range with somewhat reduced performance. The RF matching used in the ADRV9008-2W/PCBZ allows the ADRV9008-2 to operate across the entire chip frequency range with slightly reduced performance. Table 11. Observation Receiver 1 and Observation Receiver 2 Evaluation Board Matching Components for Frequency Band 75 MHz to 6000 MHz Component C215, C22 R216, R223 C217, C224 C250, C251 C218, C225 R219/R220, R226/R227 C221, C228 T205, T207 Value Do not install (DNI) 0Ω DNI 18 pF DNI 0Ω DNI Mini circuits TCM1-83X+ Table 12. Transmitter 1 and Transmitter 2 Evaluation Board Matching Components1 for Frequency Band 75 MHz to 6000 MHz Component C314, C322 R309, R312 C312, C320 C337, C336 C338, C342 R307/R308, R310/R311 C339, C341 T302, T303 1 Value DNI 0Ω DNI 18 pF DNI 0Ω DNI Mini circuits TCM1-83X+ These matches provide VDDA1P8_TX to the TXx_OUT± pins through the balun. Rev. 0 | Page 94 of 95 Data Sheet ADRV9008-2 OUTLINE DIMENSIONS 12.10 12.00 SQ 11.90 A1 BALL CORNER A1 BALL PAD CORNER 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIN A1 INDICATOR 7.755 REF A B C D E F G H J K L M N P 10.40 SQ 0.80 TOP VIEW BOTTOM VIEW 0.80 REF 8.090 REF DETAIL A DETAIL A 0.91 0.84 0.77 0.39 0.34 0.29 0.44 REF PKG-004723 SEATING PLANE 0.50 0.45 0.40 BALL DIAMETER COPLANARITY 0.12 COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1. 03-02-2015-A 1.27 1.18 1.09 Figure 301. 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-196-13) Dimensions shown in millimeters ORDERING GUIDE Model1 ADRV9008BBCZ-2 ADRV9008BBCZ-2REEL ADRV9008-2W/PCBZ 1 2 Temperature Range2 −40°C to +85°C −40°C to +85°C Package Description 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 196-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Pb-Free Evaluation Board, 75 MHz to 6000 MHz Z = RoHS Compliant Part. See the Thermal Management section. ©2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D16833-0-9/18(0) Rev. 0 | Page 95 of 95 Package Option BC-196-13 BC-196-13