ADSP-218XN

a PERFORMANCE FEATURES 12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS Sustained Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby Power Dissipation with 200 CLKIN Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode INTEGRATION FEATURES ADSP-2100 Family Code Compatible (Easy to Use Algebraic Syntax), with Instruction Set Extensions Up to 256K Bytes of On-Chip RAM, Configured as Up to 48K Words Program Memory RAM Up to 56K Words Data Memory RAM Dual-Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units Two Independent Data Address Generators Powerful Program Sequencer Provides Zero Overhead Looping Conditional Instruction Execution DSP Microcomputer ADSP-218xN Series Programmable 16-Bit Interval Timer with Prescaler 100-Lead LQFP and 144-Ball Mini-BGA SYSTEM INTERFACE FEATURES Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation All Inputs Tolerate up to 3.6 V Regardless of Mode 16-Bit Internal DMA Port for High-Speed Access to OnChip Memory (Mode Selectable) 4M-Byte Memory Interface for Storage of Data Tables and Program Overlays (Mode Selectable) 8-Bit DMA to Byte Memory for Transparent Program and Data Memory Transfers (Mode Selectable) Programmable Memory Strobe and Separate I/O Memory Space Permits “Glueless” System Design Programmable Wait State Generation Two Double-Buffered Serial Ports with Companding Hardware and Automatic Data Buffering Automatic Booting of On-Chip Program Memory from Byte-Wide External Memory, e.g., EPROM, or through Internal DMA Port Six External Interrupts 13 Programmable Flag Pins Provide Flexible System Signaling UART Emulation through Software SPORT Reconfiguration ICE-Port™ Emulator Interface Supports Debugging in Final Systems FUNCTIONAL BLOCK DIAGRAM POWER-DOWN CONTROL FULL MEMORY MODE MEMORY DATA ADDRESS GENERATORS DAG1 DAG2 PROGRAM SEQUENCER PROGRAM MEMORY UP TO 48K 24-BIT DATA MEMORY UP TO 56K 16-BIT PROGRAMMABLE I/O AND FLAGS EXTERNAL ADDRESS BUS EXTERNAL DATA BUS BYTE DMA CONTROLLER OR EXTERNAL DATA BUS TIMER INTERNAL DMA PORT HOST MODE blo ip ch ert Ins ck re. he m PROGRAM MEMORY ADDRESS gra dia DATA MEMORY ADDRESS PROGRAM MEMORY DATA DATA MEMORY DATA ARITHMETIC UNITS ALU MAC SHIFTER SERIAL PORTS SPORT0 SPORT1 ADSP-2100 BASE ARCHITECTURE ICE-Port is a trademark of Analog Devices, Inc. REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A. Tel:781/329-4700 http://www.analog.com Fax:781/326-8703 © Analog Devices, Inc., 2001 ADSP-218xN Series GENERAL DESCRIPTION This takes place while the processor continues to: • Receive and transmit data through the two serial ports • Receive and/or transmit data through the internal DMA port • Receive and/or transmit data through the byte DMA port • Decrement timer DEVELOPMENT SYSTEM The ADSP-218xN series consists of six single chip microcomputers optimized for digital signal processing applications. The high-level block diagram for the ADSP-218xN series members appears on the previous page. All series members are pin-compatible and are differentiated solely by the amount of on-chip SRAM. This feature, combined with ADSP-21xx code compatibility, provides a great deal of flexibility in the design decision. Specific family members are shown in Table 1. Table 1. ADSP-218xN DSP Microcomputer Family Program Memory (K Words) Data Memory (K Words) Analog Devices’ wide range of software and hardware development tools supports the ADSP-218xN series. The DSP tools include an integrated development environment, an evaluation kit, and a serial port emulator. VisualDSP++™ is an integrated development environment, allowing for fast and easy development, debug, and deployment. The VisualDSP++ project management environment lets programmers develop and debug an application. This environment includes an easy-to-use assembler that is based on an algebraic syntax; an archiver (librarian/library builder); a linker; a PROM-splitter utility; a cycle-accurate, instruction-level simulator; a C compiler; and a C run-time library that includes DSP and mathematical functions. Debugging both C and assembly programs with the VisualDSP++ debugger, programmers can: • View mixed C and assembly code (interleaved source and object information) • Insert break points • Set conditional breakpoints on registers, memory, and stacks • Trace instruction execution • Fill and dump memory • Source level debugging The VisualDSP++ IDE lets programmers define and manage DSP software development. The dialog boxes and property pages let programmers configure and manage all of the ADSP-218xN development tools, including the syntax highlighting in the VisualDSP++ editor. This capability controls how the development tools process inputs and generate outputs. The ADSP-2189M EZ-KIT Lite™ provides developers with a cost-effective method for initial evaluation of the powerful ADSP-218xN DSP family architecture. The ADSP-2189M EZ-KIT Lite includes a stand-alone ADSP2189M DSP board supported by an evaluation suite of VisualDSP++. With this EZ-KIT Lite, users can learn about DSP hardware and software development and evaluate potential applications of the ADSP-218xN series. The ADSP-2189M EZ-KIT Lite provides an evaluation suite of the VisualDSP++ development environment with the C compiler, assembler, and linker. The size of the DSP erxecutable that can be built using the EZ-KIT Lite tools is limited to 8K words. –2– REV. 0 Device ADSP-2184N ADSP-2185N ADSP-2186N ADSP-2187N ADSP-2188N ADSP-2189N 4 16 8 32 48 32 4 16 8 32 56 48 ADSP-218xN series members combine the ADSP-2100 family base architecture (three computational units, data address generators, and a program sequencer) with two serial ports, a 16-bit internal DMA port, a byte DMA port, a programmable timer, Flag I/O, extensive interrupt capabilities, and on-chip program and data memory. ADSP-218xN series members integrate up to 256K bytes of on-chip memory configured as up to 48K words (24-bit) of program RAM, and up to 56K words (16-bit) of data RAM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-218xN is available in a 100-lead LQFP package and 144-Ball Mini-BGA. Fabricated in a high-speed, low-power, 0.18 µm CMOS process, ADSP-218xN series members operate with a 12.5 ns instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-218xN’s flexible architecture and comprehensive instruction set allow the processor to perform multiple operations in parallel. In one processor cycle, ADSP-218xN series members can: • Generate the next program address • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computational operation VisualDSP++ and EZ-KIT Lite are trademarks of Analog Devices, Inc. ADSP-218xN Series The EZ-KIT Lite includes the following features: • 75 MHz ADSP-2189M • Full 16-Bit Stereo Audio I/O with AD73322 Codec • RS-232 Interface • EZ-ICE Connector for Emulator Control • DSP Demonstration Programs • Evaluation Suite of VisualDSP++ The ADSP-218x EZ-ICE® Emulator provides an easier and more cost-effective method for engineers to develop and optimize DSP systems, shortening product development cycles for faster time-to-market. ADSP-218xN series members integrate on-chip emulation support with a 14-pin ICE-Port interface. This interface provides a simpler target board connection that requires fewer mechanical clearance considerations than other ADSP-2100 Family EZ-ICEs. ADSP-218xN series members need not be removed from the target system when using the EZ-ICE, nor are any adapters needed. Due to the small footprint of the EZ-ICE connector, emulation can be supported in final board designs.The EZ-ICE performs a full range of functions, including: • In-target operation • Up to 20 breakpoints • Single-step or full-speed operation • Registers and memory values can be examined and altered • PC upload and download functions • Instruction-level emulation of program booting and execution • Complete assembly and disassembly of instructions • C source-level debugging Additional Information units process 16-bit data directly and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations; division primitives are also supported. The MAC performs singlecycle multiply, multiply/add, and multiply/subtract operations with 40 bits of accumulation. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control, including multiword and block floatingpoint representations. The internal result (R) bus connects the computational units so that the output of any unit may be the input of any unit on the next cycle. A powerful program sequencer and two dedicated data address generators ensure efficient delivery of operands to these computational units. The sequencer supports conditional jumps, subroutine calls, and returns in a single cycle. With internal loop counters and loop stacks, ADSP-218xN series members execute looped code with zero overhead; no explicit jump instructions are required to maintain loops. Two data address generators (DAGs) provide addresses for simultaneous dual operand fetches (from data memory and program memory). Each DAG maintains and updates four address pointers. Whenever the pointer is used to access data (indirect addressing), it is post-modified by the value of one of four possible modify registers. A length value may be associated with each pointer to implement automatic modulo addressing for circular buffers. Five internal buses provide efficient data transfer: • Program Memory Address (PMA) Bus • Program Memory Data (PMD) Bus • Data Memory Address (DMA) Bus • Data Memory Data (DMD) Bus • Result (R) Bus The two address buses (PMA and DMA) share a single external address bus, allowing memory to be expanded offchip, and the two data buses (PMD and DMD) share a single external data bus. Byte memory space and I/O memory space also share the external buses. Program memory can store both instructions and data, permitting ADSP-218xN series members to fetch two operands in a single cycle, one from program memory and one from data memory. ADSP-218xN series members can fetch an operand from program memory and the next instruction in the same cycle. In lieu of the address and data bus for external memory connection, ADSP-218xN series members may be configured for 16-bit Internal DMA port (IDMA port) connection to external systems. The IDMA port is made up of 16 This data sheet provides a general overview of ADSP218xN series functionality. For additional information on the architecture and instruction set of the processor, refer to the ADSP-218x DSP Hardware Reference and the ADSP218x DSP Instruction Set Reference. ARCHITECTURE OVERVIEW The ADSP-218xN series instruction set provides flexible data moves and multifunction (one or two data moves with a computation) instructions. Every instruction can be executed in a single processor cycle. The ADSP-218xN assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. The functional block diagram is an overall block diagram of the ADSP-218xN series. The processor contains three independent computational units: the ALU, the multiplier/ accumulator (MAC), and the shifter. The computational EZ-ICE is a registered trademark of Analog Devices, Inc. REV. 0 –3– ADSP-218xN Series data/address pins and five control pins. The IDMA port provides transparent, direct access to the DSP’s on-chip program and data RAM. An interface to low-cost byte-wide memory is provided by the Byte DMA port (BDMA port). The BDMA port is bidirectional and can directly address up to four megabytes of external RAM or ROM for off-chip storage of program overlays or data tables. The byte memory and I/O memory space interface supports slow memories and I/O memory-mapped peripherals with programmable wait state generation. External devices can gain control of external buses with bus request/grant signals (BR, BGH, and BG). One execution mode (Go Mode) allows the ADSP-218xN to continue running from on-chip memory. Normal execution mode requires the processor to halt while buses are granted. ADSP-218xN series members can respond to eleven interrupts. There can be up to six external interrupts (one edgesensitive, two level-sensitive, and three configurable) and seven internal interrupts generated by the timer, the serial ports (SPORT), the Byte DMA port, and the power-down circuitry. There is also a master RESET signal. The two serial ports provide a complete synchronous serial interface with optional companding in hardware and a wide variety of framed or frameless data transmit and receive modes of operation. Each port can generate an internal programmable serial clock or accept an external serial clock. ADSP-218xN series members provide up to 13 generalpurpose flag pins. The data input and output pins on SPORT1 can be alternatively configured as an input flag and an output flag. In addition, eight flags are programmable as inputs or outputs, and three flags are always outputs. A programmable interval timer generates periodic interrupts. A 16-bit count register (TCOUNT) decrements every n processor cycle, where n is a scaling value stored in an 8-bit register (TSCALE). When the value of the count register reaches zero, an interrupt is generated and the count register is reloaded from a 16-bit period register (TPERIOD). Serial Ports • SPORTs have independent framing for the receive and transmit sections. Sections run in a frameless mode or with frame synchronization signals internally or externally generated. Frame sync signals are active high or inverted, with either of two pulsewidths and timings. • SPORTs support serial data word lengths from 3 to 16 bits and provide optional A-law and µ-law companding, according to CCITT recommendation G.711. • SPORT receive and transmit sections can generate unique interrupts on completing a data word transfer. • SPORTs can receive and transmit an entire circular buffer of data with only one overhead cycle per data word. An interrupt is generated after a data buffer transfer. • SPORT0 has a multichannel interface to selectively receive and transmit a 24 or 32 word, time-division multiplexed, serial bitstream. • SPORT1 can be configured to have two external interrupts (IRQ0 and IRQ1) and the FI and FO signals. The internally generated serial clock may still be used in this configuration. PIN DESCRIPTIONS ADSP-218xN series members are available in a 100-lead LQFP package and a 144-Ball Mini-BGA package. In order to maintain maximum functionality and reduce package size and pin count, some serial port, programmable flag, interrupt and external bus pins have dual, multiplexed functionality. The external bus pins are configured during RESET only, while serial port pins are software configurable during program execution. Flag and interrupt functionality is retained concurrently on multiplexed pins. In cases where pin functionality is reconfigurable, the default state is shown in plain text in Table 2, while alternate functionality is shown in italics. ADSP-218xN series members incorporate two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Following is a brief list of the capabilities of the ADSP218xN SPORTs. For additional information on Serial Ports, refer to the ADSP-218x DSP Hardware Reference. • SPORTs are bidirectional and have a separate, doublebuffered transmit and receive section. • SPORTs can use an external serial clock or generate their own serial clock internally. –4– REV. 0 ADSP-218xN Series Table 2. Common-Mode Pins Pin Name # of Pins I/O Function RESET BR BG BGH DMS PMS IOMS BMS CMS RD WR IRQ2 PF7 IRQL1 PF6 IRQL0 PF5 IRQE PF4 Mode D PF3 Mode C PF2 Mode B PF1 Mode A PF0 CLKIN XTAL CLKOUT SPORT0 SPORT1 IRQ1–0, FI, FO PWD PWDACK FL0, FL1, FL2 VDDINT VDDEXT GND VDDINT VDDEXT GND EZ-Port 1Interrupt/Flag 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 3 2 4 10 4 7 20 9 I I O O O O O O O O O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I O O I/O I/O I O O I I I I I I I/O Processor Reset Input Bus Request Input Bus Grant Output Bus Grant Hung Output Data Memory Select Output Program Memory Select Output Memory Select Output Byte Memory Select Output Combined Memory Select Output Memory Read Enable Output Memory Write Enable Output Edge- or Level-Sensitive Interrupt Request1 Programmable I/O pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Level-Sensitive Interrupt Requests1 Programmable I/O Pin Edge-Sensitive Interrupt Requests1 Programmable I/O Pin Mode Select Input—Checked Only During RESET Programmable I/O Pin During Normal Operation Mode Select Input—Checked Only During RESET Programmable I/O Pin During Normal Operation Mode Select Input—Checked Only During RESET Programmable I/O Pin During Normal Operation Mode Select Input—Checked Only During RESET Programmable I/O Pin During Normal Operation Clock Input Quartz Crystal Output Processor Clock Output Serial Port I/O Pins Serial Port I/O Pins Edge- or Level-Sensitive Interrupts, FI, FO2 Power-Down Control Input Power-Down Acknowledge Control Output Output Flags Internal VDD (1.8 V) Power (LQFP) External VDD (1.8 V, 2.5 V, or 3.3 V) Power (LQFP) Ground (LQFP) Internal VDD (1.8 V) Power (Mini-BGA) External VDD (1.8 V, 2.5 V, or 3.3 V) Power (MiniBGA) Ground (Mini-BGA) For Emulation Use pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, the DSP will vector to the appropriate interrupt vector address when the pin is asserted, either by external devices or set as a programmable flag. 2SPORT configuration determined by the DSP System Control Register. Software configurable. REV. 0 –5– ADSP-218xN Series Memory Interface Pins ADSP-218xN series members can be used in one of two modes: Full Memory Mode, which allows BDMA operation with full external overlay memory and I/O capability, or Host Mode, which allows IDMA operation with limited external addressing capabilities. The operating mode is determined by the state of the Mode C pin during RESET and cannot be changed while the processor is running. Table 3 and Table 4 list the active Table 3. Full Memory Mode Pins (Mode C = 0) Pin Name # of Pins I/O Function signals at specific pins of the DSP during either of the two operating modes (Full Memory or Host). A signal in one table shares a pin with a signal from the other table, with the active signal determined by the mode that is set. For the shared pins and their alternate signals (e.g., A4/IAD3), refer to the package pinouts in Table 27 on page 40 and Table 28 on page 42. A13–0 D23–0 14 24 O I/O Address Output Pins for Program, Data, Byte, and I/O Spaces Data I/O Pins for Program, Data, Byte, and I/O Spaces (8 MSBs are also used as Byte Memory Addresses.) Table 4. Host Mode Pins (Mode C = 1) Pin Name # of Pins I/O Function IAD15–0 A0 D23–8 IWR IRD IAL IS IACK 1In 16 1 16 1 1 1 1 1 I/O O I/O I I I I O IDMA Port Address/Data Bus Address Pin for External I/O, Program, Data, or Byte Access1 Data I/O Pins for Program, Data, Byte, and I/O Spaces IDMA Write Enable IDMA Read Enable IDMA Address Latch Pin IDMA Select IDMA Port Acknowledge Configurable in Mode D; Open Drain Host Mode, external peripheral addresses can be decoded using the A0, CMS, PMS, DMS, and IOMS signals. Terminating Unused Pins Table 5 shows the recommendations for terminating unused pins. Table 5. Unused Pin Terminations I/O 3-State (Z)2 Reset State Pin Name1 Hi-Z3 Caused By Unused Configuration XTAL CLKOUT A13–1 or IAD12–0 A0 D23–8 D7 or IWR D6 or IRD D5 or IAL D4 or IS O O O (Z) I/O (Z) O (Z) I/O (Z) I/O (Z) I I/O (Z) I I/O (Z) I I/O (Z) I O O Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z I Hi-Z I Hi-Z I Hi-Z I BR, EBR IS BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR Float Float4 Float Float Float Float Float High (Inactive) Float High (Inactive) Float Low (Inactive) Float High (Inactive) –6– REV. 0 ADSP-218xN Series Table 5. Unused Pin Terminations (Continued) I/O 3-State (Z)2 Reset State Pin Name1 Hi-Z3 Caused By Unused Configuration D3 or IACK D2–0 or IAD15–13 PMS DMS BMS IOMS CMS RD WR BR BG BGH IRQ2/PF7 IRQL1/PF6 IRQL0/PF5 IRQE/PF4 PWD SCLK0 RFS0 DR0 TFS0 DT0 SCLK1 RFS1/IRQ0 DR1/FI TFS1/IRQ1 DT1/FO EE EBR EBG ERESET EMS EINT ECLK ELIN ELOUT 1CLKIN, 2All I/O (Z) I/O (Z) I/O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) O (Z) I O (Z) O I/O (Z) I/O (Z) I/O (Z) I/O (Z) I I/O I/O I I/O O I/O I/O I I/O O I I O I O I I I O Hi-Z Hi-Z Hi-Z O O O O O O O I O O I I I I I I I I I O I I I I O I I O I O I I I O BR, EBR BR, EBR IS BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR BR, EBR EE Float Float Float Float Float Float Float Float Float Float Float High (Inactive) Float Float Input = High (Inactive) or Program as Output, Set to 1, Let Float5 Input = High (Inactive) or Program as Output, Set to 1, Let Float5 Input = High (Inactive) or Program as Output, Set to 1, Let Float5 Input = High (Inactive) or Program as Output, Set to 1, Let Float5 High Input = High or Low, Output = Float High or Low High or Low High or Low Float Input = High or Low, Output = Float High or Low High or Low High or Low Float Float Float Float Float Float Float Float Float Float RESET, and PF3–0/Mode D –A are not included in this table because these pins must be used. bidirectional pins have three-stated outputs. When the pin is configured as an output, the output is Hi-Z (high impedance) when inactive. 3Hi-Z = High Impedance. 4If the CLKOUT pin is not used, turn it OFF, using CLKODIS in SPORT0 autobuffer control register. 5If the Interrupt/Programmable Flag pins are not used, there are two options: Option 1: When these pins are configured as INPUTS at reset and function as interrupts and input flag pins, pull the pins High (inactive). Option 2: Program the unused pins as OUTPUTS, set them to 1 prior to enabling interrupts, and let pins float. REV. 0 –7– ADSP-218xN Series Interrupts The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead. ADSP-218xN series members provide four dedicated external interrupt input pins: IRQ2, IRQL0, IRQL1, and IRQE (shared with the PF7–4 pins). In addition, SPORT1 may be reconfigured for IRQ0, IRQ1, FI and FO, for a total of six external interrupts. The ADSP-218xN also supports internal interrupts from the timer, the byte DMA port, the two serial ports, software, and the power-down control circuit. The interrupt levels are internally prioritized and individually maskable (except power-down and reset). The IRQ2, IRQ0, and IRQ1 input pins can be programmed to be either level- or edge-sensitive. IRQL0 and IRQL1 are level-sensitive and IRQE is edge-sensitive. The priorities and vector addresses of all interrupts are shown in Table 6. Table 6. Interrupt Priority and Interrupt Vector Addresses Source Of Interrupt Interrupt Vector Address (Hex) The IFC register is a write-only register used to force and clear interrupts. On-chip stacks preserve the processor status and are automatically maintained during interrupt handling. The stacks are 12 levels deep to allow interrupt, loop, and subroutine nesting. The following instructions allow global enable or disable servicing of the interrupts (including power-down), regardless of the state of IMASK: ENA INTS; DIS INTS; Disabling the interrupts does not affect serial port autobuffering or DMA. When the processor is reset, interrupt servicing is enabled. LOW-POWER OPERATION ADSP-218xN series members have three low-power modes that significantly reduce the power dissipation when the device operates under standby conditions. These modes are: • Power-Down • Idle • Slow Idle The CLKOUT pin may also be disabled to reduce external power dissipation. Power-Down Reset (or Power-Up with PUCR = 1) Power-Down (Nonmaskable) IRQ2 IRQL1 IRQL0 SPORT0 Transmit SPORT0 Receive IRQE BDMA Interrupt SPORT1 Transmit or IRQ1 SPORT1 Receive or IRQ0 Timer 0x0000 (Highest Priority) 0x002C 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 (Lowest Priority) ADSP-218xN series members have a low-power feature that lets the processor enter a very low-power dormant state through hardware or software control. Following is a brief list of power-down features. Refer to the ADSP-218x DSP Hardware Reference, “System Interface” chapter, for detailed information about the power-down feature. • Quick recovery from power-down. The processor begins executing instructions in as few as 200 CLKIN cycles. • Support for an externally generated TTL or CMOS processor clock. The external clock can continue running during power-down without affecting the lowest power rating and 200 CLKIN cycle recovery. • Support for crystal operation includes disabling the oscillator to save power (the processor automatically waits approximately 4096 CLKIN cycles for the crystal oscillator to start or stabilize), and letting the oscillator run to allow 200 CLKIN cycle start-up. • Power-down is initiated by either the power-down pin (PWD) or the software power-down force bit. Interrupt support allows an unlimited number of instructions to be executed before optionally powering down. The powerdown interrupt also can be used as a nonmaskable, edgesensitive interrupt. • Context clear/save control allows the processor to continue where it left off or start with a clean context when leaving the power-down state. Interrupt routines can either be nested with higher priority interrupts taking precedence or processed sequentially. Interrupts can be masked or unmasked with the IMASK register. Individual interrupt requests are logically ANDed with the bits in IMASK; the highest priority unmasked interrupt is then selected. The power-down interrupt is nonmaskable. ADSP-218xN series members mask all interrupts for one instruction cycle following the execution of an instruction that modifies the IMASK register. This does not affect serial port autobuffering or DMA transfers. The interrupt control register, ICNTL, controls interrupt nesting and defines the IRQ0, IRQ1, and IRQ2 external interrupts to be either edge- or level-sensitive. The IRQE pin is an external edge-sensitive interrupt and can be forced and cleared. The IRQL0 and IRQL1 pins are external level sensitive interrupts. –8– REV. 0 ADSP-218xN Series • The RESET pin also can be used to terminate powerdown. • Power-down acknowledge pin (PWDACK) indicates when the processor has entered power-down. Idle When the ADSP-218xN is in the Idle Mode, the processor waits indefinitely in a low-power state until an interrupt occurs. When an unmasked interrupt occurs, it is serviced; execution then continues with the instruction following the IDLE instruction. In Idle mode IDMA, BDMA, and autobuffer cycle steals still occur. Slow Idle When the IDLE (n) instruction is used, it effectively slows down the processor’s internal clock and thus its response time to incoming interrupts. The one-cycle response time of the standard idle state is increased by n, the clock divisor. When an enabled interrupt is received, ADSP-218xN series members remain in the idle state for up to a maximum of n processor cycles (n = 16, 32, 64, or 128) before resuming normal operation. When the IDLE (n) instruction is used in systems that have an externally generated serial clock (SCLK), the serial clock rate may be faster than the processor’s reduced internal clock rate. Under these conditions, interrupts must not be generated at a faster rate than can be serviced, due to the additional time the processor takes to come out of the idle state (a maximum of n processor cycles). SYSTEM INTERFACE The IDLE instruction is enhanced on ADSP-218xN series members to let the processor’s internal clock signal be slowed, further reducing power consumption. The reduced clock frequency, a programmable fraction of the normal clock rate, is specified by a selectable divisor given in the IDLE instruction. The format of the instruction is: IDLE (N); where N = 16, 32, 64, or 128. This instruction keeps the processor fully functional, but operating at the slower clock rate. While it is in this state, the processor’s other internal clock signals, such as SCLK, CLKOUT, and timer clock, are reduced by the same ratio. The default form of the instruction, when no clock divisor is given, is the standard IDLE instruction. FULL MEMORY MODE ADSP-218xN 1/2X CLOCK OR CRYSTAL CLKIN XTAL FL0–2 24 IRQ2/PF7 IRQE/PF4 DATA23–0 IRQL0/PF5 BMS IRQL1/PF6 WR MODE D/PF3 RD MODE C/PF2 MODE A/PF0 MODE B/PF1 IOMS SPORT1 SCLK1 RFS1 OR IRQ0 TFS1 OR I RQ1 DT1 OR FO PMS DR1 OR FI ert DMSIns CMS SPORT0 SCLK0 BR RFS0 BG TFS0 BGH DT0 PWD DR0 PWDACK ADDR13–0 14 A13–0 D23–16 D15–8 DATA CS A10–0 ADDR D23–8 A0–A21 Figure 1 shows typical basic system configurations with the ADSP-218xN series, two serial devices, a byte-wide EPROM, and optional external program and data overlay memories (mode-selectable). Programmable wait state generation allows the processor to connect easily to slow peripheral devices. ADSP-218xN series members also provide four external interrupts and two serial ports or six external interrupts and one serial port. Host Memory Mode allows access to the full external data bus, but limits addressing to a single address bit (A0). Through the use of external hardware, additional system peripherals can be added in this mode to generate and latch address signals. HOST MEMORY MODE ADSP-218xN 1/2X CLOCK OR CRYSTAL BYTE MEMORY CLKIN XTAL FL0–2 A0 1 16 SERIAL DEVICE e fac ter ADDR in D23–0 m ste DATA sy A13–0 re I/O SPACE he (PERIPHERALS) m DATA 2048 LOCATIONS gra CS dia OVERLAY MEMORY TWO 8K PM SEGMENTS TWO 8K DM SEGMENTS SERIAL DEVICE IRQ2/PF7 IRQE/PF4 DATA23–8 IRQL0/PF5 IRQL1/PF6 BMS MODE D/PF3 WR MODE C/PF2 RD MODE A/PF0 MODE B/PF1 SPORT1 SCLK1 RFS1 OR IRQ0 TFS1 OR IRQ1 DT1 OR FO DR1 OR FI SPORT0 SCLK0 RFS0 TFS0 DT0 DR0 IDMA PORT IRD/D6 IWR/D7 IS/D4 IAL/D5 IACK/D3 IAD15-0 IOMS PMS DMS CMS SERIAL DEVICE SERIAL DEVICE BR BG BGH PWD PWDACK SYSTEM INTERFACE OR µCONTROLLER 16 Figure 1. Basic System Interface REV. 0 –9– ADSP-218xN Series Clock Signals RESET ADSP-218xN series members can be clocked by either a crystal or a TTL-compatible clock signal. The CLKIN input cannot be halted, changed during operation, nor operated below the specified frequency during normal operation. The only exception is while the processor is in the power-down state. For additional information, refer to the ADSP-218x DSP Hardware Reference, for detailed information on this power-down feature. If an external clock is used, it should be a TTL-compatible signal running at half the instruction rate. The signal is connected to the processor’s CLKIN input. When an external clock is used, the XTAL pin must be left unconnected. ADSP-218xN series members use an input clock with a frequency equal to half the instruction rate; a 40 MHz input clock yields a 12.5 ns processor cycle (which is equivalent to 80 MHz). Normally, instructions are executed in a single processor cycle. All device timing is relative to the internal instruction clock rate, which is indicated by the CLKOUT signal when enabled. Because ADSP-218xN series members include an on-chip oscillator circuit, an external crystal may be used. The crystal should be connected across the CLKIN and XTAL pins, with two capacitors connected as shown in Figure 2. Capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. A parallelresonant, fundamental frequency, microprocessor-grade crystal should be used. A clock output (CLKOUT) signal is generated by the processor at the processor’s cycle rate. This can be enabled and disabled by the CLKODIS bit in the SPORT0 Autobuffer Control Register. The RESET signal initiates a master reset of the ADSP218xN. The RESET signal must be asserted during the power-up sequence to assure proper initialization. RESET during initial power-up must be held long enough to allow the internal clock to stabilize. If RESET is activated any time after power-up, the clock continues to run and does not require stabilization time. The power-up sequence is defined as the total time required for the crystal oscillator circuit to stabilize after a valid VDD is applied to the processor, and for the internal phase-locked loop (PLL) to lock onto the specific crystal frequency. A minimum of 2000 CLKIN cycles ensures that the PLL has locked, but does not include the crystal oscillator start-up time. During this power-up sequence the RESET signal should be held low. On any subsequent resets, the RESET signal must meet the minimum pulse-width specification (tRSP). The RESET input contains some hysteresis; however, if an RC circuit is used to generate the RESET signal, the use of an external Schmitt trigger is recommended. The master reset sets all internal stack pointers to the empty stack condition, masks all interrupts, and clears the MSTAT register. When RESET is released, if there is no pending bus request and the chip is configured for booting, the bootloading sequence is performed. The first instruction is fetched from on-chip program memory location 0x0000 once boot loading completes. POWER SUPPLIES CLKIN XTAL CLKOUT DSP ADSP-218xN series members have separate power supply connections for the internal (VDDINT) and external (VDDEXT) power supplies. The internal supply must meet the 1.8 V requirement. The external supply can be connected to a 1.8 V, 2.5 V, or 3.3 V supply. All external supply pins must be connected to the same supply. All input and I/O pins can tolerate input voltages up to 3.6 V, regardless of the external supply voltage. This feature provides maximum flexibility in mixing 1.8 V, 2.5 V, or 3.3 V components. Figure 2. External Crystal Connections –10– REV. 0 ADSP-218xN Series MODES OF OPERATION The ADSP-218xN series modes of operation appear in Table 7. Table 7. Modes of Operation Mode D Mode C Mode B Mode A Booting Method X 0 0 0 X 0 1 0 0 1 0 0 0 1 0 1 1 1 0 0 1 1 0 1 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Full Memory Mode.1 No automatic boot operations occur. Program execution starts at external memory location 0. Chip is configured in Full Memory Mode. BDMA can still be used, but the processor does not automatically use or wait for these operations. BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode. IACK has active pull-down. (Requires additonal hardware.) IDMA feature is used to load any internal memory as desired. Program execution is held off until the host writes to internal program memory location 0. Chip is configured in Host Mode. IACK has active pull-down.1 BDMA feature is used to load the first 32 program memory words from the byte memory space. Program execution is held off until all 32 words have been loaded. Chip is configured in Host Mode; IACK requires external pull-down. (Requires additonal hardware.) IDMA feature is used to load any internal memory as desired. Program execution is held off until the host writes to internal program memory location 0. Chip is configured in Host Mode. IACK requires external pull-down.1 1Considered as standard operating settings. Using these configurations allows for easier design and better memory management. Setting Memory Mode Active Configuration Memory Mode selection for the ADSP-218xN series is made during chip reset through the use of the Mode C pin. This pin is multiplexed with the DSP’s PF2 pin, so care must be taken in how the mode selection is made. The two methods for selecting the value of Mode C are active and passive. Passive Configuration Passive Configuration involves the use of a pull-up or pulldown resistor connected to the Mode C pin. To minimize power consumption, or if the PF2 pin is to be used as an output in the DSP application, a weak pull-up or pulldown resistance, on the order of 10 k , can be used. This value should be sufficient to pull the pin to the desired level and still allow the pin to operate as a programmable flag output without undue strain on the processor’s output driver. For minimum power consumption during powerdown, reconfigure PF2 to be an input, as the pull-up or pulldown resistance will hold the pin in a known state, and will not switch. Active Configuration involves the use of a three-statable external driver connected to the Mode C pin. A driver’s output enable should be connected to the DSP’s RESET signal such that it only drives the PF2 pin when RESET is active (low). When RESET is deasserted, the driver should be three-state, thus allowing full use of the PF2 pin as either an input or output. To minimize power consumption during power-down, configure the programmable flag as an output when connected to a three-stated buffer. This ensures that the pin will be held at a constant level, and will not oscillate should the three-state driver’s level hover around the logic switching point. IDMA ACK Configuration Mode D = 0 and in host mode: IACK is an active, driven signal and cannot be “wire ORed.” Mode D = 1 and in host mode: IACK is an open drain and requires an external pull-down, but multiple IACK pins can be “wire ORed” together. REV. 0 –11– ADSP-218xN Series MEMORY ARCHITECTURE The ADSP-218xN series provides a variety of memory and peripheral interface options. The key functional groups are Program Memory, Data Memory, Byte Memory, and I/O. Refer to Figure 3 through Figure 8, Table 8 on page 14, and Table 9 on page 14 for PM and DM memory allocations in the ADSP-218xN series. PROGRAM MEMORY MODEB = 1 0X3FFF 0X3FFF PROGRAM MEMORY MODEB = 0 0X3FFF PM OVERLAY 1,2 (EXTERNAL PM) PM OVERLAY 0 (RESERVED) DATA MEMORY 32 MEMORY-MAPPED CONTROL REGISTERS 0X3FE0 0X3FDF 0X3000 0X2FFF 0X2000 0X1FFF DM OVERLAY 1,2 (EXTERNAL DM) DM OVERLAY 0 (RESERVED) 0X0000 4064 RESERVED WORDS INTERNAL DM RESERVED 0X2000 0X1FFF EXTERNAL PM 0X2000 0X1FFF RESERVED 0X1000 0X0FFF INTERNAL PM 0X0000 0X0000 Figure 3. ADSP-2184 Memory Architecture PROGRAM MEMORY MODEB = 1 0X3FFF 0X3FFF PROGRAM MEMORY MODEB = 0 0X3FFF PM OVERLAY 1,2 (EXTERNAL PM) PM OVERLAY 0 (RESERVED) DATA MEMORY 32 MEMORY-MAPPED CONTROL REGISTERS 0X3FE0 0X3FDF INTERNAL DM 0X2000 0X1FFF RESERVED 0X2000 0X1FFF EXTERNAL PM 0X2000 0X1FFF INTERNAL PM DM OVERLAY 1,2 (EXTERNAL DM) DM OVERLAY 0 (INTERNAL DM) 0X0000 0X0000 0X0000 Figure 4. ADSP-2185 Memory Architecture PROGRAM MEMORY MODEB = 1 0X3FFF 0X3FFF PROGRAM MEMORY MODEB = 0 0X3FFF PM OVERLAY 1,2 (EXTERNAL PM) PM OVERLAY 0 (RESERVED) DATA MEMORY 32 MEMORY-MAPPED CONTROL REGISTERS 0X3FE0 0X3FDF INTERNAL DM RESERVED 0X2000 0X1FFF EXTERNAL PM 0X2000 0X1FFF 0X2000 0X1FFF INTERNAL PM DM OVERLAY 1,2 (EXTERNAL DM) DM OVERLAY 0 (RESERVED) 0X0000 0X0000 0X0000 Figure 5. ADSP-2186 Memory Architecture –12– REV. 0 ADSP-218xN Series PROGRAM MEMORY MODEB = 1 0X3FFF 0X3FFF PM OVERLAY 1,2 (EXTERNAL PM) PM OVERLAY 0,4,5 (INTERNAL PM) 0X2000 0X1FFF EXTERNAL PM 0X2000 0X1FFF PROGRAM MEMORY MODEB = 0 0X3FFF 32 MEMORY-MAPPED CONTROL REGISTERS 0X3FE0 0X3FDF INTERNAL DM DATA MEMORY RESERVED 0X2000 0X1FFF INTERNAL PM DM OVERLAY 1,2 (EXTERNAL DM) DM OVERLAY 0,4,5 (INTERNAL DM) 0X0000 0X0000 0X0000 Figure 6. ADSP-2187 Memory Architecture PROGRAM MEMORY MODEB = 1 0x3FFF 0x3FFF PROGRAM MEMORY MODEB = 0 0x3FFF PM OVERLAY 1,2 (EXTERNAL PM) DATA MEMORY 32 MEMORY-MAPPED CONTROL REGISTERS 0x3FE0 0x3FDF INTERNAL DM 0x2000 0x1FFF RESERVED PM OVERLAY 0,4,5,6,7 (INTERNAL PM) 0x2000 0x1FFF EXTERNAL PM 0x2000 0x1FFF INTERNAL PM DM OVERLAY 1,2 (EXTERNAL DM) DM OVERLAY 0,4,5,6,7,8 (INTERNAL DM) 0x0000 0x0000 0x0000 Figure 7. ADSP-2188 Memory Architecture PROGRAM MEMORY MODEB = 1 0X3FFF 0X3FFF PROGRAM MEMORY MODEB = 0 0X3FFF PM OVERLAY 1,2 (EXTERNAL PM) DATA MEMORY 32 MEMORY-MAPPED CONTROL REGISTERS 0X3FE0 0X3FDF INTERNAL DM 0X2000 0X1FFF RESERVED PM OVERLAY 0,4,5 (INTERNAL PM) 0X2000 0X1FFF EXTERNAL PM 0X2000 0X1FFF INTERNAL PM DM OVERLAY 1,2 (EXTERNAL DM) DM OVERLAY 0,4,5,6,7 (INTERNAL DM) 0X0000 0X0000 0X0000 Figure 8. ADSP-2189 Memory Architecture REV. 0 –13– ADSP-218xN Series Program Memory Program Memory (Full Memory Mode) is a 24-bit-wide space for storing both instruction opcodes and data. The ADSP-218xN series has up to 48K words of Program Memory RAM on chip, and the capability of accessing up to two 8K external memory overlay spaces, using the external data bus. Table 8. PMOVLAY Bits Processor PMOVLAY Memory Program Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). External program execution is not available in host mode due to a restricted data bus that is only 16 bits wide. A13 A12–0 ADSP-2184N ADSP-2185N ADSP-2186N ADSP-2187N ADSP-2188N ADSP-2189N All Processors All Processors No Internal Overlay Region 0 No Internal Overlay Region 0, 4, 5 0, 4, 5, 6, 7 0, 4, 5 1 2 Not Applicable Internal Overlay Not Applicable Internal Overlay Internal Overlay Internal Overlay External Overlay 1 External Overlay 2 Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable 0 1 Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable 13 LSBs of Address Between 0x2000 and 0x3FFF 13 LSBs of Address Between 0x2000 and 0x3FFF Data Memory Data Memory (Full Memory Mode) is a 16-bit-wide space used for the storage of data variables and for memorymapped control registers. The ADSP-218xN series has up to 56K words of Data Memory RAM on-chip. Part of this space is used by 32 memory-mapped registers. Support also exists for up to two 8K external memory overlay spaces through the external data bus. All internal accesses comTable 9. DMOVLAY Bits Processor DMOVLAY Memory plete in one cycle. Accesses to external memory are timed using the wait states specified by the DWAIT register and the wait state mode bit. Data Memory (Host Mode) allows access to all internal memory. External overlay access is limited by a single external address line (A0). A13 A12–0 ADSP-2184N ADSP-2185N ADSP-2186N ADSP-2187N ADSP-2188N ADSP-2189N All Processors No Internal Overlay Region 0 No Internal Overlay Region 0, 4, 5 0, 4, 5, 6, 7, 8 0, 4, 5, 6, 7 1 Not Applicable Internal Overlay Not Applicable Internal Overlay Internal Overlay Internal Overlay External Overlay 1 Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable 0 Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable Not Applicable 13 LSBs of Address Between 0x0000 and 0x1FFF 13 LSBs of Address Between 0x0000 and 0x1FFF All Processors 2 External Overlay 2 1 –14– REV. 0 ADSP-218xN Series Memory-Mapped Registers (New to the ADSP-218xM and N series) WAIT STATE CONTROL 2 er 0 1 st DM(0X3FFE) 1 gi 1 1 1 Re l tro DWAIT IOWAIT3 IOWAIT2 IOWAIT1 IOWAIT0 on eC tat S WAIT STATE MODE SELECT ait 0 = NORMAL MODE (PWAIT, W t DWAIT, IOWAIT0–3 = N WAIT STATES, RANGING FROM 0 TOer 7) Ins 1 = 2N + 1 MODE (PWAIT, DWAIT, IOWAIT0–3 = 2N + 1 WAIT STATES, 15 14 13 12 11 10 1 1 1 1 1 1 9 8 7 6 5 4 3 1 1 1 1 1 1 RANGING FROM 0 TO 15) ADSP-218xN series members have three memory-mapped registers that differ from other ADSP-21xx Family DSPs. The slight modifications to these registers (Wait State Control, Programmable Flag and Composite Select Control, and System Control) provide the ADSP-218xN’s wait state and BMS control features. Default bit values at reset are shown; if no value is shown, the bit is undefined at reset. Reserved bits are shown on a grey field. These bits should always be written with zeros. I/O Space (Full Memory Mode) Figure 9. Wait State Control Register Composite Memory Select ADSP-218xN series members support an additional external memory space called I/O space. This space is designed to support simple connections to peripherals (such as data converters and external registers) or to bus interface ASIC data registers. I/O space supports 2048 locations of 16-bit wide data. The lower eleven bits of the external address bus are used; the upper three bits are undefined. Two instructions were added to the core ADSP-2100 Family instruction set to read from and write to I/O memory space. The I/O space also has four dedicated three-bit wait state registers, IOWAIT0–3 as shown in Figure 9, which in combination with the wait state mode bit, specify up to 15 wait states to be automatically generated for each of four regions. The wait states act on address ranges, as shown in Table 10. Note: In Full Memory Mode, all 2048 locations of I/O space are directly addressable. In Host Memory Mode, only address pin A0 is available; therefore, additional logic is required externally to achieve complete addressability of the 2048 I/O space locations. Table 10. Wait States Address Range Wait State Register ADSP-218xN series members have a programmable memory select signal that is useful for generating memory select signals for memories mapped to more than one space. The CMS signal is generated to have the same timing as each of the individual memory select signals (PMS, DMS, BMS, IOMS) but can combine their functionality. Each bit in the CMSSEL register, when set, causes the CMS signal to be asserted when the selected memory select is asserted. For example, to use a 32K word memory to act as both program and data memory, set the PMS and DMS bits in the CMSSEL register and use the CMS pin to drive the chip select of the memory, and use either DMS or PMS as the additional address bit. The CMS pin functions like the other memory select signals with the same timing and bus request logic. A 1 in the enable bit causes the assertion of the CMS signal at the same time as the selected memory select signal. All enable bits default to 1 at reset, except the BMS bit. See Figure 10 and Figure 11 for illustration of the programmable flag and composite control register and the system control register. 0x000–0x1FF 0x200–0x3FF 0x400–0x5FF 0x600–0x7FF IOWAIT0 and Wait State Mode Select Bit IOWAIT1 and Wait State Mode Select Bit IOWAIT2 and Wait State Mode Select Bit IOWAIT3 and Wait State Mode Select Bit PROGRAMMABLE FLAG AND COMPOSITE SELECT CONTROL 15 14 1 1 13 12 1 1 11 10 1 0 9 1 8 1 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 DM(0X3FE6) BM W A IT CM SSEL 0 = D IS A B L E C MS 1 = E N A B L E C MS PFT YP E 0 = IN PU T 1 = O UTPUT ( W H E R E B IT : 1 1 - I O M , 1 0 - B M , 9 - D M , 8 - P M ) Figure 10. Programmable Flag and Composite Control Register REV. 0 –15– ADSP-218xN Series SYSTEM CONTROL 15 14 13 12 11 10 0 0 0 0 0 1 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 1 1 1 0 1 DM(0X3FFF) BDMA CONTROL 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 1 2 0 1 0 0 0 DM (0x3FE3) R ESERVED SET TO 0 SPORT0 ENABLE 0 = DISABLE 1 = ENABLE SPORT1 ENABLE 0 = DISABLE 1 = ENABLE RESERVED, A LWAYS SET TO 0 PWAIT PROGRAM MEMORY WAIT STATES BMPAGE BDMA OVERLAY BITS (SEE TABLE 12) DI SA BL E BMS 0 = EN AB LE BMS 1 = DISA B L E BMS BTYPE BDIR 0 = LOAD FROM BM 1 = STORE TO BM BCR 0 = RUN DURING BDMA 1 = HALT DURING BDMA Figure 12. BDMA Control Register SPORT1 CONFIGURE 0 = FI, FO, IRQ0, IRQ1, SC LK 1 = SPORT1 NOTE: RESERVED B ITS ARE SHOWN O N A GRAY FIELD. THESE B ITS SHOULD ALWAYS BE WRITTEN WITH ZEROS. Figure 11. System Control Register Byte Memory Select The BDMA circuit supports four different data formats that are selected by the BTYPE register field. The appropriate number of 8-bit accesses are done from the byte memory space to build the word size selected. Table 11 shows the data formats supported by the BDMA circuit. Table 11. Data Formats BTYPE Internal Memory Space Word Size Alignment The ADSP-218xN’s BMS disable feature combined with the CMS pin allows use of multiple memories in the byte memory space. For example, an EPROM could be attached to the BMS select, and a flash memory could be connected to CMS. Because at reset BMS is enabled, the EPROM would be used for booting. After booting, software could disable BMS and set the CMS signal to respond to BMS, enabling the flash memory. Byte Memory 00 01 10 11 Program Memory Data Memory Data Memory Data Memory 24 16 8 8 Full Word Full Word MSBs LSBs The byte memory space is a bidirectional, 8-bit-wide, external memory space used to store programs and data. Byte memory is accessed using the BDMA feature. The byte memory space consists of 256 pages, each of which is 16K 8 bits. The byte memory space on the ADSP-218xN series supports read and write operations as well as four different data formats. The byte memory uses data bits 15–8 for data. The byte memory uses data bits 23–16 and address bits 13–0 to create a 22-bit address. This allows up to a 4 meg 8 (32 megabit) ROM or RAM to be used without glue logic. All byte memory accesses are timed by the BMWAIT register and the wait state mode bit. Byte Memory DMA (BDMA, Full Memory Mode) Unused bits in the 8-bit data memory formats are filled with 0s. The BIAD register field is used to specify the starting address for the on-chip memory involved with the transfer. The 14-bit BEAD register specifies the starting address for the external byte memory space. The 8-bit BMPAGE register specifies the starting page for the external byte memory space. The BDIR register field selects the direction of the transfer. Finally, the 14-bit BWCOUNT register specifies the number of DSP words to transfer and initiates the BDMA circuit transfers. BDMA accesses can cross page boundaries during sequential addressing. A BDMA interrupt is generated on the completion of the number of transfers specified by the BWCOUNT register. The BWCOUNT register is updated after each transfer so it can be used to check the status of the transfers. When it reaches zero, the transfers have finished and a BDMA interrupt is generated. The BMPAGE and BEAD registers must not be accessed by the DSP during BDMA operations. The source or destination of a BDMA transfer will always be on-chip program or data memory. When the BWCOUNT register is written with a nonzero value the BDMA circuit starts executing byte memory accesses with wait states set by BMWAIT. These accesses continue until the count reaches zero. When enough accesses have occurred to create a destination word, it is transferred to or from on-chip memory. The transfer takes one The byte memory DMA controller (Figure 12) allows loading and storing of program instructions and data using the byte memory space. The BDMA circuit is able to access the byte memory space while the processor is operating normally and steals only one DSP cycle per 8-, 16-, or 24bit word transferred. –16– REV. 0 ADSP-218xN Series DSP cycle. DSP accesses to external memory have priority over BDMA byte memory accesses. The BDMA Context Reset bit (BCR) controls whether the processor is held off while the BDMA accesses are occurring. Setting the BCR bit to 0 allows the processor to continue operations. Setting the BCR bit to 1 causes the processor to stop execution while the BDMA accesses are occurring, to clear the context of the processor, and start execution at address 0 when the BDMA accesses have completed. The BDMA overlay bits specify the OVLAY memory blocks to be accessed for internal memory. Set these bits as indicated in. Note: BDMA cannot access external overlay memory regions 1 and 2. The BMWAIT field, which has four bits on ADSP-218xN series members, allows selection up to 15 wait states for BDMA transfers. Internal Memory DMA Port (IDMA Port; Host Memory Mode) Table 12. IDMA/BDMA Overlay Bits Processor IDMA/BDMA PMOVLAY IDMA/BDMA DMOVLAY ADSP-2184N ADSP-2185N ADSP-2186N ADSP-2187N ADSP-2188N ADSP-2189N 0 0 0 0, 4, 5 0, 4, 5, 6, 7 0, 4, 5 0 0 0 0, 4, 5 0, 4, 5, 6, 7, 8 0, 4, 5, 6, 7 The IDMA port has a 16-bit multiplexed address and data bus and supports 24-bit program memory. The IDMA port is completely asynchronous and can be written while the ADSP-218xN is operating at full speed. The DSP memory address is latched and then automatically incremented after each IDMA transaction. An external device can therefore access a block of sequentially addressed memory by specifying only the starting address of the block. This increases throughput as the address does not have to be sent for each memory access. IDMA Port access occurs in two phases. The first is the IDMA Address Latch cycle. When the acknowledge is asserted, a 14-bit address and 1-bit destination type can be driven onto the bus by an external device. The address specifies an on-chip memory location, the destination type specifies whether it is a DM or PM access. The falling edge of the IDMA address latch signal (IAL) or the missing edge of the IDMA select signal (IS) latches this value into the IDMAA register. Once the address is stored, data can be read from, or written to, the ADSP-218xN’s on-chip memory. Asserting the select line (IS) and the appropriate read or write line (IRD and IWR respectively) signals the ADSP-218xN that a particular transaction is required. In either case, there is a oneprocessor-cycle delay for synchronization. The memory access consumes one additional processor cycle. Once an access has occurred, the latched address is automatically incremented, and another access can occur. Through the IDMAA register, the DSP can also specify the starting address and data format for DMA operation. Asserting the IDMA port select (IS) and address latch enable (IAL) directs the ADSP-218xN to write the address onto the IAD14–0 bus into the IDMA Control Register (Figure 13). If Bit 15 is set to 0, IDMA latches the address. If Bit 15 is set to 1, IDMA latches into the OVLAY register. This register, also shown in Figure 13, is memory-mapped at address DM (0x3FE0). Note that the latched address (IDMAA) cannot be read back by the host. When Bit 14 in 0x3FE7 is set to zero, short reads use the timing shown in Figure 34 on page 37. When Bit 14 in 0x3FE7 is set to 1, timing in Figure 35 on page 38 applies for short reads in short read only mode. Set IDDMOVLAY The IDMA Port provides an efficient means of communication between a host system and ADSP-218xN series members. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’s memory-mapped control registers. A typical IDMA transfer process is shown as follows: 1. 2. 3. Host starts IDMA transfer. Host checks IACK control line to see if the DSP is busy. Host uses IS and IAL control lines to latch either the DMA starting address (IDMAA) or the PM/DM OVLAY selection into the DSP’s IDMA control registers. If Bit 15 = 1, the value of bits 7–0 represent the IDMA overlay; bits 14–8 must be set to 0. If Bit 15 = 0, the value of Bits 13–0 represent the starting address of internal memory to be accessed and Bit 14 reflects PM or DM for access. Set IDDMOVLAY and IDPMOVLAY bits in the IDMA overlay register as indicted in Table 12. Host uses IS and IRD (or IWR) to read (or write) DSP internal memory (PM or DM). Host checks IACK line to see if the DSP has completed the previous IDMA operation. Host ends IDMA transfer. 4. 5. 6. REV. 0 –17– ADSP-218xN Series and IDPMOVLAY bits in the IDMA overlay register as indicated in Table 12. Refer to the ADSP-218x DSP Hardware Reference for additional details. Note: In full memory mode all locations of 4M-byte memory space are directly addressable. In host memory mode, only address pin A0 is available, requiring additional external logic to provide address information for the byte. IDMA OVERLAY 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 DM (0x3FE7) IDMA Port Booting ADSP-218xN series members can also boot programs through its Internal DMA port. If Mode C = 1, Mode B = 0, and Mode A = 1, the ADSP-218xN boots from the IDMA port. IDMA feature can load as much on-chip memory as desired. Program execution is held off until the host writes to on-chip program memory location 0. BUS REQUEST AND BUS GRANT RESERVED SET TO 0 IDDMOVLAY IDPMOVLAY (SEE TABLE 12) SHORT READ ONLY 0 = DISABLE 1 = ENABLE ADSP-218xN series members can relinquish control of the data and address buses to an external device. When the external device requires access to memory, it asserts the Bus Request (BR) signal. If the ADSP-218xN is not performing an external memory access, it responds to the active BR input in the following processor cycle by: • Three-stating the data and address buses and the PMS, DMS, BMS, CMS, IOMS, RD, WR output drivers, RESERVED SET TO 0 IDMA CONTROL (U = UNDEFINED AT RESET) 15 14 13 12 11 10 0 U U U U U 9 U 8 U 7 U 6 U 5 U 4 U 3 U 2 U 1 U 0 U DM (0x3FE0) • Asserting the bus grant (BG) signal, and • Halting program execution. If Go Mode is enabled, the ADSP-218xN will not halt program execution until it encounters an instruction that requires an external memory access. If an ADSP-218xN series member is performing an external memory access when the external device asserts the BR signal, it will not three-state the memory interfaces nor assert the BG signal until the processor cycle after the access completes. The instruction does not need to be completed when the bus is granted. If a single instruction requires two external memory accesses, the bus will be granted between the two accesses. When the BR signal is released, the processor releases the BG signal, re-enables the output drivers, and continues program execution from the point at which it stopped. The bus request feature operates at all times, including when the processor is booting and when RESET is active. The BGH pin is asserted when an ADSP-218xN series member requires the external bus for a memory or BDMA access, but is stopped. The other device can release the bus by deasserting bus request. Once the bus is released, the ADSP-218xN deasserts BG and BGH and executes the external memory access. FLAG I/O PINS IDMAA ADDRESS IDMAD DESTINATION MEMORY TYPE 0 = PM 1 = DM NOTE: RESERVED BITS ARE SHOWN ON A GRAY FIELD. THESE BITS SHOULD ALWAYS BE WRITTEN WITH ZEROS. RESERVED SET TO 0 Figure 13. IDMA OVLAY/Control Registers Bootstrap Loading (Booting) ADSP-218xN series members have two mechanisms to allow automatic loading of the internal program memory after reset. The method for booting is controlled by the Mode A, B, and C configuration bits. When the mode pins specify BDMA booting, the ADSP218xN initiates a BDMA boot sequence when reset is released. The BDMA interface is set up during reset to the following defaults when BDMA booting is specified: the BDIR, BMPAGE, BIAD, and BEAD registers are set to 0, the BTYPE register is set to 0 to specify program memory 24bit words, and the BWCOUNT register is set to 32. This causes 32 words of on-chip program memory to be loaded from byte memory. These 32 words are used to set up the BDMA to load in the remaining program code. The BCR bit is also set to 1, which causes program execution to be held off until all 32 words are loaded into on-chip program memory. Execution then begins at address 0. The ADSP-2100 Family development software (Revision 5.02 and later) fully supports the BDMA booting feature and can generate byte memory space-compatible boot code. The IDLE instruction can also be used to allow the processor to hold off execution while booting continues through the BDMA interface. For BDMA accesses while in Host Mode, the addresses to boot memory must be constructed externally to the ADSP-218xN. The only memory address bit provided by the processor is A0. ADSP-218xN series members have eight general-purpose programmable input/output flag pins. They are controlled by two memory-mapped registers. The PFTYPE register determines the direction, 1 = output and 0 = input. The PFDATA register is used to read and write the values on the pins. Data being read from a pin configured as an input is synchronized to the ADSP-218xN’s clock. Bits that are programmed as outputs will read the value being output. The PF pins default to input during reset. –18– REV. 0 ADSP-218xN Series In addition to the programmable flags, ADSP-218xN series members have five fixed-mode flags, FI, FO, FL0, FL1, and FL2. FL0–FL2 are dedicated output flags. FI and FO are available as an alternate configuration of SPORT1. Note: Pins PF0, PF1, PF2, and PF3 are also used for device configuration during reset. INSTRUCTION SET DESCRIPTION if the RESET pin is being used as a method of setting the value of the mode pins, the effects of an emulator reset must be taken into consideration. One method of ensuring that the values located on the mode pins are those desired is to construct a circuit like the one shown in Figure 14. This circuit forces the value located on the Mode A pin to logic high, regardless of whether it is latched via the RESET or ERESET pin. The ADSP-218xN series assembly language instruction set has an algebraic syntax that was designed for ease of coding and readability. The assembly language, which takes full advantage of the processor’s unique architecture, offers the following benefits: • The algebraic syntax eliminates the need to remember cryptic assembler mnemonics. For example, a typical arithmetic add instruction, such as AR = AX0 + AY0, resembles a simple equation. • Every instruction assembles into a single, 24-bit word that can execute in a single instruction cycle. • The syntax is a superset ADSP-2100 Family assembly language and is completely source and object code compatible with other family members. Programs may need to be relocated to utilize on-chip memory and conform to the ADSP-218xN’s interrupt vector and reset vector map. • Sixteen condition codes are available. For conditional jump, call, return, or arithmetic instructions, the condition can be checked and the operation executed in the same instruction cycle. • Multifunction instructions allow parallel execution of an arithmetic instruction, with up to two fetches or one write to processor memory space, during a single instruction cycle. DESIGNING AN EZ-ICE-COMPATIBLE SYSTEM ERESET RESET ADSP-218xN 1k MODE A/PF0 PROGRAMMABLE I/O Figure 14. Mode A Pin/EZ-ICE Circuit The ICE-Port interface consists of the following ADSP218xN pins: EBR, EINT, EE, EBG, ECLK, ERESET, ELIN, EMS, and ELOUT. These ADSP-218xN pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pullup or pull-down resistors. The traces for these signals between the ADSP-218xN and the connector must be kept as short as possible, no longer than 3 inches. The following pins are also used by the EZ-ICE: BR, BG, RESET, and GND. The EZ-ICE uses the EE (emulator enable) signal to take control of the ADSP-218xN in the target system. This causes the processor to use its ERESET, EBR, and EBG pins instead of the RESET, BR, and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in the system. The EZ-ICE connects to the target system via a ribbon cable and a 14-pin female plug. The female plug is plugged onto the 14-pin connector (a pin strip header) on the target board. Target Board Connector for EZ-ICE Probe ADSP-218xN series members have on-chip emulation support and an ICE-Port, a special set of pins that interface to the EZ-ICE. These features allow in-circuit emulation without replacing the target system processor by using only a 14-pin connection from the target system to the EZ-ICE. Target systems must have a 14-pin connector to accept the EZ-ICE’s in-circuit probe, a 14-pin plug. Note: The EZ-ICE uses the same VDD voltage as the VDD voltage used for VDDEXT. Because the input pins of the ADSP-218xN series members are tolerant to input voltages up to 3.6 V, regardless of the value of VDDEXT, the voltage setting for the EZ-ICE must not exceed 3.3 V. Issuing the chip reset command during emulation causes the DSP to perform a full chip reset, including a reset of its memory mode. Therefore, it is vital that the mode pins are set correctly PRIOR to issuing a chip reset command from the emulator user interface. If a passive method of maintaining mode information is being used (as discussed in Setting Memory Mode on page 11), it does not matter that the mode information is latched by an emulator reset. However, REV. 0 The EZ-ICE connector (a standard pin strip header) is shown in Figure 15. This connector must be added to the target board design to use the EZ-ICE. Be sure to allow enough room in the system to fit the EZ-ICE probe onto the 14-pin connector. The 14-pin, 2-row pin strip header is keyed at the Pin 7 location—Pin 7 must be removed from the header. The pins must be 0.025 inch square and at least 0.20 inch in length. –19– ADSP-218xN Series Target System Interface Signals 1 GND 3 EBG 5 EBR 7 KEY (NO PIN) 2 BG 4 BR 6 EINT 8 ELIN 10 ECLK 12 EMS 14 ERESET When the EZ-ICE board is installed, the performance on some system signals changes. Design the system to be compatible with the following system interface signal changes introduced by the EZ-ICE board: • EZ-ICE emulation introduces an 8 ns propagation delay between the target circuitry and the DSP on the RESET signal. • EZ-ICE emulation introduces an 8 ns propagation delay between the target circuitry and the DSP on the BR signal. • EZ-ICE emulation ignores RESET and BR, when single-stepping. • EZ-ICE emulation ignores RESET and BR when in Emulator Space (DSP halted). • EZ-ICE emulation ignores the state of target BR in certain modes. As a result, the target system may take control of the DSP’s external memory bus only if bus grant (BG) is asserted by the EZ-ICE board’s DSP. 9 ELOUT 11 EE RESET 13 TOP VIEW Figure 15. Target Board Connector for EZ-ICE Pin spacing should be 0.1 0.1 inches. The pin strip header must have at least 0.15 inch clearance on all sides to accept the EZ-ICE probe plug. Pin strip headers are available from vendors such as 3M, McKenzie, and Samtec. Target Memory Interface For the target system to be compatible with the EZ-ICE emulator, it must comply with the memory interface guidelines listed below. PM, DM, BM, IOM, and CM Design the Program Memory (PM), Data Memory (DM), Byte Memory (BM), I/O Memory (IOM), and Composite Memory (CM) external interfaces to comply with worstcase device timing requirements and switching characteristics as specified in this data sheet. The performance of the EZ-ICE may approach published worst-case specification for some memory access timing requirements and switching characteristics. Note: If the target does not meet the worst-case chip specification for memory access parameters, the circuitry may not be able to be emulated at the desired CLKIN frequency. Depending on the severity of the specification violation, the system may be difficult to manufacture, as DSP components statistically vary in switching characteristic and timing requirements, within published limits. Restriction: All memory strobe signals on the ADSP218xN (RD, WR, PMS, DMS, BMS, CMS, and IOMS) used in the target system must have 10 k pull-up resistors connected when the EZ-ICE is being used. The pull-up resistors are necessary because there are no internal pullups to guarantee their state during prolonged three-state conditions resulting from typical EZ-ICE debugging sessions. These resistors may be removed when the EZ-ICE is not being used. –20– REV. 0 ADSP-218xN Series SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS K Grade (Commercial) Parameter 1 B Grade (Industrial) Min Max Unit Min Max VDDINT VDDEXT VINPUT2 TAMB 1Specifications 2The 1.71 1.71 VIL = – 0.3 0 1.89 3.6 VIH = + 3.6 70 1.8 1.8 VIL = – 0.3 –40 2.0 3.6 VIH = + 3.6 +85 V V V °C subject to change without notice. ADSP-218xN is 3.3 V tolerant (always accepts up to 3.6 V max VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT, because VOH (max) approximately equals VDDEXT (max). This 3.3 V tolerance applies to bidirectional pins (D23–D0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13 –A 1, PF7–PF0) and input-only pins (CLKIN, RESET, BR, DR0, DR1, PWD). ELECTRICAL CHARACTERISTICS Parameter1 Description Test Conditions Min Typ Max Unit VIH Hi-Level Input Voltage2, 3 VIL Lo-Level Input Voltage2, 3 VOH Hi-Level Output Voltage2, 4, 5 VOL IIH IIL IOZH IOZL IDD Lo-Level Output Voltage2, 4, 5 Hi-Level Input Current3 Lo-Level Input Current3 Three-State Leakage Current7 Three-State Leakage Current7 Supply Current (Idle)9 IDD Supply Current (Dynamic)10 @ VDDEXT = 1.71 to 2.0 V, VDDINT = max @ VDDEXT = 2.1 to 3.6 V, VDDINT = max @ VDDEXT 2.0 V, VDDINT = min @ VDDEXT 2.0 V, VDDINT = min @ VDDEXT = 1.71 to 2.0 V, IOH = – 0.5 mA @ VDDEXT = 2.1 to 2.9 V, IOH = – 0.5 mA @ VDDEXT = 3.0 to 3.6 V, IOH = – 0.5 mA @ VDDEXT = 1.71 to 3.6 V, IOH = – 100 µA6 @ VDDEXT = 1.71 to 3.6 V, IOL = 2.0 mA @ VDDINT = max, VIN = 3.6 V @ VDDINT = max, VIN = 0 V @ VDDEXT = max, VIN = 3.6 V8 @ VDDEXT = max, VIN = 0 V8 @ VDDINT = 1.8 V, tCK = 12.5 ns, TAMB = 25°C @ VDDINT = 1.8 V, tCK = 12.5 ns11, TAMB = 25°C 1.25 V 0.6 0.7 1.35 2.0 2.4 VDDEXT – 0.3 0.4 10 10 10 10 6 V V V V V V V µA µA µA µA mA 25 mA REV. 0 –21– ADSP-218xN Series ELECTRICAL CHARACTERISTICS Parameter1 Description (CONTINUED) Test Conditions Min Typ Max Unit IDD Supply Current (Idle) 9 IDD Supply Current (Dynamic)10 IDD CI Supply Current (PowerDown)12 Input Pin Capacitance3, 6 CO Output Pin Capacitance6, 7, 12, 13 @ VDDINT = 1.9 V, tCK = 12.5 ns, TAMB = 25°C @ VDDINT = 1.9 V, tCK = 12.5 ns11, TAMB = 25°C @ VDDINT = 1.8 V, TAMB = 25°C in Lowest Power Mode @ VIN = 1.8 V, fIN = 1.0 MHz, TAMB = 25°C @ VIN = 1.8 V, fIN = 1.0 MHz, TAMB = 25°C 6.5 mA 26 mA 100 µA 8 pF 8 pF 1Specifications 2Bidirectional subject to change without notice. pins: D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–1, PF7–0. 3Input only pins: CLKIN, RESET, BR, DR0, DR1, PWD. 4Output pins: BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2 –FL0, BGH. 5Although specified for TTL outputs, all ADSP-218xN outputs are CMOS-compatible and will drive to V DDEXT and GND, assuming no dc loads. 6Guaranteed but not tested. 7Three-statable pins: A13–A1, D23–D0, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, PF7–PF0. 80 V on BR. 9Idle refers to ADSP-218xN state of operation during execution of IDLE instruction. Deasserted pins are driven to either V DD or GND. 10I DD measurement taken with all instructions executing from internal memory. 50% of the instructions are multifunction (Types 1, 4, 5, 12, 13, 14), 30% are Type 2 and Type 6, and 20% are idle instructions. 11V = 0 V and 3 V. For typical values for supply currents, refer to Power Dissipation section. IN 12See ADSP-218x DSP Hardware Reference for details. 13Output pin capacitance is the capacitive load for any three-stated output pin. ABSOLUTE MAXIMUM RATINGS Internal Supply Voltage (VDDINT)1 . . . . . . . . –0.3 V to +2.2 V External Supply Voltage (VDDEXT) . . . . . . . . –0.3 V to +4.0 V Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to +4.0 V Output Voltage Swing3 . . . . . . . . . . .–0.5 V to VDDEXT + 0.5 V Operating Temperature Range . . . . . . . . . . . –40ºC to +85ºC Storage Temperature Range . . . . . . . . . . . . –65ºC to +150ºC Lead Temperature (5 sec) LQFP . . . . . . . . . . . . . . . –280ºC 1Stresses greater than those listed above may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2Applies to Bidirectional pins (D23–0, RFS0, RFS1, SCLK0, SCLK1, TFS0, TFS1, A13–1, PF7–0) and Input only pins (CLKIN, RESET, BR, DR0, DR1, PWD). 3Applies to Output pins (BG, PMS, DMS, BMS, IOMS, CMS, RD, WR, PWDACK, A0, DT0, DT1, CLKOUT, FL2 –0, BGH). –22– REV. 0 ADSP-218xN Series ESD SENSITIVITY CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-218xN features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Power Dissipation Assumptions: • External data memory is accessed every cycle with 50% of the address pins switching. • External data memory writes occur every other cycle with 50% of the data pins switching. • Each address and data pin has a 10 pF total load at the pin. • Application operates at VDDEXT = 3.3 V and tCK = 30 ns. Total Power Dissipation = PINT + (C VDDEXT2 f) P INT = internal power dissipation from Figure 20 on page 26. (C VDDEXT2 f) is calculated for each output, as in the example in Table 13. To determine total power dissipation in a specific application, the following equation should be applied for each output: C VDD2 f where: C = load capacitance, f = output switching frequency. Example: In an application where external data memory is used and no other outputs are active, power dissipation is calculated as follows: Table 13. Example Power Dissipation Calculation Parameters # of Pins × C (pF) × VDDEXT2 (V) × f (MHz) PD (mW) Address Data Output, WR RD CLKOUT, DMS 7 9 1 2 10 10 10 10 3.3 3.32 3.32 3.32 2 20.0 20.0 20.0 40.0 15.25 19.59 2.18 8.70 45.72 Total power dissipation for this example is PINT + 45.72 mW. REV. 0 –23– ADSP-218xN Series Environmental Conditions Table 14. Thermal Resistance LQFP (°C/W) MiniBGA (°C/W) REFERENCE SIGNAL tMEASURED tENA VOH (MEASURED) OUTPUT VOL (MEASURED) + 0.5V VOL (MEASURED) tDIS VOH (MEASURED) – 0.5V 2.0V 1.0V Rating Description 1 V OH (MEASURED) Symbol Thermal Resistance (Case-to-Ambient) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) 1Where θCA θJA θJC 48 50 2 63.3 70.7 7.4 tDECAY OUTPUT STOPS DRIVING VOL (MEASURED) OUTPUT STARTS DRIVING HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE LEVEL TO BE APPROXIMATELY 1.5V. the Ambient Temperature Rating (TAMB) is: TAMB = TCASE – (PD × θCA) TCASE = Case Temperature in °C PD = Power Dissipation in W Figure 18. Output Enable/Disable Output Disable Time Test Conditions INPUT 1.5V OUTPUT 2.0V 1.5V 0.8V Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state. The output disable time (tDIS) is the difference of tMEASURED and tDECAY, as shown in Figure 18. The time is the interval from when a reference signal reaches a high or low voltage level to when the output voltages have changed by 0.5 V from the measured output high or low voltage. The decay time, tDECAY, is dependent on the capacitive load, CL, and the current load, iL, on the output pin. It can be approximated by the following equation: C L × 0.5 V tDECAY = ------------------------iL Figure 16. Voltage Reference Levels for AC Measurements (Except Output Enable/Disable) I OL from which t DIS = t MEASURED – t DECAY TO OUTPUT PIN 1.5V 50pF is calculated. If multiple pins (such as the data bus) are disabled, the measurement value is that of the last pin to stop driving. Output Enable Time IOH Figure 17. Equivalent Loading for AC Measurements (Including All Fixtures) Output pins are considered to be enabled when they have made a transition from a high-impedance state to when they start driving. The output enable time (tENA) is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in Figure 18. If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving. –24– REV. 0 ADSP-218xN Series 80 TIMING SPECIFICATIONS SOURCE CURRENT – mA VDDEXT = 3.6V @ –40 C 60 40 20 0 –20 –40 –60 –80 VOH VDDEXT = 2 .5V @ +85 C VDDEXT = 3.3V @ +25 C This section contains timing information for the DSP’s external signals. General Notes VDDEXT = 1 .8V @ +85 C VDDEXT = 3.6V @ –40 C VOL VDDEXT ==11.8/2.5V@ +85 C VDDEXT .8/2.5V @ +85 C VDDEXT = 3.3V @ +25 C Use the exact timing information given. Do not attempt to derive parameters from the addition or subtraction of others. While addition or subtraction would yield meaningful results for an individual device, the values given in this data sheet reflect statistical variations and worst cases. Consequently, parameters cannot be added up meaningfully to derive longer times. Timing Notes 0 0.5 1.0 1.5 2.0 2.5 SOURCE VOLTAGE – V 3.0 3.5 4.0 Switching characteristics specify how the processor changes its signals. Designers have no control over this timing— circuitry external to the processor must be designed for compatibility with these signal characteristics. Switching characteristics tell what the processor will do in a given circumstance. Switching characteristics can also be used to ensure that any timing requirement of a device connected to the processor (such as memory) is satisfied. Timing requirements apply to signals that are controlled by circuitry external to the processor, such as the data input for a read operation. Timing requirements guarantee that the processor operates correctly with other devices. Frequency Dependency For Timing Specifications Figure 19. Typical Output Driver Characteristics for VDDEXT at 3.6 V, 3.3 V, 2.5 V, and 1.8 V tCK is defined as 0.5 tCKI. The ADSP-218xN uses an input clock with a frequency equal to half the instruction rate. For example, a 40 MHz input clock (which is equivalent to 25 ns) yields a 12.5 ns processor cycle (equivalent to 80 MHz). tCK values within the range of 0.5 tCKI period should be substituted for all relevant timing parameters to obtain the specification value. Example: tCKH = 0.5 tCK – 2 ns = 0.5 (12.5 ns) – 2 ns= 4.25 ns Output Drive Currents Figure 19 shows typical I-V characteristics for the output drivers on the ADSP-218xN series.The curves represent the current drive capability of the output drivers as a function of output voltage. Figure 21 shows the typical power-down supply current. Capacitive Loading Figure 22 and Figure 23 on page 26 show the capacitive loading characteristics of the ADSP-218xN. REV. 0 –25– ADSP-218xN Series 1000 60 55 POWER (PINT) – mW POW ER, INTERNAL 1, 2, 3 CURRENT (LOG SCALE) – µA 55 m W V = 2 .0 T V D D IN 9V = 1. T V D D IN V = 1 .8 T V D D IN 1V = 1 .7 V D D IN T VDD VDD VDD VDD 100 = = = = 2 .0V 1 .9V 1 .8V 1 .7V 50 45 42 m W 40 35 30 25 20 55 60 65 38 mW 34 mW 3 0 mW 50 mW 45 m W 40 mW 10 70 1/tCK – M Hz 75 80 85 15.0 14.0 13.0 POWER (PIDLE) – mW POW ER, IDLE 1, 2, 4 13 . 5 m W V = 2 .0 T V D D IN V = 1 .9 V D D IN T V = 1 .8 V D D IN T = 1 .7 1V V D D IN T 12.0 11.0 10.0 9.0 8.0 7.0 6.0 5.0 55 60 65 10 . 5 m W 9.5m W 8 .5 m W 7 .5 m W 12 m W 10 .5 m W 9m W 0 25 55 85 TEMPERATURE – °C NOTES 1. REFLECTS ADSP-218xN OPERATION IN LOWEST POWER MODE. (SEE THE "SYSTEM INTERFACE" CHAPTER OF THE ADSP-218x DSP HARDWARE REFERENCE FOR DETAILS.) 2. CURRENT REFLECTS DEVICE OPERATING WITH NO INPUT LOADS. 0 Figure 21. Typical Power-Down Current 30 T = 85 C VDD = 0 V TO 2.0V 25 RISE TIME (0.4V–2.4V) – ns 20 15 70 1/tCK – M Hz 75 80 85 POWER, IDLE n M ODES2 12.0 10.0 9.5mW POWER (PIDLEn) – mW 12.0mW 1 0.5mW 10 5 VDD COR E = 1.9V VDD COR E = 1.8V 8.0 8.5mW 0 5.2mW 4.9mW 4 .7mW 4.3mW 6.0 4.0 2.0 0.0 55 4.2mW 3.8mW 3 .4mW 0 50 100 150 CL – p F 200 250 300 Figure 22. Typical Output Rise Time vs. Load Capacitance (at Maximum Ambient Operating Temperature) 18 60 65 70 1/tCK – M Hz 75 80 85 16 VALID OUTPUT DELAY OR HOLD – ns NOT ES VALID F OR ALL TEMPERATURE GRADES. 1 14 12 10 8 6 4 2 NOMINAL –2 –4 –6 0 50 100 CL – p F 150 200 250 POW ER R EFLEC TS D EVIC E O PERATING WITH NO OUT PUT LOAD S. 2 TYPICAL POWER D ISSIPATION AT 1.8V O R 1.9V V DDINT A ND 25°C, EXCEPT WHER E SPECIFIED. 3 IDD M EASUREM ENT TAKEN W ITH ALL INSTRUCTIONS EXECU TING FROM INTERNAL MEMO RY. 50% O F THE INSTRUCTIONS ARE MU LTIFUNCTION (TYPES 1, 4, 5, 12, 13, 14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS. IDLE R EFERS TO STATE OF OPER ATION DURIN G EXECUTIO N OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EIT HER V DD O R G ND. 4 Figure 20. Power vs. Frequency Figure 23. Typical Output Valid Delay or Hold vs. Load Capacitance, CL (at Maximum Ambient Operating Temperature) –26– REV. 0 ADSP-218xN Series Clock Signals and Reset Table 15. Clock Signals and Reset Parameter Min Max Unit Timing Requirements: tCKI CLKIN Period tCKIL CLKIN Width Low tCKIH CLKIN Width High Switching Characteristics: tCKL CLKOUT Width Low CLKOUT Width High tCKH tCKOH CLKIN High to CLKOUT High Control Signals Timing Requirements: tRSP RESET Width Low tMS Mode Setup before RESET High tMH Mode Hold after RESET High 1Applies 25 8 8 0.5tCK – 3 0.5tCK – 3 0 5tCK1 7 5 40 ns ns ns ns ns ns ns ns ns 8 after power-up sequence is complete. Internal phase lock loop requires no more than 2000 CLKIN cycles, assuming stable CLKIN (not including crystal oscillator start-up time). tCKI tCKIH CLKIN tCKIL tCKOH tCKH CLKOUT tCKL MODE A D tMS RESET tMH tRSP Figure 24. Clock Signals and Reset REV. 0 –27– ADSP-218xN Series Interrupts and Flags Table 16. Interrupts and Flags Parameter Min Max Unit Timing Requirements: tIFS IRQx, FI, or PFx Setup before CLKOUT Low1, 2, 3, 4 tIFH IRQx, FI, or PFx Hold after CLKOUT High1, 2, 3, 4 Switching Characteristics: tFOH Flag Output Hold after CLKOUT Low5 tFOD Flag Output Delay from CLKOUT Low5 1If 0.25tCK + 10 0.25tCK 0.5tCK – 5 0.5tCK + 4 ns ns ns ns IRQx and FI inputs meet tIFS and tIFH setup/hold requirements, they will be recognized during the current clock cycle; otherwise the signals will be recognized on the following cycle. (Refer to “Interrupt Controller Operation” in the Program Control chapter of the ADSP-218x DSP Hardware Reference for further information on interrupt servicing.) 2Edge-sensitive interrupts require pulsewidths greater than 10 ns; level-sensitive interrupts must be held low until serviced. 3 IRQx = IRQ0, IRQ1, IRQ2, IRQL0, IRQL1, IRQLE. 4PFx = PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7. 5Flag Outputs = PFx, FL0, FL1, FL2, FO. tFOD CLKOUT tFOH FLAG OUTPUTS tIFH IRQx FI PFx tIFS Figure 25. Interrupts and Flags –28– REV. 0 ADSP-218xN Series Bus Request–Bus Grant Table 17. Bus Request–Bus Grant Parameter Min Max Unit Timing Requirements: tBH BR Hold after CLKOUT High1 tBS BR Setup before CLKOUT Low1 Switching Characteristics: tSD CLKOUT High to xMS, RD, WR Disable2 tSDB xMS, RD, WR Disable to BG Low BG High to xMS, RD, WR Enable tSE tSEC xMS, RD, WR Enable to CLKOUT High tSDBH xMS, RD, WR Disable to BGH Low3 tSEH BGH High to xMS, RD, WR Enable3 1BR 0.25tCK + 2 0.25tCK + 8 0.25tCK + 8 0 0 0.25tCK – 3 0 0 ns ns ns ns ns ns ns ns is an asynchronous signal. If BR meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on the following cycle. Refer to the ADSP-2100 Family User’s Manual for BR/BG cycle relationships. 2xMS = PMS, DMS, CMS, IOMS, BMS. 3BGH is asserted when the bus is granted and the processor or BDMA requires control of the bus to continue. tBH CLKOUT BR tBS CLKOUT PMS, DMS BMS, RD CMS, WR, IOMS BG tSD tSEC tSDB tSE BGH tSDBH tSEH Figure 26. Bus Request–Bus Grant REV. 0 –29– ADSP-218xN Series Memory Read Table 18. Memory Read Parameter Min Max Unit Timing Requirements: tRDD RD Low to Data Valid1 tAA A13–0, xMS to Data Valid2 tRDH Data Hold from RD High Switching Characteristics: tRP RD pulsewidth tCRD CLKOUT High to RD Low tASR A13–0, xMS Setup before RD Low tRDA A13–0, xMS Hold after RD Deasserted tRWR RD High to RD or WR Low 1w 2xMS 0.5tCK – 5 + w 0.75tCK – 6 + w 0 0.5tCK – 3 + w 0.25tCK – 2 0.25tCK – 3 0.25tCK – 3 0.5tCK – 3 ns ns ns ns ns ns ns ns 0.25tCK + 4 = wait states x tCK. = PMS, DMS, CMS, IOMS, BMS. CLKOUT A0–A13 DMS, PMS, BMS, I OMS, CMS tRDA RD tASR tCRD D0–D23 tRP tRWR tRDD tAA WR tRDH Figure 27. Memory Read –30– REV. 0 ADSP-218xN Series Memory Write Table 19. Memory Write Parameter Min Max Unit Switching Characteristics: tDW Data Setup before WR High1 tDH Data Hold after WR High tWP WR pulsewidth tWDE WR Low to Data Enabled tASW A13–0, xMS Setup before WR Low2 tDDR Data Disable before WR or RD Low tCWR CLKOUT High to WR Low tAW A13–0, xMS Setup before WR Deasserted A13–0, xMS Hold after WR Deasserted tWRA tWWR WR High to RD or WR Low 1 2xMS 0.5tCK– 4 + w 0.25tCK – 1 0.5tCK – 3 + w 0 0.25tCK – 3 0.25tCK – 3 0.25tCK – 2 0.75tCK – 5 + w 0.25tCK – 1 0.5tCK – 3 0.25tCK + 4 ns ns ns ns ns ns ns ns ns ns w = wait states tCK. = PMS, DMS, CMS, IOMS, BMS. CLKOUT A0–A13 DMS, PMS, BMS, CMS, IOMS WR tWRA tASW tAW tCWR D0–D23 tWP tDH tWWR tDDR tDW tWDE RD Figure 28. Memory Write REV. 0 –31– ADSP-218xN Series Serial Ports Table 20. Serial Ports Parameter Min Max Unit Timing Requirements: tSCK SCLK Period tSCS DR/TFS/RFS Setup before SCLK Low tSCH DR/TFS/RFS Hold after SCLK Low SCLKIN Width tSCP Switching Characteristics: tCC CLKOUT High to SCLKOUT tSCDE SCLK High to DT Enable tSCDV SCLK High to DT Valid tRH TFS/RFSOUT Hold after SCLK High tRD TFS/RFSOUT Delay from SCLK High DT Hold after SCLK High tSCDH tTDE TFS (Alt) to DT Enable tTDV TFS (Alt) to DT Valid tSCDD SCLK High to DT Disable tRDV RFS (Multichannel, Frame Delay Zero) to DT Valid 30 4 7 12 0.25tCK 0 0 12 0 0 12 12 12 0.25tCK + 6 12 ns ns ns ns ns ns ns ns ns ns ns ns ns ns CLKOUT tCC t CC tSCP tSCS tSCH tSCK SCLK tSCP DR TFSI N RFSIN tRD tRH RFSOUT TFSOUT tSCDV tSCDE DT tSCDD tSCDH tTDE tTDV TFS OUT ALTERNATE FRAME MODE tRDV RFSOUT MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) tTDE tTDV TFSIN ALTERNATE FRAME MODE tRDV RFSIN MULTICHANNEL MODE, FRAME DELAY 0 (MFD = 0) Figure 29. Serial Ports –32– REV. 0 ADSP-218xN Series IDMA Address Latch Table 21. IDMA Address Latch Parameter Min Max Unit Timing Requirements: tIALP Duration of Address Latch1, 2 tIASU IAD15–0 Address Setup before Address Latch End2 tIAH IAD15–0 Address Hold after Address Latch End2 tIKA IACK Low before Start of Address Latch2, 3 tIALS Start of Write or Read after Address Latch End2, 3 tIALD Address Latch Start after Address Latch End1, 2 1Start 2End 10 5 3 0 3 2 ns ns ns ns ns ns of Address Latch = IS Low and IAL High. of Address Latch = IS High or IAL Low. 3Start of Write or Read = IS Low and IWR Low or IRD Low. IACK tIKA IAL tIALD tIALP tIALP IS IAD15–0 tIASU tIAH tIASU tIAH tIALS IRD OR IWR Figure 30. IDMA Address Latch REV. 0 –33– ADSP-218xN Series IDMA Write, Short Write Cycle Table 22. IDMA Write, Short Write Cycle Parameter Min Max Unit Timing Requirements: tIKW IACK Low before Start of Write1 tIWP Duration of Write1, 2 tIDSU IAD15–0 Data Setup before End of Write2, 3, 4 IAD15–0 Data Hold after End of Write2, 3, 4 tIDH Switching Characteristic: tIKHW Start of Write to IACK High 1Start 2End 0 10 3 2 10 ns ns ns ns ns of Write = IS Low and IWR Low. of Write = IS High or IWR High. 3If Write Pulse ends before IACK Low, use specifications t IDSU, tIDH. 4If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. tIKW IACK tIKHW IS tIWP IWR tIDSU IAD15–0 DATA tIDH Figure 31. IDMA Write, Short Write Cycle –34– REV. 0 ADSP-218xN Series IDMA Write, Long Write Cycle Table 23. IDMA Write, Long Write Cycle Parameter Min Max Unit Timing Requirements: tIKW IACK Low before Start of Write1 tIKSU IAD15–0 Data Setup before End of Write2, 3, 4 tIKH IAD15–0 Data Hold after End of Write2, 3, 4 Switching Characteristics: tIKLW Start of Write to IACK Low4 Start of Write to IACK High tIKHW 1Start 2If 0 0.5tCK + 5 0 1.5tCK 10 ns ns ns ns ns of Write = IS Low and IWR Low. Write Pulse ends before IACK Low, use specifications tIDSU, tIDH. 3If Write Pulse ends after IACK Low, use specifications t IKSU, tIKH. 4This is the earliest time for IACK Low from Start of Write. For IDMA Write cycle relationships, please refer to the ADSP-2100 Family User’s Manual. tIKW IACK tIKHW tIKLW IS IWR tIKSU IAD15–0 DATA tIKH Figure 32. IDMA Write, Long Write Cycle REV. 0 –35– ADSP-218xN Series IDMA Read, Long Read Cycle Table 24. IDMA Read, Long Read Cycle Parameter Min Max Unit Timing Requirements: tIKR IACK Low before Start of Read1 tIRK End of read after IACK Low2 Switching Characteristics: tIKHR IACK High after Start of Read1 tIKDS IAD15–0 Data Setup before IACK Low tIKDH IAD15 –0 Data Hold after End of Read2 tIKDD IAD15–0 Data Disabled after End of Read2 tIRDE IAD15–0 Previous Data Enabled after Start of Read tIRDV IAD15–0 Previous Data Valid after Start of Read tIRDH1 IAD15–0 Previous Data Hold after Start of Read (DM/PM1)3 IAD15–0 Previous Data Hold after Start of Read (PM2)4 tIRDH2 1Start 2End 0 2 10 0.5tCK – 3 0 10 0 11 2tCK – 5 tCK – 5 ns ns ns ns ns ns ns ns ns ns of Read = IS Low and IRD Low. of Read = IS High or IRD High. 3DM read or first half of PM read. 4Second half of PM read. IACK tIKR IS tiKHR tIRK IRD tIRDE IAD15–0 PREVIOUS DATA tIKDS READ DATA tIKDH tIRDV tIRDH1 OR tIRDH2 tiKDD Figure 33. IDMA Read, Long Read Cycle –36– REV. 0 ADSP-218xN Series IDMA Read, Short Read Cycle Table 25. IDMA Read, Short Read Cycle Parameter1, 2 Min Max Unit Timing Requirements: tIKR IACK Low before Start of Read3 tIRP1 Duration of Read (DM/PM1)4 tIRP2 Duration of Read (PM2)5 Switching Characteristics: tIKHR IACK High after Start of Read3 IAD15–0 Data Hold after End of Read6 tIKDH tIKDD IAD15–0 Data Disabled after End of Read6 tIRDE IAD15–0 Previous Data Enabled after Start of Read tIRDV IAD15–0 Previous Data Valid after Start of Read 1Short 0 10 10 2tCK – 5 tCK – 5 10 ns ns ns ns ns ns ns ns 0 10 0 10 Read Only must be disabled in the IDMA overlay memory mapped register. This mode is disabled by clearing (=0) bit 14 of the IDMA overlay register, and is disabled by default upon reset. 2Consider using the Short Read Only mode, instead, because Short Read mode is not applicable at high clock frequencies. 3Start of Read = IS Low and IRD Low. 4DM Read or first half of PM Read. 5Second half of PM Read. 6End of Read = IS High or IRD High. IACK tIKR IS tIKHR tIRP IRD tIRDE IAD15–0 PREVIOUS DATA tIKDH tiRDV tIKDD Figure 34. IDMA Read, Short Read Cycle REV. 0 –37– ADSP-218xN Series IDMA Read, Short Read Cycle in Short Read Only Mode Table 26. IDMA Read, Short Read Cycle in Short Read Only Mode Parameter1 Min Max Unit Timing Requirements: tIKR IACK Low before Start of Read2 tIRP Duration of Read3 Switching Characteristics: tIKHR IACK High after Start of Read2 tIKDH IAD15–0 Previous Data Hold after End of Read3 tIKDD IAD15–0 Previous Data Disabled after End of Read3 tIRDE IAD15–0 Previous Data Enabled after Start of Read tIRDV IAD15–0 Previous Data Valid after Start of Read 1Short 0 10 10 0 10 0 10 ns ns ns ns ns ns ns Read Only is enabled by setting Bit 14 of the IDMA overlay Register to 1 (0x3FE7). Short Read Only can be enabled by the processor core writing to the register or by an external host writing to the register. Disabled by default. 2Start of Read = IS Low and IRD Low. Previous data remains until end of read. 3End of Read = IS High or IRD High. IA CK t IK R IS t IK H R tIRP IRD tIR D E IAD 15– 0 PR EVIO U S DA TA tIK D H t IR D V L EG EN D : IM P L IE S T H A T I S A N D I R D C A N B E H EL D IN D E F IN IT EL Y B Y H O ST tIK D D Figure 35. IDMA Read, Short Read Cycle in Short Read Only Mode –38– REV. 0 ADSP-218xN Series LQFP Package Pinout The LQFP package pinout is shown in the illustration below and in Table 27. Pin names in bold text in the table replace the plain-text-named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt and flag pins. This bit is set to 1 by default, upon reset. 100-LEAD LQFP PIN CONFIGURATION 94 PF0 [MODE A] 93 PF1 [MODE B] 92 GND 88 PF3 [MODE D] 89 PF2 [MODE C] 100 A3/IAD2 99 A2/IAD1 98 A1/IAD0 96 PWDACK 90 VDDEXT PWD 84 D23 80 GND 95 BGH 85 FL2 87 FL0 86 FL1 82 D21 83 D22 77 D17 81 D20 91 76 D16 75 D15 74 D14 73 D13 72 71 70 D12 GND D11 69 D10 68 D9 67 VDDEXT 66 GND 65 D8 A4/IAD3 A5/IAD4 GND A6/IAD5 A7/IAD6 A8/IAD7 A9/IAD8 A10/IAD9 1 2 3 4 5 6 7 8 PIN 1 IDENTIFIER A11/IAD10 9 A12/IAD11 10 A13/IAD12 11 GND 12 CLKIN 13 XTAL 14 VDDEXT 15 CLKOUT 16 GND 17 VDDINT 18 WR 19 RD 20 BMS 21 DMS 22 PMS 23 IOMS 24 CMS 25 97 A0 78 D18 79 D19 ADSP-218xN TOP VIEW (Not to Scale) 64 D7/ IWR 63 D6/ IRD 62 D5/IAL 61 D4/ IS 59 58 57 56 55 54 53 52 51 60 GND VDD INT D3/IACK D2/IAD15 D1/IAD14 D0/IAD13 BG EBG BR EBR DR1/FI 40 29 DT1/FO 37 TFS1/IRQ1 38 SCLK0 35 IRQL0+PF5 27 RFS0 33 DT0 31 DR0 34 32 36 39 41 IRQ2+PF7 30 RESET 44 GND 28 SCLK1 42 EMS 45 EE 46 43 ECLK 47 ELOUT 48 ELIN 49 IRQE+PF4 26 IRQL1+PF6 GND REV. 0 –39– RFS1/IRQ0 ERESET VDDEXT TFS0 EINT 50 ADSP-218xN Series Table 27. LQFP Package Pinout Pin # Pin Name Table 27. LQFP Package Pinout (Continued) Pin # Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 A4/IAD3 A5/IAD4 GND A6/IAD5 A7/IAD6 A8/IAD7 A9/IAD8 A10/IAD9 A11/IAD10 A12/IAD11 A13/IAD12 GND CLKIN XTAL VDDEXT CLKOUT GND VDDINT WR RD BMS DMS PMS IOMS CMS IRQE + PF4 IRQL0 + PF5 GND IRQL1 + PF6 IRQ2 + PF7 DT0 TFS0 RFS0 DR0 SCLK0 VDDEXT DT1/FO TFS1/IRQ1 RFS1/IRQ0 DR1/FI GND SCLK1 ERESET RESET EMS EE ECLK ELOUT ELIN EINT EBR 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 BR EBG BG D0/IAD13 D1/IAD14 D2/IAD15 D3/IACK VDDINT GND D4/IS D5/IAL D6/IRD D7/IWR D8 GND VDDEXT D9 D10 D11 GND D12 D13 D14 D15 D16 D17 D18 D19 GND D20 D21 D22 D23 FL2 FL1 FL0 PF3 [Mode D] PF2 [Mode C] VDDEXT PWD GND PF1 [Mode B] PF0 [Mode A] BGH PWDACK A0 A1/IAD0 A2/IAD1 A3/IAD2 –40– REV. 0 ADSP-218xN Series Mini-BGA Package Pinout The Mini-BGA package pinout is shown in the illustration below and in Table 28. Pin names in bold text in the table replace the plain text named functions when Mode C = 1. A + sign separates two functions when either function can be active for either major I/O mode. Signals enclosed in brackets [ ] are state bits latched from the value of the pin at the deassertion of RESET. The multiplexed pins DT1/FO, TFS1/IRQ1, RFS1/IRQ0, and DR1/FI, are mode selectable by setting Bit 10 (SPORT1 configure) of the System Control Register. If Bit 10 = 1, these pins have serial port functionality. If Bit 10 = 0, these pins are the external interrupt and flag pins. This bit is set to 1 by default upon reset. 144-BALL MINI-BGA PACKAGE PINOUT (BOTTOM VIEW) 12 11 10 9 8 7 6 5 4 3 2 1 GND GND D22 NC NC NC GND NC A0 GND A1/IAD0 A2/IAD1 A D16 D17 D18 D20 D23 V D D E XT GND NC NC GND A3/IAD2 A4/IAD3 B D14 NC D15 D19 D21 V D D E XT PWD A7/IAD6 A5/IAD4 RD A6/IAD5 PWDACK C GND NC D12 D13 NC PF2 [M ODE C] PF1 [M ODE B] A9/IAD8 BGH NC WR NC D D10 GND V D D E XT GND GND PF3 [M ODE D] FL 2 PF0 [M ODE A] FL 0 A8/IAD7 V D D E XT V D D E XT E D9 NC D8 D11 D7 / I WR NC NC FL 1 A11/IAD10 A12/IAD11 NC A13/IAD12 F D4 / I S NC NC D5 /IAL D6/ IRD NC NC NC A10/IAD9 GND NC XT AL G GND NC GND D3/ IACK D2/IAD15 TF S0 DT0 VD D I N T GND GND GND CLKIN H VD D INT VD D I N T D1/IAD14 BG RF S1 / IRQ0 D0/IAD13 SCLK0 V D D E XT V D D E XT NC VD D I NT CL KOUT J EBG BR EBR ERESET SCLK1 TF S1 / IRQ 1 RFS0 DMS BMS NC NC NC K EI NT EL O UT EL IN RESET GND DR0 PM S GND IO M S I RQ L 1 + P F 6 NC IRQ E + P F 4 L ECLK EE EM S NC GND DR1/FI DT 1 / F O GND CMS NC IRQ 2 + P F 7 I RQ L 0 + P F 5 M REV. 0 –41– ADSP-218xN Series Table 28. Mini-BGA Package Pinout Ball # Pin Name Table 28. Mini-BGA Package Pinout (Continued) Ball # Pin Name A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 E01 E02 A2/IAD1 A1/IAD0 GND A0 NC GND NC NC NC D22 GND GND A4/IAD3 A3/IAD2 GND NC NC GND VDDEXT D23 D20 D18 D17 D16 PWDACK A6/IAD5 RD A5/IAD4 A7/IAD6 PWD VDDEXT D21 D19 D15 NC D14 NC WR NC BGH A9/IAD8 PF1 [MODE B] PF2 [MODE C] NC D13 D12 NC GND VDDEXT VDDEXT E03 E04 E05 E06 E07 E08 E09 E10 E11 E12 F01 F02 F03 F04 F05 F06 F07 F08 F09 F10 F11 F12 G01 G02 G03 G04 G05 G06 G07 G08 G09 G10 G11 G12 H01 H02 H03 H04 H05 H06 H07 H08 H09 H10 H11 H12 J01 J02 J03 J04 J05 –42– A8/IAD7 FL0 PF0 [MODE A] FL2 PF3 [MODE D] GND GND VDDEXT GND D10 A13/IAD12 NC A12/IAD11 A11/IAD10 FL1 NC NC D7/IWR D11 D8 NC D9 XTAL NC GND A10/IAD9 NC NC NC D6/IRD D5/IAL NC NC D4/IS CLKIN GND GND GND VDDINT DT0 TFS0 D2/IAD15 D3/IACK GND NC GND CLKOUT VDDINT NC VDDEXT VDDEXT REV. 0 ADSP-218xN Series Table 28. Mini-BGA Package Pinout (Continued) Ball # Pin Name J06 J07 J08 J09 J10 J11 J12 K01 K02 K03 K04 K05 K06 K07 K08 K09 K10 K11 K12 L01 L02 L03 L04 L05 L06 L07 L08 L09 L10 L11 L12 M01 M02 M03 M04 M05 M06 M07 M08 M09 M10 M11 M12 SCLK0 D0/IAD13 RFS1/IRQ0 BG D1/IAD14 VDDINT VDDINT NC NC NC BMS DMS RFS0 TFS1/IRQ1 SCLK1 ERESET EBR BR EBG IRQE + PF4 NC IRQL1 + PF6 IOMS GND PMS DR0 GND RESET ELIN ELOUT EINT IRQL0 + PF5 IRQL2 + PF7 NC CMS GND DT1/FO DR1/FI GND NC EMS EE ECLK REV. 0 –43– ADSP-218xN Series OUTLINE DIMENSIONS Dimensions in outline dimension drawings are shown in millimeters. 144-BALL MINI-BGA (CA-144) 10.10 10.00 SQ 9.90 A1 CO RNER INDEX TRI ANG LE 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M BOTTOM VIEW DETAIL A 1.40 MAX 0.43 NOTES: 0.25 1. DIMENSIONS IN MILLIMETERS . 2. ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.15 OF ITS IDEAL POSITION, RELATIVE TO THE PACKAGE EDGES. 3. ACTUAL POSITION OF EACH BALL IS WITHIN 0.08 OF ITS IDEAL POSITION, RELATIVE TO THE BALL GRID. 4. CENTER DIMENSIONS ARE NOMINAL. 1.00 0.85 8.80 BSC SQ 0.80 BSC BALL PITCH TOP VIEW 0.55 0.50 0.45 BALL DIAMETER 0.10 MAX SEATING PLANE DETAIL A 100-LEAD METRIC THIN PLASTIC QUAD FLATPACK (LQFP) (ST-100) 16.20 16.00 SQ 15.80 14.05 14.00 SQ 13.95 12.00 TYP BSC 100 1 76 75 1.60 MAX 0.75 0.60 TYP 0.50 12 T YP SEATING PLANE TO P V IEW (PINS DOWN) 0.08 MAX LEAD COPLANARITY 0 -7 0.15 0.05 6 ±4 25 26 0.50 BSC (LEAD PITCH) 51 50 0.27 0.22 TYP ( LEAD WIDTH) 0.17 NOTES: 1. DIMENSIONS IN MILLIMETERS. 2. THE ACTUAL POSITION OF EACH L EAD IS WITHIN 0.08 OF ITS IDEAL POSITION, WHEN MEASURED IN THE LATERAL DIRECTION. 3. CENTER DIMENSIONS ARE NOMINAL. –44– REV. 0 ADSP-218xN Series ORDERING GUIDE Table 29. Ordering Guide Part Number Ambient Temperature Range Instruction Rate (MHz) Package Description Package Option ADSP-2184NKST-320 ADSP-2184NBST-320 ADSP-2185NKST-320 ADSP-2185NBST-320 ADSP-2186NKST-320 ADSP-2186NBST-320 ADSP-2187NKST-320 ADSP-2187NBST-320 ADSP-2188NKST-320 ADSP-2188NBST-320 ADSP-2189NKST-320 ADSP-2189NBST-320 ADSP-2184NKCA-320 ADSP-2184NBCA-320 ADSP-2185NKCA-320 ADSP-2185NBCA-320 ADSP-2186NKCA-320 ADSP-2186NBCA-320 ADSP-2187NKCA-320 ADSP-2187NBCA-320 ADSP-2188NKCA-320 ADSP-2188NBCA-320 ADSP-2189NKCA-320 ADSP-2189NBCA-320 0ºC to 70ºC –40ºC to +85ºC 0ºC to 70ºC –40ºC to +85ºC 0ºC to 70ºC –40ºC to +85ºC 0ºC to 70ºC –40ºC to +85ºC 0ºC to 70ºC –40ºC to +85ºC 0ºC to 70ºC –40ºC to +85ºC 0ºC to 70ºC –40ºC to 85ºC 0ºC to 70ºC –40ºC to +85ºC 0ºC to 70ºC –40ºC to +85ºC 0ºC to 70ºC –40ºC to +85ºC 0ºC to 70ºC –40ºC to +85ºC 0ºC to 70ºC –40ºC to +85ºC 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 80 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 100-Lead LQFP 144-Ball MBGA 144-Ball MBGA 144-Ball MBGA 144-Ball MBGA 144-Ball MBGA 144-Ball MBGA 144-Ball MBGA 144-Ball MBGA 144-Ball MBGA 144-Ball MBGA 144-Ball MBGA 144-Ball MBGA ST-100 ST-100 ST-100 ST-100 ST-100 ST-100 ST-100 ST-100 ST-100 ST-100 ST-100 ST-100 CA-144 CA-144 CA-144 CA-144 CA-144 CA-144 CA-144 CA-144 CA-144 CA-144 CA-144 CA-144 REV. 0 –45–