ADT7462ACPZ-REEL

Flexible Temperature and Voltage Monitor and System Fan Controller ADT7462 FEATURES One local and up to three remote temperature channels Series resistance cancellation on remote channels Thermal protection using THERM pins Up to four PWM fan drive outputs Supports both high and low frequency PWM drives Up to eight TACH inputs Measures the speed of 3-wire and 4-wire fans Automatic fan speed control loop Includes dynamic TMIN control Monitors up to 13 voltage inputs Monitors up to 7 VID inputs Includes VID-on-fly support Bidirectional reset Chassis intrusion detect SMBus 1.1- and SMBus 1.0-compatible 3.3 V and 5 V operation Extended operating range from −40°C to +125°C Space-saving 32-lead chip scale package GENERAL DESCRIPTION The ADT7462 is a flexible systems monitor IC, suitable for use in a wide variety of applications. It can monitor temperature in up to three remote locations, as well as its ambient temperature. There are up to four PWM outputs. These can be used to control the speed of a cooling fan by varying the % duty cycle of the PWM drive signal applied to the fan. The ADT7462 supports high frequency PWM for 4-wire fans and low frequency PWM for 2-wire and 3-wire fans. There are up to eight TACH inputs, which can be used to measure the speed of 3-wire and 4-wire fans. There are up to 13 voltage monitoring inputs, ranging from 12 V to 0.9 V. The ADT7462 is fully compatible with SMBus 1.1 and SMBus 1.0. The ADT7462 also includes a THERM I/O and a RESET I/O. The ADT7462 is available in a 32-lead LFCSP_VQ. Many of the pins are multifunctional. There are five easy configuration options, which are set up using the easy configuration register. Users pick the configuration closest to their requirements; individual pins can be reconfigured after the easy configuration option has been chosen. APPLICATIONS Servers and personal computers Telecommunications equipment Test equipment and measurement instruments FUNCTIONAL BLOCK DIAGRAM SMBus ADDRESS SCL SDA ALERT ADT7462 SMBus ADDRESS SELECTION VID0 TO VID6 VID REGISTER PWM REGISTERS ACOUSTIC ENHANCEMENT CONTROL AUTOMATIC FAN SPEED CONTROL DYNAMIC TMIN CONTROL FAN SPEED COUNTER SERIAL BUS INTERFACE ADDRESS POINTER REGISTER PWM CONFIGURATION REGISTERS INTERRUPT MASKING INTERRUPT STATUS REGISTERS LIMIT COMPARATORS CI PWM1 TO PWM4 FAN2MAX TACH1 TO TACH8 PERFORMANCE MONITORING VR_HOT2 VR_HOT1 THERM2 THERM1 THERMAL DIODE INPUTS VOLTAGE INPUTS THERMAL PROTECTION INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER BAND GAP TEMPERATURE SENSOR GND VALUE AND LIMIT REGISTERS 13-BIT ADC RESET CIRCUIT GPIO STATUS AND CONFIGURATION REGISTERS SCSI STATUS RESET GPIO1 TO GPIO8 SCSI_TERM1 AND SCSI_TERM2 BAND GAP REFERENCE Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 05569-001 ADT7462 TABLE OF CONTENTS Features ...................................................................................... 1 Applications............................................................................... 1 General Description ................................................................. 1 Functional Block Diagram ...................................................... 1 Revision History ....................................................................... 3 Specifications............................................................................. 4 Timing Diagram ................................................................... 5 Absolute Maximum Ratings.................................................... 6 Thermal Resistance .............................................................. 6 ESD Caution.......................................................................... 6 Pin Configuration and Function Descriptions..................... 7 Functional Description: Easy Configuration Options .. 10 Typical Performance Characteristics ................................... 15 Serial Bus Interface................................................................. 18 ADD Input........................................................................... 18 SMBus Fixed Address ........................................................ 18 SMBus Operation ............................................................... 18 Write Operations ................................................................ 20 Read Operations ................................................................. 21 Alert Response Address..................................................... 22 SMBus Timeout .................................................................. 22 Temperature and Voltage Measurement.............................. 23 Temperature Measurement ............................................... 23 Series Resistance Cancellation.......................................... 24 Voltage Measurement ........................................................ 26 Battery Measurement Input (VBATT)................................. 28 ADC Information............................................................... 29 Dynamic VID Monitoring .................................................... 30 VID Code ............................................................................ 30 Dynamic VID Monitoring ................................................ 30 Status and Mask Registers and ALERT................................ 32 Fan Control.............................................................................. 33 Fan Drive Using PWM Control........................................ 33 Fan Speed Measurement and Control.................................. 35 TACH Inputs ....................................................................... 35 Fan Speed Measurement.................................................... 35 PWM Logic State ................................................................ 37 Fan Speed Control .............................................................. 37 Programming the Automatic Fan Speed Control Loop 39 Step 1—Configuring the MUX......................................... 40 Step 2—TMIN Settings for Thermal Calibration Channels . 40 Step 3—PWMMIN for Each PWM (Fan) Output............. 42 Step 4—PWMMAX for PWM (Fan) Outputs .................... 42 Step 5—TRANGE for Temperature Channels ...................... 43 Step 6—TTHERM for Temperature Channels...................... 46 Step 7—THYST for Temperature Channels ........................ 47 Dynamic TMIN Control Programming ............................. 49 Step 8—Operating Points for Temperature Channels ... 49 Step 9—High and Low Limits for Temperature Channels 49 Step 10—Monitoring THERM.......................................... 52 Enhancing System Acoustics............................................. 52 Step 11—Ramp Rate for Acoustic Enhancement ........... 54 Fan Freewheeling Test Mode............................................. 56 THERM I/O Operation ......................................................... 57 General-Purpose I/O Pins ..................................................... 59 EDO Circuitry..................................................................... 59 Other Digital Inputs ........................................................... 60 Reset I/O .............................................................................. 60 Chassis Intrusion Input...................................................... 60 Power-Up Sequence................................................................ 61 XOR Tree Test.......................................................................... 62 Register Map............................................................................ 63 Outline Dimensions ............................................................... 90 Ordering Guide................................................................... 90 Rev. 0 | Page 2 of 92 ADT7462 REVISION HISTORY 1/06—Revision 0: Initial Version Rev. 0 | Page 3 of 92 ADT7462 SPECIFICATIONS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. 1 Table 1. Parameter POWER SUPPLY Supply Voltage Supply Current TEMPERATURE-TO-DIGITAL CONVERTER Internal Sensor, TA, Accuracy Min 3.0 Typ 3.3 1.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 ±0.5 85 34 5 2 Max 5.5 4 ±2.25 ±3.25 ±3 ±4 0.25 ±2.25 ±3.25 ±2.75 ±3.5 0.25 Unit V mA °C °C °C °C °C °C °C °C °C °C μA μA μA kΩ Test Conditions/Comments ADC active, interface inactive 2 TA Conditions VCC Conditions 0 ≤ TA ≤ 85°C 3 V ≤ VCC ≤ 3.6 V −40 ≤ TA ≤ +100°C 3 V ≤ VCC ≤ 3.6 V 0 ≤ TA ≤ 85°C 4.5 V ≤ VCC ≤ 5.5 V −40 ≤ TA ≤ +100°C 4.5 V ≤ VCC ≤ 5.5 V 0 ≤ TA ≤ 85°C −40 ≤ TA ≤ +100°C 0 ≤ TA ≤ 85°C −40 ≤ TA ≤ +100°C 3 V ≤ VCC ≤ 3.6 V 3 V ≤ VCC ≤ 3.6 V 4.5 V ≤ VCC ≤ 5.5 V 4.5 V ≤ VCC ≤ 5.5 V Resolution Remote Sensor, TD, Accuracy (−40 ≤ TD ≤ +125°C) Resolution Remote Sensor Source Current3 Series Resistance Cancellation 3 ANALOG-TO-DIGITAL CONVERTER Total Unadjusted Error, TUE 4, 5 Differential Nonlinearity, DNL Conversion Time (Voltage Input)3 Conversion Time (Local Temperature)3 Conversion Time (Remote Temperature)3 INPUT RESISTANCE Pin 7, Pin 8, Pin 13, Pin 21, Pin 22, Pin 25, Pin 28, Pin 29 Pin 15, Pin 19 Pin 23, Pin 24 Pin 26, VBATT and +1.2V (When Measured) VBATT Current Drain (When Measured) VBATT Current Drain (When Not Measured) FAN RPM TO DIGITAL CONVERTER Accuracy Internal Clock Frequency OPEN DRAIN OUTPUTS (PWM, GPIO) High Level Output Leakage Current, IOH Output Low Voltage, VOL DIGITAL OUTPUT (RESET, ALERT, THERM) Output Low Voltage, VOL RESET Pulse Width3 RESET Threshold RESET Hysteresis3 OPEN DRAIN SERIAL BUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Leakage Current, IOH High level Mid level Low level The ADT7462 cancels 2 kΩ in series with the remote thermal diode 8.53 9.01 38.36 140 225 66 120 80 16 ±3.5 ±1 9.86 10.38 42.09 % LSB ms ms ms kΩ kΩ kΩ kΩ nA nA % kHz μA V V ms V mV V μA 8 bits Attenuators enabled Attenuators enabled Attenuators enabled Attenuators cannot be disabled CR2032 battery life > 10 years CR2032 battery life > 10 years 100 140 100 82.8 90 0.1 ±8 97.2 ±1 0.4 0.4 VOUT = VCC IOUT = −3 mA, VCC = +3.3 V IOUT = −3 mA, VCC = +3.3 V Falling voltage 140 3 180 3.05 70 3.1 0.1 0.4 ±1 IOUT = −3 mA, VCC = +3.3 V VOUT = VCC Rev. 0 | Page 4 of 92 ADT7462 Parameter SERIAL BUS DIGITAL INPUTS (SDA AND SCL) Input High Voltage, VIH Input Low Voltage, VIL Hysteresis DIGITAL INPUT LOGIC LEVELS (VID0 to VID6) AND THERM, TACH, GPIO, VR_HOT, SCSI_TERM) Input High Voltage, VIH Input Low Voltage, VIL Input High Voltage, VIH ( VID0 to VID6) Input High Voltage, VIH (THERM) Input Low Voltage, VIL Hysteresis DIGITAL INPUT CURRENTS Input High Current, IIH Input Low Current, IIL Input Capacitance3 SERIAL BUS TIMING3 Clock Frequency Glitch Immunity, tSW Bus Free Time Start Setup Time, tSU;STA Start Hold Time, tHD;STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tr SCL, SDA Fall Time, tF Data Setup Time, tSU;DAT Detect Clock Low Timeout 1 Min 2.1 Typ Max Unit V V mV Test Conditions/Comments 0.4 500 1.7 0.8 0.65 2/3 VCCP1 0.4 500 −1 +1 5 400 50 1.3 0.6 0.6 1.3 0.6 1000 300 100 25 V V V V V mV μA μA pF kHz ns μs μs μs μs μs ns ns ns ms Bit 3 and Bit 4 of Configuration Register 3 = 0 Bit 3 and Bit 4 of Configuration Register 3 = 0 Bit 3 of Configuration Register 3 = 1 Bit 4 of Configuration Register 3 = 1 Bit 3 and Bit 4 of Configuration Register 3 = 1 VIN = VCC VIN = 0 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 Can be optionally enabled All voltages are measured with respect to GND, unless otherwise specified. Typical values are at TA = 25°C and represent the most likely parametric norm. Logic inputs accept input high voltages up to 5 V, even when the device is operating at supply voltages below 5 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. 2 Unused digital inputs connected to GND. 3 Guaranteed by design, not production tested. 4 Note that this specification does not apply if Pin 26 (VBATT, +1.2V) is being measured in single-channel mode. See Figure 22 in Typical Performance Characteristics for VBATT accuracy. 5 For Pin 23 and Pin 24 configured as +1.8V or +2.5V only, restricted conditions of VCC ≥ 3.3 V and +25°C ≤ TA ≤ +125°C apply. TIMING DIAGRAM tR SCL tF tHD;STA tLOW tHD;STA tHD;DAT tSU;DAT 05569-002 tHIGH tSU;STA tSU;STO SDA tBUF P S S P Figure 2. Serial Bus Timing Diagram Rev. 0 | Page 5 of 92 ADT7462 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage Voltage on +12V Pin Voltage on VBATT Pin Voltage on Any Other Input or Output Pin Input Current at Any Pin Package Input Current Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Lead Temperature (Soldering 10 sec) IR Reflow Peak Temperature ESD Rating Rating 6.5 V 20 V 4V −0.3 V to +6.5 V ±5 mA ±20 mA 150°C −40°C to +125°C −65°C to +150°C 300°C 260°C 1500 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 3. Thermal Resistance Package Type 32-Lead LFCSP_VQ θJA 32.5 θJC 32.71 Unit °C/W ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 6 of 92 ADT7462 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 28 THERM1/+1.5V1/GPIO7/VID6 29 THERM2/+1.5V2/GPIO8 32 VID5/GPIO6/PWM2 31 VID4/GPIO5/PWM1 26 VR_HOT2/+1.2V/V BATT 25 VR_HOT1/+1.2V/+3.3V 30 PWM3 27 FAN2MAX/CI VID0/GPIO1/TACH1 VID1/GPIO2/TACH2 VID2/GPIO3/TACH3 VID3/GPIO4/TACH4 VCC GND TACH5/+12V1 TACH6/+12V2 1 2 3 4 5 6 7 8 PIN 1 INDICATOR 24 VCCP2 /+1.5V/+1.8V/+2.5V 23 VCCP1 /+1.5V/+1.8V/+2.5V 22 TACH8/+12V3 21 TACH7/+5V 20 D3–/SCSI_TERM2 19 D3+/+1.25V/+0.9V 18 D2– 17 D2+ ADT7462 TOP VIEW (Not to Scale) 11 9 10 15 14 12 13 SCL SDA ADD ALERT PWM4/+3.3V RESET D1+/+2.5V/+1.8V D1–/SCSI_TERM1 16 Figure 3. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 Mnemonic VID0/GPIO1/TACH1 Description VID0: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO1: Open Drain I/O. General-purpose input/output. TACH1: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. VID1: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO2: Open Drain I/O. General-purpose input/output. TACH2: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. VID2: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO3: Open Drain I/O. General-purpose input/output. TACH3: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. VID3: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO4: Open Drain I/O. General-purpose input/output. TACH4: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. The ADT7462 can also be powered from a 5 V supply. Ground Pin. TACH5: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 5. +12V1: Analog Input. Monitors 12 V power supply (#1). Attenuators switched on by default. TACH6: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 6. +12V2: Analog Input. Monitors 12 V power supply (#2). Attenuators switched on by default. Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up. Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up. The state of this pin on power-up determines the SMBus device address. Active Low Digital Output. The ALERT pin is used to signal out-of-limit comparisons of temperature, voltage, and fan speed. This is compatible with SMBus ALERT. Rev. 0 | Page 7 of 92 05569-009 POR Default TACH1 2 VID1/GPIO2/TACH2 TACH2 3 VID2/GPIO3/TACH3 TACH3 4 VID3/GPIO4/TACH4 TACH4 5 6 7 8 9 10 11 12 VCC GND TACH5/+12V1 TACH6/+12V2 SCL SDA ADD ALERT VCC GND TACH5 TACH6 SCL SDA ADD ALERT ADT7462 Pin No. 13 Mnemonic PWM4/+3.3V Description PWM4: Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output to control the speed of Fan 4. +3.3V: Analog Input. Monitors 3.3 V power supply. Active Low Open Drain Digital I/O. Power-on reset, 5 mA driver (weak 100 kΩ pull-up), active low output (100 kΩ pull-up) with a 180 ms typical pulse width. RESET is asserted whenever VCC is below the reset threshold. It remains asserted for approximately 180 ms after VCC rises above the reset threshold. Pin 14 also functions as an active low RESET input and resets all unlocked registers to their default values. D1+: Anode Connection to Thermal Diode 1. +2.5V: Monitors 2.5 V analog input. +1.8V: Monitors 1.8 V analog input. D1−: Cathode Connection to Thermal Diode 1. SCSI_TERM1: Digital Input, SCSI Termination 1. Anode Connection to Thermal Diode 2. Cathode Connection to Thermal Diode 2. D3+: Anode Connection to Thermal Diode 3. +1.25V: Monitors 1.25 V analog input. +0.9V: Monitors 0.9 V analog input. D3−: Cathode connection to Thermal Diode 3. SCSI_TERM2: Digital Input, SCSI Termination 2. TACH7: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 7. +5V: Analog Input. Monitors 5 V power supply. TACH8: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 8. +12V3: Analog Input. Monitors 12 V power supply (#3). VCCP1: Monitors 1.2 V analog input. +1.5V: Monitors 1.5 V analog input. +1.8V: Monitors 1.8 V analog input. +2.5V: Monitors 2.5 V analog input. VCCP2: Monitors 1.2 V analog input. +1.5V: Monitors 1.5 V analog input. +1.8V: Monitors 1.8 V analog input. +2.5V: Monitors 2.5 V analog input. VR_HOT1: Digital Input Indicating Overtemperature Event on Voltage Regulator. +1.2V1: 0 V to 1.2 V Analog Input. For example, can be used to monitor GBIT. +3.3V: Analog Input. Monitors +3.3 V power supply. VR_HOT2: Digital Input Indicating Overtemperature Event on Voltage Regulator. +1.2V2: 0 V to 1.2 V Analog Input. For example, can be used to monitor FSB_VTT. VBATT: Analog Input. Monitors battery voltage, nominally 3 V. FAN2MAX: Sets fan to maximum speed when a fan fault condition occurs. Bidirectional open drain, active low I/O. CI: An active high input that captures a chassis intrusion event in Bit 6 of the digital status register. This bit remains set until cleared, as long as battery voltage is applied to the VBATT input, even when the ADT7462 is powered off. THERM1: Can be reconfigured as a bidirectional THERM pin. Can be connected to PROCHOT output of the Intel® Pentium 4 processor to time and monitor PROCHOT assertions. Can be used as an output to signal overtemperature conditions or for clock modulation purposes. +1.5V1: 0 V to 1.5 V Analog Input. Can be used to monitor ICH. GPIO7: Open Drain I/O. General-purpose input/output. VID6: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). POR Default PWM4 14 RESET RESET 15 D1+/+2.5V/+1.8V D1+ 16 17 18 19 D1−/SCSI_TERM1 D2+ D2− D3+/+1.25V/+0.9V D1− D2+ D2− D3+ 20 21 22 23 D3−/SCSI_TERM2 TACH7/+5V TACH8/+12V3 VCCP1/+1.5V/+1.8V/+2.5V D3− TACH7 TACH8 +1.8V 24 VCCP2/+1.5V/+1.8V/+2.5V +2.25V 25 VR_HOT1/+1.2V/+3.3V +3.3V 26 VR_HOT2/+1.2V/VBATT VBATT 27 FAN2MAX/CI CI 28 THERM1/+1.5V1/GPIO7/ VID6 THERM1 Rev. 0 | Page 8 of 92 ADT7462 Pin No. 29 Mnemonic THERM2/+1.5V2/GPIO8 Description THERM2: Can be reconfigured as a bidirectional THERM pin. Can be connected to PROCHOT output of the Intel Pentium 4 processor to time and monitor PROCHOT assertions. Can be used as an output to signal overtemperature conditions or for clock modulation purposes. +1.5V2: 0 V to 1.5 V Analog Input. Can be used to monitor 3GIO. GPIO8: Open Drain I/O. General-purpose input/output. Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output to control speed of Fan 3. VID4: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO5: Open Drain I/O. General-purpose input/output. PWM1: Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to control the speed of Fan 1. VID5: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO6: Open Drain I/O. General-purpose input/output. PWM2: Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse width modulated output to control the speed of Fan 2. POR Default THERM2 30 31 PWM3 VID4/GPIO5/PWM1 PWM3 PWM1 32 VID5/GPIO6/PWM2 PWM2 Rev. 0 | Page 9 of 92 ADT7462 32 PWM2 30 PWM3 31 PWM1 28 THERM1 29 THERM2 26 VBATT 25 +3.3V FUNCTIONAL DESCRIPTION: EASY CONFIGURATION OPTIONS There are a number of multifunctional pins on the ADT7462 that need to be configured on power-up to suit the desired application. Note that due to the large number of pins that need to be configured, it could take several SMBus transactions to achieve the required configuration. For this reason, the ADT7462 has five easy configuration options. The user sets a bit in the easy configuration option register (0x14) to set up the required configuration (see Table 5). Table 5. Easy Configuration Register Settings Easy Configuration Option Option 1 Option 2 Option 3 Option 4 Option 5 Register 0x14 Setting Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 27 CI TACH1 TACH2 TACH3 TACH4 VCC GND TACH5 TACH6 1 2 3 4 5 6 7 8 24 PIN 1 INDICATOR 23 22 21 20 19 18 17 ADT7462 TOP VIEW (Not to Scale) +2.5V +1.8V TACH8 TACH7 D3– D3+ D2– D2+ 11 9 13 14 10 15 12 SCL SDA ADD ALERT PWM4 RESET D1+ D1– 16 Figure 4. Configuration Option 1 Table 6. Configuration Option 1 Pin 11 21 31 41 7 8 13 15 16 19 20 21 22 23 24 25 26 27 281 29 311 321 1 Once the most convenient easy configuration option has been set, the user can configure any of the pins individually. The setup complete bit (Bit 5 of Register 0x01) must then be set to 1 to indicate that the ADT7462 is configured correctly, and then monitoring of the selected channels begins. The following is a detailed description of the five easy configuration options that are available. Configuration Option 1 Configuration Option 1 is the default configuration. It is also the most suitable for thermal monitoring, voltage monitoring, and fan control for single and dual processor systems. Features of Configuration Option 1 include the following: One local and three remote temperature channels Four PWM drives and eight TACH inputs Two THERM I/Os Voltage monitoring +3.3V +2.5V +1.8V VBATT RESET I/O CI (chassis intrusion) or FAN2MAX Figure 4 shows the pin configuration when Configuration Option 1 is chosen. Function TACH1 TACH2 TACH3 TACH4 TACH5 TACH6 PWM4 D1+ D1− D3+ D3− TACH7 TACH8 +1.8V +2.5V +3.3V VBATT CI THERM1 THERM2 PWM1 PWM2 Configuration Register Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 4 Pin Configuration Register 4 Pin Configuration Register 4 Pin Configuration Register 4 Bit Value Bit 4 = 1 Bit 3 = 1 Bit 2 = 1 Bit 1 = 1 Bit 0 = 1 Bit 7 = 1 Bit 6 = 1 Bit 6 = 1 Bit 6 = 1 Bit 5 = 1 Bit 5 = 1 Bit 3 = 1 Bit 2 = 1 Bits [1:0] = 10 Bits [7:6] = 01 Bits [5:4] = 00 Bits [3:2] = 00 Bit 1 = 1 Bits [7:6] = 1× Bits [5:4] = 1× Bit 3 = 1 Bit 2 = 1 If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7 of Pin Configuration Register 1 (0x10) = 1. Rev. 0 | Page 10 of 92 05569-010 ADT7462 27 FAN2MAX 26 VR_HOT2 Configuration Option 2 is used for thermal monitoring and fan control for Processor 1 and Processor 2 in a dual processor system. It can also monitor one set of VIDs, if required. Features of Configuration Option 2 include the following: One local and three remote thermal channels Up to four PWM drives and up to eight TACH inputs (VID pins and TACHs/PWMs are MUX’d together) Two THERM I/Os • Two VRD inputs RESET I/O Two VCCP voltage monitoring channels Figure 5 shows the pin configuration when Configuration Option 2 is chosen. TACH1 TACH2 TACH3 TACH4 VCC GND TACH5 TACH6 1 2 3 4 5 6 7 8 32 PWM2 30 PWM3 31 PWM1 28 THERM1 29 THERM2 25 VR_HOT1 Configuration Option 2 24 PIN 1 INDICATOR 23 22 21 20 19 18 17 ADT7462 TOP VIEW (Not to Scale) VCCP2 VCCP1 TACH8 TACH7 D3– D3+ D2– D2+ 11 9 14 10 15 SCL SDA ADD ALERT PWM4 RESET D1+ D1– 16 12 13 Figure 5. Configuration Option 2 Table 7. Configuration Option 2 Pin 11 21 31 41 7 8 13 15 16 19 20 21 22 23 24 25 26 27 281 29 311 321 1 Function TACH1 TACH2 TACH3 TACH4 TACH5 TACH6 PWM 4 D1+ D1− D3+ D3− TACH7 TACH8 VCCP1 VCCP2 VR_HOT1 VR_HOT2 FAN2MAX THERM1 THERM2 PWM1 PWM2 Configuration Register Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 4 Pin Configuration Register 4 Pin Configuration Register 4 Pin Configuration Register 4 Bit Value Bit 4 = 1 Bit 3 = 1 Bit 2 = 1 Bit 1 = 1 Bit 0 = 1 Bit 7 = 1 Bit 6 = 1 Bit 6 = 1 Bit 6 = 1 Bit 5 = 1 Bit 5 = 1 Bit 3 = 1 Bit 2 = 1 Bits [1:0] = 00 Bits [7:6] = 00 Bits [5:4] = 1× Bits [3:2] = 1× Bit 1 = 0 Bits [7:6] = 1× Bits [5:4] = 1× Bit 3 = 1 Bit 2 = 1 If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7 of Pin Configuration Register 1 (0x01) = 1. Rev. 0 | Page 11 of 92 05569-011 ADT7462 Configuration Option 3 Configuration Option 3 is chosen when the user wants to monitor all the voltages in the system for Processor 1 and Processor 2. Additional pins can be configured for fan control, VIDs, or GPIOs, as required. Features of Configuration Option 3 include the following: • Up to 13 different voltages monitored Three +12V +5V +3.3V +2.5V Mem_Core (+1.8V or +2.5V) Two +1.5V (3GIO and ICH) +1.2V (VCCP1, VCCP2, VCCP, GBIT) Mem_VTT (0.984 V) VBATT One local and one remote temperature channels Up to three PWM drives and up to four TACH inputs RESET I/O Figure 6 shows the pin configuration when Configuration Option 3 is chosen. Pin 11 21 31 41 7 8 13 15 16 19 20 21 22 23 24 25 26 27 281 29 311 321 1 32 PWM2 30 PWM3 31 PWM1 28 +1.5V/GPIO7 29 +1.5V/GPIO8 26 VBATT 25 +1.2V 27 CI TACH1 TACH2 TACH3 TACH4 VCC GND +12V1 +12V2 1 2 3 4 5 6 7 8 PIN 1 INDICATOR 24 VCCP2 23 VCCP1 22 +12V3 21 +5V 20 SCSI_TERM2 19 +0.9V 18 D2– 17 D2+ ADT7462 TOP VIEW (Not to Scale) 10 11 9 12 13 14 15 SCL SDA ADD ALERT +3.3V RESET +1.8V SCSI_TERM1 16 Figure 6. Configuration Option 3 Table 8. Configuration Option 3 Function TACH1 TACH2 TACH3 TACH4 +12V1 +12V2 +3.3V +1.8V SCSI_TERM1 +0.9V SCSI_TERM2 +5V +12V3 VCCP1 VCCP2 +1.2V VBATT CI +1.5V/GPIO7 +1.5V/GPIO8 PWM1 PWM2 Configuration Register Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 4 Pin Configuration Register 4 Pin Configuration Register 4 Pin Configuration Register 4 Bit Value Bit 4 = 1 Bit 3 = 1 Bit 2 = 1 Bit 1 = 1 Bit 0 = 0 Bit 7 = 0 Bit 6 = 0 Bit 6 = 0 Bit 6 = 0 Bit 5 = 0 Bit 5 = 0 Bit 3 = 0 Bit 2 = 0 Bits [1:0] = 00 Bits [7:6] = 00 Bits [5:4] = 01 Bits [3:2] = 00 Bit 1 = 1 Bits [7:6] = 01 Bits [5:4] = 01 Bit 3 = 1 Bit 2 = 1 If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7 of Pin Configuration Register 1 (0x01) = 1. Rev. 0 | Page 12 of 92 05569-012 ADT7462 27 FAN2MAX 26 VBATT 25 VR_HOT1 32 PWM2 31 PWM1 Features of Configuration Option 4 include the following: One local and two remote temperature channels Up to four PWM drives and six TACH inputs Up to eight voltages monitored +12V +5V +3.3V Two +1.5V +1.2V (VCCP1) +0.984V (Mem_VTT) VBATT THERM I/O VRD input RESET I/O Figure 7 shows the pin configuration when Configuration Option 4 is chosen. Pin 11 21 31 41 7 8 13 15 16 19 20 21 22 23 24 25 26 27 281, 2 292 311 321 1 30 PWM3 Configuration Option 4 is chosen when the user wants to monitor temperature, voltages, and fans for Processor 1 in a dual processor system. TACH1 TACH2 TACH3 TACH4 VCC GND TACH5 TACH6 29 THERM2/+1.5V 28 THERM1/+1.5V Configuration Option 4 1 2 3 4 5 6 7 8 PIN 1 INDICATOR 24 +2.5V 23 VCCP1 22 +12V3 21 +5V 20 SCSI_TERM2 19 +0.9V 18 D2– 17 D2+ ADT7462 TOP VIEW (Not to Scale) 11 9 14 10 12 SCL SDA ADD ALERT PWM 4 RESET D1+ D1– 13 16 15 Figure 7. Configuration Option 4 Table 9. Configuration Option 4 Function TACH1 TACH2 TACH3 TACH4 TACH5 TACH6 PWM4 D1+ D1− +0.9V SCSI_TERM2 +5V +12V3 VCCP1 +2.5V VR_HOT1 VBATT FAN2MAX THERM1/ +1.5V THERM2/ +1.5V PWM1 PWM2 Configuration Register Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 4 Pin Configuration Register 4 Pin Configuration Register 4 Pin Configuration Register 4 Bit Value Bit 4 = 1 Bit 3 = 1 Bit 2 = 1 Bit 1 = 1 Bit 0 = 1 Bit 7 = 1 Bit 6 = 1 Bit 6 = 1 Bit 6 = 1 Bit 5 = 0 Bit 5 = 0 Bit 3 = 0 Bit 2 = 0 Bits [1:0] = 00 Bits [7:6] = 01 Bits [5:4] = 1× Bits [3:2] = 00 Bit 1 = 0 See Table 51 See Table 51 Bit 3 = 1 Bit 2 = 1 If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7 of Pin Configuration Register 1 (0x01) = 1. 2 It is not possible to monitor +1.5V monitoring on Pin 29 and THERM1 on Pin 28. Pin 28 and Pin 29 must BOTH be configured as either +1.5V monitoring or as THERM I/O (see Table 51). Rev. 0 | Page 13 of 92 05569-013 ADT7462 27 FAN2MAX Configuration Option 5 Configuration Option 5 is chosen when the user wants to monitor temperature, voltages, and fans for Processor 2 in a dual processor system. Features of Configuration Option 5 include the following: One local and two remote temperature channels Up to three PWM drives and up to six TACHs Voltage monitoring Two +12V +3.3V Mem_Core (+1.969V) +1.8 V Two +1.5V +1.2V (VCCP2) RESET I/O Figure 8 shows the pin configuration when Configuration Option 5 is chosen. TACH1 TACH2 TACH3 TACH4 VCC GND +12V1 +12V2 1 2 3 4 5 6 7 8 32 PWM2 30 PWM3 31 PWM1 28 THERM1/+1.5V 29 THERM2/+1.5V 26 VR_HOT2 25 +1.2V 24 PIN 1 INDICATOR 23 22 21 20 19 18 17 ADT7462 TOP VIEW (Not to Scale) VCCP2 +1.8V TACH8 TACH7 D3– D3+ D2– D2+ 11 9 10 14 12 13 15 SCL SDA ADD ALERT +3.3V RESET +2.5V SCSI_TERM1 16 Figure 8. Configuration Option 5 Table 10. Configuration Option 5 Pin 11 21 31 41 7 8 13 15 16 19 20 21 22 23 24 25 26 27 281, 2 29 311 321 1 Function TACH1 TACH2 TACH3 TACH4 +12V1 +12V2 +3.3V +2.5V SCSI_TERM1 D3+ D3− TACH7 TACH8 +1.8V VCCP2 +1.2V VR_HOT2 FAN2MAX THERM1/ +1.5V THERM2/ +1.5V PWM1 PWM2 Configuration Register Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 1 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 2 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 3 Pin Configuration Register 4 Pin Configuration Register 4 Pin Configuration Register 4 Pin Configuration Register 4 Bit Value Bit 4 = 1 Bit 3 = 1 Bit 2 = 1 Bit 1 = 1 Bit 0 = 0 Bit 7 = 0 Bit 6 = 0 Bit 6 = 0 Bit 6 = 0 Bit 5 = 1 Bit 5 = 1 Bit 3 = 1 Bit 2 = 1 Bits [1:0] = 10 Bits [7:6] = 00 Bits [5:4] = 01 Bits [3:2] = 1× Bit 1 = 0 See Table 51 See Table 51 Bit 3 = 1 Bit 2 = 1 If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7 of Pin Configuration Register 1 (0x01) = 1. 2 It is not possible to monitor +1.5V monitoring on Pin 28 and THERM2 on Pin 29. Pin 28 and Pin 29 must BOTH be configured as either +1.5V monitoring or as THERM I/O. See Table 51 for more information. Rev. 0 | Page 14 of 92 05569-014 ADT7462 TYPICAL PERFORMANCE CHARACTERISTICS 0.00160 0.00155 0.00150 2 TEMPERATURE ERROR (°C) DEV2 1 VCC = 5.5V IDD (Amps) 0.00145 DEV1 0.00140 DEV3 0.00135 0.00130 0.00125 2.9 0 VCC = 3.3V 05569-003 3.4 3.9 4.4 4.9 5.4 SUPPLY VOLTAGE (V) –1 –40 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 9. Supply Current vs. Supply Voltage 0.00144 0.00142 0.00140 0.00138 0.00136 DEV2 Figure 12. Remote Sensor Temperature Error 5 1 4 2 3 4 2 1 0 –1 –2 05569-007 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MEAN LO SPEC HI SPEC TEMPERATURE ERROR (°C) 3 IDD (Amps) 0.00134 0.00132 0.00130 0.00128 0.00126 0.00124 0.00122 –45 5 55 TEMPERATURE (°C) DEV3 DEV1 5 05569-004 –3 –4 –40 105 –20 0 20 40 60 80 100 120 TEMPERATURE (°C) Figure 10. Supply Current vs. Temperature 2 Figure 13. Temperature Error Measuring Intel Pentium 4 Processor 140 120 TEMPERATURE READING (°C) TEMPERATURE ERROR (°C) 100 80 60 40 20 0 1 VCC = 5.5V INT EXT1 EXT2 EXT3 0 VCC = 3.3V –1 –40 05569-005 –20 0 20 40 60 80 100 120 0 20 40 60 TIME (Seconds) 80 100 120 TEMPERATURE (°C) Figure 11. Local Sensor Temperature Error Figure 14. DUT Response to Thermal Shock Rev. 0 | Page 15 of 92 05569-008 05569-006 ADT7462 60 25 20 TEMPERATURE ERROR (°C) 40 TEMPERATURE ERROR (°C) 100mV 15 10 5 0 –5 –10 10 20 D+ TO GND 0 D+ TO VCC –20 60mV 40mV 05569-080 –40 05569-077 –60 0 20 40 60 80 100 100 1M 10M 100M 1G RESISTANCE (MΩ) NOISE FREQUENCY (kHz) Figure 15. Temperature Error vs. Resistance (SRC) 15 10 TEMPERATURE ERROR (°C) Figure 18. Temperature Error vs. Common-Mode Noise Frequency 7 6 TEMPERATURE ERROR (°C) 5 0 –5 –10 –15 –20 10 50mV 125mV 5 4 3 2 1 05569-081 10mV 20mV 05569-078 0 –1 10 100 1M 10M 100M 1G 100 1M 10M 100M 1G POWER SUPPLY NOISE FREQUENCY (kHz) NOISE FREQUENCY (kHz) Figure 16. Local Temperature Error vs. Power Supply Noise Frequency 8 6 TEMPERATURE ERROR (°C) Figure 19. Temperature Error vs. Differential-Mode Noise Frequency 10 2 0 –2 –4 –6 –8 50mV 125mV TEMPERATURE ERROR (°C) 4 0 –10 DEV1, EXT1 –20 DEV1, EXT2 DEV1, EXT3 DEV2, EXT1 –30 DEV2, EXT2 DEV2, EXT3 –40 DEV3, EXT1 DEV3, EXT3 –50 0 2 4 6 8 10 05569-082 –10 –12 10 100 1M 10M 100M 1G POWER SUPPLY NOISE FREQUENCY (kHz) 05569-079 DEV3, EXT2 CAPACITANCE (nF) Figure 17. Remote Temperature Error vs. Power Supply Noise Frequency Figure 20. Temperature Error vs. Capacitance Between D+ and D− Rev. 0 | Page 16 of 92 ADT7462 0.200 0.198 0.196 TEMPERATURE (°C) 0.194 0.192 0.190 0.188 0.186 0.184 05569-083 5.0 4.5 POWER UP TACH ERROR (%) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 DEV1 DEV2 DEV3 05569-085 0.182 0.180 –50 0 50 STANDBY 0.5 0 2.9 3.4 3.9 4.4 SUPPLY (V) 4.9 5.4 100 150 TIMEOUT (Seconds) Figure 21. Temperature vs. Power-On Reset Timeout 3.0 1.5 Figure 23. TACH Accuracy vs. Supply Voltage DEV2 2.5 1.0 0.5 TACH ERROR (%) DEV1 VBATT READING (V) 2.0 0 DEV3 –0.5 –1.0 –1.5 –2.0 –50 1.5 DEV1 DEV2 DEV3 05569-084 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 0 50 TEMPERATURE (°C) 100 150 VOLTAGE APPLIED (V) Figure 22. VBATT Measurement vs. Applied Voltage Figure 24. TACH Accuracy vs. Temperature Rev. 0 | Page 17 of 92 05569-086 ADT7462 SERIAL BUS INTERFACE The ADT7462 is controlled through use of the serial system management bus (SMBus). The ADT7462 is connected to this bus as a slave device, under the control of a master controller. The SMBus interface in the ADT7462 is fully SMBus 1.1- and SMBus 1.0-compliant. The SMBus address is determined by the state of the ADD input on power-up. 3. Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low-to-high transition when the clock is high can be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. When all data bytes have been read or written, stop conditions are established. In write mode, the master releases the data line during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the 9th clock pulse. This is known as a No Acknowledge. The master then takes the data line low during the low period before the 10th clock pulse and then takes it high during the 10th clock pulse to assert a stop condition. ADD INPUT The ADD pin is a three-state input to the ADT7462. It is used to determine the SMBus address used. This pin is sampled on power-up only. Any changes subsequent to power-up are not reflected until the ADT7462 is powered down and back up again. The corresponding 7-bit SMBus address for the state of the ADD pin is shown in Table 11. Table 11. Corresponding SMBus Addresses for ADD Input ADD Pin High Float Low SMBus Version N/A SMBus 1.1 SMBus 1.1 SMBus Address N/A 0x5C 0x58 4. SMBUS FIXED ADDRESS The ADT7462 supports SMBus fixed address mode and is fully backwards-compatible with SMBus 1.1 and SMBus 1.0. The ADT7462 powers up with a fixed SMBus address that cannot be changed by the assign address call. The fixed address is set by the state of the ADD input pin on power-up. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. For the ADT7462, write operations contain either one or two bytes, and read operations contain one byte. To write data to one of the device data registers or read data from it, the address pointer register must be set so that the correct data register is addressed. Then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. This write operation is shown in Figure 25. The device address is sent over the bus, and then R/W is set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. SMBUS OPERATION The SMBus specification defines specific conditions for different types of read and write operations. The general SMBus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as a high-to-low transition on the serial data line, SDA, while the serial clock line, SCL, remains high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit, which determines the direction of the data transfer, that is, whether data is written to or read from the slave device. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the 9th clock pulse, known as the acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from it or written to it. If the R/W bit = 0, the master writes to the slave device. If the R/W bit = 1, the master reads from the slave device. 2. Rev. 0 | Page 18 of 92 ADT7462 When reading data from a register, there are two possibilities. • If the ADT7462’s address pointer register value is unknown or not the desired value, it must be set to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7462 as before, but only the data byte containing the register address is sent because no data is written to the register (see Figure 26). A read operation is then performed, consisting of the serial bus address and the R/W bit set to 1, followed by the data byte read from the data register (see Figure 27). • If the address pointer register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the address pointer register (see Figure 27). 1 SCL 9 It is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register, because the first data byte of a write is always written to the address pointer register. In addition to supporting the send byte and receive byte protocols, the ADT7462 also supports the read byte protocol (see System Management Bus Specifications Rev. 2.0 for more information). If several read or write operations must be performed in succession, then the master can send a repeat start condition, instead of a stop condition, to begin a new operation. 1 9 SDA START BY MASTER A6 A5 A4 A3 A2 A1 A0 R/W ACK. BY ADT7462 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADT7462 FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCL (CONTINUED) FRAME 2 ADDRESS POINTER REGISTER BYTE 9 SDA (CONTINUED) D7 D6 D5 D4 D3 D2 D1 D0 05569-015 05569-017 05569-016 ACK. BY ADT7462 FRAME 3 DATA BYTE STOP BY MASTER Figure 25. Writing a Register Address to the Address Pointer Register, Then Writing Data to the Selected Register 1 SCL 9 1 9 SDA START BY MASTER A6 A5 A4 A3 A2 A1 A0 R/W ACK. BY ADT7462 D7 D6 D5 D4 D3 D2 D1 D0 ACK. BY ADT7462 STOP BY MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 ADDRESS POINTER REGISTER BYTE Figure 26. Writing to the Address Pointer Register Only 1 SCL 9 1 9 SDA START BY MASTER A6 A5 A4 A3 A2 A1 A0 R/W ACK. BY ADT7462 D7 D6 D5 D4 D3 D2 D1 D0 NO ACK. STOP BY BY MASTER MASTER FRAME 1 SERIAL BUS ADDRESS BYTE FRAME 2 DATA BYTE FROM ADT7462 Figure 27. Reading Data from a Previously Selected Register Rev. 0 | Page 19 of 92 ADT7462 WRITE OPERATIONS The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADT7462 are discussed below. The following abbreviations are used in the diagrams: S – Start P – Stop R – Read W – Write A – Acknowledge A – No Acknowledge The ADT7462 uses the following SMBus write protocols. 4. 5. 6. 7. 8. The master sends a command code. The slave asserts an ACK on SDA. The master sends a data byte. The slave asserts an ACK on SDA. The master asserts a stop condition on SDA to end the transaction. 1 S 2 3 4 SLAVE ADDRESS 5 6 78 05569-019 SLAVE W A ADDRESS A DATA A P Figure 29. Single Byte Write to a Register Block Write In this operation, the master device writes a block of data to a slave device. The start address for a block write must have been set previously. In the case of the ADT7462, this is done by a send byte operation to set a RAM address. The user writes the number of registers to be written to in the block read command to the #Bytes bits of the Configuration 0 register. 1. 2. 3. 4. The master device asserts a start condition on the SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an ACK on the SDA. The master sends a command code that tells the slave device to expect a block write. The ADT7462 command code for a block write is 0xA0 (1010 0000). The slave asserts ACK on the SDA. The master sends the data bytes (the number of data bytes sent is written to the #Bytes bits of the Configuration 0 register). The slave asserts an ACK on the SDA after each data byte. The master sends a packet error checking (PEC) byte. The ADT7462 checks the PEC byte and issues an ACK, if correct. If incorrect (NO ACK), the master resends the data bytes. Send Byte In this operation, the master device sends a single command byte to a slave device as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an ACK on SDA. The master sends a command code. The slave asserts an ACK on SDA. The master asserts a stop condition on SDA, and the transaction ends. For the ADT7462, the send byte protocol is used to write a register address to RAM for a subsequent single byte read from the same address. This operation is shown in Figure 28. 1 S 2 SLAVE ADDRESS W 3 A 4 REGISTER ADDRESS 5 A 6 P 05569-018 5. 6. 7. 8. 9. Figure 28. Setting a Register Address for a Subsequent Read If it is required to read data from the register immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read without asserting an intermediate stop condition. 10. The master asserts a stop condition on the SDA to end the transaction. 1 2 3 4 5 6 7 8 9 10 11 12 P 05569-020 Write Byte In this operation, the master device sends a command byte and one data byte to the slave device as follows: 1. 2. 3. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an ACK on SDA. COMMAND SLAVE BYTE S ADDRESS W A A0h BLOCK A COUNT A DATA 1 A DATA 2 A DATA A PEC A 32 WRITE Figure 30. Block Write to ADT7462 Rev. 0 | Page 20 of 92 ADT7462 READ OPERATIONS The ADT7462 uses the following SMBus read protocols. 4. The master sends a command code that tells the slave device to expect a block read. The ADT7462 command code for a block read is 0xA1 (1010 0001). The slave asserts an ACK on SDA. The master asserts a repeat start condition on the SDA. The master sends the 7-bit slave address followed by the read bit (high). The slave asserts an ACK on the SDA. The ADT7462 sends a byte count telling the master how many data bytes to expect. The maximum number of bytes is 32. Receive Byte The receive byte is useful when repeatedly reading a single register. The register address needs to have been set up previously. In this operation, the master device receives a single byte from a slave device as follows: 1. 2. 3. 4. 5. 6. The master device asserts a start condition on SDA. The master sends the 7-bit slave address followed by the read bit (high). The addressed slave device asserts an ACK on SDA. The master receives a data byte. The master asserts a NO ACK on SDA. The master asserts a stop condition on SDA and the transaction ends. 5. 6. 7. 8. 9. 10. The master asserts an ACK on SDA. 11. The master receives the expected number of data bytes. 12. The master asserts an ACK on SDA after each data byte. 13. The ADT7462 issues a PEC byte to the master. The master should check the PEC byte and issue another block read if the PEC byte is incorrect. 14. A NO ACK is generated after the PEC byte to signal the end of the read. 15. The master asserts a stop condition on the SDA to end the transaction. 1 2 3 4 5 6 S 7 SLAVE ADDRESS R COMMAND S SLAVE A ADDRESS W A A1h BLOCK READ 8 A 9 10 11 12 DATA 32 A In the ADT7462, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write byte operation. 1 S 2 SLAVE ADDRESS R 3 A 4 DATA 5 A 6 P 05569-021 Figure 31. Single Byte Read from a Register Block Read In this operation, the master device reads a block of data from a slave device. The start address for a block read must have been set previously, as well as the number of bytes to be read (maximum = 32). In the case of the ADT7462, the start address is activated by a send byte operation to set a RAM address. The number of bytes to be read should be written to the #Bytes bits in the Configuration 0 register. The block read operation consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows: 1. 2. 3. The master device asserts a start condition on the SDA. The master sends the 7-bit slave address followed by the write bit (low). The addressed slave device asserts an ACK on the SDA. 13 14 15 P Figure 32. Block Read from RAM Note that although the ADT7462 supports packet error checking (PEC), its use is optional. The PEC byte is calculated using CRC-8. The frame check sequence (FCS) conforms to CRC-8 by the polynomial C( x ) = x 8 + x 2 + x 1 + 1 Consult the SMBus 1.1 specifications for more information. Rev. 0 | Page 21 of 92 05569-022 BYTE A DATA 1 A COUNT PEC A ADT7462 ALERT RESPONSE ADDRESS Alert response address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. The SMBALERT output can be used as either an interrupt output or an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the master. If a device’s SMBALERT line goes low, the following procedure occurs: 1. 2. SMBALERT is pulled low. Master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. The device whose SMBALERT output is low responds to the alert response address, and the master reads its device address. The address of the device is now known and can be interrogated in the usual way. If more than one device’s SMBALERT output is low, the one with the lowest device address has priority in accordance with normal SMBus arbitration. Once the ADT7462 has responded to the alert response address, the master must read the status registers, and the SMBALERT is cleared only if the error condition has gone away. SMBUS TIMEOUT The ADT7462 includes an SMBus timeout feature. If there is no SMBus activity for 25 ms, the ADT7462 assumes that the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus expecting data. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled. Configuration Register 3 (0x03) Bit 1 SCL_Timeout = 1; SCL timeout enabled. Bit 1 SCL_Timeout = 0; SCL timeout disabled (default). Bit 2 SDA_Timeout = 1; SDA timeout enabled. Bit 2 SDA_Timeout = 0; SDA timeout disabled (default). 3. 4. 5. Rev. 0 | Page 22 of 92 ADT7462 TEMPERATURE AND VOLTAGE MEASUREMENT TEMPERATURE MEASUREMENT The ADT7462 can measure its own ambient temperature and the temperature of up to three remote thermal diodes. These diodes can be discrete diode-connected 2N3904/6s or can be located on a processor die. Figure 33 shows how to connect a remote NPN or PNP transistor. ADT7462 D+ 2N3906 D– 2N3904 The resulting ΔVBE waveforms are passed through a 65 kHz low-pass filter to remove noise and then to a chopper-stabilized amplifier. This amplifies and rectifies the waveform to produce a dc voltage proportional to ΔVBE. The ADC digitizes this voltage, and a temperature measurement is produced. To reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles for low conversion rates. Signal conditioning and measurement of the internal temperature sensor are performed in the same manner. ADT7462 D+ D– 05569-023 VCC I N1 × I N2 × I IBIAS Figure 33. How to Measure Temperature Using Discrete Transistors Remote Thermal Diode 1 connects to Pin 15 and Pin 16. Remote Thermal Diode 2 connects to Pin 17 and Pin 18. Remote Thermal Diode 3 connects to Pin 19 and Pin 20. A simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, measuring the baseemitter voltage (VBE) of a transistor, operated at constant current. Unfortunately, this technique requires calibration to null out the effect of the absolute value of VBE, which varies from device to device. The technique used in the ADT7462 is to measure the change in VBE when the device is operated at three different currents. Previous devices have used only two operating currents; use of a third current allows automatic cancellation of any resistances in series with the external temperature sensor. Figure 34 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, but it could equally be a discrete transistor. If a discrete transistor is used, the collector is not grounded and should be linked to the base. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the D− input. C1 can optionally be added as a noise filter (recommended maximum value 1000 pF). However, a better option in noisy environments is to add a filter, as described in the Noise Filtering section. To measure ΔVBE, the operating current through the sensor is switched among three related currents. As shown in Figure 34, N1 × I and N2 × I are different multiples of the Current I. The currents through the temperature diode are switched between I and N1 × I, giving ΔVBE1, and then between I and N2 × I, giving ΔVBE2. The temperature can then be calculated using the two ΔVBE measurements. This method can also be shown to cancel the effect of any series resistance on the temperature measurement. D+ REMOTE SENSING TRANSISTOR C1* D– BIAS DIODE LOW-PASS FILTER fC = 65kHz VOUT+ TO ADC VOUT– *CAPACITOR C1 IS OPTIONAL. IT SHOULD ONLY BE USED IN NOISY ENVIRONMENTS. Figure 34. Input Signal Conditioning Temperature Measurement Results The results of the local and remote temperature measurements are stored in the local and remote temperature value registers and are compared with limits programmed into the local and remote high and low limit registers. Table 12. Temperature Measurement Registers Temperature Value Local Temperature, LSB Local Temperature, MSB Remote 1 Temperature, LSB Remote 1 Temperature, MSB Remote 2 Temperature, LSB Remote 2 Temperature, MSB Remote 3 Temperature, LSB Remote 3 Temperature, MSB Register Address Register 0x88, Bits [7:6] Register 0x89 Register 0x8A, Bits [7:6] Register 0x8B Register 0x8C, Bits [7:6] Register 0x8D Register 0x8E, Bits [7:6] Register 0x8F The temperature value is stored in two registers. The MSB has a resolution of 1°C. Only two bits in the temperature LSB register are used, Bit 7 and Bit 6, giving a temperature measurement a resolution of 0.25°C. The temperature measurement range for both local and remote measurements is from −64°C to +191°C. However, the ADT7462 itself should never be operated outside its operating temperature range, which is from −40°C to +125°C. For the remote diode, the user should refer to the data sheet of the diode. Table 13. Temperature Data Format Temperature Value −64°C −50.25°C −25°C 0°C +25°C +50.25°C +100°C MSB 0000 0000 0000 1110 0010 0111 0100 0000 0101 1001 0111 0010 1010 0100 LSB 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 0100 0000 0000 0000 Rev. 0 | Page 23 of 92 05569-024 ADT7462 When reading the full temperature value, the LSB should be read first and then the MSB. Reading the LSBs causes the current MSBs to be frozen until they are read. Reading the MSBs only does not cause any register to be locked. This is useful when a temperature reading with 1°C resolution is required. Table 14. Temperature Limit Registers Temperature Value Local Low Temperature Limit Remote 1 Low Temperature Limit Remote 2 Low Temperature Limit Remote 3 Low Temperature Limit Local High Temperature Limit Remote 1 High Temperature Limit Remote 2 High Temperature Limit Remote 3 High Temperature Limit Local THERM1 Temperature Limit Remote 1 THERM1 Temperature Limit Remote 2 THERM1Temperature Limit Remote 3 THERM1 Temperature Limit Local THERM2 Temperature Limit Remote 1 THERM2 Temperature Limit Remote 2 THERM2 Temperature Limit Remote 3 THERM2 Temperature Limit Register Address 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 Default 0x40 0x40 0x40 0x40 0x95 0x95 0x95 0x95 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 SERIES RESISTANCE CANCELLATION Parasitic resistance in series with the remote diode D+ and D− inputs can be caused by a variety of factors, including PCB track resistance and track length. This series resistance appears as a temperature offset in the remote sensor’s temperature measurement. This error typically causes a 0.8°C offset per ohm of parasitic resistance in series with the remote diode. The ADT7462 automatically cancels out the effect of this series resistance on the temperature reading, giving a more accurate result, without the need for user characterization of this resistance. The ADT7462 is designed to automatically cancel typically up to 2 kΩ of resistance. By using an advanced temperature measurement method, the process is transparent to the user. This feature also allows an RCR filter to be added to the sensor path, allowing the part to be used accurately in noisy environments. Offset Registers The ADT7462 has temperature offset registers at Register 0x56 to Register 0x59 for the local, Remote 1, Remote 2, and Remote 3 temperature channels. By doing a one-time calibration of the system, the user can determine the offset caused by system board noise and null it out using the offset registers. The offset registers automatically add a twos complement, 8-bit reading to every temperature measurement. The LSBs add 0.5°C offset to the temperature reading so the 8-bit register effectively allows temperature offsets of up to ±64°C with a resolution of 0.5°C. This ensures that the readings in the temperature measurement registers are as accurate as possible. Temperature Limits Each temperature measurement channel has a high and low temperature limit associated with it. The temperature measurements are compared with these limits, and the results of these comparisons are stored in status registers. A Logic 0 indicates an in-limit comparison, and a Logic 1 indicates an out-of-limit comparison. The ADT7462 can generate an ALERT, if configured to do so, once a status bit is set. For more information on the status registers and ALERT, see the Status and Mask Registers and ALERT section of this datasheet. Each temperature channel also has a THERM1 and a THERM2 temperature limit associated with it. Once these temperature limits are exceeded, the corresponding THERM pin is asserted low (if THERM is configured as an output), and the fans are boosted to full speed (if the boost bit is set). Table 14 shows a complete list of all the temperature limits and their default values. Temperature Offset Registers Register 0x56 Local Temperature Offset = 0x00 (0°C default) Register 0x57 Remote 1 Temperature Offset = 0x00 (0°C default) Register 0x58 Remote 2 Temperature Offset = 0x00 (0°C default) Register 0x59 Remote 3 Temperature Offset = 0x00 (0°C default) Rev. 0 | Page 24 of 92 ADT7462 Layout Considerations Digital boards can be electrically noisy environments. The ADT7462 measures very small voltages from the remote sensor, so care must be taken to minimize noise induced at the sensor inputs. The following precautions should be taken: Place the ADT7462 as close as possible to the remote sensing diode. Provided that the worst noise sources, such as clock generators, data/address buses, and CRTs, are avoided, this distance can be 4 inches to 8 inches. Route the D+ and D− tracks close together, in parallel, with grounded guard tracks on each side. To minimize inductance and reduce noise pick-up, a 5 mil track width and spacing is recommended. If possible, provide a ground plane under the tracks. GND 5MIL 5MIL D+ 5MIL 5MIL D– For really long distances (up to 100 feet), use shielded twisted pair, such as Belden No. 8451 microphone cable. Connect the twisted pair to D+ and D− and the shield to GND close to the ADT7462. Leave the remote end of the shield unconnected to avoid ground loops. • Because the measurement technique uses switched current sources, excessive cable or filter capacitance can affect the measurement. When using long cables, the filter capacitance can be reduced or removed. Noise Filtering For temperature sensors operating in noisy environments, the industry-standard practice is to place a capacitor across the D+ and D− pins to help combat the effects of noise. However, large capacitances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pF. While this capacitor does reduce the noise, it does not eliminate it, making it difficult to use the sensor in a very noisy environment. The ADT7462 has a major advantage over other devices when it comes to eliminating the effects of noise on the external sensor. The series resistance cancellation feature allows a filter to be constructed between the external temperature sensor and the device. The effect of any filter resistance seen in series with the remote sensor is automatically cancelled from the temperature result. The construction of a filter allows the ADT7462 and the remote temperature sensor to operate in noisy environments. Figure 36 shows a low-pass RCR filter, with the following values: R = 100 Ω C = 1 nF This filtering reduces both common-mode noise and differential noise. 100Ω 1nF REMOTE SENSOR 100Ω 05569-026 5MIL 5MIL GND 5MIL Figure 35. Typical Arrangement of Signal Tracks Minimize the number of copper/solder joints that can cause thermocouple effects. Where copper/solder joints are used, make sure that they are in both the D+ and D− path and at the same temperature. • Thermocouple effects should not be a major problem because 1°C corresponds to about 200 mV, and thermocouple voltages are about 3 mV/°C of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200 mV. Place a 0.1 μF bypass capacitor close to the VDD pin. In extremely noisy environments, an input filter capacitor can be placed across D+ and D− close to the ADT7462. This capacitance can affect the temperature measurement, so care must be taken to ensure that any capacitance seen at D+ and D− is a maximum of 1000 pF. This maximum value includes the filter capacitance, plus any cable or stray capacitance between the pins and the sensor diode. If the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. This works up to about 6 feet to 12 feet. 05569-025 D+ D– Figure 36. Filter Between Remote Sensor and the ADT7462 Rev. 0 | Page 25 of 92 ADT7462 VOLTAGE MEASUREMENT The ADT7462 is capable of measuring up to 13 different voltage inputs at one time. Table 15 is a list of the voltage measurement inputs and the corresponding input pins. Each pin can be configured to measure the desired voltage option using Pin Configuration 1 (0x10) to Pin Configuration 4 (0x13) or the easy configuration options. Table 15. Voltage Inputs Pin 7 8 13 15 19 21 22 23 24 25 26 28 29 Voltage Measured +12V1 +12V2 +3.3V +2.5V/+1.8V +1.25V/+0.9V +5V +12V3 VCCP1/+1.5V/+1.8V/+2.5V VCCP2/+1.5V/+1.8V/+2.5V +1.2V1 (GBIT)/+3.3V +1.2V2 (FSB_VTT)/VBATT +1.5V1 (ICH) +1.5V2 (3GIO) ICH, 3GIO, 1.5V 0.9V 8kΩ 92kΩ 35pF GBIT, FSB_VTT, VCCP1 , VCCP2 1.25V 32kΩ 77kΩ 10pF 30kΩ 72kΩ 10pF 51kΩ 66kΩ 8pF 1.8V 8kΩ 91kΩ 35pF MUX 2.5V 30kΩ 72kΩ 10pF 3.3V 57kΩ 17kΩ 5pF Input Circuit The internal structure for the voltage inputs is shown in Figure 37. Each input circuit consists of an input protection diode; an attenuator; plus a capacitor to form a first-order, low-pass filter that gives the input immunity to high frequency noise. Voltages with full-scale values greater than the reference are divided down so that the full-scale value equals the reference (2.25 V). All analog inputs are multiplexed into the on-chip, successive approximation ADC. This ADC has a resolution of ten bits. The basic input range is from 0 V to 2.25 V, but the inputs have built-in attenuators to allow measurement of larger and smaller voltages. To allow a tolerance for these voltages, the ADC produces an output of 3/4 full scale (decimal 768 or 0x300) for the nominal input voltage and so has enough headroom to cope with overvoltages. 5V 76kΩ 39kΩ 5pF 12V 100kΩ 16kΩ 5pF Figure 37. Voltage Input Structures Rev. 0 | Page 26 of 92 05569-027 ADT7462 A list of corresponding LSB and full-scale values for each input voltage is shown in Table 16. Table 16. Input Range Code Conversion Nominal Input Voltage (3/4 Scale) +12V +5V VCCP1, VCCP2 VCCP1, when VIDs are enabled +3.3V VBATT +2.5V +1.8V +1.5V +1.25V +1.2V +0.9V Pin 7, 8, 22 21 23, 24 23 13, 25 26 15, 23, 24 15, 23, 24 23, 24, 28, 29 19 25, 26 19 1 LSB Value 0.0625 0.026 0.00625 0.0125 0.0172 0.0156 0.013 0.0094 0.0078 0.0065 0.00625 0.00469 Full Scale 16 V 6.67 V 1.6 V 3.2 V 4.4 V 4V 3.33 V 2.4 V 2V 1.667 V 1.6 V 1.2 V Similarly, the voltage, given the code in a particular channel, is calculated as follows: Voltage = Code × 1 LSB where: 10 V is connected to the 12 V channel. 1 LSB = 0.0625. Code = 160 decimal. Voltage Measurement and Limit Registers The corresponding register locations for voltage measurements are listed in Table 17. Each voltage measurement channel has a high and low voltage limit associated with it. The voltage measurements are compared with these limits. The results of these comparisons are stored in status registers. A Logic 0 indicates an in-limit condition, and a Logic 1 indicates an outof-limit condition. The ADT7462 can generate an ALERT, if configured to do so, once a status bit is set. For more information on the status registers and ALERT, see the Status and Mask Registers and ALERT section of this datasheet. A complete list of all the high and low voltage limits in the ADT7462 and their default values is contained in Table 17. Example Calculations Given the LSB value for each channel, the corresponding code for each voltage (or vice versa) can be calculated. Code = Voltage 1 LSB Example: The code for 1.8 V in a 1.8 V channel is Code = 1.8 (that = 192 0.0094 is 3 scale 4 ) Table 17. Voltage Value and Limit Registers Voltage Value +12V1 +12V2 +3.3V +1.8V or +2.5V +1.25V or +0.9V +5V +12V3 VCCP1, +1.5V, +1.8V, +2.5V VCCP2, +1.5V, +1.8V, +2.5V +1.2V1 (GBIT) or +3.3V +1.2V2 (FSB_VTT) or VBATT +1.5V1 (ICH) +1.5V2 (3GIO) Pin Pin 7 Pin 8 Pin 13 Pin 15 Pin 19 Pin 21 Pin 22 Pin 23 Pin 24 Pin 25 Pin 26 Pin 28 Pin 29 Value Register Address 0xA3 0xA5 0x96 0x8B 0x8F 0xA7 0xA9 0x90 0x91 0x92 0x93 0x94 0x95 Low Limit Register Default 0x6D 0x00 0x6E 0x00 0x70 0x00 0x45 0x40 0x47 0x40 0x71 0x00 0x6F 0x00 0x72 0x20 0x73 0x00 0x74 0x00 0x75 0x80 0x76 0x00 0x77 0x00 High Limit Register Default 0x7C 0xFF 0x7D 0xFF 0x68 0xFF 0x49 0x95 0x4B 0x95 0x7E 0xFF 0x7F 0xFF 0x69 0xFF 0x6A 0xFF 0x6B 0xFF 0x6C 0xFF 0x50 0xA4 0x4C 0xA4 Rev. 0 | Page 27 of 92 ADT7462 BATTERY MEASUREMENT INPUT (VBATT) The VBATT input allows the condition of a CMOS backup battery to be monitored. This is typically a lithium coin cell, such as a CR2032. The VBATT input is accurate only for voltages greater than 1.2 V. Note that when Pin 26 is configured as a +1.2V input, voltages lower than 1.2 V are not accurately measured. Input voltage and corresponding voltage measured are shown in Figure 22. Typically, the battery in a system is required to keep some devices powered on when the system is in a powered-off state. The VBATT measurement input is designed to minimize battery drain. To reduce current drain from the battery, the lower resistor of the VBATT attenuator is not connected, except when a VBATT measurement is being made. The total current drain on the VBATT pin is 80 nA typical (for a maximum VBATT voltage = 4 V), so a CR2032 CMOS battery functions in a system in excess of the expected 10 years. Note that when a VBATT measurement is not being made, the current drain is reduced to 6 nA typical. Under normal voltage measurement operating conditions, all measurements are made in a roundrobin format, and each reading is actually the result of 16 digitally averaged measurements. However, averaging is not carried out on the VBATT measurement to reduce measurement time and, therefore, reduce the current drain from the battery. The VBATT current drain when a measurement is being made is calculated by VBATT Input Battery Protection In addition to minimizing battery current drain, the VBATT measurement circuitry is specifically designed with battery protection in mind. Internal circuitry prevents the battery from being back-biased by the ADT7462 supply or through any other path under normal operating conditions. In the unlikely event of a catastrophic ADT7462 failure, the ADT7462 includes a second level of battery protection, including a series 3 kΩ resistor to limit current to the battery, as recommended by UL. Thus, it is not necessary to add a series resistor between the battery and the VBATT input; the battery can be connected directly to the VBATT input to improve voltage measurement accuracy. VBATT 49.5k Ω 3kΩ DIGITAL CONTROL ADC 4.5pF 3kΩ 82.7k Ω Figure 38. Equivalent VBATT Input Protection Circuit I= where: T V BATT × PULSE 100 kΩ TPERIOD TPULSE is VBATT measurement time (~711 μs typical). TPERIOD is the time required to measure all analog inputs. Monitoring cycle time depends on the ADT7462 configuration. Calculating the monitoring cycle time is described in more detail in the ADC Information section. Rev. 0 | Page 28 of 92 05569-028 ADT7462 ADC INFORMATION Round Robin Both temperature and voltage measurements are analog inputs that are digitized using the on-board ADC. An internal multiplexer switches between the different analog inputs and digitizes them, in turn, in a round-robin manner. The total conversion time depends upon how the ADT7462 is configured. The conversion times for each measurement channel are shown in Table 18. The complete conversion time is the sum of the time for the voltage and temperature measurements. For example, if the ADT7462 is configured as Easy Configuration Option 1, the round-robin conversion time is calculated as follows: Total Conversion Time = 1 × (Local Conversion Time) + 3 × (Remote Conversion Time) + 4 × (Voltage Measurement Time). The TACH is not measured using the ADC and so is not part of the round-robin monitoring cycle. Table 18. Measurement Channel Conversion Times Channel Local Temperature Remote Temperature Voltage Conversion Time 9.01 ms 38.36 ms 8.53 ms Single-Channel ADC Conversions Setting Bit 2 of the EDO/single-channel enable register (0x16) places the ADT7462 into single-channel mode. In this mode the ADT7462 can be made to convert on a single voltage or temperature channel only. The channel to be converted on is selected by writing to Bits [7:3] of the EDO/single-channel enable register (0x16). When the device is in single-channel mode, the pin configuration option should not be changed. Note that when the Pin 26 voltage, which includes the VBATT option, is selected in single-channel mode, this means that voltage measurements are continuously made in the mode. If a battery is connected to this input, then this results in an excessive current drain on the battery. The specification of >10 years of battery life is valid only when the battery voltage is measured as part of the round robin and not in single-channel mode. Table 20. Single-Channel Mode Options Bits [7:3] 00 000 00 001 00 010 00 011 00100 00 101 00 110 00 111 01 000 01 001 01 010 01 011 01 100 01 101 01 110 10 000 10 001 ADC Channel Selected Pin 26 Remote 1 temperature Remote 2 temperature Remote 3 temperature Local temperature +12V1 voltage, Pin 7 +12V2 voltage, Pin 8 +12V3 voltage, Pin 22 +3.3V voltage, Pin 13 +2.5V/+1.8V voltage, Pin 15 +1.25V/0.9V voltage, Pin 19 +5V voltage, Pin 21 Pin 23 voltage Pin 24 voltage Pin 25 voltage +1.5V1 voltage, Pin 28 +1.5V2 voltage, Pin 29 For each ADC temperature and voltage measurement read from their value registers, 16 readings have actually been made internally and the results averaged before being placed in the value register. Bypass Voltage Attenuators There are up to 13 voltage measurement channels on the ADT7462. Each of these voltage measurement channels has an input structure (see Figure 37 for input structures for each of the voltage channels). Because the ADC has a voltage input range from 0 V to 2.25 V, these input circuits attenuate the voltage input using a resistor divider network to match the input range of the ADC. However, the user may occasionally want to remove the attenuators and directly apply a voltage of between 0 V and 2.25 V to the ADC. These attenuators can be disabled by setting relevant bits in the voltage attenuator configuration registers. This feature also allows the user to rescale the voltage inputs using an external attenuator circuit. However, when the attenuators are disabled, the user should ensure that the voltage on the pin never exceeds 2.25 V. Table 19. Voltage Attenuator Configuration Registers Register Name Voltage Attenuator Configuration Register 1 Voltage Attenuator Configuration Register 2 Register Address 0x18 0x19 Rev. 0 | Page 29 of 92 ADT7462 DYNAMIC VID MONITORING VID CODE The ADT7462 can be configured to monitor up to seven VID inputs. The VID code is output on seven lines from the CPU to tell the power controller what input voltage it requires. The ADT7462 can monitor the VID code and the voltage applied to the CPU to ensure that they match within an acceptable range. This acceptable range is programmable in the ADT7462. The VID lines are monitored by the ADT7462, and the VID code is stored in the VID value register (0x97), which can be read back over the SMBus. VID monitoring is enabled by setting Bit 7 (VIDs) of Pin Configuration Register 1 (0x10) to 1. See Table 21 and Table 22 for information on which pin should be connected to each VID line. When VID monitoring is enabled, all seven pins are automatically configured as VID inputs. It is not possible to select six pins as VID inputs and use the remaining pin as their alternate functions. VR10 requires only six VID lines (see Table 22). Pin 28 should be connected to ground when monitoring VR10 VID codes. VID6 reports a 0. Table 22. VR10 VID Codes VID Number VID6 VID5 VID4 VID3 VID2 VID1 VID0 Pin 28 32 31 4 3 2 1 Voltage Unused, connect to GND 12.5 mV 400 mV 200 mV 100 mV 60 mV 25 mV DYNAMIC VID MONITORING The ADT7462 supports dynamic VID monitoring. The purpose of the VID code is to tell the voltage controller what voltage, VCCP, should be applied to the CPU. The VCCP voltage applied to the processor changes as the power requirements of the processor change. The VID is compared with VCCP1 only. Note that when the VIDs are enabled, the LSB value for VCCP1 becomes 0.0125 V (see Table 16). The VID values can represent voltages from 0.8375 V to 1.6 V. The VID code is sampled by the ADT7462 every 11 μs and is stored in Register 0x97. Once the VID code has been stable (that is, does not change) for 55 μs, the measured VCCP is then compared with the VID code. The comparison table used is for either the VR10 or the VR11 specification (set by Bit 6 of Register 0x00). If the VID code and the measured VCCP do not match within a certain limit, then an ALERT is generated. The VID value decoded and the VCCP measurement must be within a window controlled by the VID high and low limits. The VID is compared with VCCP1 only. Register 0x78 holds the 4-bit VID high and low limits. The high limit has a range of 0 mV to +375 mV with a resolution of 25 mV (four bits). The low limit has a range of 0 mV to −187.5 mV with resolution of 12.5 mV (four bits). The high limit is used in a greater-than comparison, and the low limit is used in a less-than or equal-to comparison. Note that if both limits are set to 0x00, then because low limit is less than or equal to comparison, an ALERT always results. Therefore, the minimum value for low limit is 0x01. If the VCCP voltage measured and the VID code do not match to within the programmed limit, then Status Bit 6 of the digital status register gets set (Register 0xBE). This, in turn, can generate an ALERT if it is not masked. VID Value Register (0x97) Bit 0 = VID0 (reflects the logic state of Pin 1) Bit 1 = VID1 (reflects the logic state of Pin 2) Bit 2 = VID2 (reflects the logic state of Pin 3) Bit 3 = VID3 (reflects the logic state of Pin 4) Bit 4 = VID4 (reflects the logic state of Pin 31) Bit 5 = VID5 (reflects the logic state of Pin 32) Bit 6 = VID6 (reflects the logic state of Pin 28) The ADT7462 supports both the VR10 and the VR11 specifications. The default option supports the VR10 specification. To switch to the VR11 specification, set Bit 6 of Configuration Register 0 (0x00) to 1. VR11 is defined as eight bits; the ADT7462 monitors only seven VID lines (see Table 21). Table 21. VR11 VID Codes VID Number VID6 VID5 VID4 VID3 VID2 VID1 VID0 Pin 28 32 31 4 3 2 1 Voltage 400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV 6.25 mV Rev. 0 | Page 30 of 92 ADT7462 Example: VID high limit: 100 mV (Register 0x78), four MSBs set to 0100. VID low limit: 50 mV (Register 0x78), four LSBs set to 0100. VID value equates to 1.1 V. This is the read VID decoded, using either VR10 or VR11 tables. VCCP1 must be in the window of 1.05 V to 1.2 V. If the VCCP1 value is outside this window, the status bit is set and an ALERT is generated. To clear an ALERT generated in this way, read the digital status register. If the VID code and VCCP are now matching within the programmed window (that is, the error condition that caused the ALERT has gone away), then the status bit is reset and so is the ALERT. The VID to VCCP voltage tables for both VR10 and VR11 can be found on the Intel website. See the VRM and EVRD 10.0 Design Guidelines (Reg. 0.5), Page 18 and Page 19, for additional information. Rev. 0 | Page 31 of 92 ADT7462 STATUS AND MASK REGISTERS AND ALERT Status Registers Each measured temperature and voltage has an associated high and low limit. The measured values are compared with these programmable limits. The results of these comparisons are stored in the status registers. A Logic 0 in the status register represents an in-limit comparison, while a Logic 1 represents an out-of-limit comparison. Once a status bit is set, it remains set until the status register is read by the SMBus master. Once read, the status bit clears if the error condition has gone away. The status registers are duplicated to accommodate situations where there are two SMBus masters. If one master reads the host status registers and consequently clears them, the second master has no way of knowing what bits were set and what bits were cleared. The second SMBus master can read from the duplicate BMC status registers for what status bits were set. Table 23 is a list of the status registers and corresponding addresses. Table 23. Status Registers Register Name Thermal Status Register 1 Thermal Status Register 2 Thermal Status Register 3 Voltage Status Register 1 Voltage Status register 2 Fan Status Register 1 Digital Status Register 1 GPIO Status Register Host Address 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF BMC Address 0xC0 0xC1 0xC3 0xC4 0xC5 0xC6 HIGH LIMIT TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT) STICKY STATUS BIT SMBALERT 05569-029 TEMP BACK IN LIMIT (STATUS BIT STAYS SET) Figure 39. ALERT and Status Bit Behavior Figure 39 shows how the ALERT output and ‘‘sticky’’ status bits behave. Once a limit is exceeded, the corresponding status bit is set to 1. The status bit remains set until the error condition goes away and the status register is read. The status bits are referred to as sticky because they remain set until read by software. This ensures that an out-of-limit event cannot be missed, if software is polling the device periodically. Note that the ALERT output remains low for the entire duration that a reading is out-of-limit and until the status register has been read. Mask Registers The user has the option to mask out any of the individual status bits that generate an ALERT. This is achieved by setting the appropriate bit in the mask registers. The ALERT output is not asserted on the setting of a status bit if it has been masked. The status bit itself is not affected and continues to be set when an out-of-limit condition exists. Table 24 is a list of the mask registers and corresponding addresses. Table 24. Mask Registers Register Name Thermal Mask Register 1 Thermal Mask Register 2 Voltage Mask Register 1 Voltage Mask Register 2 Fan Mask Register 1 Digital Mask Register 1 GPIO Mask Register Register Address 0x30 0x31 0x32 0x33 0x34 0x35 0x36 ALERT Output The ADT7462 has an SMBus ALERT output that is asserted when one of the status bits gets set. This is to alert the master that an out-of-limit measurement has taken place or that there is a fault on one of the fan channels. An ALERT is generated as a result of a status bit being set in any of the registers. Rev. 0 | Page 32 of 92 ADT7462 FAN CONTROL FAN DRIVE USING PWM CONTROL The ADT7462 uses pulse width modulation (PWM) to control fan speed. Control relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. The advantage of using PWM control is that it uses a very simple external circuit. The specific circuit used depends upon the type of fan. There are three main fan types in use: 2-wire fans, 3-wire fans, and 4-wire fans. The 2-wire fan has only power and ground connections. The 3-wire fan has power and ground connections and a TACH output to indicate the speed of the fan. The 4-wire fan has power and ground connections, a TACH output, and a PWM input. The PWM input is connected directly to the PWM drive of the ADT7462 and is used to control the speed of the fans. For 2-wire and 3-wire fans, the low frequency PWM drive signal should be selected. For 4-wire fans, the high frequency PWM drive signal should be selected. Using the ADT7462 with 3-Wire Fans Figure 41 shows the most typical circuit used with a 3-wire fan. 12V 10kΩ TACH/AIN 10kΩ 4.7kΩ 3.3V 12V FAN 1N4148 12V ADT7462 10kΩ PWM Q1 NDT3055L 05569-031 Figure 41. Driving a 3-Wire Fan Using the ADT7462 with 2-Wire Fans Figure 40 shows the most typical circuit used with a 2-wire fan and illustrates how a 2-wire fan can be connected to the ADT7462. The low frequency PWM mode must be selected when using a 2-wire fan. +V ADT7462 3.3V 5V OR 12V FAN 1N4148 10kΩ TYPICAL PWM Q1 NDT3055L The external circuitry required is very simple. A MOSFET, such as the NDT3055L, is used as the pass device. The specifications of the MOSFET depend on the maximum current required by the fan being driven. A typical PC fan can draw a nominal current ranging from a few hundred milliamps to over an amp of current. Depending on the current rating of the fan, a SOT device can be used where board space is a concern. If you drive several fans in parallel from a single PWM output or drive larger server fans, the MOSFET must handle the higher current requirements. The only other stipulation is that the MOSFET should have a gate voltage drive, VGS < 3.3 V, for direct interfacing to the PWM pins. VGS can be greater than 3.3 V as long as the pull-up on the gate is tied to 5 V. The MOSFET should also have a low on resistance to ensure that there is not significant voltage drop across the FET, which would reduce the voltage applied across the fan and reduce the full speed of the fan. Figure 41 uses a 10 kΩ pull-up resistor for the TACH signal. This assumes that the TACH signal is an open collector from the fan. In all cases, the TACH signal from the fan must be kept below 5 V maximum to prevent damaging the ADT7462. If in doubt as to whether the fan used has an open-collector or totem-pole TACH output, use one of the input signal conditioning circuits shown in the Fan Speed Measurement section of the data sheet. Driving a 3-wire fan with a PWM signal makes the fan speed measurement more difficult because the TACH signal is chopped by the PWM drive signal. Pulse stretching is required in this case to make accurate fan speed measurements. For more information, see the Fan Speed Measurement section. 0.01µF 05569-030 TACH RSENSE 2Ω TYPICAL Figure 40. Driving a 2-Wire Fan Rev. 0 | Page 33 of 92 ADT7462 Using the ADT7462 with 4-Wire Fans Figure 42 shows the most typical circuit used with 4-wire fans. 12V 12V 12V, 4-WIRE FAN 10kΩ TACH 10kΩ 4.7kΩ TACH VCC TACH PWM Note that because the MOSFET can handle up to 3.5 A, it is simply a matter of connecting another fan directly in parallel with the first. Care should be taken in designing drive circuits with transistors and FETs to ensure that the PWM pins are not required to source current and that they sink less than the 8 mA maximum current specified on the data sheet. 3.3V 10kΩ TYPICAL TACH7 +V +V ADT7462 3.3V OR 5V 2kΩ 05569-032 PWM 3.3V ADT7462 TACH3 Figure 42. Driving a 4-Wire Fan 10kΩ TYPICAL TACH 5V OR 12V FAN 1N4148 TACH Driving Two Fans from Each PWM Note that the ADT7462 has up to eight TACH inputs available for fan speed measurement, but only four PWM drive outputs. If all eight fans are being used in the system, two fans should be driven in parallel from each PWM output. Figure 43 shows how to drive two fans in parallel using the NDT3055L MOSFET. This information is relevant for low frequency mode only (2-wire and 3-wire fans), because the PWM and TACHs need to be synchronized to obtain accurate fan speed measurements using pulse stretching (see the Fan Speed Measurement with Pulse Stretching section). In high frequency mode and when using 4-wire fans, the TACH signal is always valid because the fan is always powered on. Figure 43. Interfacing Two Fans in Parallel to a PWM Output Using a Single N-Channel MOSFET Rev. 0 | Page 34 of 92 05569-033 Because the electronics in a 4-wire fan are powered continuously, unlike previous PWM driven/powered fans, 4-wire fans tend to perform better than 3-wire fans, especially for high frequency applications. It also eliminates the requirement for pulse stretching, because the TACH signal is always available. 3.3V 5V OR 12V FAN 10kΩ TYPICAL PWM3 Q1 NDT3055L ADT7462 FAN SPEED MEASUREMENT AND CONTROL TACH INPUTS Pin 1, Pin 2, Pin 3, Pin 4, Pin 7, Pin 8, Pin 21, and Pin 22 are TACH inputs intended for fan speed measurement. Signal conditioning in the ADT7462 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 5 V, even where VCC is less than 5 V. In the event that these inputs are supplied from fan outputs that exceed 0 V to 5 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figure 44 to Figure 47 show circuits for most common fan TACH circuits. If the fan TACH output has a resistive pull-up to VCC, it can be connected directly to the fan input, as shown in Figure 44. VCC 12V PULL-UP 4.7kΩ TYPICAL If the fan has a strong pull-up (less than 1 kΩ) to 12 V or a totem-pole output, a series resistor can be added to limit the Zener current, as shown in Figure 46. Alternatively, a resistive attenuator can be used, as shown in Figure 47. R1 and R2 should be chosen such that 2 V < VPULLUP × R2/(RPULLUP + R1 + R2) < 5 V The fan inputs have an input resistance of nominally 160 kΩ to ground, so this should be taken into account when calculating resistor values. With a pull-up voltage of 12 V and a pull-up resistor of less than 1 kΩ, suitable values for R1 and R2 would be 100 kΩ and 47 kΩ. This gives a high input voltage of 3.83 V. 5V OR 12V FAN PULL-UP TYP VCC or Totem-Pole Output, Clamped with a Zener Diode and Resistor 12V VCC Figure 44. Fan with TACH Pull-Up to VCC If the fan output has a resistive pull-up to 12 V (or other voltage greater than 5 V), the fan output can be clamped with a Zener diode, as shown in Figure 45. The Zener diode voltage should be chosen so that it is greater than VIH of the TACH input but less than 5 V, allowing for the voltage tolerance of the Zener. A value of between 3 V and 5 V is suitable. 12V VCC VCC or Totem-Pole Output, Attenuated with R1/R2 FAN SPEED MEASUREMENT PULL-UP 4.7kΩ TYPICAL TACH OUTPUT TACH ZD1* FAN SPEED COUNTER 05569-035 ADT7462 *CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × VCC. Figure 45. Fan with TACH Pull-Up to Voltage > 5 V (Example, 12 V), Clamped with Zener Diode The method of fan speed measurement when using 3-wire fans differs from that used with 4-wire fans. When 3-wire fans are in use, power is continuously applied and removed from the fan, thereby chopping the TACH information. As a result, every time a fan speed measurement is to be made, the fan must be switched on for a long enough period of time that a measurement can be made. This is called pulse stretching. With 4-wire fans, power is always applied to the fan, so fan speed measurements can be made continuously, and there is no need for pulse stretching. Pulse stretching is also not necessary when driving a 3-wire fan with a dc input. The Fan Speed Measurement Without Pulse Stretching section and the Fan Speed Measurement with Pulse Stretching section describe how fan speed is measured both when pulse stretching is required and when it is not. Rev. 0 | Page 35 of 92 ADT7462 Fan Speed Measurement Without Pulse Stretching Fan speed is measured by the ADT7462, and the result is stored in the fan TACH value registers. The fan counter does not count the fan TACH output pulses directly because the fan speed can be less than 1000 rpm, and it would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on-chip 90 kHz oscillator into the input of a 16-bit counter for N periods of the fan TACH output (see Figure 48), so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed. To enable continuous measurement for 3-wire fans, set the corresponding dc bit for the TACH input in the TACH configuration register. This bit is set automatically when the HF PWM is in use with 4-wire fans. Fan Speed Measurement Registers Fan speed measurement involves a 2-register read for each measurement. The low byte should be read first. This causes the high byte to be frozen until both high and low byte registers have been read, preventing erroneous TACH readings. The fan tachometer reading registers report back the number of 11.11 μs period clocks (90 kHz oscillator) gated to the fan speed counter, from the rising edge of the first fan TACH pulse to the rising edge of the third fan TACH pulse (because two pulses per revolution are being counted). Because the device is essentially measuring the fan TACH period, the higher the count value the slower the fan is actually running. A 16-bit fan tachometer reading of 0xFFFF indicates either that the fan has stalled or is running very slowly ( (OP1 – HYS) YES NO DO NOTHING IS T1(n) – T1(n – 1) ≤ 0.25°C NO YES DO NOTHING (SYSTEM COOLING IS OFF OR CONSTANT) IS T1(n) – T1(n – 1) = 0.5 – 0.75°C IS T1(n) – T1(n – 1) = 1.0 – 1.75°C IS T1(n) – T1(n – 1) > 2.0°C DECREASE T MIN BY 4°C Figure 67. Short Cycle Steps 05569-058 DECREASE T MIN BY 1°C DECREASE T MIN BY 2°C ADT7462 Figure 68 shows the steps taken during the long cycle. WAIT 2n MONITORING CYCLES CURRENT TEMPERATURE MEASUREMENT T1(n) OPERATING POINT TEMPERATURE OP1 Because neither the operating point minus the hysteresis temperature nor the low temperature limit has been exceeded, the TMIN value is not adjusted, and the fan runs at a speed determined by the fixed TMIN and TRANGE values defined in the automatic fan speed control mode. IS T1(n) > OP1 YES DECREASE T MIN BY 1°C Example 2: Operating Point Exceeded; TMIN Reduced When the measured temperature is below the operating point temperature minus the hysteresis, TMIN remains the same. Once the temperature exceeds the operating temperature minus the hysteresis (OP − Hyst), TMIN starts to decrease as illustrated in Figure 70. This occurs during the short cycle (see Figure 67). The rate at which TMIN decreases depends on the programmed value of n. It also depends on how much the temperature has increased between this monitoring cycle and the last monitoring cycle; that is, if the temperature has increased by 1°C, then TMIN is reduced by 2°C. Decreasing TMIN has the effect of increasing the fan speed, thus providing more cooling to the system. If the temperature is slowly increasing only in the range (OP − Hyst), that is, ≤0.25°C per short monitoring cycle, then TMIN does not decrease. This allows small changes in temperature in the desired operating zone without changing TMIN. The long cycle makes no change to TMIN in the temperature range (OP − Hyst), because the temperature has not exceeded the operating temperature. Once the temperature exceeds the operating temperature, the long cycle causes TMIN to be reduced by 1°C every long cycle while the temperature remains above the operating temperature. This takes place in addition to the decrease in TMIN that would occur due to the short cycle. In Figure 69, because the temperature is increasing at a rate ≤0.25°C per short cycle, no reduction in TMIN takes place during the short cycle. Once the temperature falls below the operating temperature, TMIN stays the same. Even when the temperature starts to increase slowly, TMIN stays the same, because the temperature increases at a rate of ≤0.25°C per cycle. 05569-060 NO IS T1(n) < LOW TEMP LIMIT AND TMIN < HIGH TEMP LIMIT YES AND TMIN < OP1 AND T1(n) > TMIN NO INCREASE TMIN BY 1°C Figure 68. Long Cycle Steps The following examples illustrate some of the circumstances that might cause TMIN to increase, decrease, or stay the same. Example 1: Normal Operation—No TMIN Adjustment 1. If measured temperature never exceeds the programmed operating point minus the hysteresis temperature, then TMIN is not adjusted; that is, it remains at its current setting. 2. If measured temperature never drops below the low temperature limit, TMIN is not adjusted. THERM LIMIT HIGH TEMP LIMIT OPERATING POINT HYSTERESIS ACTUAL TEMP LOW TEMP LIMIT TMIN Figure 69. Temperature Between the Operating Point and the Low Temperature Limit 05569-059 DO NOT CHANGE Rev. 0 | Page 50 of 92 ADT7462 THERM LIMIT HIGH TEMP LIMIT OPERATING POINT HYSTERESIS ACTUAL TEMP TMIN LOW TEMP LIMIT NO CHANGE IN TMIN HERE DUE TO ANY CYCLE BECAUSE T1(n) – T1 (n – 1) ≤ 0.25°C AND T1(n) < OP = > TMIN STAYS THE SAME Figure 70. Effect of Exceeding Operating Point Minus Hysteresis Temperature Example 3: Temperature Below Low Limit, TMIN Increased When the temperature drops below the low temperature limit, TMIN may increase, as shown in Figure 71. Increasing TMIN has the effect of running the fan more slowly and, therefore, more quietly. The long cycle diagram in Figure 68 shows the conditions that need to be true for TMIN to increase. Here is a quick summary of those conditions and the reasons they need to be true. TMIN may increase, if The measured temperature has fallen below the low temperature limit. This means the user must choose the low limit carefully. It should not be so low that the temperature never falls below it, because TMIN would never increase and the fans would run faster than necessary. TMIN is below the high temperature limit. TMIN is never allowed to increase above the high temperature limit. As a result, the high limit should be sensibly chosen, because it determines how high TMIN can go. TMIN is below the operating point temperature. TMIN should never be allowed to increase above the operating point temperature, because the fans do not switch on until the temperature rises above the operating point. • The temperature is above TMIN. The dynamic TMIN control is turned off below TMIN. Figure 71 shows how TMIN increases when the current temperature is above TMIN and below the low temperature limit, and TMIN is below the high temperature limit and below the operating point. Once the temperature rises above the low temperature limit, TMIN stays the same. THERM LIMIT HIGH TEMP LIMIT OPERATING POINT HYSTERESIS LOW TEMP LIMIT TMIN ACTUAL TEMP 05569-062 Figure 71. Increasing TMIN for Quieter Operation Example 4: Preventing TMIN from Reaching Full Scale Because TMIN is dynamically adjusted, it is undesirable for TMIN to reach full scale (191°C), because the fan would never switch on. As a result, TMIN is allowed to vary only within a specified range. • The lowest possible value for TMIN is −64°C . • TMIN cannot exceed the high temperature limit. • If the temperature is below TMIN, the fan is switched off or is running at minimum speed, and dynamic TMIN control is disabled. Rev. 0 | Page 51 of 92 05569-061 DECREASE HERE DUE TO SHORT CYCLE ONLY T1(n) – T1 (n – 1) = 0.5°C OR 0.75°C = > TMIN DECREASES BY 1°C EVERY SHORT CYCLE DECREASE HERE DUE TO LONG CYCLE ONLY T1(n) – T1 (n – 1) ≤ 0.25°C AND T1(n) > OP = > TMIN DECREASES BY 1°C EVERY LONG CYCLE ADT7462 THERM LIMIT OPERATING POINT HYSTERESIS LOW TEMP LIMIT HIGH TEMP LIMIT TMIN ACTUAL TEMP The operating point for the processor can be determined by allowing the current temperature to be copied to the operating point register when the PROCHOT output pulls the THERM input low on the ADT7462. This gives the maximum temperature at which the Pentium 4 can run before clock modulation occurs. TMIN PREVENTED FROM INCREASING 05569-063 Enabling the THERM Trip Point as the Operating Point Bits [5:2] of Dynamic TMIN Control Register 1 (0x0B) enable/disable THERM monitoring to program the operating point. Table 43 details how the remote temperatures can be copied into the operating point registers on a THERM assertion. Setting these bits to 1 uses the remote temperature as the operating point temperature, overwriting the programmed operating point value in the event of a THERM assertion. Setting these bits to 0 ignores a THERM assertion, and the operating point register remains at the programmed value. Figure 72. TMIN Adjustments Limited by High Temperature Limit Enabling Dynamic TMIN Control Mode Bits [1:0] of Dynamic TMIN Control Register 1 (0x0B) enable/disable dynamic TMIN control on the temperature channels (see Table 43). Dynamic TMIN Control Register 1 (0x0B) Bit (1) Remote 2 En = 1 enables dynamic TMIN control on the Remote 2 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. Remote 2 En = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted and the channel behaves as described in the Automatic Fan Control Overview section. Bit (0) Remote 1 En = 1 enables dynamic TMIN control on the Remote 1 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. Remote 1 En = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Automatic Fan Control Overview section. ENHANCING SYSTEM ACOUSTICS Automatic fan speed control mode reacts instantaneously to changes in temperature; that is, the PWM duty cycle responds immediately to temperature change. Any impulses in temperature can cause an impulse in fan noise. For psycho-acoustic reasons, the ADT7462 can prevent the PWM output from reacting instantaneously to temperature changes. Enhanced acoustic mode controls the maximum change in PWM duty cycle at a given time. The objective is to prevent the fan from cycling up and down, annoying the user. Acoustic Enhancement Mode Overview Figure 73 gives a top-level overview of the automatic fan control circuitry on the ADT7462 and shows where acoustic enhancement fits in. Acoustic enhancement is intended as a post-design tweak made by a system or mechanical engineer evaluating best settings for the system. Having determined the optimal settings for the thermal solution, the engineer can adjust the system acoustics. The goal is to implement a system that is acoustically pleasing without causing user annoyance due to fan cycling. It is important to realize that although a system might pass an acoustic noise requirement specification (for example, 36 dB), if the fan is annoying, it fails the consumer test. STEP 10—MONITORING THERM Using the operating point limit ensures that the dynamic TMIN control mode is operating in the best possible acoustic position, while ensuring that the temperature never exceeds the maximum operating temperature. Using the operating point limit allows TMIN to be independent of system-level issues because of its self-corrective nature. In PC design, the operating point for the chassis is usually the worst-case internal chassis temperature. The optimal operating point for the processor is determined by monitoring the thermal monitor in the Intel Pentium 4 processor. To do this, the PROCHOT output of the Pentium 4 is connected to the THERM input of the ADT7462. Rev. 0 | Page 52 of 92 ADT7462 ACOUSTIC ENHANCEMENT THERMAL CALIBRATION 100% PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT) PWM CONFIG PWM GENERATOR PWM1 TMIN REMOTE 2 = CPU TEMP TRANGE 0% PWM MIN THERMAL CALIBRATION TACHOMETER 1 MEASUREMENT 100% PWM CONFIG PWM GENERATOR TACH1 CPU FAN SINK MUX 0% PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 2 MEASUREMENT PWM2 TMIN LOCAL = VRM TEMP TRANGE THERMAL CALIBRATION PWM CONFIG PWM GENERATOR TACH2 100% RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT FRONT CHASSIS PWM3 TMIN REMOTE 1 = AMBIENT TEMP TRANGE 0% TACH3 REAR CHASSIS Figure 73. Acoustic Enhacement Smoothes Fan Speed Variations Under Automatic Fan Speed Control Approaches to System Acoustic Enhancement There are two different approaches to implementing system acoustic enhancement: temperature-centric and fan-centric. The temperature-centric approach involves smoothing transient temperatures as they are measured by a temperature source (for example, Remote 1 temperature). The temperature values used to calculate the PWM duty cycle values are smoothed, reducing fan speed variation. However, this approach causes an inherent delay in updating fan speed and causes the thermal characteristics of the system to change. It also causes the system fans to stay on longer than necessary, because the fan’s reaction is merely delayed. The user has no control over noise from different fans driven by the same temperature source. Consider, for example, a system in which control of a CPU cooler fan (on PWM1) and a chassis fan (on PWM2) use Remote 1 temperature. Because the Remote 1 temperature is smoothed, both fans are updated at exactly the same rate. If the chassis fan is much louder than the CPU fan, there is no way to improve its acoustics without changing the thermal solution of the CPU cooling fan. The fan-centric approach to system acoustic enhancement controls the PWM duty cycle, driving the fan at a fixed rate (for example, 6%). Each time the PWM duty cycle is updated, it is incremented by a fixed 6%. As a result, the fan ramps smoothly to its newly calculated speed. If the temperature starts to drop, the PWM duty cycle immediately decreases by 6% at every update. Therefore, the fan ramps smoothly up or down without inherent system delay. Consider, for example, controlling the same CPU cooler fan (on PWM1) and chassis fan (on PWM2) using Remote 1 temperature. The TMIN and TRANGE settings have already been defined in automatic fan speed control mode; that is, thermal characterization of the control loop has been optimized. Now the chassis fan is noisier than the CPU cooling fan. Using the fan-centric approach, PWM2 can be placed into acoustic enhancement mode independently of PWM1. The acoustics of the chassis fan can, therefore, be adjusted without affecting the acoustic behavior of the CPU cooling fan, even though both fans are controlled by Remote 1 temperature. The fan-centric approach is how acoustic enhancement works on the ADT7462. Enabling Acoustic Enhancement for Each PWM Output Enhance Acoustics Register 1 (0x1A) Bit 0 = EA1_En = 1 enables acoustic enhancement on PWM1 output. Bit 1 = EA2_En = 1 enables acoustic enhancement on PWM2 output. Enhance Acoustics Register 2 (0x1B) Bit 0 = EA3_En = 1 enables acoustic enhancement on PWM3 output. Bit 1 = EA4_En = 1 enables acoustic enhancement on PWM4 output. Rev. 0 | Page 53 of 92 05569-064 ADT7462 Effect of Ramp Rate on Enhanced Acoustic Mode The PWM signal driving the fan has a period, T, given by the PWM drive frequency, f, because T = 1/f. For a given PWM period, T, the PWM period is subdivided into 255 equal time slots. One time slot corresponds to the smallest possible increment in the PWM duty cycle. A PWM signal of 33% duty cycle is, therefore, high for 1/3 × 255 time slots and low for 2/3 × 255 time slots. Therefore, a 33% PWM duty cycle corresponds to a signal that is high for 85 time slots and low for 170 time slots. PWM_OUT 33% DUTY CYCLE STEP 11—RAMP RATE FOR ACOUSTIC ENHANCEMENT The optimal ramp rate for acoustic enhancement can be found through system characterization after the thermal optimization has been finished. The effect of each ramp rate should be logged, if possible, to determine the best setting for a given solution. Enhanced Acoustic Register 1 (0x1A) Bits [4:2] RR1 select the ramp rate for PWM1. 85 TIME SLOTS 170 TIME SLOTS 05569-065 PWM OUTPUT (ONE PERIOD) = 255 TIME SLOTS Figure 74. 33% PWM Duty Cycle Represented in Time Slots The ramp rates in the enhanced acoustics mode are selectable from 1 to 8. The ramp rates are discrete time slots. For example, if the ramp rate is 8, then eight time slots are added to the PWM high duty cycle each time the PWM duty cycle needs to be increased. If the PWM duty cycle value needs to be decreased, it is decreased by eight time slots. Figure 75 shows how the enhanced acoustics mode algorithm operates. READ TEMPERATURE 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots =3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds Bits [7:5] RR2 select the ramp rate for PWM2. CALCULATE NEW PWM DUTY CYCLE 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots =3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds Enhanced Acoustic Register 2 (0x1B) Bits [4:2] RR3 selects the ramp rate for PWM3. NO DECREMENT PREVIOUS PWM VALUE BY RAMP RATE IS NEW PWM VALUE > PREVIOUS VALUE? YES INCREMENT PREVIOUS PWM VALUE BY RAMP RATE Figure 75. Enhanced Acoustics Algorithm 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots = 3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds Bits [7:5] RR4 select the ramp rate for PWM4. The enhanced acoustics mode algorithm calculates a new PWM duty cycle based on the temperature measured. If the new PWM duty cycle value is greater than the previous PWM value, the previous PWM duty cycle value is incremented by either 1, 2, 3, 5, 8, 12, 24, or 48 time slots, depending on the settings of the enhance acoustics registers. If the new PWM duty cycle value is less than the previous PWM value, the previous PWM duty cycle is decremented by 1, 2, 3, 5, 8, 12, 24, or 48 time slots. Each time the PWM duty cycle is incremented or decremented, its value is stored as the previous PWM duty cycle for the next comparison. A ramp rate of 1 corresponds to one time slot, which is 1/255 of the PWM period. In enhanced acoustics mode, incrementing or decrementing by 1 changes the PWM output by 1/255 × 100%. 05569-066 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots = 3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds Rev. 0 | Page 54 of 92 ADT7462 Another way to view the ramp rates is to measure the time it takes for the PWM output to ramp up from 0% to 100% duty cycle for an instantaneous change in temperature. This can be tested by putting the ADT7462 into manual mode and changing the PWM output from 0% to 100% PWM duty cycle. The PWM output takes 35 seconds to reach 100% when a ramp rate of 1 time slot is selected. Figure 76 shows remote temperature plotted against PWM duty cycle for enhanced acoustics mode. The ramp rate is set to 48, which corresponds to the fastest ramp rate. Assume that a new temperature reading is available every 115 ms. With these settings, it takes approximately 0.76 seconds to go from 33% duty cycle to 100% duty cycle (full speed). Even though the temperature increases very rapidly, the fan ramps up to full speed gradually. 140 RTEMP (°C) 120 100 80 80 60 60 PWM CYCLE (%) 40 20 0 0 20 40 100 120 Figure 78 shows the PWM output response for a ramp rate of 2. In this instance, the fan took about 17.6 seconds to reach full running speed. 140 RTEMP (°C) 120 100 120 100 80 80 PWM DUTY CYCLE (%) 60 40 40 20 0 0 TIME (s) 20 60 17.6 0 Figure 78. Enhanced Acoustics Mode with Ramp Rate = 2 Figure 79 shows how the control loop reacts to temperature with the slowest ramp rate. The ramp rate is set to 1, while all other control parameters remain the same. With the slowest ramp rate selected, it takes 35 seconds for the fan to reach full speed. 120 RTEMP (°C) 100 05569-067 140 120 100 TIME (s) 0 0.76 80 80 60 PWM DUTY CYCLE (%) 40 60 40 20 0 05569-070 Figure 76. Enhanced Acoustics Mode with Ramp Rate = 48 Figure 77 shows how changing the ramp rate from 48 to 8 affects the control loop. The overall response of the fan is slower. Because the ramp rate is reduced, it takes longer for the fan to achieve full running speed. In this case, it takes approximately 4.4 seconds for the fan to reach full speed. 120 RTEMP (°C) 100 120 100 80 60 40 40 20 20 0 05569-068 20 0 0 TIME (s) 35 140 Figure 79. Enhanced Acoustics Mode with Ramp Rate = 1 80 PWM DUTY CYCLE (%) 60 As Figure 76 to Figure 79 show, the rate at which the fan reacts to temperature change is dependent on the ramp rate selected in the enhanced acoustics registers. The higher the ramp rate, the faster the fan reaches the newly calculated fan speed. Figure 80 shows the behavior of the PWM output as temperature varies. As the temperature increases, the fan speed ramps up. Small drops in temperature do not affect the ramp-up function, because the newly calculated fan speed is still higher than the previous PWM value. Enhanced acoustics mode allows the PWM output to be made less sensitive to temperature variations. This is dependent on the ramp rate selected and programmed into the enhanced acoustics registers. 0 0 TIME (s) 4.4 Figure 77. Enhanced Acoustics Mode with Ramp Rate = 8 Rev. 0 | Page 55 of 92 05569-069 ADT7462 90 80 70 60 50 40 30 20 05569-071 The freewheeling test procedure is as follows: 1. PWM DUTY CYCLE (%) PWM1 and PWM2 go to full speed, and PWM3 and PWM4 are switched off. After the spin-up time of PWM1 and PWM2 has elapsed, the speed of Fan 1, Fan 2, Fan 3, and Fan 4 is measured. Once the speed of Fan 1 and Fan 2 is measured, PWM1 is switched off and PWM3 is spun up. After the spin-up time for PWM3 has elapsed, the speed of Fan 5 and Fan 6 is measured. After the speed of Fan 3 and Fan 4 is measured, PWM2 is switched off and PWM4 is switched on. After the spin-up time of PWM4 has elapsed, the speed of Fan 7 and Fan 8 is measured. Once the speed of all eight fans has been measured, the TACH and PWM configurations go back to their previous values. a. Fans must be in continuous mode for the freewheeling test; that is, the dc bits must be set (Register 0x08). b. To enable the freewheeling test, set the freewheeling test enable register (0x1E) to a non-zero value. Set Bit 0 to 1 to enable the freewheeling test for Fan 1, and set Bit 1 for Fan 2, all the way to Bit 7 for Fan 8. The freewheeling test enable register should be programmed after the fans present register is programmed. If the fans present register is programmed first, then the values in the two registers do not match, and the ADT7462 assumes that a fan is missing. 2. RTEMP (°C) 3. 4. 10 0 Figure 80. How Fan Reacts to Temperature Variations in Enhanced Acoustics Mode 5. Slower Ramp Rates The ADT7462 can be programmed for much longer ramp times by slowing the ramp rates. Each ramp rate can be slowed by a factor of 4. PWM1 Configuration Register (0x21) PWM2 Configuration Register (0x22) PWM3 Configuration Register (0x23) PWM4 Configuration Register (0x24) Setting Bit 3 (the SLOW bit) to 1 in the PWM1 to PWM4 registers slows the ramp rate for PWM4 by 4. The following registers must be programmed for the fan freewheeling test: Fans Present Register (0x1D) Set Bit 0 to 1 when a fan is connected to TACH1. Set Bit 1 to 1 when a fan is connected to TACH2. Set Bit 2 to 1 when a fan is connected to TACH3. Set Bit 3 to 1 when a fan is connected to TACH4. Set Bit 4 to 1 when a fan is connected to TACH5. Set Bit 5 to 1 when a fan is connected to TACH6. Set Bit 6 to 1 when a fan is connected to TACH7. Set Bit 7 to 1 when a fan is connected to TACH8. Fan Freewheeling Test Enable Register (0x1E) Set Bit 0 to 1 to enable the freewheeling test for Fan 1. Set Bit 1 to 1 to enable the freewheeling test for Fan 2. Set Bit 2 to 1 to enable the freewheeling test for Fan 3. Set Bit 3 to 1 to enable the freewheeling test for Fan 4. Set Bit 4 to 1 to enable the freewheeling test for Fan 5. Set Bit 5 to 1 to enable the freewheeling test for Fan 6. Set Bit 6 to 1 to enable the freewheeling test for Fan 7. Set Bit 7 to 1 to enable the freewheeling test for Fan 8. Fan Freewheeling Test Register (0x1C) Both the fans present register (0x1D) and freewheeling test enable register (0x1E) should be programmed before setting the relevant bits in the freewheeling test register (0x1C). The host fan status register (0xBD) should be read directly after completion of the test. Rev. 0 | Page 56 of 92 FAN FREEWHEELING TEST MODE The fan freewheeling test mode is intended to diagnose whether fans connected to the ADT7462 are working properly. It is particularly useful in the situation where fans coupled in the duct can affect the airflow of the other fan. If one fan has failed, it may not be apparent, as moving air from other fans can cause air to flow through the faulty fan, which in turn can cause the faulty fan to rotate. The fan freewheeling test is most useful in a system using primary and redundant setup. In such a system the following setup is recommended. The primary fans are Fan 1, Fan 2, Fan 3, and Fan 4. The redundant fans are Fan 5, Fan 6, Fan 7, and Fan 8. In this setup, each primary and redundant fan can be driven separately because they are driven by different PWMs. PWM 1 PWM 2 FAN 1 TACH CCT 1 FAN 5 FAN 2 TACH CCT 2 FAN 6 FAN 3 TACH CCT 3 FAN 7 FAN 4 TACH CCT 4 FAN 8 PWM 3 PWM 4 Figure 81. Fan Freewheeling Test Mode Setup 05569-072 ADT7462 THERM I/O OPERATION This section describes the operation of THERM1 and THERM2. Pin 28 and Pin 29 can both be configured as THERM inputs or outputs. THERM Input To configure THERM as an input, the Enable_THERM1_Timer bit (Bit 0) in the THERM1 configuration register (0x0E) and the Enable_THERM2_Timer bit (Bit 0) in the THERM2 configuration register (0x0F) must be set to Logic 1. The ADT7462 can then be used to detect when the THERM pins are asserted low. The THERM pins can be connected to a trip point temperature sensor or to the PROCHOT output of a CPU. With processor core voltages reducing all the time, the threshold for the AGTL+ PROCHOT output also reduces as new processors become available. Because the THERM input is typically an AGTL+ input, the thresholds can be referenced to VCCP. By setting Bit 4 of Configuration Register 3 (0x03) to 1, the THERM threshold is 2/3 × VCCP, the correct threshold for an AGTL+ signal. The THERM assert bits in Host Thermal Status Register 2 (0xB9) are set to Logic 1 whenever the THERM input is asserted low. The THERM state bits in Host Thermal Status Register 2 (0xB9) indicate that a high-to-low transition has taken place on the THERM pin. THERM Output THERM is not enabled as an output by default on power-up, but it can be enabled by setting the appropriate bits in Register 0x0E (THERM1 configuration register) and Register 0x0F (THERM2 configuration register). THERM1 and THERM2 can be configured to assert whenever a specific channel exceeds the specified THERM limit (see Table 30). Table 30. THERM O/P Channel Select and Limits Channel Enable Configuration THERM1, THERM2, Register 0x0E Register 0x0F Bit 1 = 1 Bit 1 = 1 Bit 2 = 1 Bit 2 = 1 Bit 3 = 1 Bit 3 = 1 Bit 4 = 1 Bit 4 = 1 Limit Registers THERM1 0x4C 0x4D 0x4E 0x4F THERM2 0x50 0x51 0x52 0x53 Local Remote 1 Remote 2 Remote 3 As an output, THERM is asserted low to signal that the measured THERM temperature has exceeded preprogrammed THERM temperature limits. The output is automatically pulled high again when the temperature falls below the (THERM − Hysteresis) limit. The value of hysteresis for each channel is programmable in Register 0x54 and Register 0x55, where 1 LSB = 1°C, and the maximum hysteresis for each channel is 15°C. TEMPERATURE 100°C 90°C 80°C 70°C 60°C 50°C 40°C RESET BY MASTER ALERT THERM 05569-073 THERM Timer The ADT7462 can also measure assertion times on the THERM inputs as a percentage of a timer window. The timer window for the THERM1 input is programmed using Bits [4:2] of the THERM configuration register (0x0D). The timer window for the THERM2 input is programmed using Bits [7:5] of the THERM configuration register (0x0D). Values of between 0.25 seconds and 8 seconds are programmable (see Table 31). Table 31. THERM Timer Window Code 000 001 010 011 100 101 110 111 THERM Timer Window 0.25 sec 0.5 sec 1 sec 2 sec 4 sec 8 sec 8 sec 8 sec THERM LIMIT HIGH TEMP LIMIT THERM LIMIT–HYSTERESIS 1 2 3 4 Figure 82. THERM Behavior Setting the THERM boost bits, Bit 0 and Bit 1, to logic zero (default setting) in the THERM configuration register (0x0D), sets the fans to full speed on an internal THERM event. Rev. 0 | Page 57 of 92 ADT7462 The assertion time as a percentage of the time window is stored in the THERM % on-time registers. This is a cumulative sum of the percentage of time during the THERM timer window that THERM is asserted. The % on-time and associated timer limit registers are listed in Table 32. Table 32. THERM On-Time and Timer Limit Register Channel THERM1 THERM2 % On-Time Register 0xAE 0xAF % Timer Limit Register 0x80 0x81 THERM % Limit Register The THERM % limit is programmed to Register 0x80 and Register 0x81. If the THERM is asserted for longer than the programmed percentage limit, then an ALERT is generated. The limit is programmed as a percentage of the chosen THERM timer window. Example: The THERM timer window is eight seconds, and an ALERT should be generated if the THERM is asserted for more than one second. %Limit = 1 × 100 = 12.5% 8 Once the measured percentage exceeds the corresponding percentage limit, the THERM % bit in Thermal Status Register 2 gets asserted, and an ALERT is generated (that is, if the mask bit is not set). If the limit is set to 0x00, an ALERT is generated on the first assertion. If the Limit is set to FFh, an ALERT is never generated because 0xFF corresponds to the THERM input being asserted all the time. When THERM is configured as an input only, setting Bits [1:4] of the THERM zone in THERM1 configuration register (0x0E) and THERM2 configuration register (0x0F) allows Pin 7 to operate as an I/O. The THERM % limit register is an 8 bit register. 0x00 = 0% 0xFF = 100% Therefore, 1 LSB = 0.39% 12.5% = 32dec = 0 x 20 = 00100000 0.39% Once the time window has elapsed, if the THERM limit has been exceeded, then an ALERT is generated. Rev. 0 | Page 58 of 92 ADT7462 GENERAL-PURPOSE I/O PINS The ADT7462 has eight open drain GPIO pins. GPIO1 to GPIO4 can be configured to enable event driven outputs (EDOs), and GPIO5 and GPIO6 can act as EDOs, if the EDO functionality is enabled. Two other GPIOs (GPIO 7 and GPIO 8) are standard GPIO pins that are dedicated to general-purpose logic input/output. Each GPIO pin has five data bits associated with it: three bits in a GPIO configuration register (0x09 and 0x0A), one in the GPIO status register (0xBF), and one in the GPIO mask register (0x38). SETTING a direction bit to 1 in a GPIO configuration register makes the corresponding GPIO pin an output. CLEARING the direction bit to 0 makes the corresponding GPIO an input. SETTING a polarity bit to 1 in a GPIO configuration register makes the corresponding GPIO pin active high. CLEARING the polarity bit to 0 makes the corresponding GPIO active low. When a GPIO pin is configured as an input, the corresponding bit in the GPIO status registers is read only, and it is set when the input is asserted (“asserted” can be high or low, depending on the setting of the polarity bit). When a GPIO pin is configured as an output, the corresponding bit in the GPIO status registers becomes read/write. Setting this bit then asserts the GPIO output. (Again, “asserted” can be high or low, depending on the setting of the polarity bit.) The effect of a GPIO status register bit on the INT output can be masked by setting the corresponding bit in one of the GPIO mask registers. Table 33. EDO Control (Mask) Register 0x37 and Register 0x38 Bit 7: Over/Under Voltage 0 = Drive Output X 1 = Ignore Event Bit 6: THERM 0 = Drive Output X 1 = Ignore Event Bit5: Fan Fail 0 = Drive Output X 1 = Ignore Event Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Behavior: What Drives and Latches Output X (G = GPIO) G4 or G3 or G2 or G1 G4 or G3 or G2 G4 or G2 or G1 G4 or G3 G4 or G2 or G1 G4 or G2 G4 or G1 G4 G3 or G2 or G1 G3 or G2 G3 or G1 G3 G2 or G1 G2 G1 GPIO events Ignored by Output X When the pin is configured as an output, this bit is automatically masked to prevent the data written to the status bit from causing an interrupt. When configured as inputs, the GPIO pins can be connected to external interrupt sources such as temperature sensors with digital output. EDO CIRCUITRY The ADT7462 has the added functionality that the assertion of one of the four GPIOs (GPIO1 to GPIO4) can be used to latch one of the two EDOs high or low. The ADT7462 has two EDO event mask registers (0x37 and 0x38): one mask for each EDO. See Table 33 for an explanation of event mask register functionality. The polarity of the EDOs is set in the GPIO configuration registers (0x09 and 0x0A). SETTING a polarity bit to 1 in one of the GPIO configuration registers makes the corresponding GPIO pin active high. CLEARING the polarity bit to 0 makes it active low. GPIO1 GPIO2 GPIO3 GPIO4 05569-074 EDO (GPIO 5) LATCH EVENT MASK EDO (GPIO 6) Figure 83. EDO Circuit Bits [7:5] of each event mask register allow the EDO output to be driven high or low (depending on the polarity bit of the configuration register) and latched (depending on the EDO latch bit of the configuration register), if the ADT7462 detects an overtemperature, an over/undervoltage, or a fan failure condition. Rev. 0 | Page 59 of 92 ADT7462 Table 33 shows that any of the four designated GPIO pins can be used to set or reset anyone of the two EDO outputs. 2 Using this functionality, it is possible to have the ADT7462 drive LEDs or signals based on rules. For example, if a GPIO1 (power fail), a GPIO2 (overcurrent), or an overtemperature condition occurs, EDO1 (power supply fault LED) can be latched. This does not require software handling and makes the part more autonomous. the registers are re-initialized to the default values. For example, limit registers are not all restored to the default values. This can be useful if the user needs to reset the part but does not want to completely reprogram the device. The Register Map shows which registers are reset. Locked registers are not restored to default values by a hardware reset. Note that if two ADT7462 devices are used in one system, the RESET pins should not be connected together between devices. Doing so would cause one device to reset the other on a poweron reset. OTHER DIGITAL INPUTS The ADT7462 contains other specific digital inputs that can be found on PC motherboards. These inputs can be monitored and configured for actions to occur on their assertion. Software Reset The ADT7462 can be reset in software by setting Bit 7 of Configuration Register 0 (0x00). The code 0x6D must be written to Register 0x7B before setting the software reset bit. This register is cleared to the power-on default after the software reset. Note that not all registers are restored to their default values on a reset. The same registers are reset by a hardware and software reset. The Register Map section shows a complete reference of registers that are reset. VR_HOT inputs Pin 25 and Pin 26 can be configured as VR_HOT inputs. These are specific digital signals from the CPU voltage regulator that indicate an overtemperature. On assertion of these inputs, the relevant status bits are set in the Thermal Status Register 2 (Host Register 0xB9 or BMC Register 0xC1). Assertion of these inputs can also be used to boost the fans to full speed, thus providing emergency cooling in the event of VR overtemperature. This is set using Bit 3 and Bit 4 of Configuration Register 2 (0x02). There is also an associated mask bit in Register 0x31 to mask the assertion of these inputs from the ALERT output. CHASSIS INTRUSION INPUT The chassis intrusion input is an active high input intended for detection and signaling of unauthorized tampering with the system. When this input goes high, the event is latched in Bit 7 of the digital status register (0xBE), and an interrupt is generated. The bit remains set until cleared by writing a 1 to CI reset, Bit 5 of Configuration Register 3 (0x03). The CI reset bit itself is cleared by writing a 0 to it. The CI circuit is powered from the VBATT voltage channel. Pin 26 must be configured to monitor VBATT and a battery connected in order to monitor CI events. CI monitoring is disabled if the measured VBATT value (0x93) is less than the lower voltage limit (0x75) of Pin 26. The CI input detects chassis intrusion events even when the ADT7462 is powered off (provided battery voltage is applied to VBATT) but does not immediately generate an interrupt. Once a chassis intrusion event is detected and latched, an interrupt is generated when the system is powered on. The actual detection of chassis intrusion is performed by an external circuit that detects, for example, when the cover has been removed. A wide variety of techniques can be used for the detection. For example: • • • • A microswitch that opens or closes when the cover is removed A reed switch operated by a magnet affixed to the cover A hall-effect switch operated by a magnet affixed to the cover A phototransistor that detects light when the cover is removed. SCSI_TERM inputs Pin 16 and Pin 20 can be configured as SCSI_TERM inputs. An assertion on the SCSI_TERM is recorded in Bit 4 and Bit 5 of Digital Status Register 1 (Host Register 0xBE or BMC register 0xC6). There is also an associated mask bit in Register 0x35 to mask the assertion of these inputs from the ALERT output. RESET I/O The ADT7462 includes an active low reset pin (Pin 14). The RESET pin can be both a reset input and output. RESET monitors the VCC input to the ADT7462. At power-up, RESET is asserted (pulled low) until 180 ms after the power supply has risen above the supply threshold. A power-on reset initializes all registers to the default values. VCC 1V RESET 05569-075 180ms Figure 84. Operation of RESET Output on Power-Up The RESET pin can also function as a reset input. Pulling this pin low externally resets the ADT7462. The user should wait at least 180 ms after power-up before doing a hardware reset. The reset pulse width should be greater than 0.8 ms to ensure that a reset is registered. A hardware reset differs from a power-on reset in that not all of Rev. 0 | Page 60 of 92 ADT7462 POWER-UP SEQUENCE The power-up sequence of the ADT7462 is as follows: 1. The temperature of the thermal diode connected to Pin 17 and Pin 18 (only dedicated thermal diode channel) is monitored immediately on power-up of the ADT7462. Ideally, the hottest zone should be connected to this channel so protection is provided immediately on power-up. VCCP1 is also monitored immediately on power-up. VCCP is typically connected to a main power rail. The switching on of the VCCP rail gates the fan’s quiet start-up counter. VBATT is monitored immediately on power-up before the setup complete bit (Register 0x01, Bit 5) is set. The chassis intrusion circuit (CI) is powered from VBATT. If the measured VBATT reading is lower than the lower limit (default = 0x80), the CI circuit is turned off. PWM1, PWM3, and PWM4 are not on dedicated pins. Because these pins are shared with inputs, they are allowed to float high on power-up. This means that if a fan is connected to these pins, it spins at full speed on power-up. PWM2 is switched off by default (because this is a dedicated pin). If no SMBus communication takes place within 4.6 seconds of the VCCP rail switching on, this PWM drive is driven to full speed. If SMBus communication does take place, this pin behaves as programmed. 6. No temperature or voltage (other than VCCP1 and Diode 2 and VBATT) are monitored until the setup complete bit (Bit 5) is set in Configuration Register 1 (0x01). This allows the user to program the ADT7462 as required before monitoring of all channels is enabled, thereby not generating false ALERTs. The setup complete bit should not be set until the device is fully configured for the desired monitoring functions. 2. The following steps describe how to set up the ADT7462: 1. 2. 3. Power up the device. Choose the best-suited easy configuration option for the application, changing pin functions as required. Program all appropriate limits for monitored inputs. Program device parameters, fan control parameters, mask bits, and anything else required for the application. Set the complete bit. Do not set the complete bit until the device is fully set up. 3. 4. 4. 5. Rev. 0 | Page 61 of 92 ADT7462 XOR TREE TEST The ADT7462 includes an XOR tree test mode. This mode is useful for in-circuit test equipment at board-level testing. By applying stimulus to the pins included in the XOR test, it is possible to detect opens or shorts on the system board. Figure 85 shows the signals exercised in the XOR tree test. The XOR tree test is invoked by setting Bit 6 (XOR tree test) of Configuration Register 3 (0x03). Note that the digital inputs must be selected on multifunctional pins for the XOR tree test mode. Pin 13 is the open drain output of the XOR tree test. PIN 1 PIN 2 PIN 25 PIN 3 PIN 26 PIN 4 PIN 27 PIN 7 PIN 28 PIN 8 PIN 29 PIN 16 PIN 31 PIN 13 PIN 20 PIN 32 PIN 21 05569-076 PIN 22 Figure 85. XOR Tree Test Rev. 0 | Page 62 of 92 ADT7462 REGISTER MAP Table 34. Register Map Addr 0x00 0x01 0x02 0x03 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x16 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x21 0x22 0x23 0x24 0x25 0x26 0x28 0x29 0x2A 0x2B 0x2C 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x3D 0x3E 0x3F Description Configuration 0 Configuration 1 Configuration 2 Configuration 3 TACH Enable TACH Configuration GPIO1_Bhvr GPIO2_Bhvr TMIN_Cal1 TMIN_Cal2 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R Bit 7 SW Reset RDY #FP Res T8E Res D4 D8 Res Res TW2 Res Res VID Pin 8 Pin 24 Pin 28 Res CS Pin 22 Res RR2 RR4 Fan 8 F8P Fan 8 Bhvr Bhvr Bhvr Bhvr F2 F4 7 7 7 7 7 R3D VRD2 P23 +1.5V1 (ICH) Fan 8 CI GPIO8 Volt Volt 7 7 7 Bit 6 VID Lock #FP XOR T7E Res P4 P8 Res Ver TW2 Res Res D1 Pin 13 Pin 24 Pin 28 Res CS Pin 21 Res RR2 RR4 Fan 7 F7P Fan 7 Bhvr Bhvr Bhvr Bhvr F2 F4 6 6 6 6 6 R2D VRD1 +5V +1.5V2 (3GIO) Fan 7 VID GPIO7 Temp Temp 6 6 6 Bit 5 #Byte SC FMS CI_R T6E Res D3 D7 P2R2 CYR2 TW2 Res Res D3 Pin 15 Pin 25 Pin 29 Res CS Pin 19 Pin 29 RR2 RR4 Fan 6 F6P Fan 6 Bhvr Bhvr Bhvr Bhvr F2 F4 5 5 5 5 5 R1D T2S P19 P26 Fan 6 SCSI2 GPIO6 Fan Fan 5 5 5 Bit 4 #Byte DFS VB2 TT T5E Res P3 P7 P2R2 CYR2 TW1 R3 R3 Pin 1 Pin 19 Pin 25 Pin 29 Op5 CS Pin 15 Pin 28 RR1 RR3 Fan 5 F5P Fan 5 Inv Inv Inv Inv F1 F3 4 4 4 4 4 R3 T2A P15 P25 Fan 5 SCSI1 GPIO5 Res Res 4 4 4 Bit 3 #Byte ALERT VB1 VID_T T4E DC 4/8 D2 D6 P1R2 CYR2 TW1 R2 R2 Pin 2 Pin 21 Pin 26 Pin 31 Op4 CS Pin 13 Res RR1 RR3 Fan 4 F4P Fan 4 Slow Slow Slow Slow F1 F3 3 3 3 3 3 R2 T2% +3.3V P24 Fan 4 Bit 2 #Byte Res PWM SDA T3E DC 3/7 P2 P6 P1R1 CYR1 TW1 R1 R1 Pin 3 Pin 22 Pin 26 Pin 32 Op3 SC Pin 8 Pin 25 RR1 RR3 Fan 3 F3P Fan 3 Spin Spin Spin Spin F1 F3 2 2 2 2 2 R1 T1S +12V3 Res Fan 3 Res GPIO3 GPIO3 GPIO3 2 2 2 Bit 1 #Byte Res Res SCL T2E DC 2/6 D1 D5 R2 CYR1 B2 Local Local Pin 4 Pin 23 Pin 27 Res Op2 EDO2 Pin 7 Pin 24 En2 En4 Fan 2 F2P Fan 2 Spin Spin Spin Spin Min 2 Min 4 1 1 1 1 1 Local T1A +12V2 Res Fan 2 Res GPIO2 GPIO2 GPIO2 1 1 1 Bit 0 #Byte Mon Fast GPIO T1E DC 1/5 P1 P5 R1 CYR1 B1 T1TE T2E Pin 7 Pin 23 Res Res Op1 EDO1 Pin 5 Pin 23 En1 En3 Fan 1 F1P Fan 1 Spin Spin Spin Spin Min 1 Min 3 0 0 0 0 0 Res T1% +12V1 Res Fan 1 Res GPIO1 GPIO1 GPIO1 0 0 0 Default 0x20 0x81 0x40 0x00 0x00 0xE0 0x00 0x00 0x00 0x40 0x00 0x00 0x00 0x7F 0xCE 0x42 0xFC 0x01 0x00 0xFF 0x37 0x00 0x00 0x00 0x00 0x00 0x11 0x31 0x51 0x71 0x90 0x90 0x80 0x80 0x80 0x80 0xC0 0x00 0xC0 0x00 0x00 0x00 0x38 0x00 0x00 0x00 0x62 0x41 0x04 SW Reset Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No Lockable Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No N/A N/A N/A THERM Configuration Conf_THERM1 Conf_THERM2 Pin Config 1 Pin Config 2 Pin Config 3 Pin Config 4 Easy Config EDO Enable Attenuators 1 En Attenuators 2 En Enhance Acoustics 1 Enhance Acoustics 2 Fan Free Wheel Test Fans Present Fan Free Wheel Test En PWM1 Config PWM2 Config PWM3 Config PWM4 Config PWM1, PWM2 Freq PWM3, PWM4 Freq PWM1 Min PWM2 Min PWM3 Min PWM4 Min PWM1 to PWM4 Max Thermal Mask 1 Thermal Mask 2 Voltage Mask 1 Voltage Mask 2 Fan Mask Digital Mask GPIO Mask EDO Mask 1 EDO Mask 2 Device ID Company ID Revision Number FAN2MAX GPIO4 GPIO4 GPIO4 3 3 3 Rev. 0 | Page 63 of 92 ADT7462 Addr 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F 0x60 0x61 0x62 0x63 0x64 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 Description Local Low Temp Limit Remote 1/Pin +15V Low Remote 2 Low limit Remote 3/ Pin 19 Low Local High Remote1/ Pin15 High Remote 2 High Limit Remote 3/ Pin 19 High Local THERM1/ +1.5V2 (3GIO) High Remote 1 THERM1 Limit Remote 2 THERM1 Limit Remote 3 THERM1 Limit Local THERM2/ +1.5V1 (ICH) High Remote 1 THERM2 Limit Remote 2 THERM2 Limit Remote 3 THERM2 Limit Local/Remote1 Hyst Remote 2/ Remote 3 Hyst Local Offset Remote 1 Offset Remote 2 Offset Remote 3 Offset Remote 1 Operating Point Remote 2 Operating Point Local TMIN Remote 1 TMIN Remote 2 TMIN Remote 3 TMIN Local TRANGE/Hys Remote 1 TRANGE/Hys Remote 2 TRANGE/Hys Remote 3 TRANGE/Hys Operating Point Hyst +3.3V High Limit Pin 23 Voltage High Limit Pin 24 Voltage High Limit Pin 25 Voltage High Limit Pin 26 Voltage High Limit +12V1 Low Limit +12V2 Low Limit +12V3 Low Limit +3.3V Low Limit +5V Low Limit Pin 23 Voltage Low Limit R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 LH RH2 7 7 7 7 7 7 7 7 7 7 Range Range Range Range Hys 7 7 7 7 7 7 7 7 7 7 7 Bit 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 LH RH2 6 6 6 6 6 6 6 6 6 6 Range Range Range Range Hys 6 6 6 6 6 6 6 6 6 6 6 Bit 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 LH RH2 5 5 5 5 5 5 5 5 5 5 Range Range Range Range Hys 5 5 5 5 5 5 5 5 5 5 5 Bit 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 LH RH2 4 4 4 4 4 4 4 4 4 4 Range Range Range Range Hys 4 4 4 4 4 4 4 4 4 4 4 Bit 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 R1H RH3 3 3 3 3 3 3 3 3 3 3 Hys Hys Hys Hys Res 3 3 3 3 3 3 3 3 3 3 3 Bit 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 R1H RH3 2 2 2 2 2 2 2 2 2 2 Hys Hys Hys Hys Res 2 2 2 2 2 2 2 2 2 2 2 Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R1H RH3 1 1 1 1 1 1 1 1 1 1 Hys Hys Hys Hys Res 1 1 1 1 1 1 1 1 1 1 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R1H RH3 0 0 0 0 0 0 0 0 0 0 Hys Hys Hys Hys Res 0 0 0 0 0 0 0 0 0 0 0 Default 0x40 0x40 0x40 0x40 0x95 0x95 0x95 0x95 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 0x44 0x44 0x00 0x00 0x00 0x00 0xA4 0xA4 0x9A 0x9A 0x9A 0x9A 0xC4 0xC4 0xC4 0xC4 0x40 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x20 SW Reset No No No No No No No No No No No No No No No No No No No No No No Yes Yes No Yes Yes No Yes Yes Yes Yes Yes No No No No No No No No No No No Lockable No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No Rev. 0 | Page 64 of 92 ADT7462 Addr 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x80 0x81 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA0 0xA1 0xA2 0xA3 0xA4 Description Pin 24 Voltage Low Limit Pin 25 Voltage Low Limit Pin 26 Voltage Low Limit +1.5V1 (ICH) Low Limit +1.5V2 (3GIO) Low Limit TACH1 Limit/VID TACH2 Limit TACH3 Limit TACH4 Limit TACH5/+12V1 High Limit TACH6/+12V2 High Limit TACH7/+5V High Limit TACH8/+12V3 High Limit R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Bit 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 Bit 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 Bit 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 Bit 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 Bit 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 Bit 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Default 0x00 0x00 0x80 0x00 0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF N/A N/A 0xFF 0xFF 0xFF SW Reset No No No No No No No No Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No Lockable No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No No No No No No No No No No No No No No No No THERM1 Timer Limit THERM2 Timer Limit Local Temp Value, LSBs Local Temp Value, MSBs Remote 1 Temp, LSBs Remote 1 Temp, MSBs, Pin 15 Voltage Remote 2 Temp, LSBs Remote 2 Temp, MSBs Remote 3 Temp, LSBs Remote 3 Temp, MSBs, Pin 19 Voltage Pin 23 Voltage Pin 24 Voltage Pin 25 Voltage Pin 26 Voltage +1.5V1 (ICH) Voltage +1.5V2 (3GIO) Voltage +3.3V Voltage VID Value TACH1 Value, LSBs TACH1 Value, MSBs TACH2 Value, LSBs TACH2 Value, MSBs TACH3 Value, LSBs TACH3 Value, MSBs TACH4 Value, LSBs TACH4 Value, MSBs Unused Unused TACH5 Value, LSB TACH5 MSB/+12V1 Voltage TACH6 Value, LSB Rev. 0 | Page 65 of 92 ADT7462 Addr 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF 0xC0 0xC1 0xC3 0xC4 0xC5 0xC6 Description TACH6 MSB/+12V2 Voltage TACH7 Value, LSB TACH7 MSB/+5V Voltage TACH8 Value, LSB TACH8 MSB/+12V3 Voltage PWM1 Duty Cycle PWM2 Duty Cycle PWM3 Duty Cycle PWM4 Duty Cycle R/W R R R R R R/W R/W R/W R/W R R R R R R R R R R/W R R R R R R Bit 7 7 7 7 7 7 7 7 7 7 7 7 R3D VR2 R3T2 Pin 23 +1.5V1 (ICH) Fan 8 CI GPIO8 R3D VR2 Pin 23 +1.5V1 (ICH) Fan 8 CI Bit 6 6 6 6 6 6 6 6 6 6 6 6 R2D VR1 R2T2 +5V +1.5V2 (3GIO) Fan 7 VID GPIO7 R2D VR1 5V +1.5V2 (3GIO) Fan 7 VID Bit 5 5 5 5 5 5 5 5 5 5 5 5 R1D T2S R1T2 Pin 19 Pin 26 Fan 6 SCSI2 GPIO6 R1D T2S Pin 19 Pin 26 Fan 6 SCSI2 Bit 4 4 4 4 4 4 4 4 4 4 4 4 R3 T2A LT2 Pin 15 Pin 25 Fan 5 SCSI1 GPIO5 R3 T2A Pin 15 Pin 25 Fan 5 SCSI1 Bit 3 3 3 3 3 3 3 3 3 3 3 3 R2 T2% R3T1 +3.3V Pin 24 Fan 4 Fan 2 Max GPIO4 R2 T2% +3.3V Pin 24 Fan 4 Fan 2 Max Bit 2 2 2 2 2 2 2 2 2 2 2 2 R1 T1S R2T1 +12V3 Res Fan 3 Res GPIO3 R1 T1S +12V3 Res Fan 3 Res Bit 1 1 1 1 1 1 1 1 1 1 1 1 Local T1A R1T1 +12V2 Res Fan 2 Res GPIO2 Local T1A +12V2 Res Fan 2 Res Bit 0 0 0 0 0 0 0 0 0 0 0 0 Res T1% LT1 +12V1 Res Fan 1 Res GPIO1 Res T1% +12V1 Res Fan 1 Res Default 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x0 SW Reset No No No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Lockable No No No No No No No No No No No No No No No No No No No No No No No No No THERM1 % On-Time THERM2 % On-Time Thermal Status 1, Host Thermal Status 2, Host Thermal Status 3, Host Voltage Status 1, Host Voltage Status 2, Host Fan Status, Host Digital Status, Host GPIO Status, Host Thermal Status 1, BMC Thermal Status 2, BMC Voltage Status 1, BMC Voltage Status 2, BMC Fan Status, BMC Digital Status, BMC Rev. 0 | Page 66 of 92 ADT7462 Table 35. Register 0x00 Configuration Register 0 1 Bit [5:0] 6 7 1 Name #Bytes Block Read VID Decoder SW Reset R/W R/W R/W R/W Description These bits set the number of registers to be read in a Block Read. Default = 0x20. 0 = VR10 Decoding Spec; 1 = VR11 Decoding Spec. Default = 0. Setting this bit to 1 restores all unlocked registers to their default values. Self clearing. Write 0x6D to register 0x7B before setting this bit to get a software reset. Default = 0. POR = 0x20, Lock = Y, SW Reset = Y. Table 36. Register 0x01 Configuration Register 1 1 Bit 0 1 2 3 4 5 6 Name Monitor Reserved Reserved ALERT Mode Fast Spin-Up Disable Setup Complete Lock R/W R/W R/W R/W R/W R/W R/W Write Once R Description Setting this bit to 1 enables temperature and voltage measurements. When this bit is set to 0, temperature and voltage measurements are disabled. Default = 1. Reserved. Default = 0. Reserved. Default = 0. This bit sets the ALERT mode in the ADT7462. 1 = comparator mode, 0 SMBALERT mode (default). Setting this bit to 1 disables the fast spin-up (for 2 TACH pulses) for the fan. Instead, the fans spin up for the programmed fan start-up timeout. Default = 0. Setting this bit to 1 tells the ADT7462 that setup is complete and that monitoring of all selected channels should begin. Default = 0. Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become read only and cannot be modified until the ADT7462 is powered down and powered up again. This prevents rogue programs, such as viruses, from modifying critical system limit settings. Lockable. This bit is set to 1 to indicate that the ADT7462 is fully powered up and ready to start monitoring. 7 1 RDY POR = 0x81, Lock = Y, SW Reset = Y. Table 37. Register 0x02 Configuration Register 2 1 Bit 0 1 2 3 4 5 [7:6] Name Fast Reserved PWM Mode VRD1 Boost VRD2 Boost Fans Full Speed #TACH Pulses R/W R/W R/W R/W R/W R/W R/W R/W Description In low frequency, PWM fan speed measurements are made once a second. Setting this bit to 1 increases the frequency of the fan speed measurements to 4 times a second. Default = 0. Reserved. Default = 0. This bit sets the PWM frequency mode. 0 = low frequency PWM; frequency programmable between 11 Hz and 88.2 Hz. Default = 35.3 Hz. 1 = high frequency mode, 22.5 kHz. Setting this bit to 0 causes the fans to go to full speed on assertion of VRD1. Default = 0. When this bit is set to 1, VRD1 assertions have no effect on the fan speed. Setting this bit to 0 causes the fans to go to full speed on assertion of VRD2. Default = 0. When this bit is set to 1, VRD2 assertions have no effect on the fan speed. Setting this bit to 1 drives the fans to full speed. Default = 0. In low frequency mode, the ADT7462 must pulse stretch to get an accurate fan speed measurement. The speed is always measured between the 2nd rising edge and one × TACH pulses later. This bit determines the last TACH pulse. Therefore, if the fan speed is to be measured between the second and fourth TACH pulse, 01 is written to these bits. x = 1 = 00 x = 2 = 01 (default) x = 3 = 10 x = 4 = 11 1 POR = 0x40, Lock = Y, SW Reset = Y. Rev. 0 | Page 67 of 92 ADT7462 Table 38. Register 0x03 Configuration Register 3 1 Bit 0 1 2 3 4 5 6 7 1 Name GPIO_En SCL_Timeout SDA_Timeout VID_Threshold THERM _Threshold CI Reset XOR Tree V_Core_Low R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting this bit to 1 enables the GPIOs. Default = 0. 1 = SCL Timeout Enabled. 0 = SCL timeout disabled = default. 1 = SDA Timeout Enabled. 0 = SDA timeout disabled = default. This bit sets the digital threshold for the VID’s digital inputs. 0 =default. 1 = low thresholds selected = 0.65 V. This bit sets the digital threshold for the THERM’s digital inputs. 0 =default. 1 = low thresholds selected = 2/3 VCCP1 (Pin 23). Setting this bit to 1 resets the chassis intrusion circuit. This bit clears itself. Default = 0. Setting this bit to 1 enables the XOR tree test. Default = 0. Setting this bit to 1 enables V_core_low. Default = 0. POR = 0x00, Lock = Y, SW Reset = Y. Table 39. Register 0x07 TACH Enable Register 1 Bit 0 1 2 3 4 5 6 7 1 Name TACH1 TACH2 TACH3 TACH4 TACH5 TACH6 TACH7 TACH8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting this bit to 1 enables the TACH1 measurement. Default = 0. Setting this bit to 1 enables the TACH2 measurement. Default = 0. Setting this bit to 1 enables the TACH3 measurement. Default = 0. Setting this bit to 1 enables the TACH4 measurement. Default = 0. Setting this bit to 1 enables the TACH5 measurement. Default = 0. Setting this bit to 1 enables the TACH6 measurement. Default = 0. Setting this bit to 1 enables the TACH7 measurement. Default = 0. Setting this bit to 1 enables the TACH8 measurement. Default = 0. POR = 0x00, Lock = Y, SW Reset = Y. Table 40. Register 0x08 TACH Configuration Register 1 Bit 0 1 2 3 [4:7] 1 Name DC1/5 DC2/6 DC3/7 DC4/8 RES R/W R/W R/W R/W R/W R Description Setting this bit to 1 enables continuous measurements on TACH1 and TACH5 in low frequency PWM mode. Default = 0. Setting this bit to 1 enables continuous measurements on TACH2 and TACH6 in low frequency PWM mode. Default = 0. Setting this bit to 1 enables continuous measurements on TACH3 and TACH7 in low frequency PWM mode. Default = 0. Setting this bit to 1 enables continuous measurements on TACH4 and TACH8 in low frequency PWM mode. Default = 0. Reserved for future use. POR = 0xE0, Lock = Y, SW Reset = Y. Table 41. Register 0x09 GPIO Configuration Register 1 1 Bit 0 1 2 3 4 5 6 7 1 Name GPIO1_P GPIO1_D GPIO2_P GPIO2_D GPIO3_P GPIO3_D GPIO4_P GPIO4_D R/W R/W R/W R/W R/W R/W R/W R/W R/W Description This bit sets the polarity of GPIO1. 0 = default = active low. 1= active high. This bit sets the direction of GPIO1. 0 = default = input. 1= output. This bit sets the polarity of GPIO2. 0 = default = active low. 1= active high. This bit sets the direction of GPIO2. 0 = default = input. 1= output. This bit sets the polarity of GPIO3. 0 = default = active low. 1= active high. This bit sets the direction of GPIO3. 0 = default = input. 1= output. This bit sets the polarity of GPIO4. 0 = default = active low. 1= active high. This bit sets the direction of GPIO4. 0 = default = input. 1= output. POR = 0x00, Lock = Y, SW Reset = Y. Rev. 0 | Page 68 of 92 ADT7462 Table 42. Register 0x0A GPIO Configuration Register 2 1 Bit 0 1 2 3 4 5 6 7 1 Name GPIO5_P GPIO5_D GPIO6_P GPIO6_D GPIO7_P GPIO7_D GPIO8_P GPIO8_D R/W R/W R/W R/W R/W R/W R/W R/W R/W Description This bit sets the polarity of GPIO5. 0 = default = active low. 1= active high. This bits sets the direction of GPIO5. 0 = default = input. 1= output. This bit sets the polarity of GPIO6. 0 = default = active low. 1= active high. This bits sets the direction of GPIO6. 0 = default = input. 1= output. This bit sets the polarity of GPIO7. 0 = default = active low. 1= active high. This bits sets the direction of GPIO7. 0 = default = input. 1= output. This bit sets the polarity of GPIO8. 0 = default = active low. 1= active high. This bits sets the direction of GPIO8. 0 = default = input. 1= output. POR = 0x00, Lock = Y, SW Reset = Y. Table 43. Register 0x0B Dynamic TMIN Control Register 1 1 Bit 0 1 2 Name Remote 1 En Remote 2 En PH1_TR1 R/W R/W R/W R/W Description Setting this bit to 1 enables dynamic TMIN control for the Remote 1 channel. Default = 0. Setting this bit to 1 enables dynamic TMIN control for the Remote 2 channel. Default = 0. PH1_TR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if THERM1 gets asserted externally. This happens only if the current temperature is less than the value in the operating point register. The operating point contains the temperature at which THERM1 is asserted. PH1_TR1 = 0 (default) ignores any THERM1 assertions on the THERM1 pin. The Remote 1 operating point register reflects its programmed value. PH1_RT2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if THERM1 gets asserted externally. This happens only if the current temperature is less than the value in the operating point register. The operating point contains the temperature at which THERM1 is asserted. PH1_TR1 = 0 (default) ignores any THERM1 assertions on the THERM1 pin. The Remote 2 Operating Point Register reflects its programmed value. PH2_TR1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if THERM2 gets asserted externally. This happens only if the current temperature is less than the value in the operating point register. The operating point contains the temperature at which THERM2 is asserted. PH2_TR1 = 0 (default) ignores any THERM2 assertions on the THERM2 pin. The Remote 1 operating point register reflects its programmed value. PH2_RT2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if THERM2 gets asserted externally. This happens only if the current temperature is less than the value in the operating point register. The operating point contains the temperature at which THERM2 is asserted. PH2_RT2 = 0 (default) ignores any THERM2 assertions on the THERM2 pin. The Remote 2 operating point register reflects its programmed value. Reserved for future use. 3 PH1_TR2 R/W 4 PH2_TR1 R/W 5 PH2_RT2 R/W [7:6] 1 Reserved R/W POR = 0x00, Lock = Y, SW Reset = Y. Rev. 0 | Page 69 of 92 ADT7462 Table 44. Register 0x0C Dynamic TMIN Control Register 2 1 Bit [2:0] Name CYR1 R/W R/W Description Three-bit Remote 1 cycle value. These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the Remote 1 temperature channel, in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. Decrease cycle Increase cycle 8 cycles (1 sec) 16 cycles (2 sec) 16 cycles (2 sec) 32 cycles (4 sec) 32 cycles (4 sec) 64 cycles (8 sec) 64 cycles (8 sec) 128 cycles (16 sec) 128 cycles (16 sec) 256 cycles (32 sec) 256 cycles (32 sec) 512 cycles (64 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 1024 cycles (128 sec) 2048 cycles (256 sec) Three-bit Remote 2 cycle value. These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the Remote 2 temperature channel, in terms of number of monitoring cycles. The system has associated thermal time constants that need to be found to optimize the response of fans and the control loop. Decrease cycle Increase Cycle 8 cycles (1 sec) 16 cycles (2 sec) 16 cycles (2 sec) 32 cycles (4 sec) 32 cycles (4 sec) 64 cycles (8 sec) 64 cycles (8 sec) 128 cycles (32 sec) 128 cycles (16 sec) 256 cycles (32 sec) 256 cycles (32 sec) 1024 cycles (128 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 1024 cycles (128 sec) 2048 cycles (256 sec) This bit allows the user to select between two control loops. 0 makes the control loop backwards-compatible with ADT7463 and ADT7468. 1 = ADT7462 control loop (default). Reserved for future use. [5:3] CYR2 Bits 000 001 010 011 100 101 110 111 R/W 6 7 1 Control Loop Select Reserved Bits 000 001 010 011 100 101 110 111 R/W R POR = 0x40, Lock = Y, SW Reset = Y. Rev. 0 | Page 70 of 92 ADT7462 Table 45. Register 0x0D THERM Configuration Register 1 Bit 0 Name Boost 1 R/W R/W Description Setting this bit to 0 causes the fans to go to full speed on assertion of THERM1 as an output. Setting this bit to 1 means that the fan speed is not affected when the THERM1 temperature limit is exceeded. Default = 0. Setting this bit to 0 causes the fans to go to full speed on assertion of THERM2 as an output. Setting this bit to 1 means that the fan speed is not affected when the THERM2 temperature limit is exceeded. Default = 0. These bits set the timer window for measuring THERM1 assertions. 000 = 0.25 sec 001 = 0.5 sec 010 = 1 sec 011 = 2 sec 100 = 4 sec 101 = 8 sec 110 = 8 sec 111 = 8 sec [7:5] THERM2 Timer Window R/W These bits set the timer window for measuring THERM2 assertions. 000 = 0.25 sec 001 = 0.5 sec 010 = 1 sec 011 = 2 sec 100 = 4 sec 101 = 8 sec 110 = 8 sec 111 = 8 sec 1 1 Boost 2 R/W [4:2] THERM1 Timer Window R/W POR = 0x00, Lock = Y, SW Reset = Y. Table 46. Register 0x0E THERM1 Configuration Register 1 Bit 0 1 2 3 4 [7:5] 1 Name Enable THERM1 Timer THERM1_Local THERM1_Remote 1 THERM1_Remote 2 THERM1_Remote 3 Reserved R/W R/W R/W R/W R/W R/W R Description Enables the THERM1 timer circuit. Default = 0. Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the local temperature exceeds the Local THERM1 temperature limit. Default = 0. Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the Remote 1 temperature exceeds the Remote 1 THERM1 temperature Limit. Default = 0. Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the Remote 2 temperature exceeds the Remote 2 THERM1 temperature Limit. Default = 0. Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the Remote 3 temperature exceeds the Remote 3 THERM1 temperature limit. Default = 0. Reserved for future use. POR = 0x00, Lock = Y, SW Reset = Y. Rev. 0 | Page 71 of 92 ADT7462 Table 47. Register 0x0F THERM2 Configuration Register 1 Bit 0 1 2 3 4 [7:5] 1 Name Enable THERM2 Timer THERM2_Local THERM2_Remote 1 THERM2_Remote 2 THERM2_Remote 3 Reserved R/W R/W R/W R/W R/W R/W R Description Enables the THERM2 timer circuit. Default = 0 Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the local temperature exceeds the local THERM2 temperature limit. Default = 0. Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the Remote 1 temperature exceeds the Remote 1 THERM2 temperature limit. Default = 0. Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the Remote 2 temperature exceeds the Remote 2 THERM2 temperature limit. Default = 0. Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the Remote 3 temperature exceeds the Remote 3 THERM2 temperature limit. Default = 0. Reserved for future use. POR = 0x00, Lock = Y, SW Reset = Y. Table 48. Register 0x10 Pin Configuration Register 1 1 Bit 0 1 2 3 4 5 6 7 1 Name Pin 7 Pin 4 Pin 3 Pin 2 Pin 1 Diode 3 Diode 1 VIDs R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 0 = +12V1, 1 = TACH5 input. Default =1. 0 = GPIO4; 1= TACH4 input (that is if the VIDs are not selected). Default = 1. 0 = GPIO3; 1= TACH3 input (that is if the VIDs are not selected). Default = 1. 0 = GPIO2; 1= TACH2 input (that is if the VIDs are not selected). Default = 1. 0 = GPIO1; 1= TACH1 input (that is if the VIDs are not selected). Default = 1. 1 enables the D3+ and D3− inputs on Pin 19 and Pin 20. 0 enables the voltage measurement input and SCSI_Term input. Default = 1. 1 enables the D1+ and D1− inputs on Pin 15 and Pin 16. 0 enables the voltage measurement input and SCSI_Term input. Default = 1. Setting this bit to 1 enables the VIDs on Pin 1 to Pin 4, Pin 28, Pin 31, and Pin 32. Default = 0. POR = 0x7F, Lock = Y, SW Reset = Y. Table 49. Register 0x11 Pin Configuration Register 2 1 Bit [1:0] Name Pin 23 R/W R/W Description 00 = VCCP1 selected. 01 = +2.5V. 10 = +1.8V (default). 11 = +1.5V. 0 = +12V3; 1 = TACH8. Default = 1. 0 = +5V; 1 = TACH7. Default = 1. 0 = 1.25V; 1 = +0.9V (that is, if RT3 is not selected). Default = 0. 0 = +2.5V, 1 = +1.8V (that is, if RT1 is not selected) . Default = 0. 0 = +3.3V; 1 = PWM4. Default = 1. 0 = +12V2; 1 = TACH6. Default = 1. 2 3 4 5 6 7 1 Pin 22 Pin 21 Pin 19 Pin 15 Pin 13 Pin 8 R/W R/W R/W R/W R/W R/W POR = 0xCE, Lock = Y, SW Reset = Y. Rev. 0 | Page 72 of 92 ADT7462 Table 50. Register 0x12 Pin Configuration Register 3 1 Bit 0 1 [3:2] Name Res Pin 27 Pin 26 R/W R R/W R/W Description Reserved for future use 0 = FAN2MAX; 1 = chassis intrusion (default) 00 = VBATT selected (default) 01 = +1.2V2 (FSB_VTT) 10 = VR_Hot 2 11 = VR_Hot 2 00 = +3.3V selected (default) 01 = +1.2V1 (GBIT) 10 = VR_Hot 1 11 = VR_Hot 1 00 = VCCP2 selected 01 = +2.5V (default) 10 = +1.8V 11 = +1.5V [5:4] Pin 25 R/W [7:6] Pin 24 R/W 1 POR = 0x42, Lock = Y, SW Reset = Y. Table 51. Register 0x13 Pin Configuration Register 4 1 Bit [1:0] 2 3 [5:4] Name RES Pin 32 Pin 31 Pin 29 (Pin 28, +1.5V Monitoring2) R/W R R/W R/W R/W Description Reserved. 0 = GPIO6; 1 = PWM2 (Pin 32 is VID 5 if VIDs are selected). Default = 1. 0 = GPIO5; 1 = PWM1 (Pin 31 is VID4 if VIDs are selected). Default = 1. 00 = GPIO8. 01 = +1.5V (measured on Pin 28). 10 = THERM2. 11 = THERM2 (default). (Pin 29 is VID6 if VIDs are selected.) [7:6] Pin 28 (Pin 29, +1.5V monitoring2) R/W 00 = GPIO7. 01 = +1.5V (measured on Pin 29). 10 = THERM1. 11 = THERM1 (default). 1 2 POR = 0xFC, Lock = Y, SW Reset = Y. +1.5V can be monitored on Pin 28 and Pin 29 only when both are configured as +1.5V inputs. This means that +1.5V is measured on both pins or on neither. +1.5V monitoring cannot be combined with another function on the other pin. For example, if Pin 29 is configured as +1.5V, then THERM1 cannot be selected on Pin 28, because they share the same selection bits. Table 52. Register 0x14 Easy Configuration Options 1 Bit 0 1 2 3 4 [7:5] 1 Name Easy Option 1 Select Easy Option 2 Select Easy Option 3 Select Easy Option 4 Select Easy Option 5 Select Reserved R/W R/W R/W R/W R/W R/W R Description Setting this bit to 1 enables Easy Option 1. Setting this bit to 1 enables Easy Option 2. Setting this bit to 1 enables Easy Option 3. Setting this bit to 1 enables Easy Option 4. Setting this bit to 1 enables Easy Option 5. Reserved for future use. POR = 0x01, Lock = Y, SW Reset = Y. Rev. 0 | Page 73 of 92 ADT7462 Table 53. Register 0x16 EDO/Single-Channel Enable 1 Bit 0 1 2 Name EDO_En1 EDO_En2 Single-Channel Mode Select Channel Select R/W R/W R/W R/W Description Enable EDO on GPIO5. Default = 0. Enable EDO on GPIO6. Default = 0. Setting this bit to 1 places the ADT7462 in single-channel mode. This means that it converts on one channel only. The channel it converts on is set using the channel select bits in this register. Default = 0. These bits are used to set the single channel that the ADT7462 measures in single-channel mode. 0000 0 = Pin 26 (default) 0000 1 = Remote 1 temperature 0001 0 = Remote 2 temperature 0001 1 = Remote 3 temperature 00100 = local temperature 0010 1 = +12V1 0011 0 = +12V2 0011 1 = +12V3 0100 0 = +3.3V 0100 1 = Pin 15 voltage 0101 0 = Pin 19 voltage 0101 1 = +5V 0110 0 = Pin 23 voltage 0110 1 = Pin 24 voltage 0111 0 = Pin 25 voltage 1000 0 = +1.5V2 (ICH) voltage 1000 1 = +1.5V1 (3GIO) voltage [7:3] R/W 1 POR = 0x00, Lock = Y, SW Reset = Y. Table 54. Register 0x18 Voltage Attenuator Configuration 1 1 Bit 0 1 2 3 4 5 6 7 1 Name Res Attenuator Pin 7 Attenuator Pin 8 Attenuator Pin 13 Attenuator Pin 15 Attenuator Pin 19 Attenuator Pin 21 Attenuator Pin 22 R/W R R/W R/W R/W R/W R/W R/W R/W Description Reserved for future use. Setting this bit to 0 removes the attenuators for Pin 7. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 8. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin13. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 15. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 19. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 21. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 22. Default = 1 = attenuators enabled. POR = 0xFF, Lock = Y, SW Reset = Y. Table 55. Register 0x19 Voltage Attenuator Configuration 2 1 Bit 0 1 2 3 4 5 [7:6] 1 Name Attenuator Pin 23 Attenuator Pin 24 Attenuator Pin 25 Unused Attenuator Pin 28 Attenuator Pin 29 Reserved R/W R/W R/W R/W R/W R/W R/W R/W Description Setting this bit to 0 removes the attenuators for Pin 23. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 24. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 25. Default = 1 = attenuators enabled. Default = 0. Setting this bit to 0 removes the attenuators for Pin 28. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 29. Default = 1 = attenuators enabled. Reserved for future use. Default = 00. POR = 0x37, Lock = Y, SW Reset = Y. Rev. 0 | Page 74 of 92 ADT7462 Table 56. Register 0x1A Enhance Acoustics Register 1 1 Bit 0 1 [4:2] Name EA1_En EA2_En Ramp Rate 1 R/W R/W R/W R/W Description Setting this bit to 1 enables the enhance acoustics mode for PWM1; 0 disables it. Default = 0. Setting this bit to 1 enables the enhance acoustics mode for PWM2; 0 disables it. Default = 0. These bits set the ramp rate for the enhance acoustics mode for PWM1. Default = 000. Time Slot Increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec These bits set the ramp rate for the enhance acoustics mode for PWM2. Default = 000. Time Slot Increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec [7:5] Ramp Rate 2 R/W 1 POR = 0x00, Lock = Y, SW Reset = Y. Table 57. Register 0x1B Enhance Acoustics Register 2 1 Bit 0 1 [4:2] Name EA3_En EA4_En Ramp Rate 3 R/W R/W R/W R/W Description Setting this bit to 1 enables the enhance acoustics mode for PWM3; 0 disables it. Default = 0. Setting this bit to 1 enables the enhance acoustics mode for PWM4; 0 disables it. Default = 0. These bits set the ramp rate for the enhance acoustics mode for PWM3. Default = 000. Time Slot Increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec These bits set the ramp rate for the enhance acoustics mode for PWM4. Default = 000. Time Slot Increase Time for 33% to 100% 000 = 1 35 sec 001 = 2 17.6 sec 010 = 3 11.8 sec 011 = 5 7 sec 100 = 8 4.4 sec 101 = 12 3 sec 110 = 24 1.6 sec 111 = 48 0.8 sec [7:5] Ramp Rate 4 R/W 1 POR = 0x00, Lock = Y, SW Reset = Y. Rev. 0 | Page 75 of 92 ADT7462 Table 58. Register 0x1C Fan Freewheeling Test 1 Bit 0 1 2 3 4 5 6 7 1 Name Test Fan 1 Test Fan 2 Test Fan 3 Test Fan 4 Test Fan 5 Test Fan 6 Test Fan 7 Test Fan 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Fan freewheeling test bit for Fan 1. This bit self clears once the test is complete. Fan freewheeling test bit for Fan 2. This bit self clears once the test is complete. Fan freewheeling test bit for Fan 3. This bit self clears once the test is complete. Fan freewheeling test bit for Fan 4. This bit self clears once the test is complete. Fan freewheeling test bit for Fan 5. This bit self clears once the test is complete. Fan freewheeling test bit for Fan 6. This bit self clears once the test is complete. Fan freewheeling test bit for Fan 7. This bit self clears once the test is complete. Fan freewheeling test bit for Fan 8. This bit self clears once the test is complete. POR = 0x00, Lock = Y, SW Reset = Y. Table 59. Register 0x1D Fans Present 1 Bit 0 1 2 3 4 5 6 7 1 Name Fan 1 Present Fan 2 Present Fan 3 Present Fan 4 Present Fan 5 Present Fan 6 Present Fan 7 Present Fan 8 Present R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Set this bit to 1 when Fan 1 is present. Set this bit to 1 when Fan 2 is present. Set this bit to 1 when Fan 3 is present. Set this bit to 1 when Fan 4 is present. Set this bit to 1 when Fan 5 is present. Set this bit to 1 when Fan 6 is present. Set this bit to 1 when Fan 7 is present. Set this bit to 1 when Fan 8 is present. POR = 0x00, Lock = Y, SW Reset = Y. Table 60. Register 0x1E Fan Freewheeling Test Enable 1 Bit 0 1 2 3 4 5 6 7 1 Name Test Fan 1 Test Fan 2 Test Fan 3 Test Fan 4 Test Fan 5 Test Fan 6 Test Fan 7 Test Fan 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting this bit to 1 enables the fan freewheeling test for Fan 1. Setting this bit to 1 enables the fan freewheeling test for Fan 2. Setting this bit to 1 enables the fan freewheeling test for Fan 3. Setting this bit to 1 enables the fan freewheeling test for Fan 4. Setting this bit to 1 enables the fan freewheeling test for Fan 5. Setting this bit to 1 enables the fan freewheeling test for Fan 6. Setting this bit to 1 enables the fan freewheeling test for Fan 7. Setting this bit to 1 enables the fan freewheeling test for Fan 8. POR = 0x00, Lock = Y, SW Reset = Y. Rev. 0 | Page 76 of 92 ADT7462 Table 61. PWM Configuration Registers 1 Register Address 0x21 0x22 0x23 0x24 Bit [2:0] R/W Description R/W PWM1 Configuration Register R/W PWM2 Configuration Register R/W PWM3 Configuration Register R/W PWM4 Configuration Register Name Spin-Up Timeout Power On Default 0x11 0x31 0x51 0x71 R/W R/W 3 4 [7:5] SLOW INV BHVR R/W R/W R/W Description These bits set the duration of the fan start-up timeout and the timeout for the fan freewheeling test. 000 = no start-up timeout 001 = 100 ms 010 = 250 ms 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 32 sec Setting this bit to 1 makes the ramp rate of the enhance acoustics mode 4 times longer. Setting this bit to 0, the PWM outputs are active high Setting this bit to 1, the PWM outputs are active low. These bits determine which temperature channel controls the fans in the automatic fan speed control loop. 000 = local temperature 001 = Remote 1 temperature 010 = Remote 2 temperature 011 = Remote 3 temperature 100 = off 101 = maximum fan speed calculated by the local and Remote 3 temperature channels. 110 = maximum fan speed calculated by all 4 channels. 111 = manual mode. 1 Lock = Y, SW Reset = Y. Rev. 0 | Page 77 of 92 ADT7462 Table 62. Register 0x25 PWM1, PWM2 Frequency 1 Bit 0 Name Min 1 R/W R/W Description When the ADT7462 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or at minimum PWM1 duty cycle when the controlling temperature is below its TMIN − hysteresis value. 0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM1 duty cycle below TMIN − hysteresis. When the ADT7462 is in automatic fan control mode, this bit defines whether PWM2 is off (0% duty cycle) or at minimum PWM2 duty cycle when the controlling temperature is below its TMIN − hysteresis value. 0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM2 duty cycle below TMIN − hysteresis. These bits set the frequency of PWM1 when configured in low frequency mode. 000 = 11 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz These bits set the frequency of PWM2 when configured in low frequency mode. 000 = 11 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz 1 Min 2 R/W [4:2] Low Freq 1 R/W [7:5] Low Freq 2 R/W 1 POR = 0x90, Lock = Y, SW Reset = Y. Table 63. Register 0x26 PWM3, PWM4 Frequency 1 Bit 0 Name Min 3 R/W R/W Description When the ADT7462 is in automatic fan control mode, this bit defines whether PWM3 is off (0% duty cycle) or at minimum PWM3 duty cycle when the controlling temperature is below its TMIN − hysteresis value. 0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM3 duty cycle below TMIN − hysteresis. When the ADT7462 is in automatic fan control mode, this bit defines whether PWM4 is off (0% duty cycle) or at minimum PWM4 duty cycle when the controlling temperature is below its TMIN − hysteresis value. 0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM4 duty cycle below TMIN − hysteresis. These bits set the frequency of PWM3 when configured in low frequency mode 000 = 11 Hz. 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz These bits set the frequency of PWM4 when configured in low frequency mode. 000 = 11 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz 1 Min 4 R/W [4:2] Low Freq 3 R/W [7:5] Low Freq 4 R/W 1 POR = 0x90, Lock = Y, SW Reset = Y. Rev. 0 | Page 78 of 92 ADT7462 Table 64. Minimum PWMx Duty Cycle 1 Register Address 0x28 0x29 0x2A 0x2B 1 R/W R/W R/W R/W R/W Description Minimum PWM1 duty cycle Minimum PWM2 duty cycle Minimum PWM3 duty cycle Minimum PWM4 duty cycle POR Default 0x80 0x80 0x80 0x80 Lock = Y, SW Reset = Y. Table 65. Register 0x2C Maximum PWM Duty Cycle 1 Bit [7:0] 1 Name Maximum PWM Duty Cycle R/W R/W Description This register sets the maximum % duty cycle output in automatic fan speed control mode for all four PWM outputs. POR = 0xC0, Lock = Y, SW Reset = Y. Table 66. Register 0x30 Thermal Mask Register 1 1 Bit 0 1 2 3 4 5 6 7 1 Name Reserved Local Temp Remote 1 Temp Remote 2 Temp Remote 3 Temp Diode 1 Error Diode 2 Error Diode 3 Error R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Reserved for future use. A 1 masks ALERTs for an out-of-limit condition on the local temperature channel. A 1 masks ALERTs for an out-of-limit condition on the Remote 1 temperature channel. A 1 masks ALERTs for an out-of-limit condition on the Remote 2 temperature channel. A 1 masks ALERTs for an out-of-limit condition on the Remote 3 temperature channel. A 1 masks ALERTs for an open or short condition on the Remote 1 channel. A 1 masks ALERTs for an open or short condition on the Remote 2 channel. A 1 masks ALERTs for an open or short condition on the Remote 3 channel. POR = 0x00, Lock = N, SW Reset = Y. Table 67. Register 0x31 Thermal Mask Register 2 1 Bit 0 1 2 3 4 5 6 7 1 Name THERM1 % THERM1 Assert THERM1 State THERM2 % THERM2 Assert THERM2 State VRD1_Assert VRD2_Assert R/W R/W R/W R/W R/W R/W R/W R/W R/W Description A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1. POR = 0xC0, Lock = N, SW Reset = Y. Rev. 0 | Page 79 of 92 ADT7462 Table 68. Register 0x32 Voltage Mask Register 1 1 Bit 0 1 2 3 4 5 6 7 1 Name +12V1 +12V2 +12V3 +3.3V Pin 15 Voltage Pin 19 Voltage +5V Pin 23 Voltage R/W R/W R/W R/W R/W R/W R/W R/W R/W Description A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. POR = 0x00, Lock = N, SW Reset = Y. Table 69. Register 0x33 Voltage Mask Register 2 1 Bit [2:0] 3 4 5 6 7 1 Name Reserved Pin 24 Voltage Pin 25 Voltage Pin 26 Voltage +1.5V2 (3GIO) +1.5V1 (ICH) R/W R/W R/W R/W R/W R/W R/W Description Reserved for future use. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. POR = 0x00, Lock = N, SW Reset = Y. Table 70. Register 0x34 Fan Mask Register 1 1 Bit 0 1 2 3 4 5 6 7 1 Name Fan 1 Fault Fan 2 Fault Fan 3 Fault Fan 4 Fault Fan 5 Fault Fan 6 Fault Fan 7 Fault Fan 8 Fault R/W R/W R/W R/W R/W R/W R/W R/W R/W Description A 1 masks ALERTS for the corresponding interrupt status bit. A 1 masks ALERTS for the corresponding interrupt status bit. A 1 masks ALERTS for the corresponding interrupt status bit. A 1 masks ALERTS for the corresponding interrupt status bit. A 1 masks ALERTS for the corresponding interrupt status bit. A 1 masks ALERTS for the corresponding interrupt status bit. A 1 masks ALERTS for the corresponding interrupt status bit. A 1 masks ALERTS for the corresponding interrupt status bit. POR = 0x00, Lock = N, SW Reset = Y. Table 71. Register 0x35 Digital Mask Register 1 1 Bit [2:0] 3 4 5 6 7 1 Name Reserved FAN2MAX SCSI_Term1 SCSI_Term2 VID Comparison Chassis Intrusion R/W R R/W R/W R/W R/W R/W Description Reserved for future use. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 1. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. A 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. POR = 0x38, Lock = N, SW Reset = Y. Rev. 0 | Page 80 of 92 ADT7462 Table 72. Register 0x36 GPIO Mask Register 1 Bit 0 1 2 3 4 5 6 7 1 Name GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. POR = 0x00, Lock = N, SW Reset = Y. Table 73. Register 0x37 EDO 1 Mask Register 1 Bit 0 1 2 3 4 5 6 7 1 Name GPIO1 GPIO2 GPIO3 GPIO4 Unused Fan Temp Volt R/W R/W R/W R/W R/W R/W R/W R/W R/W Description A 1 masks GPIO1 from causing an EDO1 assertion. A 1 masks GPIO2 from causing an EDO1 assertion. A 1 masks GPIO3 from causing an EDO1 assertion. A 1 masks GPIO4 from causing an EDO1 assertion. Unused. A 1 masks a fan fail condition from causing an EDO1 assertion. A 1 masks a THERM condition from causing an EDO1 assertion. A 1 masks a voltage exceed limit condition from causing an EDO1 assertion. POR = 0x00, Lock = N, SW Reset = Y. Table 74. Register 0x38 EDO 2 Mask Register 1 Bit 0 1 2 3 4 5 6 7 1 Name GPIO1 GPIO2 GPIO3 GPIO4 Unused Fan Temp Volt R/W R/W R/W R/W R/W R/W R/W R/W R/W Description A 1 masks GPIO1 from causing an EDO2 assertion. A 1 masks GPIO2 from causing an EDO2 assertion. A 1 masks GPIO3 from causing an EDO2 assertion. A 1 masks GPIO4 from causing an EDO2 assertion. Unused. A 1 masks a fan fail condition from causing an EDO2 assertion. A 1 masks a THERM condition from causing an EDO2 assertion. A 1 masks a voltage exceed limit condition from causing an EDO2 assertion. POR = 0x00, Lock = N, SW Reset = Y. Table 75. Register 0x3D Device ID Register 1 Bit [7:0] 1 Name Device ID R/W R Description This register contains the device ID (0x62) for the ADT7462. POR = 0x62. Table 76. Register 0x3E Company ID Register 1 Bit [7:0] 1 Name Company ID R/W R Description This register contains the company ID (0x41) for the ADT7462. POR = 0x41. Rev. 0 | Page 81 of 92 ADT7462 Table 77. Register 0x3F Revision Register 1 Bit [7:0] 1 Name Revision ID R/W R Description This register contains the revision ID (0x03) for the ADT7462. POR = 0x04. Table 78. Temperature Limit Registers 1 Register Address 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Local low temperature limit Remote 1 low temperature/Pin 15 voltage low limit Remote 2 low temperature limit Remote 3 low temperature/Pin 19 voltage low limit Local high temperature limit Remote 1 high temperature/Pin 15 voltage high limit Remote 2 high temperature limit Remote 3 high temperature/Pin 19 voltage high limit Local THERM1 temperature limit/+1.5V1 (ICH) voltage high limit Remote 1 THERM1 temperature limit Remote 2THERM1 temperature limit Remote 3 THERM1 temperature limit Local THERM2 temperature limit/+1.5V2 (3GIO) voltage high limit Remote 1 THERM2 temperature limit Remote 2 THERM2 temperature limit Remote 3 THERM2 temperature limit Lockable No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes POR Default 0x40 0x40 0x40 0x40 0x95 0x95 0x95 0x95 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 SW Reset = N. Table 79. Register 0x54 Local/Remote 1 Hysteresis 1 Bit [3:0] [7:4] Name Remote 1 Hystereis Local Hysteresis R/W R/W R/W Description These four bits set the Remote 1 THERM hysteresis value, 1 LSB = 1°C These four bits set the local THERM hysteresis value, 1 LSB = 1°C 0000 = 0°C 0001 = 1°C 0010 = 2°C 0011 = 3°C 0100 = 4°C (default) 0101 = 5°C 0110 = 6°C 0111 = 7°C 1000 = 8°C 1001 = 9°C 1010 = 10°C 1011 = 11°C 1100 = 12°C 1101 = 13°C 1110 = 14°C 1111 = 15°C 1 POR = 0x44, Lock = Y, SW Reset = N. Rev. 0 | Page 82 of 92 ADT7462 Table 80. Register 0x55 Remote 2/Remote 3 Hysteresis 1 Bit [3:0] [7:4] Name Remote 3 Hysteresis Remote 2 Hysteresis R/W R/W R/W Description These four bits set the Remote 3 THERM hysteresis value,1 LSB = 1°C These four bits set the Remote 2 THERM hysteresis value,1 LSB = 1°C 0000 = 0°C 0001 = 1°C 0010 = 2°C 0011 = 3°C 0100 = 4°C (default) 0101 = 5°C 0110 = 6°C 0111 = 7°C 1000 = 8°C 1001 = 9°C 1010 = 10°C 1011 = 11°C 1100 = 12°C 1101 = 13°C 1110 = 14°C 1111 = 15°C 1 POR = 0x44, Lock = Y, SW Reset = N. Table 81. Offset Registers 1 Register Address 0x56 0x57 0x58 0x59 1 R/W R/W R/W R/W R/W Description Local offset, resolution = 0.5°C Remote 1 offset, resolution = 0.5°C Remote 2 offset, resolution = 0.5°C Remote 3 offset, resolution = 0.5°C POR Default 0x00 0x00 0x00 0x00 Lock = Y, SW Reset = N. Table 82. Operating Point Registers 1 Register Address 0x5A 0x5B 1 R/W R/W R/W Description Remote 1 operating point Remote 2 operating point POR Default 0xA4 0xA4 Lock = N, SW Reset = Y. Table 83. Timing Registers 1 Register Address 0x5C 0x5D 0x5E 0x5F 1 R/W R/W R/W R/W R/W Description Local TMIN Remote 1 TMIN Remote 2 TMIN Remote 3 TMIN POR Default 0x9A 0x9A 0x9A 0x9A Lock = Y, SW Reset = Y. Rev. 0 | Page 83 of 92 ADT7462 Table 84. TRANGE/Hysteresis Registers 1 Register Address 0x60 0x61 0x62 R/W R/W R/W R/W Description Local TRANGE/ Hysteresis Remote TRANGE/ Hysteresis Remote TRANGE/ Hysteresis Remote TRANGE/ Hysteresis Name Hysteresis POR Default 0xC4 0xC4 0xC4 0x63 R/W 0xC4 Bit [3:0] R/W R/W [7:4] TRANGEe R/W Description These four bits set the hysteresis in the automatic fan speed control loop and in the dynamic TMIN control loop, 1 LSB = 1°C. 0000 = 0°C 0001 = 1°C 0010 = 2°C 0011 = 3°C 0100 = 4°C (default) 0101 = 5°C 0110 = 6°C 0111 = 7°C 1000 = 8°C 1001 = 9°C 1010 = 10°C 1011 = 11°C 1100 = 12°C 1101 = 13°C 1110 = 14°C 1111 = 15°C These four bits set the TRANGE value, that is, the slope or rate of change of fan speed with respect to temperature in the automatic fan speed control loop. 0000 = 2°C 0001 = 2.5°C 0010 = 3.3°C 0011 = 4°C 0100 = 5°C 0101 = 6.7°C 0110 = 8°C 0111 = 10°C 1000 = 13.3°C 1001 = 16°C 1010 = 20°C 1011 = 26.7°C 1100 = 32°C (default) 1101 = 40°C 1110 = 53.3°C 1111 = 80°C 1 Lock = Y, SW Reset = Y. Rev. 0 | Page 84 of 92 ADT7462 Table 85. Register 0x64 Operating Point Hysteresis 1 Bit [3:0] [7:4] Name Reserved Operating Point Hysteresis R/W R R/W Description Reserved for future use. These four bits set the operating point hysteresis for the dynamic TMIN control loop, 1 LSB = 1°C. 0000 = 0°C 0001 = 1°C 0010 = 2°C 0011 = 3°C 0100 = 4°C (default) 0101 = 5°C 0110 = 6°C 0111 = 7°C 1000 = 8°C 1001 = 9°C 1010 = 10°C 1011 = 11°C 1100 = 12°C 1101 = 13°C 1110 = 14°C 1111 = 15°C 1 POR = 0x40, Lock = Y, SW Reset = Y. Table 86. Voltage Limit Registers 1 Register Address 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description +3.3V high limit Pin 23 voltage high limit Pin 24 voltage high limit Pin 25 voltage high limit Pin 26 voltage high limit +12V1 voltage low limit +12V2 voltage low limit +12V3 voltage low limit +3.3V low limit +5V low limit Pin 23 voltage low limit Pin 24 voltage low limit Pin 25 voltage low limit Pin 26 voltage low limit +1.5V1 (ICH) voltage low limit +1.5V2 (3GIO) voltage low limit POR Default 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x20 0x00 0x00 0x80 0x00 0x00 Lock = N, SW Reset = N. Rev. 0 | Page 85 of 92 ADT7462 Table 87. TACH Limit Registers 1 Register Address 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description TACH1 limit/VID limit TACH2 limit TACH3 limit TACH4 limit TACH5 limit/+12V1 voltage high limit TACH6 limit/+12V2 voltage high limit TACH7 limit/+5V voltage high limit TACH8 limit/+12V3 voltage high limit POR Default 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF Lock = Y, SW Reset = N. Table 88. THERM Timer Limit 1 Register Address 0x80 0x81 1 R/W R/W R/W Description THERM1 % Limit THERM2 % Limit POR Default 0xFF 0xFF Lock = Y, SW Reset = N. Table 89. Temperature Value Registers 1 Register Address 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 1 R/W R R R R R R R R Description Bit [7:6] Local temperature value, LSBs Local temperature value, MSBs Bit [7:6] Remote 1 temperature value, LSBs Remote 1 temperature value, MSBs/Pin 15 Voltage Bit [7:6] Remote 2 temperature value, LSBs Remote 2 temperature value, MSBs Bit [7:6] Remote 3 temperature value, LSBs Remote 3 temperature value, MSBs/Pin 19 voltage Lock = N, SW Reset = N. Table 90. Voltage Value Registers 1 Register Address 0x90 0x91 0x92 0x93 0x94 0x95 0x96 1 R/W R R R R R R R Description Pin 23 voltage value Pin 24 voltage value Pin 25 voltage value Pin 26 voltage value +1.5V1 (ICH) voltage value +1.5V2 (3GIO) voltage value +3.3V voltage value Lock = N, SW Reset = N. Table 91. VID Value Register 1 Register Address 0x97 1 R/W R Description This register reports the state of the 7 VID inputs. Lock = N, SW Reset = N. Rev. 0 | Page 86 of 92 ADT7462 Table 92. TACH Value Registers 1 Register Address 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 1 R/W R R R R R R R R R R R R R R R R Description TACH1, LSB TACH1, MSB TACH2, LSB TACH2, MSB TACH3, LSB TACH3, MSB TACH4, LSB TACH4, MSB TACH5, LSB TACH5, MSB/+12V1 voltage value register TACH6, LSB TACH6, MSB/+12V2 voltage value register TACH7, LSB TACH7, MSB/+5V voltage value register TACH8, LSB TACH8, MSB/+12V3 voltage value register Lock = N, SW Reset = N. Table 93. Current PWM Duty Cycle Registers 1 Register Address 0xAA 0xAB 0xAC 0xAD 1 R/W R/W R/W R/W R/W Description PWM1 current duty cycle PWM2 current duty cycle PWM3 current duty cycle PWM4 current duty cycle Lock = N, SW Reset = N. Table 94. THERM Timer Value Registers 1 Register Address 0xAE 0xAF 1 R/W R R Description THERM1 timer % on-time value THERM2 timer % on-time value POR Default 0x00 0x00 Lock = N, SW Reset = N. Table 95. Register 0x0B8 Host Thermal Status Register 1 1 Register 0x0CO BMC Thermal Status Register 1 2 Bit 0 1 2 3 4 5 6 7 1 2 Name Reserved Local Temp Remote 1 Temp Remote 2 Temp Remote 3 Temp Diode 1 Error Diode 2 Error Diode 3 Error R/W R R R R R R R R Description Reserved for future use. A 1 indicates that a local temperature limit has been tripped. A 1 indicates that a Remote 1 temperature limit has been tripped. A 1 indicates that a Remote 2 temperature limit has been tripped. A 1 indicates that a Remote 3 temperature limit has been tripped. A 1 indicates that a Remote 1 diode error, either an open or a short, has occurred. A 1 indicates that a Remote 2 diode error, either an open or a short, has occurred. A 1 indicates that a Remote 3 diode error, either an open or a short, has occurred. POR = 0x00, Lock = N, SW Reset = Y. POR = 0x00, Lock = N, SW Reset = Y. Rev. 0 | Page 87 of 92 ADT7462 Table 96. Register 0xB9 Host Thermal Status Register 2 1 Register 0xC1 BMC Thermal Status Register 21 Bit 0 1 2 3 4 5 6 7 1 Name THERM1 % THERM1 Assert THERM1 State THERM2 % THERM2 Assert THERM2 State VRD1_Assert VRD2_Assert R/W R R R R R R R R Description A 1 indicates that THERM1 has been asserted for longer than the programmed THERM1 timer limit. A 1 indicates that THERM1 is asserted. A 1 indicates that a transition from high to low has taken place on the THERM1 pin. A 1 indicates that THERM2 has been asserted for longer than the programmed THERM2 timer limit. A 1 indicates that THERM2 is asserted. A 1 indicates that a transition from high to low has taken place on the THERM2 pin. A 1 indicates that VRD1 is asserted. A 1 indicates that VRD2 is asserted. POR = 0x00, Lock = N, SW Reset = Y. Table 97. Register 0xBA Thermal Status Register 3 1 Bit 0 1 2 3 4 5 6 7 1 Name Local THERM1 Remote 1 THERM1 Remote 2 THERM1 Remote 3 THERM1 Local THERM2 Remote 1 THERM2 Remote 2 THERM2 Remote 3 THERM2 R/W R R R R R R R R Description A 1 indicates that the local THERM1 limit has been exceeded. A 1 indicates that the Remote 1 THERM1 limit has been exceeded. A 1 indicates that the Remote 2 THERM1 limit has been exceeded. A 1 indicates that the Remote 3 THERM1 limit has been exceeded. A 1 indicates that the Local THERM2 limit has been exceeded. A 1 indicates that the Remote 1 THERM2 limit has been exceeded. A 1 indicates that the Remote 2 THERM2 limit has been exceeded. A 1 indicates that the Remote 3 THERM2 limit has been exceeded. POR = 0x00, Lock = N, SW Reset = Y. Table 98. Register 0xBB Host Voltage Register 1 1 Register 0xC3 BMC Voltage Register 11 Bit 0 1 2 3 4 5 6 7 1 Name +12V1 +12V2 +12V3 +3.3V Pin 15 Voltage Pin 19 Voltage +5V Pin 23 Voltage R/W R R R R R R R R Description A 1 indicates that a +12V1 voltage limit has been tripped. A 1 indicates that a +12V2 voltage limit has been tripped. A 1 indicates that a +12V3 voltage limit has been tripped. A 1 indicates that a +3.3V voltage limit has been tripped. A 1 indicates that a Pin 15 voltage limit has been tripped. A 1 indicates that a Pin 19 voltage limit has been tripped. A 1 indicates that a +5V voltage limit has been tripped. A 1 indicates that a Pin 23 voltage limit has been tripped. POR = 0x00, Lock = N, SW Reset = Y. Rev. 0 | Page 88 of 92 ADT7462 Table 99. Register 0xBC Host Voltage Status Register 2 1 Register 0xC4 BMC Voltage Status Register 21 Bit [2:0] 3 4 5 6 7 1 Name Reserved Pin 24 Voltage Pin 25 Voltage Pin 26 Voltage +1.5V2 (3GIO) +1.5V1 (ICH) R/W R R R R R R Description Reserved for future use. A 1 indicates that a Pin 24 voltage limit has been tripped. A 1 indicates that a Pin 25 voltage limit has been tripped. A 1 indicates that a Pin 26 voltage limit has been tripped. A 1 indicates that a +1.5V2 (3GIO) voltage limit has been tripped. A 1 indicates that a +1.5V1 (ICH) voltage limit has been tripped. POR = 0x00, Lock = N, SW Reset = Y. Table 100. Register 0xBD Host Fan Status Register 1 1 Register 0xC5 BMC Fan Status Register 11 Bit 0 1 2 3 4 5 6 7 1 Name Fan 1 Fault Fan 2 Fault Fan 3 Fault Fan 4 Fault Fan 5 Fault Fan 6 Fault Fan 7 Fault Fan 8 Fault R/W R R R R R R R R Description A 1 indicates a Fan 1 fault. A 1 indicates a Fan 2 fault. A 1 indicates a Fan 3 fault. A 1 indicates a Fan 4 fault. A 1 indicates a Fan 5 fault. A 1 indicates a Fan 6 fault. A 1 indicates a Fan 7 fault. A 1 indicates a Fan 8 fault. POR = 0x00, Lock = N, SW Reset = Y. Table 101. Register 0xBE Host Digital Status Register 1 1 Register 0xC6 BMC Digital Status Register 11 Bit [2:0] 3 4 5 6 7 1 Name Reserved FAN2MAX SCSI_Term1 SCSI_Term2 VID Comparison Chassis Intrusion R/W R R R R R R Description Reserved for future use. A 1 indicates that the FAN2MAX has been asserted as an input. A 1 indicates that the SCSI_Term1 digital input has been asserted. A 1 indicates that the SCSI_Term2 digital input has been asserted. A 1 indicates a VID comparison fault. A 1 indicates that the chassis intrusion digital input has been asserted. POR = 0x00, Lock = N, SW Reset = Y. Table 102. Register 0xBF GPIO Status Register 1 Bit 0 1 2 3 4 5 6 7 1 Name GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description A 1 indicates that GPIO1 is asserted. A 1 indicates that GPIO2 is asserted. A 1 indicates that GPIO3 is asserted. A 1 indicates that GPIO4 is asserted. A 1 indicates that GPIO5 is asserted. A 1 indicates that GPIO6 is asserted. A 1 indicates that GPIO7 is asserted. A 1 indicates that GPIO8 is asserted. POR = 0x00, Lock = N, SW Reset = Y. Rev. 0 | Page 89 of 92 ADT7462 OUTLINE DIMENSIONS 5.00 BSC SQ 0.60 MAX 0.60 MAX 25 24 32 1 PIN 1 INDICATOR PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ 0.50 BSC EXPOSED PAD (BOTTOM VIEW) 17 16 8 3.25 3.10 SQ 2.95 0.50 0.40 0.30 12° MAX 9 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 86. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm × 5 mm Body, Very Thin Quad (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model ADT7462ACPZ-500RL7 1 ADT7462ACPZ-REEL1 ADT7462ACPZ -REEL71 EVAL-ADT7462EB 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ 32-Lead LFCSP_VQ Evaluation Board Package Option CP-32-2 CP-32-2 CP-32-2 Z = Pb-free part. Rev. 0 | Page 90 of 92 ADT7462 NOTES Rev. 0 | Page 91 of 92 ADT7462 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05569-0-1/06(0) Rev. 0 | Page 92 of 92