ADT7462 Flexible Temperature, Voltage Monitor, and System Fan Controller
The ADT7462 is a flexible systems monitor IC, suitable for use in a wide variety of applications. It can monitor temperature in up to three remote locations, as well as its ambient temperature. There are up to four PWM outputs. These can be used to control the speed of a cooling fan by varying the % duty cycle of the PWM drive signal applied to the fan. The ADT7462 supports high frequency PWM for 4−wire fans and low frequency PWM for 2−wire and 3−wire fans. Up to eight TACH inputs can be used to measure the speed of 3−wire and 4−wire fans. There are up to 13 voltage monitoring inputs, ranging from 12 V to 0.9 V. The ADT7462 is fully compatible with SMBus 1.1 and SMBus 1.0. The ADT7462 also includes a THERM I/O and a RESET I/O. The ADT7462 is available in a 32−lead LFCSP_VQ. Many of the pins are multi−functional. Five easy configuration options can be set up using the easy configuration register. Users choose the configuration closest to their requirements; individual pins can be reconfigured after the easy configuration option has been chosen.
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ADT 7462ACPZ #YYWW AL CCCCC
LFCSP−32 CASE 932
XX # YYWW AL CC
= Device Code = Pb−Free Package = Date Code = Assembly Lot = Country Code
PIN ASSIGNMENT
THERM1/+1.5V1/GPIO7/VID6 VR_HOT2/+1.2V2/V BATT
26
• One Local and Up to Three Remote Temperature Channels Series • • • • • • • • • • • •
Resistance Cancellation On Remote Channels Thermal Protection Using THERM Pins Up to Four PWM Fan Drive Outputs Supports Both High and Low Frequency PWM Drives Up to Eight TACH Inputs Measures the Speed of 3−Wire and 4−Wire Fans Automatic Fan Speed Control Loop Includes Dynamic TMIN Control Monitors Up to 13 V Inputs Monitors Up to 7 VID Inputs; Includes On−The−Fly (OTF) VID Support Bidirectional Reset Chassis Intrusion Detect SMBus 1.1 and SMBus 1.0 Compatible 3.3 V and 5.0 V Operation Extended Operating Range from −40°C to +125°C Space−Saving 32−Lead Chip Scale Package
VID4/GPIO5/PWM1
29
28
27
31
30
25
VR_HOT1/+1.2V1/+3.3V
THERM2/+1.5V2/GPIO8
VID5/GPIO6/PWM2
PWM3
FAN2MAX/CI
VID0/GPIO1/TACH1 VID1/GPIO2/TACH2 VID2/GPIO3/TACH3 VID3/GPIO4/TACH4 V CC GND TACH5/+12V1 TACH6/+12V2
1 2 3 4 5 6 7 8 10
PIN 1 INDICATOR
24 23 22 21 20 19 18 17
V CCP2/ +1.5V/+1.8V/+2.5V V CCP1 / +1.5V/+1.8V/+2.5V TACH8/+12V3 TACH7/+5V D3–/SCSI_TERM2 D3+/+1.25V/+0.9V D2– D2+
32
ADT7462
11
9
12
13
14
15
Applications
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 80 of this data sheet.
• Servers and Personal Computers • Telecommunications Equipment • Test Equipment and Measurement Instruments
© Semiconductor Components Industries, LLC, 2010
January, 2010 − Rev. 3
1
Publication Order Number: ADT7462/D
D1–/SCSI_TERM1
PWM4/+3.3V
D1+/+2.5V/+1.8V
ADD
SCL
SDA
ALERT
RESET
16
ADT7462
ADD SCL SDA ALERT
ADT7462
SMBus ADDRESS SELECTION VID0 TO VID6 VID REGISTER PWM REGISTERS ACOUSTIC ENHANCEMENT CONTROL AUTOMATIC FAN SPEED CONTROL DYNAMIC TMIN CONTROL SERIAL BUS INTERFACE ADDRESS POINTER REGISTER PWM CONFIGURATION REGISTERS INTERRUPT MASKING INTERRUPT STATUS REGISTERS LIMIT COMPARATORS CI
PWM1 TO PWM4 FAN2MAX TACH1 TO TACH8
FAN SPEED COUNTER
PERFORMANCE MONITORING VR_HOT2 VR_HOT1 THERM2 THERM1 THERMAL DIODE INPUTS VOLTAGE INPUTS THERMAL PROTECTION INPUT SIGNAL CONDITIONING AND ANALOG MULTIPLEXER BAND GAP TEMPERATURE SENSOR GND
VALUE AND LIMIT REGISTERS 13−BIT ADC RESET CIRCUIT GPIO STATUS AND CONFIGURATION REGISTERS SCSI STATUS RESET GPIO1 TO GPIO8 SCSI_TERM1 AND SCSI_TERM2
BAND GAP REFERENCE
Figure 1. Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Voltage on +12V Pin Voltage on VBATT Pin Voltage on Any Other Input or Output Pin Input Current at Any Pin Package Input Current Maximum Junction Temperature (TJMAX) Operating Temperature Range Storage Temperature Range Lead Temperature, Soldering Lead Temperature (Soldering, 10 sec) IR Reflow Peak Temperature Rating 6.5 20 4.0 −0.3 to +6.5 ±5 ±20 150 −40 to +125 −65 to +150 300 260 Unit V V V V mA mA °C °C °C °C
ESD Rating 1500 V Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
THERMAL CHARACTERISTICS
Package Type 32−Lead LFCSP_VQ qJA 32.5 qJC 32.71 Unit °C/W
1. qJA is specified for the worst−case conditions, that is, a device soldered in a circuit board for surface−mount packages.
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ADT7462
PIN ASSIGNMENT
Pin No. 1 Mnemonic VID0/GPIO1/TACH1 Description VID0: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO1: Open−Drain I/O. General−purpose input/output. TACH1: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1. VID1: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO2: Open−Drain I/O. General−purpose input/output. TACH2: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2. VID2: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO3: Open−Drain I/O. General−purpose input/output. TACH3: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3. VID3: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO4: Open−Drain I/O. General−purpose input/output. TACH4: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4. Power Supply. Can be powered by 3.3 V standby if monitoring in low power states is required. The ADT7462 can also be powered from a 5.0 V supply. Ground Pin. TACH5: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 5. +12V1: Analog Input. Monitors 12 V Power Supply 1. Attenuators switched on by default. TACH6: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 6. +12V2: Analog Input. Monitors 12 V Power Supply 2. Attenuators switched on by default. Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pullup. Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pullup. The state of this pin on powerup determines the SMBus device address. Active Low Open−Drain Digital Output. Requires 10 kW typical pullup. The ALERT pin is used to signal out−of−limit comparisons of temperature, voltage, and fan speed. This is compatible with SMBus ALERT. PWM4: Digital Output (Open Drain). Requires 10 kW typical pullup. Pulse−width modulated output to control the speed of Fan 4. +3.3V: Analog Input. Monitors 3.3 V power supply. Active Low Open−Drain Digital I/O. Power−on reset, 5 mA driver (weak 100 kW pullup), active low output (100 kW pullup) with a 180 ms typical pulse width. RESET is asserted whenever VCC is below the reset threshold. It remains asserted for approximately 180 ms after VCC rises above the reset threshold. Pin 14 also functions as an active low RESET input and resets all unlocked registers to their default values. D1+: Anode Connection to Thermal Diode 1. +2.5V: Monitors 2.5 V analog input. +1.8V: Monitors 1.8 V analog input. D1−: Cathode Connection to Thermal Diode 1. SCSI_TERM1: Digital Input, SCSI Termination 1. Anode Connection to Thermal Diode 2. Cathode Connection to Thermal Diode 2. D3+: Anode Connection to Thermal Diode 3. +1.25V: Monitors 1.25 V analog input. +0.9V: Monitors 0.9 V analog input. D3−: Cathode connection to Thermal Diode 3. SCSI_TERM2: Digital Input, SCSI Termination 2. TACH7: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 7. +5V: Analog Input. Monitors 5.0 V power supply. POR Default TACH1
2
VID1/GPIO2/TACH2
TACH2
3
VID2/GPIO3/TACH3
TACH3
4
VID3/GPIO4/TACH4
TACH4
5 6 7
VCC GND TACH5/+12V1
VCC GND TACH5
8
TACH6/+12V2
TACH6
9 10 11 12
SCL SDA ADD ALERT
SCL SDA ADD ALERT
13
PWM4/+3.3V
PWM4
14
RESET
RESET
15
D1+/+2.5V/+1.8V
D1+
16 17 18 19
D1−/SCSI_TERM1 D2+ D2− D3+/+1.25V/+0.9V
D1− D2+ D2− D3+
20 21
D3−/SCSI_TERM2 TACH7/+5V
D3− TACH7
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ADT7462
Pin No. 22 23 Mnemonic TACH8/+12V3 VCCP1/+1.5V/+1.8V/+2.5V Description TACH8: Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 8. +12V3: Analog Input. Monitors 12 V Power Supply 3. VCCP1: Monitors 1.2 V analog input. +1.5V: Monitors 1.5 V analog input. +1.8V: Monitors 1.8 V analog input. +2.5V: Monitors 2.5 V analog input. VCCP2: Monitors 1.2 V analog input. +1.5V: Monitors 1.5 V analog input. +1.8V: Monitors 1.8 V analog input. +2.5V: Monitors 2.5 V analog input. VR_HOT1: Digital Input Indicating Overtemperature Event on Voltage Regulator. +1.2V1: 0 V to 1.2 V Analog Input. For example, can be used to monitor GBIT. +3.3V: Analog Input. Monitors 3.3 V power supply. VR_HOT2: Digital Input Indicating Overtemperature Event on Voltage Regulator. +1.2V2: 0 V to 1.2 V Analog Input. For example, can be used to monitor FSB_VTT. VBATT: Analog Input. Monitors battery voltage, nominally 3.0 V. FAN2MAX: Sets fan to maximum speed when a fan fault condition occurs. Bidirectional open drain, active low I/O. CI: An active high input that captures a chassis intrusion event in Bit 7 of the digital status register. This bit remains set until cleared, as long as battery voltage is applied to the VBATT input, even when the ADT7462 is powered off. THERM1: Can be reconfigured as a bidirectional THERM pin. Can be connected to the PROCHOT output of the Intel® Pentium® 4 processor to time and monitor PROCHOT assertions. Can be used as an output to signal overtemperature conditions or for clock modulation purposes. +1.5V1: 0 V to 1.5 V Analog Input. Can be used to monitor ICH. GPIO7: Open−Drain I/O. General−purpose input/output. VID6: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). THERM2: Can be reconfigured as a bidirectional THERM pin. Can be connected to the PROCHOT output of the Intel Pentium 4 processor to time and monitor PROCHOT assertions. Can be used as an output to signal overtemperature conditions or for clock modulation purposes. +1.5V2: 0 V to 1.5 V Analog Input. Can be used to monitor 3GIO. GPIO8: Open−Drain I/O. General−purpose input/output. Digital Output (Open Drain). Requires 10 kW typical pullup. Pulse−width modulated output to control the speed of Fan 3. VID4: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO5: Open−Drain I/O. General−purpose input/output. PWM1: Digital Output (Open Drain). Requires 10 kW typical pullup. Pulse−width modulated output to control the speed of Fan 1. VID5: Digital Input (Open Drain). Voltage supply readouts from CPU. This value is read in to the VID value register (0x97). GPIO6: Open−Drain I/O. General−purpose input/output. PWM2: Digital Output (Open Drain). Requires 10 kW typical pullup. Pulse−width modulated output to control the speed of Fan 2. POR Default TACH8 +1.8V
24
VCCP2/+1.5V/+1.8V/+2.5V
+2.5V
25
VR_HOT1/+1.2V1/+3.3V
+3.3V
26
VR_HOT2/+1.2V2/VBATT
VBATT
27
FAN2MAX/CI
CI
28
THERM1/+1.5V1/GPIO7/VID6
THERM1
29
THERM2/+1.5V2/GPIO8
THERM2
30 31
PWM3 VID4/GPIO5/PWM1
PWM3 PWM1
32
VID5/GPIO6/PWM2
PWM2
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ADT7462
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)
Parameter Power Supply Supply Voltage Supply Current, ICC Temperature−to−Digital Converter Internal Sensor, TA, Accuracy ADC active, Interface inactive (Note 2) TA Conditions 0°C ≤ TA ≤ 85°C −40°C ≤ TA ≤ +100°C 0°C ≤ TA ≤ 85°C −40°C ≤ TA ≤ +100°C 0°C ≤ TA ≤ 85°C −40°C ≤ TA ≤ +100°C 0°C ≤ TA ≤ 85°C −40°C ≤ TA ≤ +100°C High level Mid level Low level The ADT7462 cancels 2 kW in series with the remote thermal diode VCC Conditions 3 V ≤ VCC ≤ 3.6 V 3 V ≤ VCC ≤ 3.6 V 4.5 V ≤ VCC ≤ 5.5 V 4.5 V ≤ VCC ≤ 5.5 V 3 V ≤ VCC ≤ 3.6 V 3 V ≤ VCC ≤ 3.6 V 4.5 V ≤ VCC ≤ 5.5 V 4.5 V ≤ VCC ≤ 5.5 V ±0.5 ±2.25 ±3.25 ±3.0 ±4.0 0.25 ±0.5 ±2.25 ±3.25 ±2.75 ±3.5 0.25 85 34 5.0 2.0 °C 3.0 3.3 1.5 5.5 4.0 V mA Test Conditions / Comments Min Typ Max Unit
Resolution Remote Sensor, TD, Accuracy (−40°C ≤ TD ≤ +125°C)
°C °C
Resolution Remote Sensor Source Current (Note 3) Series Resistance Cancellation (Note 3) ANALOG−TO−DIGITAL CONVERTER Total Unadjusted Error, TUE (Note 4 and 5) Differential Non−linearity, DNL Conversion Time (Voltage Input) (Note 3) Conversion Time (Local Temperature) (Note 3) Conversion Time (Remote Temperature) (Note 3) INPUT RESISTANCE Pin 7, Pin 8, Pin 13, Pin 21, Pin 22, Pin 25, Pin 28, Pin 29 Pin 15, Pin 19 Pin 23, Pin 24 Pin 26, VBATT and +1.2V2 (When Measured) VBATT Current Drain (When Measured) VBATT Current Drain (When Not Measured) FAN RPM TO DIGITAL CONVERTER Accuracy Internal Clock Frequency OPEN−DRAIN OUTPUTS (PWM, GPIO) High Level Output Leakage Current, IOH Output Low Voltage, VOL Output Low Voltage, VOL RESET Pulse Width (Note 3) RESET Threshold RESET Hysteresis (Note 3) Falling voltage VOUT = VCC IOUT = −3 mA, VCC = +3.3 V IOUT = −3 mA, VCC = +3.3 V 140 3.0 180 3.05 70 0.1 82.8 90 Attenuators enabled Attenuators enabled Attenuators enabled Attenuators cannot be disabled CR2032 battery life > 10 years CR2032 battery life > 10 years 100 140 225 66 120 80 16 8 bits 8.53 9.01 38.36
°C mA
kW
±3.5 ±1.0 9.86 10.38 42.09
% LSB ms ms ms
kW kW kW 140 100 kW nA nA
±8.0 97.2 ±1.0 0.4 0.4 3.1
% kHz mA V V ms V mV
DIGITAL OUTPUT (RESET,ALERT, THERM)
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ADT7462
ELECTRICAL CHARACTERISTICS TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted. (Note 1)
Parameter OPEN−DRAIN SERIAL BUS OUTPUT (SDA) Output Low Voltage, VOL High Level Output Leakage Current, IOH Input High Voltage, VIH Input Low Voltage, VIL Hysteresis DIGITAL INPUT LOGIC LEVELS (VID0 to VID6) AND THERM, TACH, GPIO, VR_HOT, SCSI_TERM) Input High Voltage, VIH Input Low Voltage, VIL Input High Voltage, VIH (VID0 to VID6) Input High Voltage, VIH (THERM) Input Low Voltage, VIL Hysteresis DIGITAL INPUT CURRENTS Input High Current, IIH Input Low Current, IIL Input Capacitance (Note 3) SERIAL BUS TIMING (Note 3) Clock Frequency Glitch Immunity, tSW Bus Free Time Start Setup Time, tSU;STA Start Hold Time, tHD;STA SCL Low Time, tLOW SCL High Time, tHIGH SCL, SDA Rise Time, tR SCL, SDA Fall Time, tF Data Setup Time, tSU;DAT Detect Clock Low Timeout See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 See Figure 2 Can be optionally enabled 100 25 1.3 0.6 0.6 1.3 0.6 1000 300 50 400 kHz ns ms ms ms ms ms ns ns ns ms VIN = VCC VIN = 0 5.0 −1.0 +1.0 mA mA pF Bit 3 and Bit 4 of Configuration Register 3 = 0 Bit 3 and Bit 4 of Configuration Register 3 = 0 Bit 3 of Configuration Register 3 = 1 Bit 4 of Configuration Register 3 = 1 Bit 3 and Bit 4 of Configuration Register 3 = 1 500 0.65 2/3 VCCP1 0.4 1.7 0.8 V V V V V mV 500 IOUT = −3 mA, VCC = +3.3 V VOUT = VCC 2.1 0.8 0.1 0.4 ±1.0 V mA V V mV Test Conditions / Comments Min Typ Max Unit
SERIAL BUS DIGITAL INPUTS (SDA AND SCL)
1. All voltages are measured with respect to GND, unless otherwise specified. Typical values are at TA = 25°C and represent the most likely parametric norm. Logic inputs accept input high voltages up to 5.0 V, even when the device is operating at supply voltages below 5.0 V. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. 2. Unused digital inputs connected to GND. 3. Guaranteed by design, not production tested. 4. Note that this specification does not apply if Pin 26 (VBATT, +1.2V) is being measured in single−channel mode. See Figure 16 in the Typical Performance Characteristics section for VBATT accuracy. 5. For Pin 23 and Pin 24 configured as +1.8V or +2.5V only, restricted conditions of VCC ≥ 3.3 V and +25°C ≤ TA ≤ +125°C apply.
tR
SCL
tF
tHD;STA
tLOW tHD;STA tHD;DAT tSU;DAT tHIGH tSU;STA tSU;STO
SDA P
tBUF
S
S
P
Figure 2. Serial Bus Timing Diagram
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ADT7462
TYPICAL PERFORMANCE CHARACTERISTICS
0.00160 0.00155 DEV2 0.00150 IDD (Amps) 0.00145 DEV1 0.00140 DEV3 0.00135 0.00130 0.00125 2.9 IDD (Amps)
0.00144 0.00142 0.00140 0.00138 0.00136 0.00134 0.00132 0.00130 0.00128 0.00126 0.00124 3.4 3.9 4.4 4.9 5.4 0.00122 –45 5 55 TEMPERATURE (5C) 105 DEV3 DEV1 DEV2
SUPPLY VOLTAGE (V)
Figure 3. Supply Current vs. Supply Voltage
Figure 4. Supply Current vs. Temperature
2
2
TEMPERATURE ERROR (5C)
1
VCC = 5.5V
TEMPERATURE ERROR (5C)
1 VCC = 5.5V
0
VCC = 3.3V
0
VCC = 3.3V
–1 –40
–20
0
20
40
60
80
100
120
–1 –40
–20
0
20
40
60
80
100
120
TEMPERATURE (5C)
TEMPERATURE (5C)
Figure 5. Local Sensor Temperature Error
Figure 6. Remote Sensor Temperature Error
5 4 TEMPERATURE ERROR (5C) 3 2 1 0 –1 –2 –3 –4 –40
140 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 MEAN HI SPEC TEMPERATURE READING (5C) LO SPEC 120 100 80 60 40 20 0 –20 0 20 40 60 80 100 120 TEMPERATURE (5C) INT EXT1 EXT2 EXT3
0
20
40
60 TIME (Seconds)
80
100
120
Figure 7. Temperature Error Measuring Intel Pentium 4 Processor
Figure 8. ADT7462 Response to Thermal Shock
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ADT7462
TYPICAL PERFORMANCE CHARACTERISTICS
60
15 10 TEMPERATURE ERROR (5C) 5 0 –5 –10 –15 –20 10 50mV 125mV
40 TEMPERATURE ERROR (°C)
20 D+ TO GND 0 D+ TO V CC –20
–40
–60
0
20
40
60
80
100
100
1M
10M
100M
1G
RESISTANCE (MΩ)
POWER SUPPLY NOISE FREQUENCY (kHz)
Figure 9. Remote Temperature Error vs. Resistance (SRC)
8 6 TEMPERATURE ERROR (5C) TEMPERATURE ERROR (5C) 4 2 0 –2 –4 –6 –8 –10 –12 10 100 1M 10M 100M 1G 50mV 125mV
Figure 10. Local Temperature Error vs. Power Supply Noise Frequency
25 20 15 10 5 0 –5 –10 10 100mV
60mV
40mV
100
1M
10M
100M
1G
POWER SUPPLY NOISE FREQUENCY (kHz)
NOISE FREQUENCY (kHz)
Figure 11. Remote Temperature Error vs. Power Supply Noise Frequency
7 6 TEMPERATURE ERROR (5C) 5 4 3 2 1 0 –1 10 10mV 20mV TEMPERATURE ERROR (5C)
Figure 12. Remote Temperature Error vs. Common−Mode Noise Frequency
10
0
–10 DEV1, EXT1 –20 DEV1, EXT2 DEV1, EXT3 –30 DEV2, EXT1 DEV2, EXT2 DEV2, EXT3 –40 DEV3, EXT1 DEV3, EXT2 DEV3, EXT3
100
1M
10M
100M
1G
–50
0
2
4
6
8
10
NOISE FREQUENCY (kHz)
CAPACITANCE (nF)
Figure 13. Remote Temperature Error vs. Differential−Mode Noise Frequency http://onsemi.com
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Figure 14. Remote Temperature Error vs. Capacitance Between D+ and D−
ADT7462
TYPICAL PERFORMANCE CHARACTERISTICS
0.200 0.198 0.196 TEMPERATURE (5C) 0.194 0.192 0.190 0.188 0.186 0.184 0.182 0.180 –50 0 50 TIMEOUT (Seconds) STANDBY POWERUP VOLTAGE APPLIED TO V BATT (V)
3.0
2.5
2.0
1.5 DEV1 DEV2 DEV3
1.0
0.5
100
150
0
0
0.5
1.0
1.5
2.0
2.5
3.0
VBATT READING (V)
Figure 15. Local Temperature vs. Power−On Reset Timeout
Figure 16. Applied Voltage vs. VBATT Reading
5.0 4.5 4.0 3.5 TACH ERROR (%) 3.0 2.5 2.0 1.5 1.0 0.5 0 2.9 3.4 3.9 4.4 SUPPLY (V) 4.9 5.4 DEV1 DEV2 DEV3 TACH ERROR (%)
1.5 DEV2 1.0 0.5 0 DEV3 –0.5 –1.0 –1.5 –2.0 –50 DEV1
0
50 TEMPERATURE (5C)
100
150
Figure 17. TACH Accuracy vs. Supply Voltage
Figure 18. TACH Accuracy vs. Temperature
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ADT7462
There are a number of multifunctional pins on the ADT7462 that need to be configured on powerup to suit the desired application. Note that due to the large number of pins that need to be configured, it could take several SMBus transactions to achieve the required configuration. For this reason, the ADT7462 has five easy configuration options. The user sets a bit in the easy configuration option register (0x14) to set up the required configuration (see Table 1).
Table 1. Easy Configuration Register Settings
Easy Configuration Option Option 1 Option 2 Option 3 Option 4 Option 5 Register 0x14 Setting Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Pin 1† 2† 3† 4† 7 8 13 15 16 19 20 21 22 23 24 25 26 27 28† 29 31† 32†
PWM2 PWM1 PWM3 THERM2 THERM1 CI VBATT +3.3V
29 28 27 26 31 32 30 25
Function Description: Easy Configuration Options
TACH1 TACH2 TACH3 TACH4 VCC GND TACH5 TACH6
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
24 23 22 21 20 19 18 17
ADT7462
TOP VIEW (Not to Scale)
+2.5V +1.8V TACH8 TACH7 D3– D3+ D2– D2+
10
11
9
12
13
14
15
Figure 19. Configuration Option 1 Table 2. Configuration Option 1
Function TACH1 TACH2 TACH3 TACH4 TACH5 TACH6 PWM4 D1+ D1− D3+ D3− TACH7 TACH8 +1.8V +2.5V +3.3V VBATT CI THERM1 THERM2 PWM1 PWM2 Configuration Register Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 4 Pin Configuration Reg 4 Pin Configuration Reg 4 Pin Configuration Reg 4 Bit Value Bit 4 = 1 Bit 3 = 1 Bit 2 = 1 Bit 1 = 1 Bit 0 = 1 Bit 7 = 1 Bit 6 = 1 Bit 6 = 1 Bit 6 = 1 Bit 5 = 1 Bit 5 = 1 Bit 3 = 1 Bit 2 = 1 Bits [1:0] = 10 Bits [7:6] = 01 Bits [5:4] = 00 Bits [3:2] = 00 Bit 1 = 1 Bits [7:6] = 1× Bits [5:4] = 1× Bit 3 = 1 Bit 2 = 1
Once the most convenient easy configuration option has been set, the user can configure any of the pins individually. The setup complete bit (Bit 5 of Register 0x01) must then be set to 1 to indicate that the ADT7462 is configured correctly, and then monitoring of the selected channels begins. The following is a detailed description of the five easy configuration options that are available.
Configuration Option 1
Configuration Option 1 is the default configuration. It is also the most suitable for thermal monitoring, voltage monitoring, and fan control for single and dual processor systems. Features of Configuration Option 1 include the following: • One local and three remote temperature channels • Four PWM drives and eight TACH inputs • Two THERM I/Os • Voltage monitoring • +3.3V • +2.5V • +1.8V • VBATT • RESET I/O • CI (chassis intrusion) or FAN2MAX Figure 19 shows the pin configuration when Configuration Option 1 is chosen.
†If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7 of Pin Configuration Register 1 (0x10) = 1.
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SCL SDA ADD ALERT PWM4 RESET D1+ D1–
16
ADT7462
Configuration Option 2
Configuration Option 2 is used for thermal monitoring and fan control for Processor 1 and Processor 2 in a dual processor system. It can also monitor one set of VIDs, if required. Features of Configuration Option 2 include the following: • One local and three remote thermal channels • Up to four PWM drives and up to eight TACH inputs (VID pins and TACHs/PWMs are muxed together) • Two THERM I/Os • Two VRD inputs • RESET I/O • Two VCCP voltage monitoring channels Figure 20 shows the pin configuration when Configuration Option 2 is chosen.
PWM2 PWM1 PWM3 THERM2 THERM1 FAN2MAX VR_HOT2 VR_HOT1
Table 3. Configuration Option 2
Pin 1† 2† 3† 4† 7 8 13 15 16 19 20 21 22 23 24 25 26 27 28† 29 31† 32† Function TACH1 TACH2 TACH3 TACH4 TACH5 TACH6 PWM4 D1+ D1− D3+ D3− TACH7 TACH8 VCCP1 VCCP2 VR_HOT1 VR_HOT2 FAN2MAX THERM1 THERM2 PWM1 PWM2 Configuration Register Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 4 Pin Configuration Reg 4 Pin Configuration Reg 4 Pin Configuration Reg 4 Bit Value Bit 4 = 1 Bit 3 = 1 Bit 2 = 1 Bit 1 = 1 Bit 0 = 1 Bit 7 = 1 Bit 6 = 1 Bit 6 = 1 Bit 6 = 1 Bit 5 = 1 Bit 5 = 1 Bit 3 = 1 Bit 2 = 1 Bits [1:0] = 00 Bits [7:6] = 00 Bits [5:4] = 1× Bits [3:2] = 1× Bit 1 = 0 Bits [7:6] = 1× Bits [5:4] = 1× Bit 3 = 1 Bit 2 = 1
27
26
29
31
32
30
28
25
TACH1 TACH2 TACH3 TACH4 VCC GND TACH5 TACH6
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
24 23 22 21 20 19 18 17
ADT7462
TOP VIEW (Not to Scale)
VCCP2 VCCP1 TACH8 TACH7 D3– D3+ D2– D2+
10
11
12
13
14
15
9
SCL SDA ADD ALERT PWM4 RESET D1+ D1–
16
Figure 20. Configuration Option 2
†If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7 of Pin Configuration Register 1 (0x10) = 1.
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ADT7462
Configuration Option 3
Configuration Option 3 is used to monitor all the voltages in the system for Processor 1 and Processor 2. Additional pins can be configured for fan control, VIDs, or GPIOs, as required. Features of Configuration Option 3 include the following: • Up to 13 different voltages monitored • Three +12V • +5V • +3.3V • +2.5V • +1.8V • Two +1.5V • Two +1.2V (VCCP1, VCCP2) • 0.9V • VBATT • One local and one remote temperature channels • Up to three PWM drives and up to four TACH inputs • RESET I/O Figure 21 shows the pin configuration when Configuration Option 3 is chosen.
PWM2 PWM1 PWM3 +1.5V/GPIO8 +1.5V/GPIO7 CI VBATT +1.2V
Table 4. Configuration Option 3
Pin 1† 2† 3† 4† 7 8 13 15 16 19 20 21 22 23 24 25 26 27 28† Function TACH1 TACH2 TACH3 TACH4 +12V1 +12V2 +3.3V +1.8V SCSI_ TERM1 +0.9V SCSI_ TERM2 +5V +12V3 VCCP1 VCCP2 +1.2V VBATT CI +1.5V/ GPIO7 +1.5V/ GPIO8 PWM1 PWM2 Configuration Register Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 4 Pin Configuration Reg 4 Pin Configuration Reg 4 Pin Configuration Reg 4 Bit Value Bit 4 = 1 Bit 3 = 1 Bit 2 = 1 Bit 1 = 1 Bit 0 = 0 Bit 7 = 0 Bit 6 = 0 Bit 6 = 0 Bit 6 = 0 Bit 5 = 0 Bit 5 = 0 Bit 3 = 0 Bit 2 = 0 Bits [1:0] = 00 Bits [7:6] = 00 Bits [5:4] = 01 Bits [3:2] = 00 Bit 1 = 1 Bits [7:6] = 01 Bits [5:4] = 01 Bit 3 = 1 Bit 2 = 1
29
28
27
26
31
32
30
25
TACH1 TACH2 TACH3 TACH4 VCC GND +12V1 +12V2
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
24 23 22 21 20 19 18 17
ADT7462
TOP VIEW (Not to Scale)
VCCP2 VCCP1 +12V3 +5V SCSI_TERM2 +0.9V D2– D2+
29 31† 32†
†If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7 of Pin Configuration Register 1 (0x10) = 1.
10
11
9
12
13
14
15
Figure 21. Configuration Option 3
SCL SDA ADD ALERT +3.3V RESET +1.8V SCSI_TERM1
16
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ADT7462
Configuration Option 4
Configuration Option 4 is used to monitor temperature, voltages, and fans for Processor 1 in a dual processor system. Features of Configuration Option 4 include the following: • One local and two remote temperature channels • Up to four PWM drives and six TACH inputs • Up to eight voltages monitored • +12V • +5V • +3.3V • Two +1.5V • +1.2V (VCCP1) • +0.984V (Mem_VTT) • VBATT • THERM I/O • VRD input • RESET I/O Figure 22 shows the pin configuration when Configuration Option 4 is chosen.
PWM2 PWM1 PWM3 THERM2/+1.5V THERM1/+1.5V FAN2MAX VBATT VR_HOT1
Table 5. Configuration Option 4
Pin 1† 2† 3† 4† 7 8 13 15 16 19 20 21 22 23 24 25 26 27 28
†*
Function TACH1 TACH2 TACH3 TACH4 TACH5 TACH6 PWM4 D1+ D1− +0.9V SCSI_ TERM2 +5V +12V3 VCCP1 +2.5V VR_HOT1 VBATT FAN2MAX THERM1/ +1.5V THERM2/ +1.5V PWM1 PWM2
Configuration Register Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 4 Pin Configuration Reg 4 Pin Configuration Reg 4 Pin Configuration Reg 4
Bit Value Bit 4 = 1 Bit 3 = 1 Bit 2 = 1 Bit 1 = 1 Bit 0 = 1 Bit 7 = 1 Bit 6 = 1 Bit 6 = 1 Bit 6 = 1 Bit 5 = 0 Bit 5 = 0 Bit 3 = 0 Bit 2 = 0 Bits [1:0] = 00 Bits [7:6] = 01 Bits [5:4] = 1× Bits [3:2] = 00 Bit 1 = 0 See Table 51 See Table 51 Bit 3 = 1 Bit 2 = 1
29
28
27
26
31
32
30
25
TACH1 TACH2 TACH3 TACH4 VCC GND TACH5 TACH6
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
24 23 22 21 20 19 18 17
ADT7462
TOP VIEW (Not to Scale)
+2.5V VCCP1 +12V3 +5V SCSI_TERM2 +0.9V D2− D2+
29* 31† 32†
Figure 22. Configuration Option 4
SCL SDA ADD ALERT PWM4 RESET D1+ D1–
†If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7 of Pin Configuration Register 1 (0x10) = 1. *It is not possible to configure +1.5V monitoring on Pin 29 and THERM1 on Pin 28. Pin 28 must both be configured as either +1.5V monitoring or as THERM I/O (see Table 47).
10
11
9
12
13
14
15
16
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ADT7462
Configuration Option 5
Configuration Option 5 is used to monitor temperature, voltages, and fans for Processor 2 in a dual processor system. Features of Configuration Option 5 include the following: • One local and two remote temperature channels • Up to three PWM drives and up to six TACH inputs • Voltage monitoring • Two +12V • +3.3V • Mem_Core (+1.969V) • +1.8 V • Two +1.5V • +1.2V (VCCP2) • RESET I/O Figure 23 shows the pin configuration when Configuration Option 5 is chosen.
PWM2 PWM1 PWM3 THERM2/+1.5V THERM1/+1.5V FAN2MAX VR_HOT2 +1.2V
Table 6. Configuration Option 5
Pin 1† 2† 3† 4† 7 8 13 15 16 19 20 21 22 23 24 25 26 27 28
†*
Function TACH1 TACH2 TACH3 TACH4 +12V1 +12V2 +3.3V +2.5V SCSI_ TERM1 D3+ D3− TACH7 TACH8 +1.8V VCCP2 +1.2V VR_HOT2 FAN2MAX THERM1/ +1.5V THERM2/ +1.5V PWM1 PWM2
Configuration Register Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 1 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 2 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 3 Pin Configuration Reg 4 Pin Configuration Reg 4 Pin Configuration Reg 4 Pin Configuration Reg 4
Bit Value Bit 4 = 1 Bit 3 = 1 Bit 2 = 1 Bit 1 = 1 Bit 0 = 0 Bit 7 = 0 Bit 6 = 0 Bit 6 = 0 Bit 6 = 0 Bit 5 = 1 Bit 5 = 1 Bit 3 = 1 Bit 2 = 1 Bits [1:0] = 10 Bits [7:6] = 00 Bits [5:4] = 01 Bits [3:2] = 1× Bit 1 = 0 See Table 51 See Table 51 Bit 3 = 1 Bit 2 = 1
26
29
28
31
32
30
27
25
TACH1 TACH2 TACH3 TACH4 VCC GND +12V1 +12V2
1 2 3 4 5 6 7 8
PIN 1 INDICATOR
24 23 22 21 20 19 18 17
ADT7462
TOP VIEW (Not to Scale)
VCCP2 +1.8V TACH8 TACH7 D3– D3+ D2− D2+
29* 31† 32†
11
14
10
12
13
15
9
SCL SDA ADD ALERT +3.3V RESET +2.5V SCSI_TERM1
16
Figure 23. Configuration Option 5
†If VIDs are selected, these pins are configured as VIDs. To enable VIDs, set Bit 7 of Pin Configuration Register 1 (0x10) = 1. *It is not possible to configure +1.5V monitoring on Pin 29 and THERM1 on Pin 28. Pin 28 must both be configured as either +1.5V monitoring or as THERM I/O (see Table 47).
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ADT7462
Serial Bus Interface
The ADT7462 is controlled through use of the serial system management bus (SMBus). The ADT7462 is connected to this bus as a slave device, under the control of a master controller. The SMBus interface in the ADT7462 is fully SMBus 1.1 and SMBus 1.0 compliant. The SMBus address is determined by the state of the ADD input on powerup.
ADD Input
The ADD pin is a three−state input to the ADT7462. It is used to determine the SMBus address used. This pin is sampled on powerup only. Any changes subsequent to powerup are not reflected until the ADT7462 is powered down and back up again. The corresponding 7−bit SMBus address for the state of the ADD pin is shown in Table 7.
Table 7. Corresponding SMBus Addresses for ADD Input
ADD Pin High Float Low SMBus Version N/A SMBus 1.1 SMBus 1.1 SMBus Address N/A 0x5C 0x58
SMBus Fixed Address
The ADT7462 supports SMBus fixed address mode and is fully backward compatible with SMBus 1.1 and SMBus 1.0. The ADT7462 powers up with a fixed SMBus address that cannot be changed by the assign address call. The fixed address is set by the state of the ADD input pin on powerup. The ADT7462 also responds to the SMBus device default address of 0x61.
SMBus Operation
The SMBus specification defines specific conditions for different types of read and write operations. The general SMBus protocol operates as follows: 1. The master initiates data transfer by establishing a start condition, defined as a high−to−low transition on the serial data line, SDA, while the serial clock line, SCL, remains high. This indicates that an address/data stream follows. All slave peripherals connected to the serial bus respond to the start condition and shift in the next eight bits, consisting of a 7−bit address (MSB first) plus a R/W bit, which determines the direction of the data transfer, that is, whether data is written to or read from the slave device. 2. The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the 9th clock pulse, known as the acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from it or written to it. If the R/W bit = 0, the master writes to the slave device. If the R/W bit = 1, the master reads from the slave device.
3. Data is sent over the serial bus in sequences of nine clock pulses: eight bits of data followed by an acknowledge bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, because a low−to−high transition when the clock is high can be interpreted as a stop signal. The number of data bytes that can be transmitted over the serial bus in a single read or write operation is limited only by what the master and slave devices can handle. 4. When all data bytes have been read or written, stop conditions are established. In write mode, the master releases the data line during the 10th clock pulse to assert a stop condition. In read mode, the master device overrides the acknowledge bit by pulling the data line high during the low period before the 9th clock pulse. This is known as a no acknowledge. The master then takes the data line low during the low period before the 10th clock pulse and then takes it high during the 10th clock pulse to assert a stop condition. Any number of bytes of data can be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation. For the ADT7462, write operations contain either one or two bytes, and read operations contain one byte. To write data to one of the device data registers or to read data from it, the address pointer register must be set so that the correct data register is addressed. Then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the address pointer register. If data is to be written to the device, the write operation contains a second data byte that is written to the register selected by the address pointer register. This write operation is shown in Figure 24. The device address is sent over the bus, and then R/W is set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the address pointer register. The second data byte is the data to be written to the internal data register. When reading data from a register, there are two possibilities. • If the ADT7462 address pointer register value is unknown or not the desired value, it must be set to the correct value before data can be read from the desired data register. This is done by performing a write to the ADT7462 as before, but only the data byte containing the register address is sent because no data is written to the register (see Figure 25). A read operation is then performed, consisting of the serial bus address and the R/W bit set to 1, followed by the data byte read from the data register (see Figure Figure 26).
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ADT7462 • If the address pointer register is known to be already at
the desired address, data can be read from the corresponding data register without first writing to the address pointer register (see Figure 26). It is possible to read a data byte from a data register without first writing to the address pointer register, if the address pointer register is already at the correct value. However, it is not possible to write data to a register without writing to the address pointer register, because the
1 SCL
first data byte of a write is always written to the address pointer register. In addition to supporting the send byte and receive byte protocols, the ADT7462 also supports the read byte protocol (see System Management Bus Specifications Rev. 2.0 for more information). If several read or write operations must be performed in succession, then the master can send a repeat start condition, instead of a stop condition, to begin a new operation.
9 1 9
SDA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADT7462
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7462
FRAME 1 SERIAL BUS ADDRESS BYTE 1 SCL (CONTINUED)
FRAME 2 ADDRESS POINTER REGISTER BYTE 9
SDA (CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7462 STOP BY MASTER
FRAME 3 DATA BYTE
Figure 24. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1 SCL 9 1 9
SDA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADT7462
D7
D6
D5
D4
D3
D2
D1
D0 ACK. BY ADT7462 STOP BY MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 ADDRESS POINTER REGISTER BYTE
Figure 25. Writing to the Address Pointer Register Only
1 SCL 9 1 9
SDA START BY MASTER
A6
A5
A4
A3
A2
A1
A0
R/W ACK. BY ADT7462
D7
D6
D5
D4
D3
D2
D1
D0 NO ACK. STOP BY BY MASTER MASTER
FRAME 1 SERIAL BUS ADDRESS BYTE
FRAME 2 DATA BYTE FROM ADT7462
Figure 26. Reading Data from a Previously Selected Register Write Operations Send Byte
The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADT7462 are discussed below. The following abbreviations are used in the diagrams: • S ⎯ Start • P ⎯ Stop • R ⎯ Read • W ⎯ Write • A ⎯ Acknowledge • A ⎯ No Acknowledge The ADT7462 uses the following SMBus write protocols.
In this operation, the master device sends a single command byte to a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7−bit slave address followed by the write bit (low). 3. The addressed slave device asserts an ACK on SDA. 4. The master sends a command code. 5. The slave asserts an ACK on SDA. 6. The master asserts a stop condition on SDA to end the transaction.
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ADT7462
For the ADT7462, the send byte protocol is used to write a register address to RAM for a subsequent single byte read from the same address. This operation is shown in Figure 27.
1 S 2 3 4 REGISTER ADDRESS 56 AP SLAVE WA ADDRESS
Block Write
Figure 27. Setting a Register Address for Subsequent Read
If it is required to read data from the register immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read without asserting an intermediate stop condition.
Write Byte
In this operation, the master device sends a command byte and one data byte to the slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7−bit slave address followed by the write bit (low). 3. The addressed slave device asserts an ACK on SDA. 4. The master sends a command code. 5. The slave asserts an ACK on SDA. 6. The master sends a data byte. 7. The slave asserts an ACK on SDA. 8. The master asserts a stop condition on SDA to end the transaction.
1 2 3 4 SLAVE ADDRESS 5 A 6 7 8 SLAVE S ADDRESS W A DATA A P
In this operation, the master device writes a block of data to a slave device. The start address for a block write must be set previously. In the case of the ADT7462, this is done by a send byte operation to set a RAM address. The user writes the number of registers to be written to in the block read command to the #Bytes bits of the Configuration 0 register. 1. The master device asserts a start condition on SDA. 2. The master sends the 7−bit slave address followed by the write bit (low). 3. The addressed slave device asserts an ACK on SDA. 4. The master sends a command code that tells the slave device to expect a block write. The ADT7462 command code for a block write is 0xA0 (1010 0000). 5. The slave asserts an ACK on SDA. 6. The master sends the data bytes (the number of data bytes sent is written to the #Bytes bits of the Configuration 0 register). 7. The slave asserts an ACK on SDA after each data byte. 8. The master sends a packet error checking (PEC) byte. 9. The ADT7462 checks the PEC byte and issues an ACK, if correct. If incorrect (NO ACK), the master resends the data bytes. 10. The master asserts a stop condition on SDA to end the transaction.
Figure 28. Single−Byte Write to a Register
1 2 3 4 5 6 7 8 9 10 11 12 P COMMAND 0xA0 S SLAVE WA A BYTE A DATA 1 A DATA 2 A DATA A PEC A 32 ADDRESS COUNT BLOCK WRITE
Figure 29. Block Write to ADT7462 Read Operations
The ADT7462 uses the following SMBus read protocols.
Receive Byte
For the ADT7462, the receive byte protocol is used to read a single byte of data from a register whose address has previously been set by a send byte or write a byte operation.
1 2 3 4 DATA 56 AP SLAVE S ADDRESS R A
The receive byte is useful when repeatedly reading a single register. The register address must be set up previously. In this operation, the master device receives a single byte from a slave device as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7−bit slave address followed by the read bit (high). 3. The addressed slave device asserts an ACK on SDA. 4. The master receives a data byte. 5. The master asserts a NO ACK on SDA. 6. The master asserts a stop condition on SDA to end the transaction.
Figure 30. Single−Byte Read from a Register Block Read
In this operation, the master device reads a block of data from a slave device. The start address for a block read must be set previously, as well as the number of bytes to be read (maximum = 32). In the case of the ADT7462, the start address is activated by a send byte operation to set a RAM address. The number of bytes to be read should be written to
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ADT7462
the #Bytes bits in the Configuration 0 register. The block read operation consists of a send byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows: 1. The master device asserts a start condition on SDA. 2. The master sends the 7−bit slave address followed by the write bit (low). 3. The addressed slave device asserts an ACK on SDA. 4. The master sends a command code that tells the slave device to expect a block read. The ADT7462 command code for a block read is 0xA1 (1010 0001). 5. The slave asserts an ACK on SDA. 6. The master asserts a repeat start condition on SDA. 7. The master sends the 7−bit slave address followed by the read bit (high). 8. The slave asserts an ACK on SDA. 9. The ADT7462 sends a byte count telling the master how many data bytes to expect. The maximum number of bytes is 32. 10. The master asserts an ACK on SDA. 11. The master receives the expected number of data bytes. 12. The master asserts an ACK on SDA after each data byte. 13. The ADT7462 issues a PEC byte to the master. The master should check the PEC byte and issue another block read if the PEC byte is incorrect. 14. A NO ACK is generated after the PEC byte to signal the end of the read. 15. The master asserts a stop condition on SDA to end the transaction.
1 2 3 4 5 6 S 7 SLAVE ADDRESS R COMMAND SLAVE S W A 0xA1 BLOCK A ADDRESS READ 8 A 9 10 11 12 A DATA 32 A
master. If a device’s SMBALERT line goes low, the following procedure occurs: 1. SMBALERT is pulled low. 2. The master initiates a read operation and sends the alert response address (ARA = 0001 100). This is a general call address that must not be used as a specific device address. 3. The device whose SMBALERT output is low responds to the ARA, and the master reads its device address. The address of the device is now known and can be interrogated in the usual way. 4. If more than one device’s SMBALERT output is low, the one with the lowest device address has priority in accordance with normal SMBus arbitration. 5. Once the ADT7462 has responded to the ARA, the master must read the status registers, and the SMBALERT is cleared only if the error condition has gone away.
SMBus Timeout
The ADT7462 includes an SMBus timeout feature. If there is no SMBus activity for 25 ms, the ADT7462 assumes that the bus is locked and releases the bus. This prevents the device from locking or holding the SMBus while the device is expecting data. Some SMBus controllers cannot handle the SMBus timeout feature, so it can be disabled.
Configuration Register 3 (0x03)
Bit 1 SCL_Timeout = 1; SCL timeout enabled. Bit 1 SCL_Timeout = 0; SCL timeout disabled (default). Bit 2 SDA_Timeout = 1; SDA timeout enabled. Bit 2 SDA_Timeout = 0; SDA timeout disabled (default). Temperature and Voltage Measurement
Temperature Measurement
13
14 15 P
BYTE A DATA 1 COUNT
PEC A
Figure 31. Block Read from RAM
The ADT7462 can measure its own ambient temperature and the temperature of up to three remote thermal diodes. These diodes can be discrete diode−connected 2N3904/ 2N3906s or they can be located on a processor die. Figure 32 shows how to connect a remote NPN or PNP transistor.
ADT7462
D+ D– 2N3906 2N3904
Note that although the ADT7462 supports packet error checking (PEC), its use is optional. The PEC byte is calculated using CRC−8. The frame check sequence (FCS) conforms to CRC−8 by the polynomial.
C(x) + x 8 ) x 2 ) x 1 ) 1
ADT7462
D+ D–
Consult the SMBus 1.1 specifications for more information.
Alert Response Address
Figure 32. How to Measure Temperature Using Discrete Transistors
Alert Response Address (ARA) is a feature of SMBus devices that allows an interrupting device to identify itself to the host when multiple devices exist on the same bus. The SMBALERT output can be used as either an interrupt output or an SMBALERT. One or more outputs can be connected to a common SMBALERT line connected to the
Remote Thermal Diode 1 connects to Pin 15 and Pin 16. Remote Thermal Diode 2 connects to Pin 17 and Pin 18. Remote Thermal Diode 3 connects to Pin 19 and Pin 20. A simple method of measuring temperature is to exploit the negative temperature coefficient of a diode, measuring the base−emitter voltage (VBE) of a transistor, operated at
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ADT7462
constant current. Unfortunately, this technique requires calibration to cancel the effect of the absolute value of VBE, which varies from device to device. The technique used in the ADT7462 is to measure the change in VBE when the device is operated at three different currents. Previous devices have used only two operating currents; use of a third current allows automatic cancellation of any resistances in series with the external temperature sensor. Figure 33 shows the input signal conditioning used to measure the output of an external temperature sensor. This figure shows the external sensor as a substrate transistor, but it could equally be a discrete transistor. If a discrete transistor is used, the collector is not grounded and should be linked to the base. To prevent ground noise from interfering with the measurement, the more negative terminal of the sensor is not referenced to ground but is biased above ground by an internal diode at the D− input. C1 can optionally be added as a noise filter (recommended maximum value 1000 pF). However, a better option in noisy environments is to add a filter, as described in the Noise Filtering section. To measure DVBE, the operating current through the sensor is switched among three related currents. As shown in Figure 33, N1 × I and N2 × I are different multiples of the Current I. The currents through the temperature diode are switched between I and N1 × I, giving DVBE1, and then between I and N2 × I, giving DVBE2. The temperature can then be calculated using the two DVBE measurements. This method can also be shown to cancel the effect of any series resistance on the temperature measurement.
IBIAS
The resulting DVBE waveforms are passed through a 65 kHz low−pass filter to remove noise and then to a chopper−stabilized amplifier. This amplifies and rectifies the waveform to produce a dc voltage proportional to DVBE. The ADC digitizes this voltage, and a temperature measurement is produced. To reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles for low conversion rates. Signal conditioning and measurement of the internal temperature sensor are performed in the same manner (see Figure 33).
Temperature Measurement Results
The results of the local and remote temperature measurements are stored in the local and remote temperature value registers and are compared with limits programmed into the local and remote high and low limit registers.
Table 8. Temperature Measurement Registers
Temperature Value Local Temperature, LSB Local Temperature, MSB Remote 1 Temperature, LSB Remote 1 Temperature, MSB Remote 2 Temperature, LSB Remote 2 Temperature, MSB Remote 3 Temperature, LSB Remote 3 Temperature, MSB Register Address Register 0x88, Bits [7:6] Register 0x89 Register 0x8A, Bits [7:6] Register 0x8B Register 0x8C, Bits [7:6] Register 0x8D Register 0x8E, Bits [7:6] Register 0x8F
VCC I N1 y I N2 y I
D+ REMOTE SENSING TRANSISTOR C1* D– BIAS DIODE LOW−PASS FILTER fC = 65kHz
VOUT+ TO ADC VOUT–
*CAPACITOR C1 IS OPTIONAL. IT SHOULD ONLY BE USED IN NOISY ENVIRONMENTS.
Figure 33. Input Signal Conditioning
The temperature value is stored in two registers. The MSB has a resolution of 1°C. Only two bits in the temperature LSB register are used, Bit 7 and Bit 6, giving a temperature measurement resolution of 0.25°C. The temperature measurement range for both local and remote measurements is from −64°C to +191°C. However, the ADT7462 itself should never be operated outside its operating temperature range, which is from −40°C to +125°C. For the remote diode, the user should refer to the data sheet of the diode.
Table 9. Temperature Data Format
Temperature Value −64°C −50.25°C −25°C 0°C +25°C +50.25°C +100°C MSB 0000 0000 0000 1110 0010 0111 0100 0000 0101 1001 0111 0010 1010 0100 LSB 0000 0000 0100 0000 0000 0000 0000 0000 0000 0000 0100 0000 0000 0000
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ADT7462
When reading the full temperature value, the LSB should be read first and then the MSB. Reading the LSBs causes the current MSBs to be frozen until they are read. Reading the MSBs only does not cause any register to be locked. This is useful when a temperature reading with 1°C resolution is required.
Series Resistance Cancellation Table 10. Temperature Limit Registers
Temperature Value Local Low Temperature Limit Remote 1 Low Temperature Limit Remote 2 Low Temperature Limit Remote 3 Low Temperature Limit Local High Temperature Limit Remote 1 High Temperature Limit Remote 2 High Temperature Limit Remote 3 High Temperature Limit Local THERM1 Temperature Limit Remote 1 THERM1 Temperature Limit Remote 2 THERM1 Temperature Limit Remote 3 THERM1 Temperature Limit Local THERM2 Temperature Limit Remote 1 THERM2 Temperature Limit Remote 2 THERM2 Temperature Limit Remote 3 THERM2 Temperature Limit Register Address 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 Default 0x40 0x40 0x40 0x40 0x95 0x95 0x95 0x95 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4
Parasitic resistance in series with the remote diode D+ and D− inputs can be caused by a variety of factors, including PCB track resistance and track length. This series resistance appears as a temperature offset in the remote sensor’s temperature measurement. This error typically causes a 0.8°C offset per ohm of parasitic resistance in series with the remote diode. The ADT7462 automatically cancels out the effect of this series resistance on the temperature reading, giving a more accurate result, without the need for user characterization of this resistance. The ADT7462 is designed to automatically cancel typically up to 2 kW of resistance. By using an advanced temperature measurement method, the process is transparent to the user. This feature also allows an RCR filter to be added to the sensor path, allowing the part to be used accurately in noisy environments.
Temperature Limits
Offset Registers
Each temperature measurement channel has a high and low temperature limit associated with it. The temperature measurements are compared with these limits, and the results of these comparisons are stored in status registers. A Logic 0 indicates an in−limit comparison, and a Logic 1 indicates an out−of−limit comparison. The ADT7462 can generate an ALERT, if configured to do so, after a status bit is set. For more information on the status registers and ALERT, see the Status and Mask Registers ALERT section. Each temperature channel also has a THERM1 and a THERM2 temperature limit associated with it. When these temperature limits are exceeded, the corresponding THERM pin is asserted low (if THERM is configured as an output), and the fans are boosted to full speed (if the boost bit is set). Table 10 shows a complete list of all the temperature limits and their default values.
The ADT7462 has temperature offset registers at Register 0x56 to Register 0x59 for the local, Remote 1, Remote 2, and Remote 3 temperature channels. By doing a one−time calibration of the system, the user can determine the offset caused by system board noise and cancel it using the offset registers. The offset registers automatically add a twos complement, 8−bit reading to every temperature measurement. The LSBs add 0.5°C offset to the temperature reading so the 8−bit register effectively allows temperature offsets of up to ±64°C with a resolution of 0.5°C. This ensures that the readings in the temperature measurement registers are as accurate as possible.
Temperature Offset Registers
Register 0x56 Local Temperature Offset = 0x00 (00°C default) Register 0x57 Remote 1 Temperature Offset = 0x00 (0°C default) Register 0x58 Remote 2 Temperature Offset = 0x00 (0°C default) Register 0x59 Remote 3 Temperature Offset = 0x00 (0°C default)
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Layout Considerations
Digital boards can be electrically noisy environments. The ADT7462 measures very small voltages from the remote sensor, so care must be taken to minimize noise induced at the sensor inputs. The following precautions should be taken: • Place the ADT7462 as close as possible to the remote sensing diode. Provided that the worst noise sources, such as clock generators, data/address buses, and CRTs, are avoided, this distance can be 4 inches to 8 inches. • Route the D+ and D− tracks close together, in parallel, with grounded guard tracks on each side. To minimize inductance and reduce noise pickup, a 5 mil track width and spacing is recommended. If possible, provide a ground plane under the tracks.
GND 5MIL 5MIL D+ 5MIL 5MIL D– 5MIL 5MIL GND 5MIL
• For really long distances (up to 100 feet), use shielded
•
twisted pair, such as Belden No. 8451 microphone cable. Connect the twisted pair to D+ and D− and the shield to GND close to the ADT7462. Leave the remote end of the shield unconnected to avoid ground loops. Because the measurement technique uses switched current sources, excessive cable or filter capacitance can affect the measurement. When using long cables, the filter capacitance can be reduced or removed.
Noise Filtering
Figure 34. Typical Arrangement of Signal Tracks
• Minimize the number of copper/solder joints that can
•
•
•
cause thermo−couple effects. Where copper/solder joints are used, make sure that they are in both the D+ and D− path and at the same temperature. Thermocouple effects should not be a major problem because 1°C corresponds to about 200 mV, and thermocouple voltages are about 3 mV/°C of temperature difference. Unless there are two thermocouples with a large temperature differential between them, thermocouple voltages should be much less than 200 mV. Place a 0.1 mF bypass capacitor close to the VCC pin. In extremely noisy environments, an input filter capacitor can be placed across D+ and D− close to the ADT7462. This capacitance can affect the temperature measurement, so care must be taken to ensure that any capacitance seen at D+ and D− is a maximum of 1000 pF. This maximum value includes the filter capacitance, plus any cable or stray capacitance between the pins and the sensor diode. If the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. This works from about 6 feet up to 12 feet.
For temperature sensors operating in noisy environments, the industry−standard practice is to place a capacitor across the D+ and D− pins to help combat the effects of noise. However, large capacitances affect the accuracy of the temperature measurement, leading to a recommended maximum capacitor value of 1000 pF. While this capacitor does reduce noise, it does not eliminate it, making it difficult to use the sensor in a very noisy environment. The ADT7462 has a major advantage over other devices in eliminating the effects of noise on the external sensor. The series resistance cancellation feature allows a filter to be constructed between the external temperature sensor and the device. The effect of any filter resistance seen in series with the remote sensor is automatically canceled from the temperature result. The construction of a filter allows the ADT7462 and the remote temperature sensor to operate in noisy environments. Figure 35 shows a low−pass RCR filter, with the following values: R = 100 W C = 1 nF This filtering reduces both common−mode noise and differential noise.
100Ω D+ 1nF D–
REMOTE SENSOR
100Ω
Figure 35. Filter Between Remote Sensor and ADT7462 Voltage Measurement
The ADT7462 is capable of measuring up to 13 different voltage inputs at one time. Table 11 is a list of the voltage measurement inputs and the corresponding input pins. Each pin can be configured to measure the desired voltage option using the Pin Configuration 1 (0x10) to Pin Configuration 4 (0x13) registers or the easy configuration options.
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ADT7462
Table 11. Voltage Inputs
Pin 7 8 13 15 19 21 22 23 24 25 26 28 29 +12V1 +12V2 +3.3V +2.5V / +1.8V +1.25V / +0.9V +5V +12V3 VCCP1 / +1.5V / +1.8V / +2.5V VCCP2 / +1.5V / +1.8V / +2.5V +1.2V1 (GBIT) / +3.3V +1.2V2 (FSB_VTT) / VBATT +1.5V1 (ICH) +1.5V2 (3GIO)
2.5V 1.8V ICH, 3GIO, 1.5V 1.25V 0.9V 8kΩ 92kΩ 35pF
Voltage Measured
GBIT, FSB_VTT, VCCP1, VCCP2
32kΩ 77kΩ 10pF
30kΩ 72kΩ 10pF
51kΩ 66kΩ 8pF
8kΩ 91kΩ 35pF
MUX
30kΩ 72kΩ 10pF
Input Circuit
The internal structure for the voltage inputs is shown in Figure 36. Each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a first−order, low−pass filter that gives the input immunity to high frequency noise. Voltages with full−scale values greater than the reference are divided so that the full−scale value equals the reference (2.25 V). All analog inputs are multiplexed into the on−chip, successive approximation ADC. This ADC has a resolution of ten bits. The basic input range is from 0 V to 2.25 V, but the inputs have built−in attenuators to allow measurement of larger and smaller voltages. To allow a tolerance for these voltages, the ADC produces an output of 3/4 full scale (decimal 768 or 0x300) for the nominal input voltage and so has enough headroom to cope with overvoltages. A list of corresponding LSB and full−scale values for each input voltage is shown in Table 12.
Table 12. Input Range Code Conversion
Nominal Input Voltage (3/4 Scale) +12V +5V VCCP1, VCCP2 VCCP1, when VIDs are enabled +3.3V VBATT +2.5V +1.8V +1.5V +1.25V +1.2V +0.9V Pin No. 7, 8, 22 21 23, 24 23 13, 25 26 15, 23, 24 15, 23, 24 23, 24, 28, 29 19 25, 26 19 1 LSB Value 0.0625 0.026 0.00625 0.0125 0.0172 0.0156 0.013 0.0094 0.0078 0.0065 0.00625 0.00469 Full Scale 16 V 6.67 V 1.6 V 3.2 V 4.4 V 4.0 V 3.33 V 2.4 V 2.0 V 1.667 V 1.6 V 1.2 V
3.3V
68kΩ 71kΩ 5pF
5V
76kΩ 39kΩ 5pF
12V
100kΩ 16kΩ 5pF
Figure 36. Voltage Input Structures Example Calculations
Given the LSB value for each channel, the corresponding code for each voltage (or vice versa) can be calculated.
Code + Voltage 1 LSB
Example: The code for 1.8 V in a 1.8 V channel is:
Code + 1.8 + 192 (that is, 3 4 scale) 0.0094
Similarly, the voltage, given the code in a particular channel, is calculated as follows:
Voltage + Code 1 LSB
where: 10 V is connected to the 12 V channel. 1 LSB = 0.0625. Code = 160 decimal.
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ADT7462
Voltage Measurement and Limit Registers
The corresponding register locations for voltage measurements are listed in Table 13. Each voltage measurement channel has a high and low voltage limit associated with it. The voltage measurements are compared with these limits. The results of these comparisons are stored in status registers. A Logic 0 indicates an in−limit condition,
Table 13. Voltage Value and Limit Registers
and a Logic 1 indicates an out−of−limit condition. The ADT7462 can generate an ALERT, if configured to do so, when a status bit is set. For more information on the status registers and ALERT, see the Status and Mask Registers ALERT section. A complete list of all the high and low voltage limits in the ADT7462 and their default values is contained in Table 13.
Low Limit Voltage Value +12V1 +12V2 +3.3V +1.8V or +2.5V +1.25V or +0.9V +5V +12V3 VCCP1, +1.5V, +1.8V, +2.5V VCCP2, +1.5V, +1.8V, +2.5V +1.2V1 (GBIT) or +3.3V +1.2V2 (FSB_VTT) or VBATT +1.5V1 (ICH) +1.5V2 (3GIO) Pin No. 7 8 13 15 19 21 22 23 24 25 26 28 29 Value Register Address 0xA3 0xA5 0x96 0x8B 0x8F 0xA7 0xA9 0x90 0x91 0x92 0x93 0x94 0x95 Register 0x6D 0x6E 0x70 0x45 0x47 0x71 0x6F 0x72 0x73 0x74 0x75 0x76 0x77 Default 0x00 0x00 0x00 0x40 0x40 0x00 0x00 0x20 0x00 0x00 0x80 0x00 0x00
High Limit Register 0x7C 0x7D 0x68 0x49 0x4B 0x7E 0x7F 0x69 0x6A 0x6B 0x6C 0x50 0x4C Default 0xFF 0xFF 0xFF 0x95 0x95 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xA4 0xA4
The VBATT input allows the condition of a CMOS backup battery to be monitored. This is typically a lithium coin cell, such as a CR2032. The VBATT input is accurate only for voltages greater than 1.2 V. Note that when Pin 26 is configured as a +1.2V input, voltages lower than 1.2 V are not accurately measured. Input voltage and corresponding voltage measured are shown in Figure 16. Typically, the battery in a system is required to keep some devices powered on when the system is in a powered−off state. The VBATT measurement input is designed to minimize battery drain. To reduce current drain from the battery, the lower resistor of the VBATT attenuator is not connected, except when a VBATT measurement is being made. The total current drain on the VBATT pin is 80 nA typical (for a maximum VBATT voltage = 4.0 V), so a CR2032 CMOS battery functions in a system in excess of the expected 10 years. Note that when a VBATT measurement is not being made, the current drain is reduced to 16 nA typical. Under normal voltage measurement operating conditions, all measurements are made in a round−robin format, and each reading is actually the result of 16 digitally averaged measurements. However, averaging is not carried out on the VBATT measurement to reduce measurement time and, therefore, reduce the current drain from the battery.
Battery Measurement Input (VBATT)
The VBATT current drain when a measurement is being made is calculated by:
I+ V BATT 100 kW t pulse t period
where: tPULSE is the VBATT measurement time (~711 ms typical). tPERIOD is the time required to measure all analog inputs. Monitoring cycle time depends on the ADT7462 configuration. Calculating the monitoring cycle time is described in more detail in the ADC Information section. In addition to minimizing battery current drain, the VBATT measurement circuitry is specifically designed with battery protection in mind. Internal circuitry prevents the battery from being back−biased by the ADT7462 supply or through any other path under normal operating conditions. In the unlikely event of a catastrophic ADT7462 failure, the ADT7462 includes a second level of battery protection, including a series 3 kW resistor to limit current to the battery, as recommended by UL (see Figure 37). Thus, it is not necessary to add a series resistor between the battery and the VBATT input; the battery can be connected directly to the VBATT input to improve voltage measurement accuracy.
VBATT Input Battery Protection
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ADT7462
VBATT 49.5kΩ 3kΩ DIGITAL CONTROL ADC
attenuators are disabled, the user should ensure that the voltage on the pin never exceeds 2.25 V.
Table 15. Voltage Attenuator Configuration Registers
Register Name Voltage Attenuator Configuration Register 1 Register Address 0x18 0x19
4.5pF
3kΩ 82.7kΩ
Figure 37. Equivalent VBATT Input Protection Circuit
Voltage Attenuator Configuration Register 2
ADC Information
Round Robin
Single−Channel ADC Conversions
Both temperature and voltage measurements are analog inputs that are digitized using the on−board ADC. An internal multiplexer switches between the different analog inputs and digitizes them, in turn, in a round−robin manner. The total conversion time depends upon how the ADT7462 is configured. The conversion times for each measurement channel are shown in Table 14. The complete conversion time is the sum of the time for the voltage and temperature measurements. For example, if the ADT7462 is configured as Easy Configuration Option 1, the round−robin conversion time is calculated as follows: Total Conversion Time = 1 × (Local Conversion Time) + 3 × (Remote Conversion Time) + 4 × (Voltage Measurement Time) The TACH is not measured using the ADC and so is not part of the round−robin monitoring cycle.
Table 14. Measurement Channel Conversion Times
Channel Local Temperature Remote Temperature Voltage Conversion Time (ms) 9.01 38.36 8.53
Setting Bit 2 of the EDO Enable register (0x16) places the ADT7462 into single−channel mode. In this mode, the ADT7462 can be made to convert on a single voltage or temperature channel only. The channel to be converted on is selected by writing to Bits [7:3] of the EDO (single−channel) Enable register (0x16). When the device is in single−channel mode, the pin configuration option should not be changed. Note that when the Pin 26 voltage, which includes the VBATT option, is selected in single−channel mode, this means that voltage measurements are continuously made in this mode. If a battery is connected to this input, this results in an excessive current drain on the battery. The specification of >10 years of battery life is valid only when the battery voltage is measured as part of the round robin and not in single−channel mode.
Table 16. Single−Channel Mode Options
Bits [7:3] ADC Channel Selected +1.2V2 voltage, Pin 26 Remote 1 temperature Remote 2 temperature Remote 3 temperature Local temperature +12V1 voltage, Pin 7 +12V2 voltage, Pin 8 +12V3 voltage, Pin 22 +3.3V voltage, Pin 13 +2.5V/+1.8V voltage, Pin 15 +1.25V/+0.9V voltage, Pin 19 +5V voltage, Pin 21 +1.5V/+1.8V/+2.5V voltage, Pin 23 +1.5V/+1.8V/+2.5V voltage, Pin 24 +1.2V1/+3.3V voltage, Pin 25 +1.5V1 voltage, Pin 28 +1.5V2 voltage, Pin 29
0000 0 0000 1
0001 0 0001 1 0010 0 0010 1 0011 0 0011 1 0100 0 0100 1 0101 0 0101 1 0110 0 0110 1 0111 0 1000 0 1000 1
For each ADC temperature and voltage measurement read from their value registers, 16 readings have actually been made internally and the results averaged before being placed in the value register.
Bypass Voltage Attenuators
There are up to 13 voltage measurement channels on the ADT7462. Each of these voltage measurement channels has an input structure (see Figure 36 for input structures for each of the voltage channels). Because the ADC has a voltage input range from 0 V to 2.25 V, these input circuits attenuate the voltage input using a resistor divider network to match the input range of the ADC. However, the user may occasionally want to remove the attenuators and directly apply a voltage of between 0 V and 2.25 V to the ADC. These attenuators can be disabled by setting relevant bits in the voltage attenuator configuration registers (see Table 15). This feature also allows the user to rescale the voltage inputs using an external attenuator circuit. However, when the
Dynamic VID Functionality
VID Code
The ADT7462 can be configured to monitor up to seven VID inputs. The VID code is output on seven lines from the CPU to tell the power controller what input voltage it requires. The ADT7462 can monitor the VID code and the
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ADT7462
voltage applied to the CPU to ensure that they match within an acceptable range. This acceptable range is programmable in the ADT7462. The VID lines are monitored by the ADT7462, and the VID code is stored in the VID Value register (0x97), which can be read back over the SMBus. VID monitoring is enabled by setting Bit 7 (VIDs) of Pin Configuration Register 1 (0x10) to 1. See Table 17 and Table 18 for information on which pin should be connected to each VID line. When VID monitoring is enabled, all seven pins are automatically configured as VID inputs. It is not possible to select six pins as VID inputs and use the remaining pin as an alternate function.
VID Value Register (0x97) Dynamic VID Monitoring
Bit 0 = VID0 (reflects the logic state of Pin 1) Bit 1 = VID1 (reflects the logic state of Pin 2) Bit 2 = VID2 (reflects the logic state of Pin 3) Bit 3 = VID3 (reflects the logic state of Pin 4) Bit 4 = VID4 (reflects the logic state of Pin 31) Bit 5 = VID5 (reflects the logic state of Pin 32) Bit 6 = VID6 (reflects the logic state of Pin 28) The ADT7462 supports both the VR10 and the VR11 specifications. The default option supports the VR10 specification. To switch to the VR11 specification, set Bit 6 of Configuration Register 0 (0x00) to 1. VR11 is defined as eight bits; the ADT7462 monitors only seven VID lines (see Table 17).
Table 17. VR11 VID Codes
VID Number VID6 VID5 VID4 VID3 VID2 VID1 VID0 Pin No. 28 32 31 4 3 2 1 Voltage 400 mV 200 mV 100 mV 50 mV 25 mV 12.5 mV 6.25 mV
The ADT7462 supports dynamic VID monitoring. The purpose of the VID code is to tell the voltage controller what VCCP voltage should be applied to the CPU. The VCCP voltage applied to the processor changes as the power requirements of the processor change. The VID is compared with VCCP1 only. Note that when the VIDs are enabled, the LSB value for VCCP1 becomes 0.0125 V (see Table 12). The VID values can represent voltages from 0.8375 V to 1.6 V. The VID code is sampled by the ADT7462 every 11 ms and is stored in Register 0x97. Once the VID code has been stable (that is, does not change) for 55 ms, the measured VCCP is then compared with the VID code. The comparison table used is for either the VR10 or the VR11 specification (set by Bit 6 of Register 0x00). If the VID code and the measured VCCP do not match within a certain limit, an ALERT is generated. The VID value decoded and the VCCP measurement must be within a window controlled by the VID high and low limits. The VID is compared with VCCP1 only. Register 0x78 holds the 4−bit VID high and low limits. The high limit has a range of 0 mV to 375 mV with a resolution of 25 mV (four bits). The low limit has a range of 0 mV to −187.5 mV with a resolution of 12.5 mV (four bits). The high limit is used in a greater−than comparison, and the low limit is used in a less−than−or−equal−tocomparison. Note that if both limits are set to 0x00, because the low limit is less than or equal to the comparison, an ALERT always results. Therefore, the minimum value for low limit is 0x01. If the VCCP voltage measured and the VID code do not match to within the programmed limit, Status Bit 6 of the digital status register is set (Register 0xBE). This, in turn, can generate an ALERT if it is not masked.
Example
VR10 requires only six VID lines (see Table 18). Pin 28 should be connected to ground when monitoring VR10 VID codes. VID6 reports a 0.
Table 18. VR10 VID Codes
VID Number VID6 VID5 VID4 VID3 VID2 VID1 VID0 Pin No. 28 32 31 4 3 2 1 Voltage Unused, connect to GND 12.5 mV 400 mV 200 mV 100 mV 60 mV 25 mV
VID high limit: 100 mV (Register 0x78), four MSBs set to 0100. VID low limit: 50 mV (Register 0x78), four LSBs set to 0100. VID value equates to 1.1 V. This is the read VID decoded, using either VR10 or VR11 tables. VCCP1 must be in the window of 1.05 V to 1.2 V. If the VCCP1 value is outside this window, the status bit is set and an ALERT is generated. To clear an ALERT generated in this way, read the digital status register. If the VID code and VCCP are now matching within the programmed window (that is, the error condition that caused the ALERT has gone away), then the status bit is reset and so is the ALERT. The VID to VCCP voltage tables for both VR10 and VR11 can be found on the Intel website. See the Voltage Regulator Module (VRM) and Enterprise Voltage Regulator−Down (EVRD) 10.0 Design Guidelines, Page 18 and Page 19, for additional information.
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Status and Mask Registers and ALERT
Status Registers
Each measured temperature and voltage has an associated high and low limit. The measured values are compared with these programmable limits. The results of these comparisons are stored in the status registers. A Logic 0 in the status register represents an in−limit comparison, while a Logic 1 represents an out−of−limit comparison. Once a status bit is set, it remains set until the status register is read by the SMBus master. Once read, the status bit is cleared if the error condition has gone away. The status registers are duplicated to accommodate situations where there are two SMBus masters. If one master reads the host status registers and consequently clears them, the second master has no way of knowing what bits were set and what bits were cleared. The second SMBus master can read from the duplicate BMC status registers to determine which status bits were set. Table 19 is a list of the status registers and corresponding addresses.
Table 19. Status Registers
Register Name Thermal Status Register 1 Thermal Status Register 2 Thermal Status Register 3 Voltage Status Register 1 Voltage Status Register 2 Fan Status Register 1 Digital Status Register 1 GPIO Status Register Host Address 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF BMC Address 0xC0 0xC1 − 0xC3 0xC4 0xC5 0xC6 −
corresponding status bit is set to 1. The status bit remains set until the error condition goes away and the status register is read. The status bits are referred to as sticky because they remain set until read by software. This ensures that an out−of−limit event cannot be missed, if software is polling the device periodically. Note that the ALERT output remains low for the entire duration that a reading is out of limit and until the status register has been read.
Mask Registers
The user has the option of masking any of the individual status bits that generate an ALERT. This is achieved by setting the appropriate bit in the mask registers. The ALERT output is not asserted on the setting of a status bit if it has been masked. The status bit itself is not affected and continues to be set when an out−of−limit condition exists. Table 20 is a list of the mask registers and corresponding addresses.
Table 20. Mask Registers
Register Name Thermal Mask Register 1 Thermal Mask Register 2 Voltage Mask Register 1 Voltage Mask Register 2 Fan Mask Register Digital Mask Register GPIO Mask Register Register Address 0x30 0x31 0x32 0x33 0x34 0x35 0x36
Fan Control
Fan Drive Using PWM Control
ALERT Output
The ADT7462 has an SMBus ALERT output that is asserted when one of the status bits is set. This is to alert the master that an out−of−limit measurement has taken place or that there is a fault on one of the fan channels. An ALERT is generated as a result of a status bit being set in any of the registers.
HIGH LIMIT
TEMPERATURE CLEARED ON READ (TEMP BELOW LIMIT) STICKY STATUS BIT SMBALERT TEMP BACK IN LIMIT (STATUS BIT STAYS SET)
The ADT7462 uses pulse−width modulation (PWM) to control fan speed. Control relies on varying the duty cycle (or on/off ratio) of a square wave applied to the fan to vary the fan speed. The advantage of using PWM control is that it uses a very simple external circuit. The specific circuit used depends upon the type of fan. There are three main fan types in use: 2−wire fans, 3−wire fans, and 4−wire fans. The 2−wire fan has only power and ground connections. The 3−wire fan has power and ground connections and a TACH output to indicate the speed of the fan. The 4−wire fan has power and ground connections, a TACH output, and a PWM input. The PWM input is connected directly to the PWM drive of the ADT7462 and is used to control the speed of the fans. For 2−wire and 3−wire fans, the low frequency PWM drive signal should be selected. For 4−wire fans, the high frequency PWM drive signal should be selected.
Using the ADT7462 with 2−Wire Fans
Figure 38. ALERT and Status Bit Behavior
Figure 38 shows how the ALERT output and “sticky” status bits behave. When a limit is exceeded, the
Figure 39 shows the most typical circuit used with a 2−wire fan and illustrates how a 2−wire fan can be connected to the ADT7462. The low frequency PWM mode must be selected when using a 2−wire fan.
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ADT7462
+V
ADT7462
3.3 V
5.0 V or 12 V FAN
1N4148
10 kΩ TYPICAL PWM
Q1 NDT3055L
Driving a 3−wire fan with a PWM signal makes the fan speed measurement more difficult because the TACH signal is chopped by the PWM drive signal. Pulse stretching is required in this case to make accurate fan speed measurements. For more information, see the Fan Speed Measurement section.
Using the ADT7462 with 4−Wire Fans
TACH
0.01 mF
RSENSE 2Ω TYPICAL
Figure 41 shows the most typical circuit used with 4−wire fans.
12 V 10 kΩ TACH 10 kΩ 4.7 kΩ TACH 12 V 12 V, 4−WIRE FAN VCC TACH PWM
Figure 39. Driving a 2−Wire Fan Using the ADT7462 with 3−Wire Fans
Figure 40 shows the most typical circuit used with a 3−wire fan.
12 V 10 kΩ TACH/AIN 10 kΩ 4.7 kΩ 3.3 V 12 V FAN 1N4148 12 V
ADT7462
3.3 V or 5.0 V 2 kΩ
PWM
Figure 41. Driving a 4−Wire Fan
ADT7462
10 kΩ PWM Q1 NDT3055L
Because the electronics in a 4−wire fan are powered continuously, unlike previous PWM driven/powered fans, 4−wire fans tend to perform better than 3−wire fans, especially for high frequency applications. 4−wire frames also eliminate the requirement for pulse stretching, because the TACH signal is always available.
Driving Two Fans from Each PWM
Figure 40. Driving a 3−Wire Fan
The external circuitry required is very simple. A MOSFET, such as the NDT3055L, is used as the pass device. The specifications of the MOSFET depend on the maximum current required by the fan being driven. A typical PC fan can draw a nominal current ranging from a few hundred milliamps to over an amp of current. Depending on the current rating of the fan, a SOT device can be used where board space is a concern. If several fans in parallel are driven from a single PWM output or if larger server fans are driven, the MOSFET must handle the higher current requirements. The only other stipulation is that the MOSFET should have a gate voltage drive, VGS < 3.3 V, for direct interfacing to the PWM pins. VGS can be greater than 3.3 V as long as the pullup on the gate is tied to 5.0 V. The MOSFET should also have a low on resistance to ensure that there is not a significant voltage drop across the FET, which would reduce the voltage applied across the fan and reduce the full speed of the fan. Figure 40 uses a 10 kW pullup resistor for the TACH signal. This assumes that the TACH signal is an open−collector from the fan. In all cases, the TACH signal from the fan must be kept below 5.0 V maximum to prevent damaging the ADT7462. If in doubt as to whether the fan used has an open−collector or totem−pole TACH output, use one of the input signal conditioning circuits shown in the Fan Speed Measurement section.
Note that the ADT7462 has up to eight TACH inputs available for fan speed measurement, but only four PWM drive outputs. If all eight fans are being used in the system, two fans should be driven in parallel from each PWM output. Figure 42 shows how to drive two fans in parallel using the NDT3055L MOSFET. This information is relevant for low frequency mode only (2−wire and 3−wire fans), because the PWM and TACHs need to be synchronized to obtain accurate fan speed measurements using pulse stretching (see the Fan Speed Measurement with Pulse Stretching section). In high frequency mode and when using 4−wire fans, the TACH signal is always valid because the fan is always powered on. Note that because the MOSFET can handle up to 3.5 A, it is simply a matter of connecting another fan directly in parallel with the first. Care should be taken in designing drive circuits with transistors and FETs to ensure that the PWM pins are not required to source current and that they sink less than the 8 mA maximum current specified on the MOSFET data sheet.
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3.3 V 10 kΩ TYPICAL TACH7 3.3 V +V +V 5.0 V or 12 V FAN 5.0V or 12 V FAN 1N4148 TACH 12 V VCC
PULLUP 4.7 kΩ TYPICAL
TACH OUTPUT
TACH ZD1*
ADT7462
TACH3
FAN SPEED COUNTER
10 kΩ TYPICAL 3.3 V TACH
ADT7462
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 y V CC.
10 kΩ TYPICAL PWM3 Q1 NDT3055L
Figure 44. Fan with TACH Pullup to Voltage > 5.0 V, (Example 12 V) Clamped with Zener Diode
Figure 42. Interfacing Two Fans in Parallel to a PWM Output Using a Single N−Channel MOSFET
Fan Speed Measurement and Control
TACH Inputs
Pin 1, Pin 2, Pin 3, Pin 4, Pin 7, Pin 8, Pin 21, and Pin 22 are TACH inputs intended for fan speed measurement. Signal conditioning in the ADT7462 accommodates the slow rise and fall times typical of fan tachometer outputs. The maximum input signal range is 0 V to 5.0 V, even when VCC is less than 5.0 V. In the event that these inputs are supplied from fan outputs that exceed 0 V to 5.0 V, either resistive attenuation of the fan signal or diode clamping must be included to keep inputs within an acceptable range. Figure 43 to Figure 46 show circuits for most common fan TACH circuits. If the fan TACH output has a resistive pullup to VCC, it can be connected directly to the fan input, as shown in Figure 43.
12 V PULLUP 4.7 kΩ TYPICAL VCC
If the fan has a strong pullup (less than 1 kW) to 12 V or a totem−pole output, a series resistor can be added to limit the Zener current, as shown in Figure 45. Alternatively, a resistive attenuator can be used, as shown in Figure 46. R1 and R2 should be chosen such that: 2.0 V < VPULLUP × R2/(RPULLUP + R1 + R2) < 5.0 V The fan inputs have an input resistance of nominally 160 kW to ground, so this should be taken into account when calculating resistor values. With a pullup voltage of 12 V and a pullup resistor of less than 1 kW, suitable values for R1 and R2 would be 100 kW and 47 kW. This gives a high input voltage of 3.83 V.
FAN 5.0 V or 12 V VCC
PULLUP TYP < 1 kΩ or TOTEM POLE
R1 10 kΩ TACH OUTPUT
TACH ZD1 ZENER*
FAN SPEED COUNTER
ADT7462
*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 y VCC.
Figure 45. Fan with Strong TACH Pullup to >VCC or Totem−Pole Output, Clamped with Zener Diode and Resistor
12 V VCC
TACH OUTPUT TACH
FAN SPEED COUNTER
ADT7462
< 1 kΩ
R1* TACH OUTPUT
TACH R2*
FAN SPEED COUNTER
Figure 43. Fan with TACH Pullup to VCC
ADT7462
If the fan output has a resistive pullup to 12 V (or other voltage greater than 5.0 V), the fan output can be clamped with a Zener diode, as shown in Figure 44. The Zener diode voltage should be chosen so that it is greater than VIH of the TACH input but less than 5.0 V, allowing for the voltage tolerance of the Zener diode. A value of between 3.0 V and 5.0 V is suitable.
*SEE TEXT
Figure 46. Fan with Strong TACH Pullup to >VCC or Totem−Pole Output, Attenuated with R1/R2 Fan Speed Measurement
The method of fan speed measurement when using 3−wire fans differs from that used with 4−wire fans. When 3−wire
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fans are in use, power is continuously applied and removed from the fan, thereby chopping the TACH information. As a result, every time a fan speed measurement is to be made, the fan must be switched on for a long enough period of time that a measurement can be made. This is called pulse stretching. With 4−wire fans, power is always applied to the fan, so fan speed measurements can be made continuously, and there is no need for pulse stretching. Pulse stretching is also not necessary when driving a 3−wire fan with a dc input. The Fan Speed Measurement with Pulse Stretching section, which describes how fan speed is measured both when pulse stretching is required and when it is not.
Fan Speed Measurement Without Pulse Stretching Driving and Measuring the Speed of Two Fans from One PWM Output
When pulse stretching is enabled, the ADT7462 measures fan speed once a second. The counter then counts up from the first to the third TACH pulse; this value is stored in the TACH value register. The PWM drive returns to its previous programmed value. Each TACH input is synchronized to a particular PWM output. The PWM and TACH pins must be connected as shown in Figure 48 to ensure that pulse stretching is synchronized between the PWM output and the TACH inputs, and an accurate fan speed measurement is made on each fan.
PWM1 PWM2
Fan speed is measured by the ADT7462, and the result is stored in the fan TACH value registers. The fan counter does not count the fan TACH output pulses directly because the fan speed can be less than 1000 rpm, and it would take several seconds to accumulate a reasonably large and accurate count. Instead, the period of the fan revolution is measured by gating an on−chip 90 kHz oscillator into the input of a 16−bit counter for N periods of the fan TACH output (see Figure 47), so the accumulated count is actually proportional to the fan tachometer period and inversely proportional to the fan speed.
CLOCK
FAN 1
FAN 2
FAN 3
FAN 4
TACH1 TACH5
TACH2 TACH6
TACH3 TACH7
TACH4 TACH8
FAN 5
FAN 6
FAN 7
FAN 8
PWM3
PWM4
Figure 48. Synchronizing Fan PWM Output and TACH Inputs Driving and Measuring the Speed of One Fan from One PWM Output
1 2 3 4
PWM
TACH
Figure 47. Fan Speed Measurement
To enable continuous measurement for 3−wire fans, set the corresponding dc bit for the TACH input in the TACH configuration register. This bit is set automatically when the HF PWM is in use with 4−wire fans.
Fan Speed Measurement with Pulse Stretching
If four single fans are being controlled and measured by the ADT7462, the following configuration should be used. This applies only to 3−wire fans controlled using low frequency PWM with pulse stretching enabled. Fan 1 is driven by PWM1 and measured using TACH1. Fan 2 is driven by PWM2 and measured using TACH3. Fan 3 is driven by PWM3 and measured using TACH5. Fan 4 is driven by PWM4 and measured using TACH7.
PWM1 PWM2
The method for measuring fan speed for 3−wire fans requiring pulse stretching is similar to the method described in the Fan Speed Measurement without Pulse Stretching section for continuous measurements. The main difference is that the PWM drive must be synchronized to the TACH input so that the ADT7462 knows that pulse stretching is taking place while the TACH is being measured. PWM1 is synchronized with TACH1 and TACH2. PWM2 is synchronized with TACH3 and TACH4. PWM3 is synchronized with TACH5 and TACH6. PWM4 is synchronized with TACH7 and TACH8.
FAN 1
FAN 2
TACH1 TACH5
TACH3 TACH7
FAN 3
FAN 4
PWM3
PWM4
Figure 49. Driving and Measuring the Speed on a Single Fan
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The PWM output is pulse stretched until a valid TACH is read on both TACH inputs synchronized to the particular PWM output. If one fan is connected to one PWM output, the PWM output is pulse stretched until the counter has timed out on the disconnected TACH input. In this case, the pulse is stretching longer than necessary in an effort to sense a disconnected fan. The speed of the connected fan may be increased and an audible change in fan speed may be observed. There are two options to prevent the PWM output from being stretched longer than necessary in this case. • Connect the two synchronized TACH inputs together; for example, if PWM1 is driving a single fan being sensed on TACH1 only, connect TACH1 and TACH2 together. • Turn off pulse stretching on the unused TACH input; that is, if PWM1 is driving a single fan being sensed on TACH1 only, turn off pulse stretching on TACH 2 in Register 0x08. In this register: Bit 0 controls pulse stretching on TACH1 and TACH5. Bit 1 controls pulse stretching on TACH2 and TACH6. Bit 2 controls pulse stretching on TACH3 and TACH7. Bit 3 controls pulse stretching on TACH4 and TACH8. Note that the TACH assignments in this register differ from the TACHs synchronized to each PWM output. Therefore, if the intention is to drive and sense four fans, connecting the TACHs together as described in Option 1 allows pulse stretching on all channels. To enable fan speed measurements four times a second, set the FAST bit (Bit 0) of Configuration Register 2 (0x02). When the FAST bit is set, fan TACH readings are updated every 250 ms.
Fan Speed Measurement Registers Table 21. Tachometer Value and Limit Registers
TACH TACH1 TACH2 TACH3 TACH4 TACH5 TACH6 TACH7 TACH8 Low Byte Value Register 0x98 0x9A 0x9C 0x9E 0xA2 0xA4 0xA6 0xA8 High Byte Value Register 0x99 0x9B 0x9D 0x9F 0xA3 0xA5 0xA7 0xA9 8−Bit Limit Register 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F
Calculating Fan Speed
Assuming a fan with two pulses per revolution (and two pulses per revolution being measured), fan speed is calculated by:
Fan Speed(RPM) + (freq 60) Fan Tachometer Reading
(eq. 1)
where: Fan Tachometer Reading is the 16−bit fan tachometer reading. freq is the oscillator frequency, 90 kHz. Example: TACH1 high byte (Register 0x99) = 0x17 TACH1 low byte (Register 0x98) = 0xFF What is the speed of Fan 1 in rpm?
Fan 1 Tachometer Reading + 0 17FF + 6143 Decimal
(eq. 2)
RPM + (freq RPM + (90000
60) Fan 1 Tachometer Reading 60) 6143
(eq. 3) (eq. 4) (eq. 5)
Fan speed measurement involves a 2−register read for each measurement. The low byte should be read first. This causes the high byte to be frozen until both high and low byte registers have been read, preventing erroneous TACH readings. The fan tachometer reading registers report back the number of 11.11 ms period clocks (90 kHz oscillator) gated to the fan speed counter, from the rising edge of the first fan TACH pulse to the rising edge of the third fan TACH pulse (because two pulses per revolution are being counted). Because the device is essentially measuring the fan TACH period, the higher the count value, the slower the fan is actually running. A 16−bit fan tachometer reading of 0xFFFF indicates either that the fan has stalled or is running very slowly ( (OP1 – HYS) YES
NO
DO NOTHING
IS T1(n) – T1(n – 1) ≤ 0.25°C NO
YES
DO NOTHING (SYSTEM COOLING IS OFF OR CONSTANT)
IS T1(n) − T1(n − 1) = 0.5 − 0.755C IS T1(n) − T1(n − 1) = 1.0 − 1.755C IS T1(n) − T1(n − 1) > 2.05C
DECREASE T MIN BY 15C DECREASE T MIN BY 25C DECREASE T MIN BY 45C
Figure 68. Short Cycle Steps
Figure 69 shows the steps taken during the long cycle.
WAIT 2n MONITORING CYCLES CURRENT TEMPERATURE MEASUREMENT T1(n) OPERATING POINT TEMPERATURE OP1
IS T1(n) > OP1
YES
DECREASE TMIN BY 15C
NO IS T1(n) < LOW TEMP LIMIT AND TMIN < HIGH TEMP LIMIT YES AND TMIN < OP1 AND T1(n) > TMIN NO
INCREASE TMIN BY 15C
DO NOT CHANGE
Figure 69. Long Cycle Steps
Because neither the operating point minus the hysteresis temperature nor the low temperature limit has been exceeded, the TMIN value is not adjusted, and the fan runs at a speed determined by the fixed TMIN and TRANGE values defined in the automatic fan speed control mode. Example 2: Operating Point Exceeded, TMIN Reduced When the measured temperature is below the operating point temperature minus the hysteresis, TMIN remains the same. Once the temperature exceeds the operating temperature minus the hysteresis (OP − Hyst), TMIN starts to decrease as illustrated in Figure 71. This occurs during the short cycle (see Figure 68). The rate at which TMIN decreases depends on the programmed value of n. It also depends on how much the temperature has increased between this monitoring cycle and the last monitoring cycle; that is, if the temperature has increased by 1°C, then TMIN is reduced by 2°C. Decreasing TMIN has the effect of increasing the fan speed, thus providing more cooling to the system. If the temperature is slowly increasing only in the range (OP − Hyst), that is, ≤0.25°C per short monitoring cycle, then TMIN does not decrease. This allows small changes in temperature in the desired operating zone without changing TMIN. The long cycle makes no change to TMIN in the temperature range (OP − Hyst), because the temperature has not exceeded the operating temperature. When the temperature exceeds the operating temperature, the long cycle causes TMIN to be reduced by 1°C every long cycle while the temperature remains above the operating temperature. This takes place in addition to the decrease in TMIN that would occur due to the short cycle. In Figure 70, because the temperature is increasing at a rate ≤0.25°C per short cycle, no reduction in TMIN takes place during the short cycle.
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When the temperature falls below the operating temperature, TMIN stays the same. Even when the temperature starts to increase slowly, TMIN stays the same, because the temperature increases at a rate of ≤0.25°C per cycle.
THERM LIMIT HIGH TEMP LIMIT OPERATING POINT HYSTERESIS
Figure 72 shows how TMIN increases when the current temperature is above TMIN and below the low temperature limit, and TMIN is below the high temperature limit and below the operating point. When the temperature rises above the low temperature limit, TMIN stays the same.
THERM LIMIT HIGH TEMP LIMIT OPERATING POINT HYSTERESIS
ACTUAL TEMP
TMIN LOW TEMP LIMIT
NO CHANGE IN TMIN HERE DUE TO ANY CYCLE BECAUSE T1(n) – T1 (n – 1) ≤ 0.255C AND T1(n) < OP = > TMIN STAYS THE SAME
LOW TEMP LIMIT TMIN
ACTUAL TEMP
Figure 72. Increasing TMIN for Quieter Operation
DECREASE HERE DUE TO SHORT CYCLE ONLY T1(n) – T1 (n – 1) ≤ 0.255C OR 0.755C = > TMIN DECREASES BY 15C EVERY SHORT CYCLE
DECREASE HERE DUE TO LONG CYCLE ONLY T1(n) – T1 (n – 1) ≤ 0.255C AND T1(n) > OP = > TMIN DECREASES BY 15C EVERY LONG CYCLE
Figure 71. Effect of Exceeding Operating Point Minus Hysteresis Temperature
Example 3: Temperature Below Low Limit, TMIN Increased When the temperature drops below the low temperature limit, TMIN may increase, as shown in Figure 72. Increasing TMIN has the effect of running the fan more slowly and, therefore, more quietly. The long cycle diagram in Figure 69 shows the conditions that need to be true for TMIN to increase. The following is a quick summary of those conditions and the reasons they need to be true: TMIN may increase, if • The measured temperature has fallen below the low temperature limit. This means the user must choose the low limit carefully. It should not be so low that the temperature never falls below it, because TMIN would never increase and the fans would run faster than necessary. • TMIN is below the high temperature limit. TMIN is never allowed to increase above the high temperature limit. As a result, the high limit should be sensibly chosen, because it determines how high TMIN can go. • TMIN is below the operating point temperature. TMIN should never be allowed to increase above the operating point temperature, because the fans do not switch on until the temperature rises above the operating point. • The temperature is above TMIN. The dynamic TMIN control is turned off below TMIN.
Because TMIN is dynamically adjusted, it is undesirable for TMIN to reach full scale (191°C), because the fan would never switch on. As a result, TMIN is allowed to vary only within a specified range. • The lowest possible value for TMIN is −64°C. • TMIN cannot exceed the high temperature limit. • If the temperature is below TMIN, the fan is switched off or is running at minimum speed, and dynamic TMIN control is disabled.
THERM LIMIT OPERATING POINT HYSTERESIS
Example 4: Preventing TMIN from Reaching Full Scale
ACTUAL LOW TEMP TEMP LIMIT HIGH TEMP LIMIT TMIN
TMIN PREVENTED FROM INCREASING
Figure 73. TMIN Adjustments Limited by High Temperature Limit
Bits [1:0] of Dynamic TMIN Control Register 1 (0x0B) enable/disable dynamic TMIN control on the temperature channels (see Table 39). Bit 1 (Remote 2 En) = 1 enables dynamic TMIN control on the Remote 2 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. Bit 1 (Remote 2 En) = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted and the channel behaves as described in the Automatic Fan Control Overview section.
Dynamic TMIN Control Register 1 (0x0B)
Enabling Dynamic TMIN Control Mode
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Bit 0 (Remote 1 En) = 1 enables dynamic TMIN control on the Remote 1 temperature channel. The chosen TMIN value is dynamically adjusted based on the current temperature, operating point, and high and low limits for this zone. Bit 0 (Remote 1 En) = 0 disables dynamic TMIN control. The TMIN value chosen is not adjusted, and the channel behaves as described in the Automatic Fan Control Overview section.
Step 10—Monitoring THERM
temperatures can be copied into the operating point registers on a THERM assertion. Setting these bits to 1 uses the remote temperature as the operating point temperature, overwriting the programmed operating point value in the event of a THERM assertion. Setting these bits to 0 ignores a THERM assertion, and the operating point register remains at the programmed value.
Enhancing System Acoustics
Using the operating point limit ensures that the dynamic TMIN control mode is operating in the best possible acoustic position, while ensuring that the temperature never exceeds the maximum operating temperature. Using the operating point limit allows TMIN to be independent of system−level issues because of its self−corrective nature. In PC design, the operating point for the chassis is usually the worst−case internal chassis temperature. The optimal operating point for the processor is determined by monitoring the thermal monitor in the Intel Pentium 4 processor. To do this, the PROCHOT output of the Pentium 4 is connected to the THERM input of the ADT7462. The operating point for the processor can be determined by allowing the current temperature to be copied to the operating point register when the PROCHOT output pulls the THERM input low on the ADT7462. This gives the maximum temperature at which the Pentium 4 can run before clock modulation occurs.
Enabling the THERM Trip Point as the Operating Point
Automatic fan speed control mode reacts instantaneously to changes in temperature; that is, the PWM duty cycle responds immediately to temperature change. Any impulses in temperature can cause an impulse in fan noise. For psycho−acoustic reasons, the ADT7462 can prevent the PWM output from reacting instantaneously to temperature changes. Enhanced acoustic mode controls the maximum change in PWM duty cycle at a given time. The objective is to prevent the fan from cycling up and down, annoying the user.
Acoustic Enhancement Mode Overview
Bits [5:2] of Dynamic TMIN Control Register 1 (0x0B) enable/disable THERM monitoring to program the operating point. Table 39 details how the remote
Figure 74 gives a top−level overview of the automatic fan control circuitry on the ADT7462 and shows where acoustic enhancement fits in. Acoustic enhancement is intended as a post−design tweak made by a system or mechanical engineer evaluating best settings for the system. Having determined the optimal settings for the thermal solution, the engineer can adjust the system acoustics. The goal is to implement a system that is acoustically pleasing without causing user annoyance due to fan cycling. It is important to realize that although a system might pass an acoustic noise requirement specification (for example, 36 dB), if the fan is annoying, it fails the consumer test.
ACOUSTIC ENHANCEMENT
THERMAL CALIBRATION
100%
PWM MIN RAMP CONTROL (ACOUSTIC ENHANCEMENT)
PWM CONFIG PWM GENERATOR PWM1
TMIN REMOTE 2 = CPU TEMP
TRANGE
0% PWM MIN
THERMAL CALIBRATION
TACHOMETER 1 MEASUREMENT
100%
PWM CONFIG PWM GENERATOR
TACH1
CPU FAN SINK
MUX
0% PWM MIN
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 2 MEASUREMENT
PWM2
TMIN LOCAL = VRM TEMP
TRANGE
THERMAL CALIBRATION
PWM CONFIG PWM GENERATOR
TACH2
100%
RAMP CONTROL (ACOUSTIC ENHANCEMENT) TACHOMETER 3 AND 4 MEASUREMENT
FRONT CHASSIS PWM3
TMIN REMOTE 1 = AMBIENT TEMP
TRANGE
0%
TACH3
Figure 74. Acoustic Enhancement Smoothes Fan Speed Variations Under Automatic Fan Speed Control http://onsemi.com
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Approaches to System Acoustic Enhancement Effect of Ramp Rate on Enhanced Acoustic Mode
There are two different approaches to implementing system acoustic enhancement: temperature−centric and fan−centric. The temperature−centric approach involves smoothing transient temperatures as they are measured by a temperature source (for example, Remote 1 temperature). The temperature values used to calculate the PWM duty cycle values are smoothed, reducing fan speed variation. However, this approach causes an inherent delay in updating fan speed and causes the thermal characteristics of the system to change. It also causes the system fans to stay on longer than necessary, because the fan’s reaction is merely delayed. The user has no control over noise from different fans driven by the same temperature source. Consider, for example, a system in which control of a CPU cooler fan (on PWM1) and a chassis fan (on PWM2) uses Remote 1 temperature. Because the Remote 1 temperature is smoothed, both fans are updated at exactly the same rate. If the chassis fan is much louder than the CPU fan, there is no way to improve its acoustics without changing the thermal solution of the CPU cooling fan. The fan−centric approach to system acoustic enhancement controls the PWM duty cycle, driving the fan at a fixed rate (for example, 6%). Each time the PWM duty cycle is updated, it is incremented by a fixed 6%. As a result, the fan ramps smoothly to its newly calculated speed. If the temperature starts to drop, the PWM duty cycle immediately decreases by 6% at every update. Therefore, the fan ramps smoothly up or down without inherent system delay. Consider, for example, controlling the same CPU cooler fan (on PWM1) and chassis fan (on PWM2) using Remote 1 temperature. The TMIN and TRANGE settings have already been defined in automatic fan speed control mode; that is, thermal characterization of the control loop has been optimized. The chassis fan is noisier than the CPU cooling fan. Using the fan−centric approach, PWM2 can be placed into acoustic enhancement mode independently of PWM1. The acoustics of the chassis fan can, therefore, be adjusted without affecting the acoustic behavior of the CPU cooling fan, even though both fans are controlled by Remote 1 temperature. The fan−centric approach is how acoustic enhancement works on the ADT7462. Enabling Acoustic Enhancement for Each PWM Output
Enhanced Acoustics Register 1 (0x1A)
The PWM signal driving the fan has a period, t, given by the PWM drive frequency, f, because t = 1/f. For a given PWM period, t, the PWM period is subdivided into 255 equal time slots. One time slot corresponds to the smallest possible increment in the PWM duty cycle. A PWM signal of 33% duty cycle is, therefore, high for 1/3 × 255 time slots and low for 2/3 × 255 time slots. Therefore, a 33% PWM duty cycle corresponds to a signal that is high for 85 time slots and low for 170 time slots.
PWM_OUT 33% DUTY CYCLE 85 TIME SLOTS 170 TIME SLOTS PWM OUTPUT (ONE PERIOD) = 255 TIME SLOTS
Figure 75. 33% PWM Duty Cycle Represented in Time Slots
The ramp rates in the enhanced acoustics mode are selectable from 1 to 8. The ramp rates are discrete time slots. For example, if the ramp rate is 8, then eight time slots are added to the PWM high duty cycle each time the PWM duty cycle needs to be increased. If the PWM duty cycle value needs to be decreased, it is decreased by eight time slots. Figure 76 shows how the enhanced acoustics mode algorithm operates.
READ TEMPERATURE
CALCULATE NEW PWM DUTY CYCLE
IS NEW PWM VALUE > PREVIOUS VALUE? YES INCREMENT PREVIOUS PWM VALUE BY RAMP RATE
NO
DECREMENT PREVIOUS PWM VALUE BY RAMP RATE
Figure 76. Enhanced Acoustics Mode Algorithm
Bit 0 (En1) = 1 enables acoustic enhancement on PWM1 output. Bit 1 (En2) = 1 enables acoustic enhancement on PWM2 output.
Enhanced Acoustics Register 2 (0x1B)
Bit 0 (En3) = 1 enables acoustic enhancement on PWM3 output. Bit 1 (En4) = 1 enables acoustic enhancement on PWM4 output.
The enhanced acoustics mode algorithm calculates a new PWM duty cycle based on the temperature measured. If the new PWM duty cycle value is greater than the previous PWM value, the previous PWM duty cycle value is incremented by either 1, 2, 3, 5, 8, 12, 24, or 48 time slots, depending on the settings of the enhanced acoustics registers. If the new PWM duty cycle value is less than the previous PWM value, the previous PWM duty cycle is decremented by 1, 2, 3, 5, 8, 12, 24, or 48 time slots. Each time the PWM duty cycle is incremented or decremented, its value is stored as the previous PWM duty cycle for the next comparison.
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A ramp rate of 1 corresponds to one time slot, which is 1/255 of the PWM period. In enhanced acoustics mode, incrementing or decrementing by 1 changes the PWM output by 1/255 × 100%.
Step 11—Ramp Rate for Acoustic Enhancement
The optimal ramp rate for acoustic enhancement can be found through system characterization after the thermal optimization has been finished. The effect of each ramp rate should be logged, if possible, to determine the best setting for a given solution.
Enhanced Acoustics Register 1 (0x1A)
Bits [4:2] RR1 select the ramp rate for PWM1. 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots = 3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds Bits [7:5] RR2 select the ramp rate for PWM2. 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots = 3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds
Enhanced Acoustics Register 2 (0x1B)
Another way to view the ramp rates is to measure the time it takes for the PWM output to ramp up from 0% to 100% duty cycle for an instantaneous change in temperature. This can be tested by putting the ADT7462 into manual mode and changing the PWM output from 0% to 100% PWM duty cycle. The PWM output takes 35 seconds to reach 100% when a ramp rate of one time slot is selected. Figure 77 shows remote temperature plotted against PWM duty cycle for enhanced acoustics mode. The ramp rate is set to 48, which corresponds to the fastest ramp rate. Assume that a new temperature reading is available every 115 ms. With these settings, it takes approximately 0.76 seconds to go from 33% duty cycle to 100% duty cycle (full speed). Even though the temperature increases very rapidly, the fan ramps up to full speed gradually.
140 120 100 80 60 60 PWM CYCLE (%) 40 20 0 40 RTEMP (5C) 100 120
80
20
0
TIME (s)
0 0.76
Figure 77. Enhanced Acoustics Mode with Ramp Rate = 48
Bits [4:2] RR3 select the ramp rate for PWM3. 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots = 3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds Bits [7:5] RR4 select the ramp rate for PWM4. 000 = 1 time slot = 35 seconds 001 = 2 time slots = 17.6 seconds 010 = 3 time slots = 11.8 seconds 011 = 5 time slots = 7 seconds 100 = 8 time slots = 4.4 seconds 101 = 12 time slots = 3 seconds 110 = 24 time slots = 1.6 seconds 111 = 48 time slots = 0.8 seconds
Figure 78 shows how changing the ramp rate from 48 to 8 affects the control loop. The overall response of the fan is slower. Because the ramp rate is reduced, it takes longer for the fan to achieve full running speed. In this case, it takes approximately 4.4 seconds for the fan to reach full speed.
120 RTEMP (5C) 100 140 120 100 PWM DUTY CYCLE (%) 60 60 40 40 20 20 0 80
80
0
0
TIME (s)
4.4
Figure 78. Enhanced Acoustics Mode with Ramp Rate = 8
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Figure 79 shows the PWM output response for a ramp rate of 2. In this instance, the fan takes about 17.6 seconds to reach full running speed.
140 RTEMP (5C) 120 100 80 PWM DUTY CYCLE (%) 60 40 20 0 0 TIME (s) 40 60 100 120 90 80 70 60 50 40 30 20 10 0 20 0 RTEMP (5C) PWM DUTY CYCLE (%)
80
Figure 81. How Fan Reacts to Temperature Variations in Enhanced Acoustics Mode Slower Ramp Rates
17.6
Figure 79. Enhanced Acoustics Mode with Ramp Rate = 2
Figure 80 shows how the control loop reacts to temperature with the slowest ramp rate. The ramp rate is set to 1, while all other control parameters remain the same. With the slowest ramp rate selected, it takes 35 seconds for the fan to reach full speed.
120 RTEMP (5C) 100 120 100 80 80 60 PWM DUTY CYCLE (%) 40 60 40 20 0 140
The ADT7462 can be programmed for much longer ramp times by slowing the ramp rates. Each ramp rate can be slowed by a factor of 4. PWM1 Configuration Register (0x21) PWM2 Configuration Register (0x22) PWM3 Configuration Register (0x23) PWM4 Configuration Register (0x24) Setting Bit 3 (the SLOW bit) to 1 in the PWM1 to PWM4 configuration registers slows the ramp rate for PWM1 to PWM4 by 4.
Fan Freewheeling Test Mode
20
0 0 TIME (s)
35
Figure 80. Enhanced Acoustics Mode with Ramp Rate = 1
As Figure 77 to Figure 80 show, the rate at which the fan reacts to temperature change is dependent on the ramp rate selected in the enhanced acoustics registers. The higher the ramp rate, the faster the fan reaches the newly calculated fan speed. Figure 81 shows the behavior of the PWM output as temperature varies. As the temperature increases, the fan speed ramps up. Small drops in temperature do not affect the ramp−up function, because the newly calculated fan speed is still higher than the previous PWM value. Enhanced acoustics mode allows the PWM output to be made less sensitive to temperature variations. This is dependent on the ramp rate selected and programmed into the enhanced acoustics registers.
The fan freewheeling test mode is intended to diagnose whether fans connected to the ADT7462 are working properly. It is particularly useful where fans coupled in the duct can affect the airflow of another fan. If one fan has failed, it may not be apparent, because moving air from other fans can cause air to flow through the faulty fan, which in turn can cause the faulty fan to rotate. The fan freewheeling test is most useful in a system using primary and redundant setup. In such a system, the following setup is recommended. The primary fans are Fan 1, Fan 2, Fan 3, and Fan 4. The redundant fans are Fan 5, Fan 6, Fan 7, and Fan 8. In this setup, each primary and redundant fan can be driven separately because they are driven by different PWMs.
PWM 1 PWM 2
FAN 1 TACH CCT 1 FAN 5
FAN 2 TACH CCT 2 FAN 6
FAN 3 TACH CCT 3 FAN 7
FAN 4 TACH CCT 4 FAN 8
PWM 3
PWM 4
Figure 82. Fan Freewheeling Test Mode Setup
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The freewheeling test procedure is as follows: 1. PWM1 and PWM2 go to full speed, and PWM3 and PWM4 are switched off. 2. After the spin−up time of PWM1 and PWM2 has elapsed, the speed of Fan 1, Fan 2, Fan 3, and Fan 4 is measured. 3. After the speed of Fan 1 and Fan 2 is measured, PWM1 is switched off and PWM3 is spun up. After the spin−up time for PWM3 has elapsed, the speed of Fan 5 and Fan 6 is measured. 4. After the speed of Fan 3 and Fan 4 is measured, PWM2 is switched off and PWM4 is switched on. After the spin−up time of PWM4 has elapsed, the speed of Fan 7 and Fan 8 is measured. 5. After the speed of all eight fans has been measured, the TACH and PWM configurations return to their previous values. • Fans must be in continuous mode for the freewheeling test; that is, the dc bits must be set (Register 0x08). • To enable the freewheeling test, set the freewheeling test enable register (0x1E) to a nonzero value. Set Bit 0 = 1 to enable the freewheeling test for Fan 1, and set Bit 1 for Fan 2, all the way to Bit 7 for Fan 8. The freewheeling test enable register should be programmed after the fans present register is programmed. If the fans present register is not programmed first, then the values in the two registers do not match, and the ADT7462 assumes that a fan is missing. The following registers must be programmed for the fan freewheeling test: Fans Present Register (0x1D) Set Bit 0 to 1 when a fan is connected to TACH1. Set Bit 1 to 1 when a fan is connected to TACH2. Set Bit 2 to 1 when a fan is connected to TACH3. Set Bit 3 to 1 when a fan is connected to TACH4. Set Bit 4 to 1 when a fan is connected to TACH5. Set Bit 5 to 1 when a fan is connected to TACH6. Set Bit 6 to 1 when a fan is connected to TACH7. Set Bit 7 to 1 when a fan is connected to TACH8. Fan Freewheeling Test Enable Register (0x1E) Set Bit 0 to 1 to enable the freewheeling test for Fan 1. Set Bit 1 to 1 to enable the freewheeling test for Fan 2. Set Bit 2 to 1 to enable the freewheeling test for Fan 3. Set Bit 3 to 1 to enable the freewheeling test for Fan 4. Set Bit 4 to 1 to enable the freewheeling test for Fan 5. Set Bit 5 to 1 to enable the freewheeling test for Fan 6. Set Bit 6 to 1 to enable the freewheeling test for Fan 7. Set Bit 7 to 1 to enable the freewheeling test for Fan 8. Fan Freewheeling Test Register (0x1C) Both the Fans Present register (0x1D) and the freewheeling test enable register (0x1E) should be programmed before setting the relevant bits in the fan freewheeling test register (0x1C). The host fan status register (0xBD) should be read directly after completion of the test.
THERM I/O Operation
This section describes the operation of THERM1 and THERM2. Pin 28 and Pin 29 can both be configured as THERM inputs or outputs.
THERM Output THERM is not enabled as an output by default on powerup,
but it can be enabled by setting the appropriate bits in Register 0x0E (THERM1 configuration register) and Register 0x0F (THERM2 configuration register). THERM1 and THERM2 can be configured to assert whenever a specific channel exceeds the specified THERM limit (see Table 30).
Table 26. THERM Output Channel Select and Limits
Configuration Channel Enable Local Remote 1 Remote 2 Remote 3 THERM1, Register 0x0E Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 THERM2, Register 0x0F Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Bit 4 = 1 Limit Registers THERM1 THERM2
0x4C 0x4D 0x4E 0x4F
0x50 0x51 0x52 0x53
As an output, THERM is asserted low to signal that the measured THERM temperature has exceeded pre− programmed THERM temperature limits. The output is automatically pulled high again when the temperature falls below the (THERM − Hysteresis) limit. The value of hysteresis for each channel is programmable in Register 0x54 and Register 0x55, where 1 LSB = 1°C, and the maximum hysteresis for each channel is 15°C. Setting the THERM boost bits, Bit 0 and Bit 1, to Logic 0 (default setting) in the THERM configuration register (0x0D), sets the fans to full speed on an internal THERM event.
THERM Input
To configure THERM as an input, the THERM1_Timer_Enable (T1TE) bit (Bit 0) in the THERM1 configuration register (0x0E) and the THERM2_Timer_Enable (T2TE) bit (Bit 0) in the THERM2 configuration register (0x0F) must be set to Logic 1. The ADT7462 can then be used to detect when the THERM pins are asserted low. The THERM pins can be connected to a trip point temperature sensor or to the PROCHOT output of a CPU. With processor core voltages reducing all the time, the threshold for the AGTL + PROCHOT output is also reduced as new processors become available. Because the THERM input is typically an AGTL + input, the thresholds can be referenced to VCCP. By setting Bit 4 of Configuration Register 3 (0x03) to 1, the THERM threshold is 2/3 × VCCP, the correct threshold for an AGTL + signal. The THERM assert bits in Host Thermal Status Register 2
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(0xB9) are set to Logic 1 whenever the THERM input is asserted low. The THERM state bits in Host Thermal Status Register 2 (0xB9) indicate that a high−to−low transition has taken place on the THERM pin.
TEMPERATURE 1005C 905C 805C 705C 605C 505C 405C ALERT THERM 1 2 3 RESET BY MASTER 4 THERM LIMIT HIGH TEMP LIMIT THERM LIMIT HYSTERESIS
When the measured percentage exceeds the corresponding percentage limit, the T1% bit in Host Thermal Status Register 2 (0xB9) is asserted, and an ALERT is generated (that is, if the mask bit is not set). If the limit is set to 0x00, an ALERT is generated on the first assertion. If the limit is set to 0xFF, an ALERT is never generated because 0xFF corresponds to the THERM input being asserted all the time. When THERM is configured as an input only, setting Bits [4:1] of the THERM zone in the THERM1 configuration register (0x0E) and the THERM2 configuration register (0x0F) allows Pin 28/Pin 29 to operate as an I/O.
THERM Timer Limit Register
Figure 83. THERM Behavior THERM Timer
The ADT7462 can also measure assertion times on the THERM inputs as a percentage of a timer window. The timer window for the THERM1 input is programmed using Bits [4:2] of the THERM configuration register (0x0D). The timer window for the THERM2 input is programmed using Bits [7:5] of the THERM configuration register (0x0D). Values from 0.25 sec to 8 sec are programmable (see Table 27).
Table 27. THERM Timer Window
Code 000 001 010 011 100 101 110 111 THERM Timer Window 0.25 sec 0.5 sec 1 sec 2 sec 4 sec 8 sec 8 sec 8 sec
The THERM timer limit is programmed to Register 0x80 and Register 0x81. If THERM is asserted for longer than the programmed percentage limit, then an ALERT is generated. The limit is programmed as a percentage of the chosen THERM timer window. EXAMPLE: The THERM timer window is eight seconds, and an ALERT should be generated if THERM is asserted for more than one second.
%Limit + 1 8 0 00 + 0%; 0 100 + 12.5% FF + 100%
The THERM timer limit register is an 8−bit register. Therefore, 1 LSB = 0.39%
12.5% + 32 decimal + 0 0.39% 20 + 00100000
When the time window has elapsed, if the THERM limit has been exceeded, then an ALERT is generated.
General−Purpose I/O Pins
The assertion time as a percentage of the timer window is stored in the THERM % on−time registers. This is a cumulative sum of the percentage of time during the THERM timer window that THERM is asserted. The % on−time and associated timer limit registers are listed in Table 28.
Table 28. THERM On−Time and Timer Limit Register
Channel THERM1 THERM2 % On−Time Register 0xAE 0xAF % Timer Limit Register 0x80 0x81
The ADT7462 has eight open−drain GPIO pins. GPIO1 to GPIO4 can be configured to enable event driven outputs (EDOs), and GPIO5 and GPIO6 can act as EDOs, if the EDO functionality is enabled. Two other GPIOs (GPIO7 and GPIO8) are standard GPIO pins that are dedicated to general−purpose logic input/output. Each GPIO pin has five data bits associated with it: three bits in a GPIO configuration register (0x09 and 0x0A), one in the GPIO status register (0xBF), and one in the GPIO mask register (0x36). Setting a direction bit to 1 in a GPIO configuration register makes the corresponding GPIO pin an output. Clearing the direction bit to 0 makes the corresponding GPIO pin an input. Setting a polarity bit to 1 in a GPIO configuration register makes the corresponding GPIO pin active high. Clearing the polarity bit to 0 makes the corresponding GPIO pin active low. When a GPIO pin is configured as an input, the corresponding bit in the GPIO status register is read−only, and it is set when the input is asserted (“asserted” can be high or low, depending on the setting of the polarity bit).
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When a GPIO pin is configured as an output, the corresponding bit in the GPIO status register becomes read/write. Setting this bit then asserts the GPIO output. (Again, “asserted” can be high or low, depending on the setting of the polarity bit.) The effect of a GPIO status register bit on the ALERT output can be masked by setting the corresponding bit in one of the GPIO mask registers. When the pin is configured as an output, the corresponding status bit is automatically masked to prevent the data written to the status bit from causing an interrupt. When configured as inputs, the GPIO pins can be connected to external interrupt sources such as temperature sensors with digital output.
EDO Circuitry
The polarity of the EDOs is set in the GPIO configuration registers (0x09 and 0x0A). Setting a polarity bit to 1 in one of the GPIO configuration registers makes the corresponding GPIO pin active high. Clearing the polarity bit to 0 makes it active low.
GPIO1 GPIO2 GPIO3 GPIO4 LATCH EVENT MASK
EDO (GPIO5) EDO (GPIO6)
Figure 84. EDO Circuit
The ADT7462 has the added functionality that the assertion of one of the four GPIOs (GPIO1 to GPIO4) can be used to latch one of the two EDOs high or low. The ADT7462 has two EDO event mask registers (0x37 and 0x38): one mask for each EDO. See Table 29 for an explanation of event mask register functionality.
Bit 7: Overvoltage/ Undervoltage 0 = Drive Output X 1 = Ignore Event
Bits [7:5] of each event mask register (0x37 and 0x38) allow the EDO output to be driven high or low (depending on the polarity bit of the configuration register) and latched (depending on the EDO latch bit of the configuration register), if the ADT7462 detects an overtemperature, an over/undervoltage, or a fan failure condition.
Table 29. EDO Control (Mask) Register 0x37 and Register 0x38
Bit 6: THERM 0 = Drive Output X 1 = Ignore Event Bit 5: Fan Fail 0 = Drive Output X 1 = Ignore Event Bit 3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Behavior: What Drives and Latches Output X (G = GPIO) G4 or G3 or G2 or G1 G4 or G3 or G2 G4 or G3 or G1 G4 or G3 G4 or G2 or G1 G4 or G2 G4 or G1 G4 G3 or G2 or G1 G3 or G2 G3 or G1 G3 G2 or G1 G2 G1 GPIO events ignored by Output X
Table 29 shows that any of the four designated GPIO pins can be used to set or reset either one of the two EDO outputs. Using this functionality, it is possible to have the ADT7462 drive LEDs or signals based on rules. For example, if a GPIO1 (power fail), a GPIO2 (overcurrent), or an overtemperature condition occurs, EDO1 (power supply fault LED) can be latched. This does not require software handling and makes the part more autonomous.
Other Digital Inputs
monitored and configured for actions to occur on their assertion.
VR_HOT Inputs
The ADT7462 contains other specific digital inputs that can be found on PC motherboards. These inputs can be
Pin 25 and Pin 26 can be configured as VR_HOT inputs. These are specific digital signals from the CPU voltage regulator that indicate an overtemperature. On assertion of these inputs, the relevant status bits are set in Thermal Status Register 2 (Host Register 0xB9 or BMC Register 0xC1). Assertion of these inputs can also be used to boost the fans to full speed, thus providing emergency cooling in the event of VR overtemperature. This is set using Bit 3 (VRD1) and
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Bit 4 (VRD2) of Configuration Register 2 (0x02). There is also an associated mask bit in Register 0x31 to mask the assertion of these inputs from the ALERT output.
SCSI_TERM Inputs Chassis Intrusion Input
Pin 16 and Pin 20 can be configured as SCSI_TERM inputs. An assertion on the SCSI_TERM is recorded in Bit 4 and Bit 5 of Host Digital Status Register (0xBE) or BMC Digital Status Register (0xC6). There is also an associated mask bit in Register 0x35 to mask the assertion of these inputs from the ALERT output.
Reset I/O
The ADT7462 includes an active low reset pin (Pin 14). The RESET pin can be both a reset input and output. RESET monitors the VCC input to the ADT7462. At powerup, RESET is asserted (pulled low) until 180 ms after the power supply has risen above the supply threshold. A power−on reset initializes all registers to the default values.
VCC 1.0 V
RESET
180 ms
Figure 85. Operation of RESET Output on Powerup
The RESET pin can also function as a reset input. Pulling this pin low externally resets the ADT7462. The user should wait at least 180 ms after powerup before doing a hardware reset. The reset pulse width should be greater than 0.8 ms to ensure that a reset is registered. A hardware reset differs from a power−on reset in that not all of the registers are reinitialized to the default values. For example, limit registers are not all restored to the default values. This can be useful if the user needs to reset the part but does not want to completely reprogram the device. The Register Map section show, which registers, are reset. Locked registers are not restored to default values by a hardware reset. Note that if two ADT7462 devices are used in one system, the RESET pins should not be connected together between devices. Doing so causes one device to reset the other on a power−on reset.
Software Reset
The chassis intrusion (CI) input is an active high input intended for detection and signaling of unauthorized tampering with the system. When this input goes high, the event is latched in Bit 7 of Host Digital Status Register (0xBE), and an interrupt is generated. The bit remains set until cleared by writing a 1 to CI reset (CI_R), Bit 5 of Configuration Register 3 (0x03). The CI reset bit is cleared by writing a 0 to it. The CI circuit is powered from the VBATT voltage channel. Pin 26 must be configured to monitor VBATT and a battery must be connected to monitor CI events. CI monitoring is disabled if the measured VBATT value (0x93) is less than the lower voltage limit (0x75) of Pin 26. The CI input detects chassis intrusion events even when the ADT7462 is powered off (provided battery voltage is applied to VBATT) but does not immediately generate an interrupt. When a chassis intrusion event is detected and latched, an interrupt is generated when the system is powered on. The actual detection of chassis intrusion is performed by an external circuit that detects, for example, when the cover has been removed. A wide variety of techniques can be used for chassis detection. For example, • A microswitch that opens or closes when the cover is removed • A reed switch operated by a magnet affixed to the cover • A hall−effect switch operated by a magnet affixed to the cover • A photo−transistor that detects light when the cover is removed
Powerup Sequence
The ADT7462 can be reset in software by setting Bit 7 of Configuration Register 0 (0x00). The code 0x6D must be written to Register 0x7B before setting the software reset bit. This register is cleared to the power−on default after the software reset. Note that not all registers are restored to their default values on a reset. The same registers are reset by a hardware and software reset. The Register Map section provides a complete reference of registers that are reset.
The powerup sequence of the ADT7462 is as follows: 1. The temperature of the thermal diode connected to Pin 17 and Pin 18 (only dedicated thermal diode channel) is monitored immediately on powerup of the ADT7462. Ideally, the hottest zone should be connected to this channel so protection is provided immediately on powerup. 2. VCCP1 is also monitored immediately on powerup. VCCP1 is typically connected to a main power rail. Switching on the VCCP1 rail gates the fan’s quiet startup counter. 3. VBATT is monitored immediately on powerup before the setup complete bit (Register 0x01, Bit 5) is set. The chassis intrusion circuit (CI) is powered from VBATT. If the measured VBATT reading is lower than the lower limit (default = 0x80), the CI circuit is turned off. 4. PWM1, PWM2, and PWM4 are not on dedicated pins. Because these pins are shared with inputs, they are allowed to float high on powerup. This means that if a fan is connected to these pins, it spins at full speed on powerup.
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5. PWM3 is switched off by default (because this is a dedicated pin). If no SMBus communication takes place within 4.6 seconds of the VCCP rail switching on, this PWM drive is driven to full speed. If SMBus communication does take place, this pin behaves as programmed. 6. No temperature or voltage (other than VCCP1, Diode 2, and VBATT) is monitored until the setup complete bit (Bit 5) is set in Configuration Register 1 (0x01). This allows the user to program the ADT7462 as required before monitoring of all channels is enabled, thereby not generating false ALERTs. The setup complete bit should not be set until the device is fully configured for the desired monitoring functions. The following steps describe how to set up the ADT7462: 1. Powerup the device. 2. Choose the best−suited easy configuration option for the application, changing pin functions as required.
PIN 1 PIN 2
3. Program all appropriate limits for monitored inputs. Program device parameters, fan control parameters, mask bits, and anything else required for the application. 4. Set the setup complete bit. Do not set this bit until the device is fully set up.
XOR Tree Test
The ADT7462 includes an XOR tree test mode. This mode is useful for in−circuit test equipment at board−level testing. By applying stimulus to the pins included in the XOR test, it is possible to detect opens or shorts on the system board. Figure 86 shows the signals exercised in the XOR tree test. The XOR tree test is invoked by setting Bit 6 (XOR) of Configuration Register 3 (0x03). Note that the digital inputs must be selected on multifunctional pins for the XOR tree test mode. Pin 13 is the open−drain output of the XOR tree test.
PIN 25
PIN 3
PIN 26
PIN 4
PIN 27
PIN 7
PIN 28
PIN 8
PIN 29
PIN 16
PIN 31 PIN 13
PIN 20
PIN 32
PIN 21
PIN 22
Figure 86. XOR Tree Test
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Register Tables Table 30. Register Map
Addr
0x00 0x01 0x02 0x03 0x07 0x08 0x09 0x0A 0x0B 0x0C
Description Config 0 Config 1 Config 2 Config 3 TACH Enable TACH Config GPIO1_ Bhvr GPIO2_ Bhvr TMIN_Cal1 TMIN_Cal2 THERM Conf Conf_ THERM1 Conf_ THERM2 Pin Conf 1 Pin Conf 2 Pin Conf 3 Pin Conf 4 Easy Conf EDO Enable Attenuators 1 En Attenuators 2 En Enhanced Acoustics 1 Enhanced Acoustics 2 Fan Freewheel Test Fans Present Fan Freewheel TestEn PWM1 Config PWM2 Config PWM3 Config PWM4 Config PWM1, PWM2 Freq PWM3, PWM4 Freq PWM1 Min
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7
SW Reset RDY #FP V_Core_ Low T8E Res D4 D8 Res Res
Bit 6
VID Lock #FP XOR T7E Res P4 P8 Res Ctrl Loop Select TW2 Res Res D1 Pin 13 Pin 24 Pin 28 Res CS Pin 21 Res RR2 RR4 Fan 7 F7P Fan 7
Bit 5
# Bytes SC FMS CI_R T6E Res D3 D7 P2R2 CYR2
Bit 4
# Bytes DFS VRD2 TT T5E Res P3 P7 P2R1 CYR2
Bit 3
#Bytes ALERT VRD1 VID_T T4E DC 4/8 D2 D6 P1R2 CYR2
Bit 2
# Bytes Res PWM SDA T3E DC 3/7 P2 P6 P1R1 CYR1
Bit 1
# Bytes Res Res SCL T2E DC 2/6 D1 D5 R2 CYR1
Bit 0
# Bytes Mon FAST GPIO T1E DC 1/5 P1 P5 R1 CYR1
De− fault
0x20 0x81 0x80 0x00 0x00 0x0F 0x00 0x00 0x00 0x40
SW Reset
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Lock able
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x16 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TW2 Res Res VID Pin 8 Pin 24 Pin 28 Res CS Pin 22 Res RR2 RR4 Fan 8 F8P Fan 8
TW2 Res Res D3 Pin 15 Pin 25 Pin 29 Res CS Pin 19 Pin 29 RR2 RR4 Fan 6 F6P Fan 6
TW1 R3 R3 Pin 1 Pin 19 Pin 25 Pin 29 Op5 CS Pin 15 Pin 28 RR1 RR3 Fan 5 F5P Fan 5
TW1 R2 R2 Pin 2 Pin 21 Pin 26 Pin 31 Op4 CS Pin 13 Res RR1 RR3 Fan 4 F4P Fan 4
TW1 R1 R1 Pin 3 Pin 22 Pin 26 Pin 32 Op3 SC Pin 8 Pin 25 RR1 RR3 Fan 3 F3P Fan 3
B2 Local Local Pin 4 Pin 23 Pin 27 Res Op2 EDO2 Pin 7 Pin 24 En2 En4 Fan 2 F2P Fan 2
B1 T1TE T2TE Pin 7 Pin 23 Res Res Op1 EDO1 Res Pin 23 En1 En3 Fan 1 F1P Fan 1
0x00 0x00 0x00 0x7F 0xCE 0x42 0xFC 0x01 0x00 0xFF 0x37 0x00 0x00 0x00 0x00 0x00
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
0x21 0x22 0x23 0x24 0x25
R/W R/W R/W R/W R/W
BHVR BHVR BHVR BHVR F2
BHVR BHVR BHVR BHVR F2
BHVR BHVR BHVR BHVR F2
INV INV INV INV F1
SLOW SLOW SLOW SLOW F1
Spin Spin Spin Spin F1
Spin Spin Spin Spin Min 2
Spin Spin Spin Spin Min 1
0x11 0x31 0x51 0x71 0x90
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
0x26
R/W
F4
F4
F4
F3
F3
F3
Min 4
Min 3
0x90
Yes
Yes
0x28
R/W
7
6
5
4
3
2
1
0
0x80
Yes
Yes
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Table 30. Register Map
Addr
0x29 0x2A 0x2B 0x2C 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x3D 0x3E 0x3F 0x44 0x45
Description PWM2 Min PWM3 Min PWM4 Min PWM1 to PWM4 Max Thermal Mask 1 Thermal Mask 2 Voltage Mask 1 Voltage Mask 2 Fan Mask Digital Mask GPIO Mask EDO Mask 1 EDO Mask 2 Device ID Comp ID Rev No Local Low Temp Limit Remote 1/Pin 15 Low Temp Limit Remote 2 Low Temp Limit Remote 3/Pin 19 Low Temp Limit Local High Limit Remote 1/Pin 15 High Limit Remote 2 High Limit Remote 3/Pin 19 High Limit Local THERM1/ +1.5V2 (3GIO) High Remote 1 THERM1 Limit Remote 2 THERM1 Limit Remote 3 THERM1 Limit
R/W
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R/W R/W
Bit 7
7 7 7 7 R3D VRD2 P23 +1.5V1 (ICH) Fan 8 CI GPIO8 Volt Volt 7 7 7 7 7
Bit 6
6 6 6 6 R2D VRD1 +5V +1.5V2 (3GIO) Fan 7 VID GPIO7 Temp Temp 6 6 6 6 6
Bit 5
5 5 5 5 R1D T2S P19 P26 Fan 6 SCSI2 GPIO6 Fan Fan 5 5 5 5 5
Bit 4
4 4 4 4 R3 T2A P15 P25 Fan 5 SCSI1 GPIO5 Res Res 4 4 4 4 4
Bit 3
3 3 3 3 R2 T2% +3.3V P24 Fan 4 FAN2MAX GPIO4 GPIO4 GPIO4 3 3 3 3 3
Bit 2
2 2 2 2 R1 T1S +12V3 Res Fan 3 Res GPIO3 GPIO3 GPIO3 2 2 2 2 2
Bit 1
1 1 1 1 Local T1A +12V2 Res Fan 2 Res GPIO2 GPIO2 GPIO2 1 1 1 1 1
Bit 0
0 0 0 0 Res T1% +12V1 Res Fan 1 Res GPIO1 GPIO1 GPIO1 0 0 0 0 0
De− fault
0x80 0x80 0x80 0xC0 0x00 0xC0 0x00 0x00 0x00 0x38 0x00 0x00 0x00 0x62 0x41 0x04 0x40 0x40
SW Reset
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No
Lock able
Yes Yes Yes Yes No No No No No No No No No N/A N/A N/A No No
0x46
R/W
7
6
5
4
3
2
1
0
0x40
No
No
0x47
R/W
7
6
5
4
3
2
1
0
0x40
No
No
0x48 0x49
R/W R/W
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
0x95 0x95
No No
No No
0x4A 0x4B
R/W R/W
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
0x95 0x95
No No
No No
0x4C
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
0x4D
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
0x4E
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
0x4F
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
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Table 30. Register Map
Addr
0x50
Description Local THERM2/ +1.5V1 (ICH) High Remote 1 THERM2 Limit Remote 2 THERM2 Limit Remote 3 THERM2 Limit Local/Remote1 Temp Hyst Remote 2/ Remote 3 Temp Hyst Local Offset Remote 1 Offset Remote 2 Offset Remote 3 Offset Remote 1 Operating Point Remote 2 Operating Point Local Temp TMIN Remote 1 Temp TMIN Remote 2 Temp TMIN Remote 3 Temp TMIN Local TRANGE/ Hyst Remote 1 TRANGE/ Hyst Remote 2 TRANGE/ Hyst Remote 3 TRANGE/ Hyst Operating Point Hyst +3.3V High Limit Pin 23 Voltage High Limit Pin 24 Voltage High Limit Pin 25 Voltage High Limit
R/W
R/W
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
De− fault
0xA4
SW Reset
No
Lock able
Yes
0x51
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
0x52
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
0x53
R/W
7
6
5
4
3
2
1
0
0xA4
No
Yes
0x54
R/W
LH
LH
LH
LH
R1H
R1H
R1H
R1H
0x44
No
Yes
0x55
R/W
R2H
R2H
R2H
R2H
R3H
R3H
R3H
R3H
0x44
No
Yes
0x56 0x57 0x58 0x59 0x5A
R/W R/W R/W R/W R/W
7 7 7 7 7
6 6 6 6 6
5 5 5 5 5
4 4 4 4 4
3 3 3 3 3
2 2 2 2 2
1 1 1 1 1
0 0 0 0 0
0x00 0x00 0x00 0x00 0xA4
No No No No Yes
Yes Yes Yes Yes Yes
0x5B
R/W
7
6
5
4
3
2
1
0
0xA4
Yes
Yes
0x5C 0x5D 0x5E 0x5F 0x60
R/W R/W R/W R/W R/W
7 7 7 7 Range
6 6 6 6 Range
5 5 5 5 Range
4 4 4 4 Range
3 3 3 3 Hys
2 2 2 2 Hys
1 1 1 1 Hys
0 0 0 0 Hys
0x9A 0x9A 0x9A 0x9A 0xC4
Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes
0x61
R/W
Range
Range
Range
Range
Hys
Hys
Hys
Hys
0xC4
Yes
Yes
0x62
R/W
Range
Range
Range
Range
Hys
Hys
Hys
Hys
0xC4
Yes
Yes
0x63
R/W
Range
Range
Range
Range
Hys
Hys
Hys
Hys
0xC4
Yes
Yes
0x64 0x68 0x69
R/W R/W R/W
Hys 7 7
Hys 6 6
Hys 5 5
Hys 4 4
Res 3 3
Res 2 2
Res 1 1
Res 0 0
0x40 0xFF 0xFF
Yes No No
Yes No No
0x6A
R/W
7
6
5
4
3
2
1
0
0xFF
No
No
0x6B
R/W
7
6
5
4
3
2
1
0
0xFF
No
No
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56
ADT7462
Table 30. Register Map
Addr
0x6C
Description Pin 26 Voltage High Limit +12V1 Low Limit +12V2 Low Limit +12V3 Low Limit +3.3V Low Limit +5V Low Limit Pin 23 Voltage Low Limit Pin 24 Voltage Low Limit Pin 25 Voltage Low Limit Pin 26 Voltage Low Limit +1.5V1 (ICH) Low Limit +1.5V2 (3GIO) Low Limit TACH1 Limit/VID TACH2 Limit TACH3 Limit TACH4 Limit TACH5/+12 V1 High Limit TACH6/+12 V2 High Limit TACH7/+5V High Limit TACH8/+12 V3 High Limit THERM1 Timer Limit THERM2 Timer Limit Local Temp Value, LSBs Local Temp Value, MSBs Remote 1 Temp, LSBs
R/W
R/W
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
De− fault
0xFF
SW Reset
No
Lock able
No
0x6D 0x6E 0x6F 0x70 0x71 0x72
R/W R/W R/W R/W R/W R/W
7 7 7 7 7 7
6 6 6 6 6 6
5 5 5 5 5 5
4 4 4 4 4 4
3 3 3 3 3 3
2 2 2 2 2 2
1 1 1 1 1 1
0 0 0 0 0 0
0x00 0x00 0x00 0x00 0x00 0x20
No No No No No No
No No No No No No
0x73
R/W
7
6
5
4
3
2
1
0
0x00
No
No
0x74
R/W
7
6
5
4
3
2
1
0
0x00
No
No
0x75
R/W
7
6
5
4
3
2
1
0
0x80
No
No
0x76
R/W
7
6
5
4
3
2
1
0
0x00
No
No
0x77
R/W
7
6
5
4
3
2
1
0
0x00
No
No
0x78 0x79 0x7A 0x7B 0x7C
R/W R/W R/W R/W R/W
7 7 7 7 7
6 6 6 6 6
5 5 5 5 5
4 4 4 4 4
3 3 3 3 3
2 2 2 2 2
1 1 1 1 1
0 0 0 0 0
0xFF 0xFF 0xFF 0xFF 0xFF
No No No No No
Yes Yes Yes Yes Yes
0x7D
R/W
7
6
5
4
3
2
1
0
0xFF
No
Yes
0x7E 0x7F
R/W R/W
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
0xFF 0xFF
No No
Yes Yes
0x80 0x81 0x88
R/W R/W R
7 7 7
6 6 6
5 5 5
4 4 4
3 3 3
2 2 2
1 1 1
0 0 0
0xFF 0xFF 0x00
No No No
Yes Yes No
0x89
R
7
6
5
4
3
2
1
0
0x00
No
No
0x8A
R
7
6
5
4
3
2
1
0
0x00
No
No
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57
ADT7462
Table 30. Register Map
Addr
0x8B
Description Remote 1 Temp, MSBs, Pin 15 Volt Remote 2 Temp, LSBs Remote 2 Temp, MSBs Remote 3 Temp, LSBs Remote 3 Temp, MSBs, Pin 19 Volt Pin 23 Voltage Pin 24 Voltage Pin 25 Voltage Pin 26 Voltage +1.5V1 (ICH) Volt +1.5V2 (3GIO) Voltage +3.3V Voltage VID Value TACH1 Value, LSBs TACH1 Value, MSBs TACH2 Value, LSBs TACH2 Value, MSBs TACH3 Value, LSBs TACH3 Value, MSBs TACH4 Value, LSBs TACH4 Value, MSBs Unused Unused TACH5 Value, LSB TACH5 MSB/ +12V1V TACH6 Value, LSB
R/W
R
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
De− fault
0x00
SW Reset
No
Lock able
No
0x8C
R
7
6
5
4
3
2
1
0
0x00
No
No
0x8D
R
7
6
5
4
3
2
1
0
0x00
No
No
0x8E
R
7
6
5
4
3
2
1
0
0x00
No
No
0x8F
R
7
6
5
4
3
2
1
0
0x00
No
No
0x90 0x91 0x92 0x93 0x94 0x95
R R R R R R
7 7 7 7 7 7
6 6 6 6 6 6
5 5 5 5 5 5
4 4 4 4 4 4
3 3 3 3 3 3
2 2 2 2 2 2
1 1 1 1 1 1
0 0 0 0 0 0
0x00 0x00 0x00 0x00 0x00 0x00
No No No No No No
No No No No No No
0x96 0x97 0x98
R R R
7 7 7
6 6 6
5 5 5
4 4 4
3 3 3
2 2 2
1 1 1
0 0 0
0x00 0x00 0xFF
No No No
No No No
0x99
R
7
6
5
4
3
2
1
0
0xFF
No
No
0x9A
R
7
6
5
4
3
2
1
0
0xFF
No
No
0x9B
R
7
6
5
4
3
2
1
0
0xFF
No
No
0x9C
R
7
6
5
4
3
2
1
0
0xFF
No
No
0x9D
R
7
6
5
4
3
2
1
0
0xFF
No
No
0x9E
R
7
6
5
4
3
2
1
0
0xFF
No
No
0x9F
R
7
6
5
4
3
2
1
0
0xFF
No
No
0xA0 0xA1 0xA2 0xA3
R R R R
7 7 7 7
6 6 6 6
5 5 5 5
4 4 4 4
3 3 3 3
2 2 2 2
1 1 1 1
0 0 0 0
N/A N/A 0xFF 0xFF
No No No No
No No No No
0xA4
R
7
6
5
4
3
2
1
0
0xFF
No
No
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58
ADT7462
Table 30. Register Map
Addr
0xA5
Description TACH6 MSB/+12V 2 Voltage TACH7 Value, LSB TACH7 MSB/+5V Voltage TACH8 Value, LSB TACH8 MSB/+12V 3 Voltage PWM1 Duty Cycle PWM2 Duty Cycle PWM3 Duty Cycle PWM4 Duty Cycle THERM1 %On−Time THERM2 %On−Time Thermal Status 1, Host Thermal Status 2, Host Thermal Status 3, Host Voltage Status 1, Host Voltage Status 2, Host Fan Status, Host Digital Status, Host GPIO Status, Host Thermal Status 1, BMC Thermal Status 2, BMC Voltage Status 1, BMC Voltage Status 2, BMC Fan Status, BMC Digital Status, BMC
R/W
R
Bit 7
7
Bit 6
6
Bit 5
5
Bit 4
4
Bit 3
3
Bit 2
2
Bit 1
1
Bit 0
0
De− fault
0xFF
SW Reset
No
Lock able
No
0xA6 0xA7
R R
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
0xFF 0xFF
No No
No No
0xA8 0xA9
R R
7 7
6 6
5 5
4 4
3 3
2 2
1 1
0 0
0xFF 0xFF
No No
No No
0xAA 0xAB 0xAC 0xAD 0xAE 0xAF 0xB8
R/W R/W R/W R/W R R R
7 7 7 7 7 7 R3D
6 6 6 6 6 6 R2D
5 5 5 5 5 5 R1D
4 4 4 4 4 4 R3
3 3 3 3 3 3 R2
2 2 2 2 2 2 R1
1 1 1 1 1 1 Local
0 0 0 0 0 0 Res
0x00 0x00 0xC0 0x00 0x00 0x00 0x00
No No No No No No Yes
No No No No No No No
0xB9
R
VR2
VR1
T2S
T2A
T2%
T1S
T1A
T1%
0x00
Yes
No
0xBA
R
R3T2
R2T2
R1T2
LT2
R3T1
R2T1
R1T1
LT1
0x00
Yes
No
0xBB
R
Pin 23
+5V
Pin 19
Pin 15
+3.3V
+12V3
+12V2
+12V1
0x00
Yes
No
0xBC
R
+1.5V1 (ICH) Fan 8 CI
+1.5V2 (3GIO) Fan 7 VID
Pin 26
Pin 25
Pin 24
Res
Res
Res
0x00
Yes
No
0xBD 0xBE
R R
Fan 6 SCSI2
Fan 5 SCSI1
Fan 4 FAN2MAX
Fan 3 Res
Fan 2 Res
Fan 1 Res
0x00 0x00
Yes Yes
No No
0xBF
R/W
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
0x00
Yes
No
0xC0
R
R3D
R2D
R1D
R3
R2
R1
Local
Res
0x00
Yes
No
0xC1
R
VR2
VR1
T2S
T2A
T2%
T1S
T1A
T1%
0x00
Yes
No
0xC3
R
Pin 23
+5V
Pin 19
Pin 15
+3.3V
+12V3
+12V2
+12V1
0x00
Yes
No
0xC4
R
+1.5V1 (ICH) Fan 8 CI
+1.5V2 (3GIO) Fan 7 VID
Pin 26
Pin 25
Pin 24
Res
Res
Res
0x00
Yes
No
0xC5 0xC6
R R
Fan 6 SCSI2
Fan 5 SCSI1
Fan 4 FAN2MAX
Fan 3 Res
Fan 2 Res
Fan 1 Res
0x00 0x00
Yes Yes
No No
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59
ADT7462
Table 31. Register 0x00 — Configuration Register 0 (Note 1)
Bit [5:0] 6 7 Name #Bytes Block Read VID Decoder SW Reset R/W R/W R/W R/W Description These bits set the number of registers to be read in a block read. Default = 0x20. 0 = VR10 Decoding Spec; 1 = VR11 Decoding Spec. Default = 0. Setting this bit to 1 restores all unlocked registers to their default values. Self−clearing. Write 0x6D to register 0x7B before setting this bit to get a software reset. Default = 0.
1. POR = 0x20, Lock = Y, SW Reset = Y.
Table 32. Register 0x01 — Configuration Register 1 (Note 1)
Bit 0 1 2 3 4 5 6 Name Monitor Reserved Reserved ALERT Mode Disable Fast Spin−Up Setup Complete Lock R/W R/W R/W R/W R/W R/W R/W Write Once Description Setting this bit to 1 enables temperature and voltage measurements. When this bit is set to 0, temperature and voltage measurements are disabled. Default = 1. Reserved. Default = 0. Reserved. Default = 0. This bit sets the ALERT mode in the ADT7462. 1 = comparator mode, 0 = SMBALERT mode (default). Setting this bit to 1 disables the fast spin−up (for two TACH pulses) for the fans. Instead, the fans spin up for the programmed fan startup timeout. Default = 0. Setting this bit to 1 tells the ADT7462 that setup is complete and that monitoring of all selected channels should begin. Default = 0. Logic 1 locks all limit values at their current settings. When this bit is set, all lockable registers become read−only and cannot be modified until the ADT7462 is powered down and powered up again. This prevents rogue programs, such as viruses, from modifying critical system limit settings. Lockable. This bit is set to 1 to indicate that the ADT7462 is fully powered up and ready to start monitoring.
7
RDY
R
1. POR = 0x81, Lock = Y, SW Reset = Y.
Table 33. Register 0x02 — Configuration Register 2 (Note 1)
Bit 0 1 2 3 4 5 [7:6] Name FAST Reserved PWM Mode VRD1 Boost VRD2 Boost Fans Full Speed #TACH Pulses R/W R/W R/W R/W R/W R/W R/W R/W Description In low frequency, PWM fan speed measurements are made once a second. Setting this bit to 1 increases the frequency of the fan speed measurements to 4 times a second. Default = 0. Reserved. Default = 0. This bit sets the PWM frequency mode. 0 = low frequency PWM; frequency programmable between 11 Hz and 88.2 Hz. Default = 35.3 Hz. 1 = high frequency mode, 22.5 kHz. Setting this bit to 0 causes the fans to go to full speed on assertion of VRD1. Default = 0. When this bit is set to 1, VRD1 assertions have no effect on the fan speed. Setting this bit to 0 causes the fans to go to full speed on assertion of VRD2. Default = 0. When this bit is set to 1, VRD2 assertions have no effect on the fan speed. Setting this bit to 1 drives the fans to full speed. Default = 0. In low frequency mode, the ADT7462 must pulse stretch to get an accurate fan speed measurement. The speed is always measured between the 2nd rising edge and one × TACH pulses later. This bit determines the last TACH pulse. Therefore, if the fan speed is to be measured between the second and fourth TACH pulse, 01 is written to these bits. x = 1 = 00 x = 2 = 01 x = 3 = 10 (default) x = 4 = 11
1. POR = 0x80, Lock = Y, SW Reset = Y.
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60
ADT7462
Table 34. Register 0x03 — Configuration Register 3 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name GPIO_En SCL_Timeout SDA_Timeout VID_Threshold THERM_ Threshold CI Reset XOR Tree V_Core_Low R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting this bit to 1 enables the GPIOs. Default = 0. 1 = SCL timeout enabled. 0 = SCL timeout disabled = default. 1 = SDA timeout enabled. 0 = SDA timeout disabled = default. This bit sets the digital threshold for the VID digital inputs. 0 =default. 1 = low thresholds selected = 0.65 V. This bit sets the digital threshold for the THERM digital inputs. 0 =default. 1 = low thresholds selected = 2/3 VCCP1 (Pin 23). Setting this bit to 1 resets the chassis intrusion circuit. This bit clears itself. Default = 0. Setting this bit to 1 enables the XOR tree test. Default = 0. Setting this bit to 1 enables V_core_low. Default = 0.
1. POR = 0x00, Lock = Y, SW Reset = Y.
Table 35. Register 0x07 — TACH Enable Register (Note 1)
Bit 0 1 2 3 4 5 6 7 Name TACH1 TACH2 TACH3 TACH4 TACH5 TACH6 TACH7 TACH8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting this bit to 1 enables the TACH1 measurement. Default = 0. Setting this bit to 1 enables the TACH2 measurement. Default = 0. Setting this bit to 1 enables the TACH3 measurement. Default = 0. Setting this bit to 1 enables the TACH4 measurement. Default = 0. Setting this bit to 1 enables the TACH5 measurement. Default = 0. Setting this bit to 1 enables the TACH6 measurement. Default = 0. Setting this bit to 1 enables the TACH7 measurement. Default = 0. Setting this bit to 1 enables the TACH8 measurement. Default = 0.
1. POR = 0x00, Lock = Y, SW Reset = Y.
Table 36. Register 0x08 — TACH Configuration Register (Note 1)
Bit 0 Name DC 1/5 R/W R/W Description Setting this bit to 1 enables continuous measurements on TACH1 and TACH5 in low frequency PWM mode. Continuous measurement means that pulse stretching is turned off and the PWM output and TACH inputs are no longer synchronized. Default = 1. Setting this bit to 1 enables continuous measurements on TACH2 and TACH6 in low frequency PWM mode. Continuous measurement means that pulse stretching is turned off and the PWM output and TACH inputs are no longer synchronized. Default = 1. Setting this bit to 1 enables continuous measurements on TACH3 and TACH7 in low frequency PWM mode. Continuous measurement means that pulse stretching is turned off and the PWM output and TACH inputs are no longer synchronized. Default = 1. Setting this bit to 1 enables continuous measurements on TACH4 and TACH8 in low frequency PWM mode. Continuous measurement means that pulse stretching is turned off and the PWM output and TACH inputs are no longer synchronized. Default = 1. Reserved for future use.
1
DC 2/6
R/W
2
DC 3/7
R/W
3
DC 4/8
R/W
[7:4]
Reserved
R
1. POR = 0x0F, Lock = Y, SW Reset = Y.
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61
ADT7462
Table 37. Register 0x09 — GPIO Configuration Register 1 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name GPIO1_P GPIO1_D GPIO2_P GPIO2_D GPIO3_P GPIO3_D GPIO4_P GPIO4_D R/W R/W R/W R/W R/W R/W R/W R/W R/W Description This bit sets the polarity of GPIO1. 0 = default = active low. 1= active high. This bit sets the direction of GPIO1. 0 = default = input. 1= output. This bit sets the polarity of GPIO2. 0 = default = active low. 1= active high. This bit sets the direction of GPIO2. 0 = default = input. 1= output. This bit sets the polarity of GPIO3. 0 = default = active low. 1= active high. This bit sets the direction of GPIO3. 0 = default = input. 1= output. This bit sets the polarity of GPIO4. 0 = default = active low. 1= active high. This bit sets the direction of GPIO4. 0 = default = input. 1= output.
1. POR = 0x00, Lock = Y, SW Reset = Y.
Table 38. Register 0x0A — GPIO Configuration Register 2 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name GPIO5_P GPIO5_D GPIO6_P GPIO6_D GPIO7_P GPIO7_D GPIO8_P GPIO8_D R/W R/W R/W R/W R/W R/W R/W R/W R/W Description This bit sets the polarity of GPIO5. 0 = default = active low. 1= active high. This bit sets the direction of GPIO5. 0 = default = input. 1= output. This bit sets the polarity of GPIO6. 0 = default = active low. 1= active high. This bit sets the direction of GPIO6. 0 = default = input. 1= output. This bit sets the polarity of GPIO7. 0 = default = active low. 1= active high. This bit sets the direction of GPIO7. 0 = default = input. 1= output. This bit sets the polarity of GPIO8. 0 = default = active low. 1= active high. This bit sets the direction of GPIO8. 0 = default = input. 1= output.
1. POR = 0x00, Lock = Y, SW Reset = Y.
Table 39. Register 0x0B — Dynamic TMIN Control Register 1 (Note 1)
Bit 0 1 2 Name Remote 1 En Remote 2 En P1R1 R/W R/W R/W R/W Description Setting this bit to 1 enables dynamic TMIN control for the Remote 1 channel. Default = 0. Setting this bit to 1 enables dynamic TMIN control for the Remote 2 channel. Default = 0. P1R1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if THERM1 is asserted externally. This happens only if the current temperature is less than the value in the operating point register. The operating point contains the temperature at which THERM1 is asserted. P1R1 = 0 (default) ignores any THERM1 assertions on the THERM1 pin. The Remote 1 operating point register reflects its programmed value. P1R2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if THERM1 is asserted externally. This happens only if the current temperature is less than the value in the operating point register. The operating point contains the temperature at which THERM1 is asserted. P1R2 = 0 (default) ignores any THERM1 assertions on the THERM1 pin. The Remote 2 operating point register reflects its programmed value. P2R1 = 1 copies the Remote 1 current temperature to the Remote 1 operating point register if THERM2 is asserted externally. This happens only if the current temperature is less than the value in the operating point register. The operating point contains the temperature at which THERM2 is asserted. P2R1 = 0 (default) ignores any THERM2 assertions on the THERM2 pin. The Remote 1 operating point register reflects its programmed value. P2R2 = 1 copies the Remote 2 current temperature to the Remote 2 operating point register if THERM2 is asserted externally. This happens only if the current temperature is less than the value in the operating point register. The operating point contains the temperature at which THERM2 is asserted. P2R2 = 0 (default) ignores any THERM2 assertions on the THERM2 pin. The Remote 2 operating point register reflects its programmed value. Reserved for future use.
3
P1R2
R/W
4
P2R1
R/W
5
P2R2
R/W
[7:6]
Reserved
R/W
1. POR = 0x00, Lock = Y, SW Reset = Y.
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62
ADT7462
Table 40. Register 0x0C — Dynamic TMIN Control Register 2 (Note 1)
Bit [2:0] Name CYR1 R/W R/W Description Three−bit Remote 1 cycle value. These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the Remote 1 temperature channel, in terms of number of monitoring cycles. The system has associated thermal time constants that must be found to optimize the response of fans and the control loop. Bits 000 001 010 011 100 101 110 111 [5:3] CYR2 R/W Decrease cycle 8 cycles (1 sec) 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) Increase cycle 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 2048 cycles (256 sec)
Three−bit Remote 2 cycle value. These three bits define the delay time between making subsequent TMIN adjustments in the control loop for the Remote 2 temperature channel, in terms of number of monitoring cycles. The system has associated thermal time constants that must be found to optimize the response of fans and the control loop. Bits 000 001 010 011 100 101 110 111 Decrease cycle 8 cycles (1 sec) 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) Increase Cycle 16 cycles (2 sec) 32 cycles (4 sec) 64 cycles (8 sec) 128 cycles (16 sec) 256 cycles (32 sec) 512 cycles (64 sec) 1024 cycles (128 sec) 2048 cycles (256 sec)
6 7
Control Loop Select Reserved
R/W R
This bit allows the user to select between two control loops. 0 makes the control loop backwards compatible with the ADT7463 and ADT7468. 1 = ADT7462 control loop (default). Reserved for future use.
1. POR = 0x40, Lock = Y, SW Reset = Y.
Table 41. Register 0x0D — THERM Configuration Register (Note 1)
Bit 0 Name Boost 1 R/W R/W Description Setting this bit to 0 causes the fans to go to maximum PWM on assertion of THERM1 as an output. Setting this bit to 1 means that the fan speed is not affected when the THERM1 temperature limit is exceeded. Default = 0. Setting this bit to 0 causes the fans to go to maximum PWM on assertion of THERM2 as an output. Setting this bit to 1 means that the fan speed is not affected when the THERM2 temperature limit is exceeded. Default = 0. These bits set the timer window for measuring THERM1 assertions. 000 = 0.25 sec 001 = 0.5 sec 010 = 1 sec 011 = 2 sec 100 = 4 sec 101 = 8 sec 110 = 8 sec 111 = 8 sec These bits set the timer window for measuring THERM2 assertions. 000 = 0.25 sec 001 = 0.5 sec 010 = 1 sec 011 = 2 sec 100 = 4 sec 101 = 8 sec 110 = 8 sec 111 = 8 sec
1
Boost 2
R/W
[4:2]
THERM1 Timer Window
R/W
[7:5]
THERM2 Timer Window
R/W
1. POR = 0x00, Lock = Y, SW Reset = Y.
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Table 42. Register 0x0E — THERM1 Configuration Register (Note 1)
Bit 0 1 2 3 4 [7:5] Name THERM1 Timer Enable THERM1_Local THERM1_ Remote 1 THERM1_ Remote 2 THERM1_ Remote 3 Reserved R/W R/W R/W R/W R/W R/W R Description Enables the THERM1 timer circuit. Default = 0. Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the local temperature exceeds the local THERM1 temperature limit. Default = 0. Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the Remote 1 temperature exceeds the Remote 1 THERM1 temperature limit. Default = 0. Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the Remote 2 temperature exceeds the Remote 2 THERM1 temperature limit. Default = 0. Setting the bit to 1 means that the THERM1 pin is asserted low as an output whenever the Remote 3 temperature exceeds the Remote 3 THERM1 temperature limit. Default = 0. Reserved for future use.
1. POR = 0x00, Lock = Y, SW Reset = Y.
Table 43. Register 0x0F — THERM2 Configuration Register (Note 1)
Bit 0 1 2 3 4 [7:5] Name THERM2 Timer Enable THERM2_Local THERM2_ Remote 1 THERM2_ Remote 2 THERM2_ Remote 3 Reserved R/W R/W R/W R/W R/W R/W R Description Enables the THERM2 timer circuit. Default = 0. Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the local temperature exceeds the local THERM2 temperature limit. Default = 0. Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the Remote 1 temperature exceeds the Remote 1 THERM2 temperature limit. Default = 0. Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the Remote 2 temperature exceeds the Remote 2 THERM2 temperature limit. Default = 0. Setting the bit to 1 means that the THERM2 pin is asserted low as an output whenever the Remote 3 temperature exceeds the Remote 3 THERM2 temperature limit. Default = 0. Reserved for future use.
1. POR = 0x00, Lock = Y, SW Reset = Y.
Table 44. Register 0x10 — Pin Configuration Register 1 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name Pin 7 Pin 4 Pin 3 Pin 2 Pin 1 Diode 3 Diode 1 VIDs R/W R/W R/W R/W R/W R/W R/W R/W R/W 0 = +12V1; 1 = TACH5 input. Default =1. 0 = GPIO4; 1= TACH4 input (that is, if the VIDs are not selected). Default = 1. 0 = GPIO3; 1= TACH3 input (that is, if the VIDs are not selected). Default = 1. 0 = GPIO2; 1= TACH2 input (that is, if the VIDs are not selected). Default = 1. 0 = GPIO1; 1= TACH1 input (that is, if the VIDs are not selected). Default = 1. 1 enables the D3+ and D3− inputs on Pin 19 and Pin 20. 0 enables the voltage measurement input and SCSI_TERM2 input. Default = 1. 1 enables the D1+ and D1− inputs on Pin 15 and Pin 16. 0 enables the voltage measurement input and SCSI_TERM1 input. Default = 1. Setting this bit to 1 enables the VIDs on Pin 1 to Pin 4, Pin 28, Pin 31, and Pin 32. Default = 0. Description
1. POR = 0x7F, Lock = Y, SW Reset = Y.
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ADT7462
Table 45. Register 0x11 — Pin Configuration Register 2 (Note 1)
Bit [1:0] Name Pin 23 R/W R/W 00 = VCCP1 selected. 01 = +2.5V. 10 = +1.8V (default). 11 = +1.5V. 0 = +12V3; 1 = TACH8. Default = 1. 0 = +5V; 1 = TACH7. Default = 1. 0 = +1.25V; 1 = +0.9V (that is, if RT3 is not selected). Default = 0. 0 = +2.5V, 1 = +1.8V (that is, if RT1 is not selected). Default = 0. 0 = +3.3V; 1 = PWM4. Default = 1. 0 = +12V2; 1 = TACH6. Default = 1. Description
2 3 4 5 6 7
Pin 22 Pin 21 Pin 19 Pin 15 Pin 13 Pin 8
R/W R/W R/W R/W R/W R/W
1. POR = 0xCE, Lock = Y, SW Reset = Y.
Table 46. Register 0x12 — Pin Configuration Register 3 (Note 1)
Bit 0 1 [3:2] Name Reserved Pin 27 Pin 26 R/W R R/W R/W Reserved for future use. 0 = FAN2MAX; 1 = chassis intrusion (default). 00 = VBATT selected (default). 01 = +1.2V2 (FSB_VTT). 10 = VR_HOT2. 11 = VR_HOT2. 00 = +3.3V selected (default). 01 = +1.2V1 (GBIT). 10 = VR_HOT1. 11 = VR_HOT1. 00 = VCCP2 selected. 01 = +2.5V (default). 10 = +1.8V. 11 = +1.5V. Description
[5:4]
Pin 25
R/W
[7:6]
Pin 24
R/W
1. POR = 0x42, Lock = Y, SW Reset = Y.
Table 47. Register 0x13 — Pin Configuration Register 4 (Note 1)
Bit [1:0] 2 3 [5:4] Name Reserved Pin 32 Pin 31 Pin 29 (Pin 28, +1.5V Monitoring) (Note 2) Pin 28 (Pin 29, +1.5V Monitoring) (Note 3) R/W R R/W R/W R/W Reserved. 0 = GPIO6; 1 = PWM2 (Pin 32 is VID5 if VIDs are selected). Default = 1. 0 = GPIO5; 1 = PWM1 (Pin 31 is VID4 if VIDs are selected). Default = 1. 00 = GPIO8. 01 = +1.5V (measured on Pin 28). 10 = THERM2. 11 = THERM2 (default).(Pin 28 is VID6 if VIDs are selected.) 00 = GPIO7. 01 = +1.5V (measured on Pin 29). 10 = THERM1. 11 = THERM1 (default). Description
[7:6]
R/W
1. POR = 0xFC, Lock = Y, SW Reset = Y. 2. +1.5V can be monitored on Pin 28 and 29 only when both are configured as +1.5V inputs. This means that +1.5V is measured on both pins or on neither. +1.5V monitoring cannot be combined with another function on the other pin. For example, if Pin 29 is configured as +1.5V, then THERM1 cannot be selected on Pin 28, because they share the same selection bits.
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Table 48. Register 0x14 — Easy Configuration Options (Note 1)
Bit 0 1 2 3 4 [7:5] Name Easy Option 1 Select Easy Option 2 Select Easy Option 3 Select Easy Option 4 Select Easy Option 5 Select Reserved R/W R/W R/W R/W R/W R/W R Description Setting this bit to 1 enables Easy Option 1. Setting this bit to 1 enables Easy Option 2. Setting this bit to 1 enables Easy Option 3. Setting this bit to 1 enables Easy Option 4. Setting this bit to 1 enables Easy Option 5. Reserved for future use.
1. POR = 0x01, Lock = Y, SW Reset = Y.
Table 49. Register 0x16 — EDO/Single Channel Enable (Note 1)
Bit 0 1 2 Name EDO_En1 EDO_En2 Single−Channel Mode Select Channel Select R/W R/W R/W R/W Enable EDO on GPIO5. Default = 0. Enable EDO on GPIO6. Default = 0. Setting this bit to 1 places the ADT7462 in single−channel mode. This means that it converts on one channel only. The channel it converts on is set using the channel select bits in this register. Default = 0. These bits are used to set the single channel that the ADT7462 measures in single−channel mode. 0000 0 = Pin 26 (default) 0000 1 = Remote 1 temperature 0001 0 = Remote 2 temperature 0001 1 = Remote 3 temperature 0010 0 = Local temperature 0010 1 = +12V1 0011 0 = +12V2 0011 1 = +12V3 0100 0 = +3.3V 0100 1 = Pin 15 voltage 0101 0 = Pin 19 voltage 0101 1 = +5V 0110 0 = Pin 23 voltage 0110 1 = Pin 24 voltage 0111 0 = Pin 25 voltage 1000 0 = +1.5V1 (ICH) voltage 1000 1 = +1.5V2 (3GIO) voltage Description
[7:3]
R/W
1. POR = 0x00, Lock = Y, SW Reset = Y.
Table 50. Register 0x18 — Voltage Attenuator Configuration 1 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name Reserved Attenuator Pin 7 Attenuator Pin 8 Attenuator Pin 13 Attenuator Pin 15 Attenuator Pin 19 Attenuator Pin 21 Attenuator Pin 22 R/W R R/W R/W R/W R/W R/W R/W R/W Reserved for future use. Setting this bit to 0 removes the attenuators for Pin 7. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 8. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin13. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 15. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 19. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 21. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 22. Default = 1 = attenuators enabled. Description
1. POR = 0xFF, Lock = Y, SW Reset = Y.
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Table 51. Register 0x19 — Voltage Attenuator Configuration 2 (Note 1)
Bit 0 1 2 3 4 5 [7:6] Name Attenuator Pin 23 Attenuator Pin 24 Attenuator Pin 25 Reserved Attenuator Pin 28 Attenuator Pin 29 Reserved R/W R/W R/W R/W R/W R/W R/W R/W Description Setting this bit to 0 removes the attenuators for Pin 23. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 24. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 25. Default = 1 = attenuators enabled. Reserved for future use. Default = 0. Setting this bit to 0 removes the attenuators for Pin 28. Default = 1 = attenuators enabled. Setting this bit to 0 removes the attenuators for Pin 29. Default = 1 = attenuators enabled. Reserved for future use. Default = 00.
1. POR = 0x37, Lock = Y, SW Reset = Y.
Table 52. Register 0x1A — Enhanced Acoustics Register 1
Bit 0 1 [4:2] Mnemonic En1 En2 Ramp Rate 1 R/W R/W R/W R/W Description Setting this bit to 1 enables the enhanced acoustics mode for PWM1; 0 disables it. Default = 0. Setting this bit to 1 enables the enhanced acoustics mode for PWM2; 0 disables it. Default = 0. These bits set the ramp rate for the enhanced acoustics mode for PWM1. Default = 000. Time Slot Increase 000 = 1 001 = 2 010 = 3 011 = 5 100 = 8 101 = 12 110 = 24 111 = 48 [7:5] Ramp Rate 2 R/W Time Slot Increase 000 = 1 001 = 2 010 = 3 011 = 5 100 = 8 101 = 12 110 = 24 111 = 48 1. POR = 0x00, Lock = Y, SW Reset = Y. Time for 33% to 100% 35 sec 17.6 sec 11.8 sec 7.0 sec 4.4 sec 3.0 sec 1.6 sec 0.8 sec Time for 33% to 100% 35 sec 17.6 sec 11.8 sec 7.0 sec 4.4 sec 3.0 sec 1.6 sec 0.8 sec
These bits set the ramp rate for the enhanced acoustics mode for PWM2. Default = 000.
Table 53. Register 0x1B — Enhanced Acoustics Register 2
Bit 0 1 [4:2] Mnemonic En3 En4 Ramp Rate 3 R/W R/W R/W R/W Description Setting this bit to 1 enables the enhanced acoustics mode for PWM3; 0 disables it. Default = 0. Setting this bit to 1 enables the enhanced acoustics mode for PWM4; 0 disables it. Default = 0. These bits set the ramp rate for the enhanced acoustics mode for PWM3. Default = 000. Time Slot Increase 000 = 1 001 = 2 010 = 3 011 = 5 100 = 8 101 = 12 110 = 24 111 = 48 [7:5] Ramp Rate 4 R/W Time Slot Increase 000 = 1 001 = 2 010 = 3 011 = 5 100 = 8 101 = 12 110 = 24 111 = 48 1. POR = 0x00, Lock = Y, SW Reset = Y. Time for 33% to 100% 37.5 sec 18.8 sec 12.5 sec 7.5 sec 4.7 sec 3.1 sec 1.6 sec 0.8 sec Time for 33% to 100% 35 sec 17.6 sec 11.8 sec 7.0 sec 4.4 sec 3.0 sec 1.6 sec 0.8 sec
These bits set the ramp rate for the enhanced acoustics mode for PWM4. Default = 000.
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Table 54. Register 0x1C — Fan Freewheeling Test (Note 1)
Bit 0 1 2 3 4 5 6 7 Name Test Fan 1 Test Fan 2 Test Fan 3 Test Fan 4 Test Fan 5 Test Fan 6 Test Fan 7 Test Fan 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Fan freewheeling test bit for Fan 1. This bit self−clears when the test is complete. Fan freewheeling test bit for Fan 2. This bit self−clears when the test is complete. Fan freewheeling test bit for Fan 3. This bit self−clears when the test is complete. Fan freewheeling test bit for Fan 4. This bit self−clears when the test is complete. Fan freewheeling test bit for Fan 5. This bit self−clears when the test is complete. Fan freewheeling test bit for Fan 6. This bit self−clears when the test is complete. Fan freewheeling test bit for Fan 7. This bit self−clears when the test is complete. Fan freewheeling test bit for Fan 8. This bit self−clears when the test is complete.
1. POR = 0x00, Lock = Y, SW Reset = Y.
Table 55. Register 0x1D — Fans Present (Note 1)
Bit 0 1 2 3 4 5 6 7 Name Fan 1 Present Fan 2 Present Fan 3 Present Fan 4 Present Fan 5 Present Fan 6 Present Fan 7 Present Fan 8 Present R/W R/W R/W R/W R/W R/W R/W R/W R/W Set this bit to 1 when Fan 1 is present. Set this bit to 1 when Fan 2 is present. Set this bit to 1 when Fan 3 is present. Set this bit to 1 when Fan 4 is present. Set this bit to 1 when Fan 5 is present. Set this bit to 1 when Fan 6 is present. Set this bit to 1 when Fan 7 is present. Set this bit to 1 when Fan 8 is present. Description
1. POR = 0x00, Lock = Y, SW Reset = Y.
Table 56. Register 0x1E — Fan Freewheeling Test Enable (Note 1)
Bit 0 1 2 3 4 5 6 7 Name Test Fan 1 Test Fan 2 Test Fan 3 Test Fan 4 Test Fan 5 Test Fan 6 Test Fan 7 Test Fan 8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Setting this bit to 1 enables the fan freewheeling test for Fan 1. Setting this bit to 1 enables the fan freewheeling test for Fan 2. Setting this bit to 1 enables the fan freewheeling test for Fan 3. Setting this bit to 1 enables the fan freewheeling test for Fan 4. Setting this bit to 1 enables the fan freewheeling test for Fan 5. Setting this bit to 1 enables the fan freewheeling test for Fan 6. Setting this bit to 1 enables the fan freewheeling test for Fan 7. Setting this bit to 1 enables the fan freewheeling test for Fan 8.
1. POR = 0x00, Lock = Y, SW Reset = Y.
Table 57. PWM Configuration Registers (Note 1)
Register Address 0x21 0x22 0x23 0x24 1. Lock = Y, SW Reset = Y. R/W R/W R/W R/W R/W Description PWM1 Configuration Register PWM2 Configuration Register PWM3 Configuration Register PWM4 Configuration Register Power−On Default 0x11 0x31 0x51 0x71
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Table 58. Register 0x21, Register 0x22, Register 0x23, Register 0x24 — PWM1, PWM2, PWM3 and PWM4 Configuration Registers
Bit [2:0] Name Spin−Up Timeout R/W R/W Description These bits set the duration of the fan startup timeout and the timeout for the fan freewheeling test. 000 = No startup timeout 001 = 100 ms 010 = 250 ms 011 = 400 ms 100 = 667 ms 101 = 1 sec 110 = 2 sec 111 = 32 sec Setting this bit to 1 makes the ramp rate of the enhance acoustics mode four times longer. Setting this bit to 0, the PWM outputs are active low. Setting this bit to 1, the PWM outputs are active high (default). These bits determine which temperature channel controls the fans in the automatic fan speed control loop. 000 = Local temperature 001 = Remote 1 temperature 010 = Remote 2 temperature 011 = Remote 3 temperature 100 = Off 101 = Maximum fan speed calculated by the local and Remote 3 temperature channels 110 = Maximum fan speed calculated by all four channels 111 = Manual mode
3 4 [7:5]
SLOW INV BHVR
R/W R/W R/W
Table 59. Register 0x25 — PWM1, PWM2 Frequency (Note 1)
Bit 0 Name Min 1 R/W R/W Description When the ADT7462 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle) or at minimum PWM1 duty cycle when the controlling temperature is below its TMIN − hysteresis value. 0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM1 duty cycle below TMIN − hysteresis. When the ADT7462 is in automatic fan control mode, this bit defines whether PWM2 is off (0% duty cycle) or at minimum PWM2 duty cycle when the controlling temperature is below its TMIN − hysteresis value. 0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM2 duty cycle below TMIN − hysteresis. These bits set the frequency of PWM1 when configured in low frequency mode. 000 = 11 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz These bits set the frequency of PWM2 when configured in low frequency mode. 000 = 11 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz
1
Min 2
R/W
[4:2]
Low Freq 1
R/W
[7:5]
Low Freq 2
R/W
1. POR = 0x90, Lock = Y, SW Reset = Y.
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Table 60. Register 0x26 — PWM3, PWM4 Frequency (Note 1)
Bit 0 Name Min 3 R/W R/W Description When the ADT7462 is in automatic fan control mode, this bit defines whether PWM3 is off (0% duty cycle) or at minimum PWM3 duty cycle when the controlling temperature is below its TMIN − hysteresis value. 0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM3 duty cycle below TMIN − hysteresis. When the ADT7462 is in automatic fan control mode, this bit defines whether PWM4 is off (0% duty cycle) or at minimum PWM4 duty cycle when the controlling temperature is below its TMIN − hysteresis value. 0 = 0% duty cycle below TMIN − hysteresis (default); 1 = minimum PWM4 duty cycle below TMIN − hysteresis. These bits set the frequency of PWM3 when configured in low frequency mode. 000 = 11 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz These bits set the frequency of PWM4 when configured in low frequency mode. 000 = 11 Hz 001 = 14.7 Hz 010 = 22.1 Hz 011 = 29.4 Hz 100 = 35.3 Hz (default) 101 = 44.1 Hz 110 = 58.8 Hz 111 = 88.2 Hz
1
Min 4
R/W
[4:2]
Low Freq 3
R/W
[7:5]
Low Freq 4
R/W
1. POR = 0x90, Lock = Y, SW Reset = Y.
Table 61. Minimum PWMx Duty Cycle (Note 1)
Register Address 0x28 0x29 0x2A 0x2B 1. Lock = Y, SW Reset = Y. R/W R/W R/W R/W R/W Description Minimum PWM1 duty cycle Minimum PWM2 duty cycle Minimum PWM3 duty cycle Minimum PWM4 duty cycle POR Default 0x80 0x80 0x80 0x80
Table 62. Register 0x2C — Maximum PWM Duty Cycle (Note 1)
Bit [7:0] Name Maximum PWM Duty Cycle R/W R/W Description This register sets the maximum % duty cycle output in automatic fan speed control mode for all four PWM outputs.
1. POR = 0xC0, Lock = Y, SW Reset = Y.
Table 63. Register 0x30 — Thermal Mask Register 1 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name Reserved Local Temp Remote 1 Temp Remote 2 Temp Remote 3 Temp Diode 1 Error Diode 2 Error Diode 3 Error R/W R/W R/W R/W R/W R/W R/W R/W R/W Reserved for future use. 1 masks ALERTs for an out−of−limit condition on the local temperature channel. 1 masks ALERTs for an out−of−limit condition on the Remote 1 temperature channel. 1 masks ALERTs for an out−of−limit condition on the Remote 2 temperature channel. 1 masks ALERTs for an out−of−limit condition on the Remote 3 temperature channel. 1 masks ALERTs for an open or short condition on the Remote 1 channel. 1 masks ALERTs for an open or short condition on the Remote 2 channel. 1 masks ALERTs for an open or short condition on the Remote 3 channel. Description
1. POR = 0x00, Lock = N, SW Reset = Y.
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Table 64. Register 0x31 — Thermal Mask Register 2 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name THERM1 % THERM1 Assert THERM1 State THERM2 % THERM2 Assert THERM2 State VRD1_Assert VRD2_Assert R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 1 masks ALERTs for the corresponding interrupt status bit. Default = 1. 1 masks ALERTs for the corresponding interrupt status bit. Default = 1.
1. POR = 0xC0, Lock = N, SW Reset = Y.
Table 65. Register 0x32 — Voltage Mask Register 1 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name +12V1 +12V2 +12V3 +3.3V Pin 15 Voltage Pin 19 Voltage +5V Pin 23 Voltage R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit.
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 66. Register 0x33 — Voltage Mask Register 2 (Note 1)
Bit [2:0] 3 4 5 6 7 Name Reserved Pin 24 Voltage Pin 25 Voltage Pin 26 Voltage +1.5V2 (3GIO) +1.5V1 (ICH) R/W R/W R/W R/W R/W R/W R/W Reserved for future use. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. Description
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 67. Register 0x34 — Fan Mask Register (Note 1)
Bit 0 1 2 3 4 5 6 7 Name Fan 1 Fault Fan 2 Fault Fan 3 Fault Fan 4 Fault Fan 5 Fault Fan 6 Fault Fan 7 Fault Fan 8 Fault R/W R/W R/W R/W R/W R/W R/W R/W R/W Description 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit. 1 masks ALERTs for the corresponding interrupt status bit.
1. POR = 0x00, Lock = N, SW Reset = Y.
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Table 68. Register 0x35 — Digital Mask Register (Note 1)
Bit [2:0] 3 4 5 6 7 Name Reserved FAN2MAX SCSI1 SCSI2 VID Comparison Chassis Intrusion R/W R R/W R/W R/W R/W R/W Reserved for future use. 1 masks ALERTs for the corresponding interrupt status bit. Default = 1. 1 masks ALERTs for the corresponding interrupt status bit. Default = 1. 1 masks ALERTs for the corresponding interrupt status bit. Default = 1. 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. 1 masks ALERTs for the corresponding interrupt status bit. Default = 0. Description
1. POR = 0x38, Lock = N, SW Reset = Y.
Table 69. Register 0x36 — GPIO Mask Register (Note 1)
Bit 0 1 2 3 4 5 6 7 Name GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit. A 1 masks ALERTs for the corresponding interrupt status bit.
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 70. Register 0x37 — EDO 1 Mask Register (Note 1)
Bit 0 1 2 3 4 5 6 7 Name GPIO1 GPIO2 GPIO3 GPIO4 Reserved Fan Temp Volt R/W R/W R/W R/W R/W R/W R/W R/W R/W Description A 1 masks GPIO1 from causing an EDO1 assertion. A 1 masks GPIO2 from causing an EDO1 assertion. A 1 masks GPIO3 from causing an EDO1 assertion. A 1 masks GPIO4 from causing an EDO1 assertion. Unused. A 1 masks a fan−fail condition from causing an EDO1 assertion. A 1 masks a THERM condition from causing an EDO1 assertion. A 1 masks a voltage exceed limit condition from causing an EDO1 assertion.
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 71. Register 0x38 — EDO 2 Mask Register (Note 1)
Bit 0 1 2 3 4 5 6 7 Name GPIO1 GPIO2 GPIO3 GPIO4 Reserved Fan Temp Volt R/W R/W R/W R/W R/W R/W R/W R/W R/W Description A 1 masks GPIO1 from causing an EDO2 assertion. A 1 masks GPIO2 from causing an EDO2 assertion. A 1 masks GPIO3 from causing an EDO2 assertion. A 1 masks GPIO4 from causing an EDO2 assertion. Unused. A 1 masks a fan−fail condition from causing an EDO2 assertion. A 1 masks a THERM condition from causing an EDO2 assertion. A 1 masks a voltage exceed limit condition from causing an EDO2 assertion.
1. POR = 0x00, Lock = N, SW Reset = Y.
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Table 72. Register 0x3D — Device ID Register (Note 1)
Bit [7:0] Name Device ID R/W R Description This register contains the device ID (0x62) for the ADT7462.
1. POR = 0x62, SW Reset = N.
Table 73. Register 0x3E — Company ID Register (Note 1)
Bit [7:0] Name Company ID R/W R Description This register contains the company ID (0x41) for the ADT7462.
1. POR = 0x41, SW Reset = N.
Table 74. Register 0x3F — Revision Register (Note 1)
Bit [7:0] Name Revision ID R/W R Description This register contains the revision ID (0x04) for the ADT7462.
1. POR = 0x04, SW Reset = N.
Table 75. Temperature Limit Registers (Note 1)
Register Address 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F 0x50 0x51 0x52 0x53 1. SW Reset = N. R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Local low temperature limit. Remote 1 low temperature/Pin 15 voltage low limit. Remote 2 low temperature limit. Remote 3 low temperature/Pin 19 voltage low limit. Local high temperature limit. Remote 1 high temperature/Pin 15 voltage high limit. Remote 2 high temperature limit. Remote 3 high temperature/Pin 19 voltage high limit. Local THERM1 temperature limit/+1.5V2 (3GIO) voltage high limit. Remote 1 THERM1 temperature limit. Remote 2 THERM1 temperature limit. Remote 3 THERM1 temperature limit. Local THERM2 temperature limit/+1.5V1 (ICH) voltage high limit. Remote 1 THERM2 temperature limit. Remote 2 THERM2 temperature limit. Remote 3 THERM2 temperature limit. Lockable No No No No No No No No Yes Yes Yes Yes Yes Yes Yes Yes POR Default 0x40 0x40 0x40 0x40 0x95 0x95 0x95 0x95 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4 0xA4
Table 76. Register 0x54 — Local/Remote 1 Temperature Hysteresis (Note 1)
Bit [3:0] [7:4] Name Remote 1 Hysteresis Local Hysteresis R/W R/W R/W Description These four bits set the Remote 1 THERM hysteresis value, 1 LSB = 1°C. These four bits set the local THERM hysteresis value, 1 LSB = 1°C. 0000 = 0°C 0001 = 1°C 0010 = 2°C 0011 = 3°C 0100 = 4°C (default) 0101 = 5°C 0110 = 6°C 0111 = 7°C 1000 = 8°C 1001 = 9°C 1010 = 10°C 1011 = 11°C 1100 = 12°C 1101 = 13°C 1110 = 14°C 1111 = 15°C
1. POR = 0x44, Lock = Y, SW Reset = N.
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Table 77. Register 0x55 — Remote 2/Remote 3 Temperature Hysteresis (Note 1)
Bit [3:0] [7:4] Name Remote 3 Hysteresis Remote 2 Hysteresis R/W R/W R/W Description These four bits set the Remote 3 THERM hysteresis value, 1 LSB = 1°C. These four bits set the Remote 2 THERM hysteresis value, 1 LSB = 1°C. 0000 = 0°C 0001 = 1°C 0010 = 2°C 0011 = 3°C 0100 = 4°C (default) 0101 = 5°C 0110 = 6°C 0111 = 7°C 1000 = 8°C 1001 = 9°C 1010 = 10°C 1011 = 11°C 1100 = 12°C 1101 = 13°C 1110 = 14°C 1111 = 15°C
1. POR = 0x44, Lock = Y, SW Reset = N.
Table 78. Offset Registers (Note 1)
Register Address 0x56 0x57 0x58 0x59 R/W R/W R/W R/W R/W Description Local offset, resolution = 0.5°C. Remote 1 offset, resolution = 0.5°C. Remote 2 offset, resolution = 0.5°C. Remote 3 offset, resolution = 0.5°C. POR Default 0x00 0x00 0x00 0x00
1. Lock = Y, SW Reset = N.
Table 79. Operating Point Registers (Note 1)
Register Address 0x5A 0x5B 1. Lock = Y, SW Reset = Y. R/W R/W R/W Description Remote 1 operating point. Remote 2 operating point. POR Default 0xA4 0xA4
Table 80. Timing Registers (Note 1)
Register Address 0x5C 0x5D 0x5E 0x5F 1. Lock = Y, SW Reset = Y. R/W R/W R/W R/W R/W Local temperature TMIN. Remote 1 temperature TMIN. Remote 2 temperature TMIN. Remote 3 temperature TMIN. Description POR Default 0x9A 0x9A 0x9A 0x9A
Table 81. TRANGE/Hysteresis Registers (Note 1)
Register Address 0x60 0x61 0x62 0x63 1. Lock = Y, SW Reset = Y. R/W R/W R/W R/W R/W Local TRANGE/Hysteresis Remote 1 TRANGE/Hysteresis Remote 2 TRANGE/Hysteresis Remote 3 TRANGE/Hysteresis Description POR Default 0xC4 0xC4 0xC4 0xC4
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Table 82. Register 0x60, Register 61, Register 62, Register 63 — Local, Remote 1, Remote 2, and Remote 3 TRANGE/Hysteresis
Bit [3:0] Name Hysteresis R/W R/W Description These four bits set the hysteresis in the automatic fan speed control loop and in the dynamic TMIN control loop, 1 LSB = 1°C. 0000 = 0°C 0001 = 1°C 0010 = 2°C 0011 = 3°C 0100 = 4°C (default) 0101 = 5°C 0110 = 6°C 0111 = 7°C 1000 = 8°C 1001 = 9°C 1010 = 10°C 1011 = 11°C 1100 = 12°C 1101 = 13°C 1110 = 14°C 1111 = 15°C These four bits set the TRANGE value, that is, the slope or rate of change of fan speed with respect to temperature in the automatic fan speed control loop. 0000 = 2°C 0001 = 2.5°C 0010 = 3.3°C 0011 = 4°C 0100 = 5°C 0101 = 6.7°C 0110 = 8°C 0111 = 10°C 1000 = 13.3°C 1001 = 16°C 1010 = 20°C 1011 = 26.7°C 1100 = 32°C (default) 1101 = 40°C 1110 = 53.3°C 1111 = 80°C
[7:4]
Range
R/W
Table 83. Register 0x64 — Operating Point Hysteresis (Note 1)
Bit [3:0] [7:4] Name Reserved Operating Point Hysteresis R/W R R/W Reserved for future use. These four bits set the operating point hysteresis for the dynamic TMIN control loop, 1 LSB = 1°C. 0000 = 0°C 0001 = 1°C 0010 = 2°C 0011 = 3°C 0100 = 4°C (default) 0101 = 5°C 0110 = 6°C 0111 = 7°C 1000 = 8°C 1001 = 9°C 1010 = 10°C 1011 = 11°C 1100 = 12°C 1101 = 13°C 1110 = 14°C 1111 = 15°C Description
1. POR = 0x40, Lock = Y, SW Reset = Y.
Table 84. Voltage Limit Registers (Note 1)
Register Address 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W +3.3V high limit. Pin 23 voltage high limit. Pin 24 voltage high limit. Pin 25 voltage high limit. Pin 26 voltage high limit. +12V1 voltage low limit. +12V2 voltage low limit. +12V3 voltage low limit. +3.3V low limit. +5V low limit. Pin 23 voltage low limit. Pin 24 voltage low limit. Pin 25 voltage low limit. Pin 26 voltage low limit. +1.5V1 (ICH) voltage low limit. +1.5V2 (3GIO) voltage low limit. Description POR Default 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x20 0x00 0x00 0x80 0x00 0x00
1. Lock = N, SW Reset = N.
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Table 85. TACH Limit Registers (Note 1)
Register Address 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F R/W R/W R/W R/W R/W R/W R/W R/W R/W TACH1 limit/VID limit. TACH2 limit. TACH3 limit. TACH4 limit. TACH5 limit/+12V1 voltage high limit. TACH6 limit/+12V2 voltage high limit. TACH7 limit/+5V voltage high limit. TACH8 limit/+12V3 voltage high limit. Description POR Default 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
1. Lock = Y, SW Reset = N.
Table 86. THERM Timer Limit Registers (Note 1)
Register Address 0x80 0x81 R/W R/W R/W THERM1 Timer Limit. THERM2 Timer Limit. Description POR Default 0xFF 0xFF
1. Lock = Y, SW Reset = N.
Table 87. Temperature Value Registers (Note 1)
Register Address 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 1. Lock = N, SW Reset = N. R/W R R R R R R R R Description Bits [7:6] Local temperature value, LSBs. Local temperature value, MSBs. Bits [7:6] Remote 1 temperature value, LSBs. Remote 1 temperature value, MSBs/Pin 15 voltage. Bits [7:6] Remote 2 temperature value, LSBs. Remote 2 temperature value, MSBs. Bits [7:6] Remote 3 temperature value, LSBs. Remote 3 temperature value, MSBs/Pin 19 voltage. POR Default 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Table 88. Voltage Value Registers (Note 1)
Register Address 0x90 0x91 0x92 0x93 0x94 0x95 0x96 1. Lock = N, SW Reset = N. R/W R R R R R R R Pin 23 voltage value. Pin 24 voltage value. Pin 25 voltage value. Pin 26 voltage value. +1.5V1 (ICH) voltage value. +1.5V2 (3GIO) voltage value. +3.3V voltage value. Description POR Default 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Table 89. VID Value Registers (Note 1)
Register Address 0x97 1. Lock = N, SW Reset = N. R/W R Description This register reports the state of the seven VID inputs. POR Default 0x00
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Table 90. TACH Value Registers (Note 1)
Register Address 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 1. Lock = N, SW Reset = N. R/W R R R R R R R R R R R R R R R R TACH1, LSB. TACH1, MSB. TACH2, LSB. TACH2, MSB. TACH3, LSB. TACH3, MSB. TACH4, LSB. TACH4, MSB. TACH5, LSB. TACH5, MSB/+12V1 voltage value register. TACH6, LSB. TACH6, MSB/+12V2 voltage value register. TACH7, LSB. TACH7, MSB/+5V voltage value register. TACH8, LSB. TACH8, MSB/+12V3 voltage value register. Description POR Default 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF
Table 91. PWM Current Duty Cycle Registers (Note 1)
Register Address 0xAA 0xAB 0xAC 0xAD R/W R/W R/W R/W R/W Description PWM1 current duty cycle. PWM2 current duty cycle. PWM3 current duty cycle. PWM4 current duty cycle. POR Default 0x00 0x00 0xC0 0x00
1. Lock = N, SW Reset = N.
Table 92. THERM Timer Value Registers (Note 1)
Register Address 0xAE 0xAF 1. Lock = N, SW Reset = N. R/W R R Description THERM1 timer % on−time value. THERM2 timer % on−time value. POR Default 0x00 0x00
Table 93. Register 0xB8 — Host Thermal Status Register 1 (Note 1); Register 0xC0 — BMC Thermal Status Register 1 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name Reserved Local Temp Remote 1 Temp Remote 2 Temp Remote 3 Temp Diode 1 Error Diode 2 Error Diode 3 Error R/W R R R R R R R R Reserved for future use. A 1 indicates that a local temperature limit has been tripped. A 1 indicates that a Remote 1 temperature limit has been tripped. A 1 indicates that a Remote 2 temperature limit has been tripped. A 1 indicates that a Remote 3 temperature limit has been tripped. A 1 indicates that a Remote 1 diode error, either an open or a short, has occurred. A 1 indicates that a Remote 2 diode error, either an open or a short, has occurred. A 1 indicates that a Remote 3 diode error, either an open or a short, has occurred. Description
1. POR = 0x00, Lock = N, SW Reset = Y.
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Table 94. Register 0xB9 — Host Thermal Status Register 2 (Note 1); Register 0xC1 — BMC Thermal Status Register 2 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name THERM1 % THERM1 Assert THERM1 State THERM2 % THERM2 Assert THERM2 State VRD1_Assert VRD2_Assert R/W R R R R R R R R Description A 1 indicates that THERM1 has been asserted for longer than the programmed THERM1 timer limit. A 1 indicates that THERM1 is asserted. A 1 indicates that a transition from high to low has taken place on the THERM1 pin. A 1 indicates that THERM2 has been asserted for longer than the programmed THERM2 timer limit. A 1 indicates that THERM2 is asserted. A 1 indicates that a transition from high to low has taken place on the THERM2 pin. A 1 indicates that VRD1 is asserted. A 1 indicates that VRD2 is asserted.
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 95. Register 0xBA — Host Thermal Status Register 3 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name Local THERM1 Remote 1 THERM1 Remote 2 THERM1 Remote 3 THERM1 Local THERM2 Remote 1 THERM2 Remote 2 THERM2 Remote 3 THERM2 R/W R R R R R R R R Description A 1 indicates that the local THERM1 limit has been exceeded. A 1 indicates that the Remote 1 THERM1 limit has been exceeded. A 1 indicates that the Remote 2 THERM1 limit has been exceeded. A 1 indicates that the Remote 3 THERM1 limit has been exceeded. A 1 indicates that the Local THERM2 limit has been exceeded. A 1 indicates that the Remote 1 THERM2 limit has been exceeded. A 1 indicates that the Remote 2 THERM2 limit has been exceeded. A 1 indicates that the Remote 3 THERM2 limit has been exceeded.
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 96. Register 0xBB — Host Voltage Status Register 1 (Note 1); Register 0xC3 — BMC Voltage Register 1 (Note 1)
Bit 0 1 2 3 4 5 6 7 Name +12V1 +12V2 +12V3 +3.3V Pin 15 Voltage Pin 19 Voltage +5V Pin 23 Voltage R/W R R R R R R R R Description A 1 indicates that a +12V1 voltage limit has been tripped. A 1 indicates that a +12V2 voltage limit has been tripped. A 1 indicates that a +12V3 voltage limit has been tripped. A 1 indicates that a +3.3V voltage limit has been tripped. A 1 indicates that a Pin 15 voltage limit has been tripped. A 1 indicates that a Pin 19 voltage limit has been tripped. A 1 indicates that a +5V voltage limit has been tripped. A 1 indicates that a Pin 23 voltage limit has been tripped.
1. POR = 0x00, Lock = N, SW Reset = Y.
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Table 97. Register 0xBC — Host Voltage Status Register 2 (Note 1); Register 0xC4 — BMC Voltage Status Register 2 (Note 1)
Bit [2:0] 3 4 5 6 7 Name Reserved Pin 24 Voltage Pin 25 Voltage Pin 26 Voltage +1.5V2 (3GIO) +1.5V1 (ICH) R/W R R R R R R Reserved for future use. A 1 indicates that a Pin 24 voltage limit has been tripped. A 1 indicates that a Pin 25 voltage limit has been tripped. A 1 indicates that a Pin 26 voltage limit has been tripped. A 1 indicates that a +1.5V2 (3GIO) voltage limit has been tripped. A 1 indicates that a +1.5V1 (ICH) voltage limit has been tripped. Description
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 98. Register 0xBD — Host Fan Status Register (Note 1); Register 0xC5 — BMC Fan Status Register (Note 1)
Bit 0 1 2 3 4 5 6 7 Name Fan 1 Fault Fan 2 Fault Fan 3 Fault Fan 4 Fault Fan 5 Fault Fan 6 Fault Fan 7 Fault Fan 8 Fault R/W R R R R R R R R A 1 indicates a Fan 1 fault. A 1 indicates a Fan 2 fault. A 1 indicates a Fan 3 fault. A 1 indicates a Fan 4 fault. A 1 indicates a Fan 5 fault. A 1 indicates a Fan 6 fault. A 1 indicates a Fan 7 fault. A 1 indicates a Fan 8 fault. Description
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 99. Register 0xBE — Host Digital Status Register (Note 1); Register 0xC6 — BMC Digital Status Register (Note 1)
Bit [2:0] 3 4 5 6 7 Name Reserved FAN2MAX SCSI1 SCSI2 VID Comparison Chassis Intrusion R/W R R R R R R Reserved for future use. A 1 indicates that the FAN2MAX has been asserted as an input. A 1 indicates that the SCSI_TERM1 digital input has been asserted. A 1 indicates that the SCSI_TERM2 digital input has been asserted. A 1 indicates a VID comparison fault. A 1 indicates that the chassis intrusion digital input has been asserted. Description
1. POR = 0x00, Lock = N, SW Reset = Y.
Table 100. Register 0xBF — Host GPIO Status Register (Note 1)
Bit 0 1 2 3 4 5 6 7 Name GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 R/W R/W R/W R/W R/W R/W R/W R/W R/W A 1 indicates that GPIO1 is asserted. A 1 indicates that GPIO2 is asserted. A 1 indicates that GPIO3 is asserted. A 1 indicates that GPIO4 is asserted. A 1 indicates that GPIO5 is asserted. A 1 indicates that GPIO6 is asserted. A 1 indicates that GPIO7 is asserted. A 1 indicates that GPIO8 is asserted. Description
1. POR = 0x00, Lock = N, SW Reset = Y.
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ORDERING INFORMATION
Device Number ADT7462ACPZ−5RL7 ADT7462ACPZ−R7 ADT7462ACPZ−REEL −40°C to +125°C 32−Lead LFCSP_VQ CP−32−2 Temperature Range Package Type Package Option Shipping† 500 Tape & Reel 1500 Tape & Reel 5000 Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *The “Z’’ suffix indicates Pb−Free part.
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PACKAGE DIMENSIONS
LFCSP32 5x5, 0.5P CASE 932AE−01 ISSUE A
D D1
PIN ONE REFERENCE
A B
E1 0.20 C 0.20 C
E
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSIONS: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30mm FROM THE TERMINAL TIP. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D D1 D2 E E1 E2 e H K L M MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 5.00 BSC 4.75 BSC 2.95 3.25 5.00 BSC 4.75 BSC 2.95 3.25 0.50 BSC −−− 12 ° 0.20 −−− 0.30 0.50 −−− 0.60
TOP VIEW H
0.10 C
NOTE 4
(A3) A
0.08 C
A1 SIDE VIEW
C K
4X
SEATING PLANE
4X
M
9
D2
M
SOLDERING FOOTPRINT*
5.30 3.14
32X
17 PIN 1 INDICATOR 1 32 25 32X
E2
32X
0.63
L 3.14
1 5.30
e BOTTOM VIEW
b 0.10 C A B 0.05 C
NOTE 3
PACKAGE OUTLINE
0.50 PITCH
0.28
DIMENSIONS: MILLIMETERS
32X
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
Pentium is a registered trademark of Intel Corporation.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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