Precision Analog Microcontroller, 12-Bit Analog
I/O, ARM7TDMI MCU with Enhanced IRQ Handler
ADuC7023
Data Sheet
FEATURES
APPLICATIONS
Analog I/O
Multichannel, 12-bit, 1 MSPS ADC
Up to 12 ADC channels
Fully differential and single-ended modes
0 V to VREF analog input range
12-bit voltage output DACs
4 DAC outputs available
On-chip voltage reference
On-chip temperature sensor
Voltage comparator
Microcontroller
ARM7TDMI core, 16-bit/32-bit RISC architecture
JTAG port supports code download and debug
Clocking options
Trimmed on-chip oscillator (±3%)
External watch crystal
External clock source up to 44 MHz
41.78 MHz PLL with programmable divider
Memory
62 kB Flash/EE memory, 8 kB SRAM
In-circuit download, JTAG-based debug
Software-triggered in-circuit reprogrammability
Vectored interrupt controller for FIQ and IRQ
8 priority levels for each interrupt type
Interrupt on edge or level external pin inputs
On-chip peripherals
2× fully I2C-compatible channels
SPI (20 Mbps in master mode, 10 Mbps in slave mode)
With 4-byte FIFO on input and output stages
Up to 20 GPIO pins—Digital only GPIOs are 5 V tolerant
3× general-purpose timers
Watchdog timer (WDT)
Programmable logic array (PLA)
16 PLA elements
16-bit, 5-channel PWM
Power
Specified for 3 V operation
Active mode: 11 mA at 5 MHz, 28 mA at 41.78 MHz
Packages and temperature range
32-lead 5 mm × 5 mm LFCSP
40-lead LFCSP
36-Lead WLCSP
Fully specified for −40°C to +125°C operation
Tools
Low cost QuickStart development system
Full third-party support
Optical networking
Industrial control and automation systems
Smart sensors, precision instrumentation
Base station systems
Rev. H
GENERAL DESCRIPTION
The ADuC7023 is a fully integrated, 1 MSPS, 12-bit data acquisition
system, incorporating high performance multichannel ADCs,
16-bit/32-bit MCUs, and Flash/EE memory on a single chip.
The ADC consists of up to 12 single-ended inputs. An additional four
inputs are available but are multiplexed with the four DAC output
pins. The ADC can operate in single-ended or differential input
modes. The ADC input voltage is 0 V to VREF. A low drift band gap
reference, temperature sensor, and voltage comparator complete
the ADC peripheral set.
The DAC output range is programmable to one of two voltage ranges.
The DAC outputs have an enhanced feature of being able to retain
their output voltage during a watchdog or software reset sequence.
The devices operate from an on-chip oscillator and a PLL, generating
an internal high frequency clock of 41.78 MHz. This clock is routed
through a programmable clock divider from which the MCU core
clock operating frequency is generated. The microcontroller core is an
ARM7TDMI®, 16-bit/32-bit RISC machine that offers up to 41 MIPS
peak performance. Eight kilobytes of SRAM and 62 kilobytes of
nonvolatile Flash/EE memory are provided on chip. The ARM7TDMI
core views all memory and registers as a single linear array.
The ADuC7023 contains an advanced interrupt controller. The
vectored interrupt controller (VIC) allows every interrupt to be
assigned a priority level. It also supports nested interrupts to a
maximum level of eight per IRQ and FIQ. When IRQ and FIQ
interrupt sources are combined, a total of 16 nested interrupt
levels are supported.
On-chip factory firmware supports in-circuit download via the I2C
serial interface port, and nonintrusive emulation is supported via
the JTAG interface. These features are incorporated into a low cost
QuickStart™ development system supporting this MicroConverter®
family. The part contains a 16-bit PWM with five output signals.
For communication purposes, the part contains 2 × I2C channels that
can be individually configured for master or slave mode. An SPI
interface supporting both master and slave modes is also provided.
The parts operate from 2.7 V to 3.6 V and are specified over an
industrial temperature range of −40°C to +125°C. The ADuC7023 is
available in either a 32-lead or 40-lead LFCSP package. A 36-ball
wafer level CSP package (WLCSP) is also available.
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ADuC7023
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Flash/EE Control Interface ....................................................... 40
Applications ...................................................................................... 1
Execution Time from SRAM and Flash/EE ........................... 43
General Description ......................................................................... 1
Reset and Remap ........................................................................ 43
Revision History ............................................................................... 3
Other Analog Peripherals ............................................................. 46
Functional Block Diagram .............................................................. 5
DAC ............................................................................................. 46
Specifications .................................................................................... 6
Power Supply Monitor .............................................................. 48
Timing Specifications .................................................................. 9
Comparator ................................................................................. 48
Absolute Maximum Ratings ......................................................... 14
Oscillator and PLL—Power Control ....................................... 50
ESD Caution................................................................................ 14
Digital Peripherals .......................................................................... 53
Pin Configurations and Function Descriptions ......................... 15
General-Purpose Input/Output ............................................... 53
Typical Performance Characteristics ........................................... 19
Serial Peripheral Interface ......................................................... 56
Terminology .................................................................................... 20
I C ..................................................................................................... 61
ADC Specifications .................................................................... 20
Configuring External Pins for I2C Functionality ................... 61
DAC Specifications .................................................................... 20
Serial Clock Generation ............................................................ 61
Overview of the ARM7TDMI Core ............................................. 21
I2C Bus Addresses ...................................................................... 61
Thumb Mode (T) ....................................................................... 21
I2C Registers ................................................................................ 62
Long Multiply (M) ..................................................................... 21
Programmable Logic Array (PLA) .......................................... 69
EmbeddedICE (I) ....................................................................... 21
Pulse-Width Modulator ................................................................ 73
Exceptions ................................................................................... 21
Pulse-Width Modulator General Overview ........................... 73
ARM Registers ............................................................................ 21
Processor Reference Peripherals .................................................. 78
Interrupt Latency........................................................................ 22
Interrupt System......................................................................... 78
Memory Organization ................................................................... 23
IRQ ............................................................................................... 78
Memory Access........................................................................... 23
Fast Interrupt Request (FIQ) .................................................... 79
Flash/EE Memory....................................................................... 23
Vectored Interrupt Controller (VIC) ...................................... 80
SRAM ........................................................................................... 23
Timers .......................................................................................... 85
Memory Mapped Registers ....................................................... 23
Hardware Design Considerations .................................................. 90
ADC Circuit Overview .................................................................. 31
Power Supplies ............................................................................. 90
Transfer Function ...................................................................... 31
Grounding and Board Layout Recommendations ................ 91
Typical Operation ...................................................................... 32
Clock Oscillator .......................................................................... 91
MMR Interface ........................................................................... 32
Power-On Reset Operation ...................................................... 92
Converter Operation.................................................................. 35
Typical System Configuration .................................................. 93
Driving the Analog Inputs ........................................................ 36
Development Tools ........................................................................ 94
Calibration................................................................................... 36
PC-Based Tools .......................................................................... 94
Temperature Sensor ................................................................... 36
In-Circuit I2C Downloader ....................................................... 94
Band Gap Reference ................................................................... 38
Outline Dimensions ....................................................................... 95
Nonvolatile Flash/EE Memory ..................................................... 39
Ordering Guide .......................................................................... 97
2
Programming .............................................................................. 39
Security ........................................................................................ 40
Rev. H | Page 2 of 98
Data Sheet
ADuC7023
REVISION HISTORY
11/2020—Rev. G to Rev. H
Changes to Table 59 ........................................................................55
Updated Outline Dimensions .......................................................95
Changes to Ordering Guide...........................................................97
1/2015—Rev. F to Rev. G
Changes to Table 53 ........................................................................51
Changes to I2C Section ...................................................................60
Changes to Table 65 ........................................................................61
Changes to Table 72 ........................................................................64
Changes to I2CREPS Bit Description, Table 73 .........................66
5/2014—Rev. E to Rev. F
Change CONVSTART Pin to CONVSTART Pin ............... Throughout
Change to Layout, Power Requirements Parameter, Table 1 ..... 7
Change to Table 8 ...........................................................................13
Changes to Figure 7 and Table 9...................................................14
Change to Table 21 .........................................................................28
Change to Figure 23 ........................................................................30
Change to JTAG Access Section ...................................................37
Changes to Table 36 ........................................................................42
Changes to Table 55 ........................................................................51
Changes to I2C Bus Addresses Section .........................................59
Change to Table 84 .........................................................................71
Added PWM2LEN Register Section ............................................75
7/2013—Rev. D to Rev. E
Changes to Ordering Guide...........................................................95
7/2013—Rev. C to Rev. D
Added WLCSP (Throughout) ......................................................... 1
Changes to Features Section ............................................................ 1
Added Shared Analog/Digital Inputs to AGND Rating of
−0.3 V to AVDD + 0.3 V, Endnote 1, and Endnote 2; Table 8 ...13
Added Figure 9; Renumbered Sequentially; Added WLCSP Pin
Numbers to Table 9 ........................................................................14
Changes to Pin P1.7/PWM3/SDA1/PLAI[6] and Pin
P1.6/PWM2/SCL1/PLAI[5] Descriptions; Table 9 ....................16
Changes to ADC Circuit Overview Section, Transfer Function
Section, and Figure 20 Caption .....................................................29
Changes to Typical Operation Section, ADCCON Register
Section, and ADCON[13] Description in Table 24 ...................30
Changes to Bits[4:3] Value 10 Description; Table 24 ................31
Changes to Converter Operation Section and Deleted Pseudo
Differential Mode Section ..............................................................33
Changes to Figure 27 and Figure 28 Caption..............................34
Changes to Table 30 and Following Text ....................................36
Changes to JTAG Access Section..................................................37
Changes to References to ADC and the DACs Section .............45
Changes to General-Purpose Input/Output Section..................51
Changes to SPIDIV Register Section............................................56
Changes to Bits[1:0] Value 01 Description; Table 66 ................61
Changes to T0CLRI Register Section ...........................................84
Changes to Figure 53 ......................................................................90
Updated Outline Dimensions ....................................................... 93
Changes to Ordering Guide .......................................................... 95
5/2012—Rev. B to Rev. C
Changed SDATA to SDA and SCLK to SCL, Table 2; SDATA
to SDA and SCLK to SCL, Table 3; and SDATA to SDA and
SCLK to SCL, Figure 2...................................................................... 8
Changes to Figure 7, Figure 8, and Table 9 ................................. 14
Changed SCLK to SCL, Table 17 .................................................. 25
Changed SCLK to SCL, Table 18 .................................................. 26
Changes to Bit 6, Table 24 and 4 to 0, Description Column,
Table 25 ............................................................................................ 30
Changed Reference in REFCON Register Section from Table 22
to Table 30 ........................................................................................ 35
Added Note 1 to Table 53 .............................................................. 49
Changes to Note 1, Table 55 .......................................................... 50
Changed SPICLK (Serial Clock I/O) Pin Section to SCLK
(Serial Clock I/O) Pin Section ....................................................... 53
Changed SPICLK to SCLK in Serial Peripheral Interface
Section and in SCLK (Serial Clock I/O) Pin Section ................. 53
Changes to Table 79........................................................................ 68
Changes to Timers Section ............................................................ 82
Added Hours, Minutes, Seconds, and 1/128 Format Section and
Table 101 .......................................................................................... 82
Changes to T0LD Register Section and T1LD Register Section..... 83
Changes to T2LD Register Section....................................................... 85
Updated Outline Dimensions ....................................................... 92
Changes to Ordering Guide .......................................................... 93
7/2010—Rev. A to Rev. B
Changes to Temperature Sensor Parameter in Table 1 ............... 6
Change to Table 10 and changes to Table 11 .............................. 23
Changes to Table 12 and Table 13 ................................................ 24
Changes to Table 16 and Table 17 ................................................ 25
Changes to Table 18........................................................................ 26
Change to Table 21 and changes to Table 22 .............................. 27
Changes to Table 24........................................................................ 29
Changes to ADCGN Register and ADCOF Register Sections . 32
Changes to Temperature Sensor Section ..................................... 34
Changes to Table 29........................................................................ 35
Change to REMAP Register and RSTCLR Register Sections ... 41
Change to RSTKEY1 Register and RSTKEY2 Register
Sections ............................................................................................. 42
Changes to Oscillator and PLL—Power Control Section ......... 48
Changes to General-Purpose Input/Output Section ................. 51
Changes to Serial Peripheral Interface Section ........................... 53
Changes to Table 75........................................................................ 67
Changes to Table 83 and Pulse-Width Modulator General
Overview Section ............................................................................ 70
Changes to Table 84........................................................................ 71
Change to Table 85 ......................................................................... 72
Change to FIQSTAN Register Section ......................................... 81
Change to T2CLRI Register Section............................................. 85
Rev. H | Page 3 of 98
ADuC7023
Data Sheet
6/2010—Rev. 0 to Rev. A
Changes to Temperature Sensor Parameter in Table 1 .............. 6
Changes to Table 24 ....................................................................... 29
Changes to Temperature Sensor Section .................................... 34
Changes to DACBKEY0 Register Section and to Table 43 ...... 47
Changes to Ordering Guide .......................................................... 93
1/2010—Revision 0: Initial Version
Rev. H | Page 4 of 98
Data Sheet
ADuC7023
FUNCTIONAL BLOCK DIAGRAM
ADC0
MUX
12-BIT
DAC
DAC1
12-BIT
DAC
DAC2
12-BIT
DAC
DAC3
40-LEAD LFCSP
TEMP
SENSOR
ADC2/CMP0
VECTORED
INTERRUPT
CONTROLLER
BAND GAP
REF
CMPOUT
DAC0
ADuC7023
1MSPS
12-BIT ADC
ADC12
ADC3/CMP1
12-BIT
DAC
VREF
XCLKI
ARM7TDMI-BASED MCU WITH
ADDITIONAL PERIPHERALS
OSC
AND PLL
XCLKO
PSM
PLA
2k × 32 SRAM
31k × 16 FLASH/EEPROM
GPIO
PWM
POR
3 GENERALPURPOSE TIMERS
SPI, 2 × I2C
JTAG
08675-001
RST
Figure 1.
Rev. H | Page 5 of 98
ADuC7023
Data Sheet
SPECIFICATIONS
AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
ADC CHANNEL SPECIFICATIONS
ADC Power-Up Time
DC Accuracy1, 2
Resolution
Integral Nonlinearity
Min
Max
5
±0.6
±1.0
±0.5
+0.7/−0.6
1
±1.5
±1
±1
±2
±1
±2
+1/−0.9
69
−78
−75
−80
±1
20
Bits
LSB
LSB
LSB
LSB
LSB
Test Conditions/Comments
Eight acquisition clocks and fADC/2
VCM ± VREF/26
0 to VREF
±6
±4
±15
75
51
1
AVDD
2.5 V internal reference
1.0 V external reference
2.5 V internal reference
1.0 V external reference
ADC input is a dc voltage
LSB
LSB
LSB
LSB
dB
dB
dB
dB
2.5
0.625
Unit
μs
12
Differential Nonlinearity3, 4
DC Code Distribution
ENDPOINT ERRORS5
Offset Error
Offset Error Match
Gain Error
Gain Error Match
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Total Harmonic Distortion (THD)
Peak Harmonic or Spurious Noise
Channel-to-Channel Crosstalk
ANALOG INPUT
Input Voltage Ranges
Differential Mode
Single-Ended Mode
Leakage Current
Input Capacitance
ON-CHIP VOLTAGE REFERENCE
Output Voltage
Accuracy
Reference Temperature Coefficient
Power Supply Rejection Ratio
Output Impedance
Internal VREF Power-On Time
EXTERNAL REFERENCE INPUT
Input Voltage Range
DAC CHANNEL SPECIFICATIONS
DC Accuracy7
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error8
Gain Error Mismatch
DC Accuracy9
Resolution
Relative Accuracy
Differential Nonlinearity
Offset Error
Gain Error10
Gain Error Mismatch
ANALOG OUTPUTS
Output Voltage Range 1
Output Voltage Range 2
Output Impedance
Typ
V
V
μA
pF
V
mV
ppm/°C
dB
Ω
ms
fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS
Includes distortion and noise components
Measured on adjacent channels
During ADC acquisition
0.47 μF from VREF to AGND
TA = 25°C
TA = 25°C
V
RL = 5 kΩ, CL = 100 pF
12
±2
Guaranteed monotonic
2.5 V internal reference
0.1
Bits
LSB
LSB
mV
%
%
12
±2.5
±1
±15
±1
0.1
Bits
LSB
LSB
mV
%
%
Guaranteed monotonic
2.5 V internal reference
0 to 2.5
0 to AVDD
2
V
V
Ω
±1
±15
±1
Rev. H | Page 6 of 98
% of full scale on DAC0
RL = 1 kΩ, CL = 100 pF
% of full scale on DAC0
VREF range: AGND to AVDD
Data Sheet
Parameter
DAC IN OP AMP MODE
DAC Output Buffer in Op Amp Mode
Input Offset Voltage
Input Offset Voltage Drift
Input Offset Current
Input Bias Current
Gain
Unity-Gain Frequency
CMRR
Settling Time
Output Slew Rate
PSRR
DAC AC CHARACTERISTICS
Voltage Output Settling Time
Digital-to-Analog Glitch Energy
COMPARATOR
Input Offset Voltage
Input Bias Current
Input Voltage Range
Input Capacitance
Hysteresis4, 6
Response Time
TEMPERATURE SENSOR
Voltage Output at 25°C
Voltage TC
Accuracy with No Calibration
Accuracy with One Point Calibration
Using Contents of TEMPREF Register
θJA Thermal Impedance
40-Lead LFCSP
32-Lead LFCSP
POWER SUPPLY MONITOR (PSM)
IOVDD Trip Point Selection
Power Supply Trip Point Accuracy
POWER-ON RESET
WATCHDOG TIMER (WDT)
Timeout Period
FLASH/EE MEMORY
Endurance11
Data Retention12
DIGITAL INPUTS
Logic 1 Input Current
Logic 0 Input Current
Input Capacitance
LOGIC INPUTS4
VINL, Input Low Voltage
VINH, Input High Voltage
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage13
CRYSTAL INPUTS XCLKI AND XCLKO
Logic Inputs, XCLKI Only
VINL, Input Low Voltage
VINH, Input High Voltage
XCLKI Input Capacitance
XCLKO Output Capacitance
ADuC7023
Min
Typ
Unit
Test Conditions/Comments
±0.25
8
0.3
0.4
80
5
80
10
1.5
75
mV
μV/°C
nA
nA
dB
MHz
dB
μs
V/μs
dB
5 kΩ load
RL = 5 kΩ, CL = 100 pF
10
±20
μs
nV-sec
±10
1
mV
μA
V
pF
mV
AGND
Max
AVDD – 1.2
7
2
15
3
μs
1.369
4.42
±3
±1.5
V
mV/°C
°C
°C
26
32.5
°C/W
°C/W
2.79
±2
2.41
V
%
V
0
512
10,000
20
1 LSB change at major carry (where maximum number of
bits simultaneously change in the DACxDAT register)
Hysteresis can be turned on or off via the CMPHYST bit
in the CMPCON register
100 mV overdrive and configured with CMPRES = 11
Indicates die temperature
One trip point
Of the selected nominal trip point voltage
sec
Cycles
Years
±0.2
−40
−80
10
RL = 5 kΩ, CL = 100 pF
RL = 5 kΩ, CL = 100 pF
±1
−60
−120
μA
μA
μA
pF
0.8
V
V
TJ = 85°C
All digital inputs excluding XCLKI and XCLKO
VIH = VDD or VIH = 5 V
VIL = 0 V; except TDI
VIL = 0 V; TDI
All logic inputs excluding XCLKI
2.0
2.4
0.4
1.1
1.7
20
20
V
V
V
V
pF
pF
Rev. H | Page 7 of 98
All digital outputs excluding XCLKO
ISOURCE = 1.6 mA
ISINK = 1.6 mA
ADuC7023
Parameter
INTERNAL OSCILLATOR
MCU CLOCK RATE
From 32 kHz Internal Oscillator
From 32 kHz External Crystal
Using an External Clock
Data Sheet
Min
IOVDD Current in Pause Mode
IOVDD Current in Sleep Mode
Additional Power Supply Currents
ADC
DAC
ESD TESTS
HBM Passed
FICDM Passed
Max
Test Conditions/Comments
±3
Unit
kHz
%
44
41.78
kHz
MHz
MHz
MHz
CD = 7
CD = 0
TA = 85°C
TA = 125°C
Core clock = 41.78 MHz
326
41.78
0.05
0.05
START-UP TIME
At Power-On
From Pause/Nap Mode
From Sleep Mode
From Stop Mode
PROGRAMMABLE LOGIC ARRAY (PLA)
Pin Propagation Delay
Element Propagation Delay
POWER REQUIREMENTS14, 15
Power Supply Voltage Range
AVDD to AGND and IOVDD to DGND
Analog Power Supply Currents
AVDD Current
Digital Power Supply Current
IOVDD Current in Normal Mode
Typ
32.768
66
24
3.07
1.58
1.7
ms
ns
μs
ms
ms
12
2.5
ns
ns
2.7
3.6
200
8.5
11
28
14
230
10
15
35
20
650
1.4
0.7
400
1
From input pin to output pin
V
μA
ADC in idle mode
mA
mA
mA
mA
μA
Code executing from Flash/EE
CD = 7
CD = 3
CD = 0 (41.78 MHz clock)
CD = 0 (41.78 MHz clock)
TA = 125°C
mA
mA
μA
3
1.0
CD = 0
CD = 7
At 1 MSPS
At 62.5 kSPS
Per DAC
2.5 V reference, TA = 25°C
kV
kV
All ADC channel specifications are guaranteed during normal microcontroller core operation.
Apply to all ADC input channels.
3
Measured using the factory-set default values in the ADC offset register (ADCOF) and gain coefficient register (ADCGN).
4
Not production tested but supported by design and/or characterization data on production release.
5
Measured using the factory-set default values in ADCOF and ADCGN with an external AD845 op amp as an input buffer stage as shown in Figure 28. Based on external ADC
system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section).
6
The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified.
7
DAC linearity is calculated using a reduced code range of 100 to 3995.
8
DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
9
DAC linearity is calculated using a reduced code range of 100 to 3995.
10
DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF.
11
Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
12
Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
13
Test carried out with a maximum of eight I/Os set to a low output level.
14
Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: normal mode with 3.6 V supply, pause mode with
3.6 V supply, and sleep mode with 3.6 V supply.
15
IOVDD power supply current decreases typically by 2 mA during a Flash/EE erase cycle.
2
Rev. H | Page 8 of 98
Data Sheet
ADuC7023
TIMING SPECIFICATIONS
Table 2. I2C Timing in Fast Mode (400 kHz)
Parameter
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
Description
SCL low pulse width
SCL high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCL and SDA
Fall time for both SCL and SDA
Min
200
100
300
100
0
100
100
1.3
Slave
Max
Master
Typ
1360
1140
Unit
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
740
400
800
300
300
200
Table 3. I2C Timing in Standard Mode (100 kHz)
Parameter
tL
tH
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
tF
Description
SCL low pulse width
SCL high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Bus-free time between a stop condition and a start condition
Rise time for both SCL and SDA
Fall time for both SCL and SDA
tBUF
Slave
Max
Min
4.7
4.0
4.0
250
0
4.7
4.0
4.7
Unit
μs
ns
μs
ns
μs
μs
μs
μs
μs
ns
3.45
1
300
tSUP
tR
MSB
tDSU
LSB
tSHD
P
S
tDHD
2–7
tR
tRSU
tH
1
SCL (I)
MSB
tF
tDSU
tDHD
tPSU
ACK
8
tL
9
tSUP
STOP
START
CONDITION CONDITION
1
S(R)
REPEATED
START
Figure 2. I2C-Compatible Interface Timing
Rev. H | Page 9 of 98
tF
08675-002
SDA (I/O)
ADuC7023
Data Sheet
Table 4. SPI Master Mode Timing (Phase Mode = 1)
Parameter
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
Min
Typ
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
Max
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
MSB
MOSI
MISO
tDR
MSB IN
BIT 6 TO BIT 1
BIT 6 TO BIT 1
tDSU
tDHD
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
Rev. H | Page 10 of 98
LSB
LSB IN
08675-003
1
Description
SCLK low pulse width1
SCLK high pulse width1
Data output valid after SCLK edge
Data input setup time before SCLK edge1
Data input hold time after SCLK edge1
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
ADuC7023
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter
tSL
tSH
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
Min
Typ
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
75
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDOSU
MSB
MOSI
MISO
tDF
MSB IN
tDSU
tDR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
LSB IN
08675-004
1
Description
SCLK low pulse width1
SCLK high pulse width1
Data output valid after SCLK edge
Data output setup before SCLK edge
Data input setup time before SCLK edge1
Data input hold time after SCLK edge1
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Rev. H | Page 11 of 98
ADuC7023
Data Sheet
Table 6. SPI Slave Mode Timing (Phase Mode = 1)
Parameter
tSS
Description
SS to SCLK edge
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tSFS
SCLK low pulse width1
SCLK high pulse width1
Data output valid after SCLK edge
Data input setup time before SCLK edge1
Data input hold time after SCLK edge1
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SS high after SCLK edge
Typ
Max
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
0
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SS
tSFS
tSS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
MSB
MOSI
MISO
MSB IN
tDR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
tDSU
LSB
LSB IN
08675-005
1
Min
200
tDHD
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
Rev. H | Page 12 of 98
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Sheet
ADuC7023
Table 7. SPI Slave Mode Timing (Phase Mode = 0)
Parameter
tSS
Description
SS to SCLK edge
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
SCLK low pulse width1
SCLK high pulse width1
Data output valid after SCLK edge
Data input setup time before SCLK edge1
Data input hold time after SCLK edge1
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Data output valid after SS edge
SS high after SCLK edge
Typ
Max
Unit
ns
(SPIDIV + 1) × tUCLK
(SPIDIV + 1) × tUCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
1 × tUCLK
2 × tUCLK
5
5
5
5
12.5
12.5
12.5
12.5
25
0
tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
SS
tSFS
tSS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDOCS
tDF
MSB
MOSI
MISO
MSB IN
tDSU
tDR
BIT 6 TO BIT 1
BIT 6 TO BIT 1
LSB
LSB IN
08675-006
1
Min
200
tDHD
Figure 6. SPI Slave Mode Timing (Phase Mode = 0)
Rev. H | Page 13 of 98
ADuC7023
Data Sheet
ABSOLUTE MAXIMUM RATINGS
AGND = GNDREF, TA = 25°C, unless otherwise noted.
Table 8.
Parameter
AVDD to IOVDD
AGND to DGND
IOVDD to DGND, AVDD to AGND
Digital Input Voltage to DGND1
Digital Output Voltage to DGND1
Shared Analog/Digital Inputs to AGND2
VREF to AGND
Analog Inputs to AGND
Analog Outputs to AGND
Operating Temperature Range, Industrial
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
40-Lead LFCSP
32-Lead LFCSP
36-Lead WLCSP
Peak Solder Reflow Temperature
SnPb Assemblies (10 sec to 30 sec)
RoHS Compliant Assemblies
(20 sec to 40 sec)
Rating
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +6 V
−0.3 V to +5.3 V
−0.3 V to IOVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
26°C/W
32.5°C/W
50°C/W
240°C
260°C
1
These limits apply to the P0.0, P0.1, P0.2, P0.3, P0.4, P0.5, P0.6, P0.7, P1.0,
P1.1, P1.6, and P1.7 pins.
2
These limits apply to the P1.2, P1.3, P1.4, P1.5, P2.0, P2.2, P2.3, and P2.4 pins.
Rev. H | Page 14 of 98
Data Sheet
ADuC7023
40
39
38
37
36
35
34
33
32
31
32
31
30
29
28
27
26
25
AGND
ADC3/CMP1
ADC2/CMP0
ADC1
ADC0
VREF
P1.3/ADC5/IRQ3/PLAI[4]
P1.2/ADC4/IRQ2/PLAI[3]/ECLK
P2.4/ADC9/PLAI[10]
P2.3/ADC8/PLAO[7]
AGND
ADC3/CMP1
ADC2/CMP0
ADC1
ADC0
VREF
P1.3/ADC5/IRQ3/PLAI[4]
P1.2/ADC4/IRQ2/PLAI[3]/ECLK
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
P0.5/SDA0/PLAI[1]/COMPOUT 8
ADuC7023
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
P0.3/PLAO[9]/TCK
P0.2/PLAO[8]/TDI
P0.1/PLAI[9]/TDO
P0.0/nTRST/ADCBUSY/PLAI[8]/BM
TMS
RTCK
XCLKO
XCLKI
NOTES
1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND
EITHER CONNECTED TO AGND OR LEFT FLOATING.
08675-048
NOTES
1. EXPOSED PAD. THE PADDLE NEEDS TO BE SOLDERED AND
EITHER CONNECTED TO AGND OR LEFT FLOATING.
Figure 8. 32-Lead LFCSP Pin Configuration
Figure 7. 40-Lead LFCSP Pin Configuration
BALL A1
CORNER
1
2
3
4
5
6
A
A1
A2
A3
A4
A5
A6
B
B1
B2
B3
B4
B5
B6
C
C1
C2
C3
C4
C5
C6
D
D1
D2
D3
D4
D5
D6
E
E1
E2
E3
E4
E5
E6
F
F1
F2
F3
F4
F5
F6
TOP VIEW
(BALL SIDE DOWN)
Not to Scale
08675-109
ADuC7023
Figure 9. 36-Lead WLCSP Pin Configuration
Table 9. Pin Function Descriptions
40LFCSP
0
Pin No.
3236LFCSP WLCSP
0
N/A
Mnemonic
Exposed Paddle
36
37
38
39
32
28
29
30
31
N/A
ADC0
ADC1
ADC2/CMP0
ADC3/CMP1
P2.4/ADC9/PLAI[10]
A4
B4
A5
B5
B2
Description
Exposed Pad. The paddle needs to be soldered and either connected to
AGND or left floating.
Single-Ended or Differential Analog Input 0.
Single-Ended or Differential Analog Input 1.
Single-Ended or Differential Analog Input 2/Comparator Positive Input.
Single-Ended or Differential Analog Input 3/Comparator Negative Input.
General-Purpose Input and Output Port 2.4/ADC Single-Ended or Differential Analog Input/Programmable Logic Array Input Element 10.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.
Rev. H | Page 15 of 98
08675-007
P0.6/MISO/PLAI[2]
P0.7/MOSI/PLAO[0]
P1.0/SPICLK/PWM0/PLAO[1]
P1.1/SS/IRQ1/PWM1/PLAO[2]/TI
P1.6/PWM2/SCL1/PLAI[5]
P1.7/PWM3/SDA1/PLAI[6]
DGND
IOVDD
LV DD
RST
11
12
13
14
15
16
17
18
19
20
TOP VIEW
(Not to Scale)
AV DD
GNDREF
DAC0
DAC1
DAC2
DAC3
P0.4/IRQ0/SCL0/PLAI[0]/CONVSTART
P2.2/ADC7/SYNC/PLAO[6]
P1.5/ADC6/PWMTRIPINPUT /PLAO[4]
P0.3/PLAO[9]/TCK
P0.2/PLAO[8]/TDI
P0.1/PLAI[9]/TDO
P0.0/nTRST/ADCBUSYPLAI[8]/BM
TMS
RTCK
XCLKO
XCLKI
9
10
11
12
13
14
15
16
ADuC7023
30
29
28
27
26
25
24
23
22
21
P0.6/MISO/SCL1/PLAI[2]
P0.7/MOSI/SDA1/PLAO[0]
P1.0/SPICLK/PWM0/PLAO[1]
P1.1/SS/IRQ1/PWM1/PLAO[2]/T1
DGND
IOVDD
LV DD
RST
AV DD 1
GNDREF 2
DAC0 3
DAC1 4
DAC2 5
DAC3 6
P1.4/ADC10/PLAO[3] 7
P2.0/ADC12/PWM4/PLAI[7] 8
P0.4/IRQ0/SCL0/PLAI[0]/CONVSTART 9
P0.5/SDA0/PLAI[1]/COMPOUT 10
ADuC7023
Data Sheet
40LFCSP
31
Pin No.
3236LFCSP WLCSP
N/A
A1
Mnemonic
P2.3/ADC8/PLAO[7]
30
N/A
B1
P2.2/ADC7/SYNC/PLAO[6]
8
N/A
E6
P2.0/ADC12/PWM4/PLAI[7]
2
2
C4
GNDREF
3
4
5
6
24
3
4
5
6
20
C5
C6
D5
D6
D2
DAC0
DAC1
DAC2
DAC3
TMS
25
21
D1
P0.0/nTRST/ADCBUSY/PLAI[8]/BM
26
22
C1
P0.1/PLAI[9]/TDO
27
23
C2
P0.2/PLAO[8]/TDI
Description
General-Purpose Input and Output Port 2.3/ADC Single-Ended or
Differential Analog Input 8/Programmable Logic Array Output Element 7.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, pull-up resistor should be
disabled manually.
General-Purpose Input and Output Port 2.2/ADC Single-Ended or
Differential Analog Input 7/PWM Sync/Programmable Logic Array Output
Element 6. By default, this pin is configured as a digital input with a weak
pull-up resistor enabled. When used as ADC input, pull-up resistor should
be disabled manually.
General-Purpose Input and Output Port 2.0/ADC Single-Ended or
Differential Analog Input 12/PWM Output 4/Programmable Logic Array
Input Element 7. By default, this pin is configured as a digital input with a
weak pull-up resistor enabled. When used as an ADC input, it is not
possible to disable the internal pull-up resister. This means that this pin
has a higher leakage current value than other analog input pins.
Ground Voltage Reference for the ADC. For optimal performance, the
analog power supply should be separated from DGND.
DAC0 Voltage Output or ADC Input.
DAC1 Voltage Output or ADC Input.
DAC2 Voltage Output
DAC3 Voltage Output
Test Mode Select, JTAG Test Port Input. Debug and download access.
This pin has an internal pull-up resistor to IOVDD. In some cases an external
pull-up resistor is also required to ensure the part does not enter an
erroneous state.
This is a multifunction pin as follows:
General-Purpose Input and Output Port 0.0. By default, this pin is
configured as GPIO.
JTAG Reset Input. Debug and download access. If this pin is held low, JTAG
access is not possible because the JTAG interface is held in reset and
P0.1/P0.2/P0.3 are configured as GPIO pins.
ADC Busy Signal.
Programmable Logic Array Input Element 8.
Boot Mode Entry Pin. The ADuC7023 enters I2C download mode if BM is
low at reset with a flash address 0x80014 = 0xFFFFFFFFF. The ADuC7023
executes code if BM is pulled high at reset or if BM is low at reset with a
flash address 0x80014 not equal to 0xFFFFFFFFF.
The default value of this pin depends on the level of P0.0/BM. If P0.0/
BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this
pin defaults to a JTAG test data output pin and does not work as a GPIO.
This is a multifunction pin as follows:
General-Purpose Input and Output Port 0.1.
Programmable Logic Array Input Element 9.
Test Data Out, JTAG Test Port Output. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code,
and the GP0CON/GP0DAT register bits affecting this pin must not be
changed as doing so disables JTAG access.
The default value of this pin depends on the level of P0.0/BM. If P0.0/
BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin
defaults to a JTAG test data input pin and does not work as a GPIO. This is
a multifunction pin as follows:
General-Purpose Input and Output Port 0.2.
Programmable Logic Array Output Element 8.
Test Data In, JTAG Test Port Input. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code,
and the GP0CON/GP0DAT register bits affecting this pin must not be
changed as doing so disables JTAG access.
Rev. H | Page 16 of 98
Data Sheet
ADuC7023
40LFCSP
28
Pin No.
3236LFCSP WLCSP
24
C3
Mnemonic
P0.3/PLAO[9]/TCK
17
18
19
13
14
15
E3
F3
D3
DGND
IOVDD
LVDD
20
23
16
19
F2
E1
RST
RTCK
9
7
F6
P0.4/IRQ0/SCL0/PLAI[0]/CONV
10
8
E5
P0.5/SDA0/PLAI[1]/COMPOUT
9
F5
P0.6/MISO/SCL1/PLAI[2]
10
D4
P0.7/MOSI/SDA1/PLAO[0]
11
P0.6/MISO/PLAI[2]
12
P0.7/MOSI/PLAO[0]
21
17
F1
XCLKI
22
16
18
N/A
E2
N/A
XCLKO
P1.7/PWM3/SDA1/PLAI[6]
15
N/A
N/A
P1.6/PWM2/SCL1/PLAI[5]
29
N/A
N/A
P1.5/ADC6/PWMTRIPINPUT/PLAO[4]
7
N/A
N/A
P1.4/ADC10/PLAO[3]
Description
The default value of this pin depends on the level of P0.0/BM. If P0.0/BM =
0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin
defaults to a JTAG test data clock pin. This is a multifunction pin as follows:
General-Purpose Input and Output Port 0.3.
Programmable Logic Array Output Element 9.
Test Clock, JTAG Test Port Clock Input. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code
and the GP0CON/GP0DAT register bits affecting this pin must not be
changed as doing so disables JTAG access.
Digital Ground.
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
2.6 V Output of the On-Chip Voltage Regulator. This output must be
connected to a 0.47 μF capacitor to DGND only.
Reset Input, Active Low.
Return JTAG Clock Signal. This is not the standard JTAG clock signal. It is
an output signal from the JTAG controller. If using a 20-lead JTAG header,
connect to Pin 11.
General-Purpose Input and Output Port 0.4/External Interrupt Request 0/ I2C0
Clock Signal/Programmable Logic Array Input Element 0/ADC External
Convert Start. By default, this pin is configured as a digital input with a
weak pull-up resistor enabled.
General-Purpose Input and Output Port 0.5/I2C0 Data Signal/ Programmable
Logic Array Input Element 1/Voltage Comparator Output. By default, this
pin is configured as a digital input with a weak pull-up resistor enabled.
General-Purpose Input and Output Port 0.6/SPI MISO Signal/I2C1 Clock On
32-Lead and 36-Ball Packages/Programmable Logic Array Input Element 2.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.
General-Purpose Input and Output Port 0.7/SPI MOSI Signal/I2C1 Data
Signal On 32-Lead and 36-Ball Packages/Programmable Logic Array Output
Element 0.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled.
General-Purpose Input and Output Port 0.6/SPI MISO Signal/Programmable
Logic Array Input Element 2. By default, this pin is configured as a digital input
with a weak pull-up resistor enabled.
General-Purpose Input and Output Port 0.7/SPI MOSI Signal/Programmable
Logic Array Output Element 0. By default this pin is configured as a digital
input with a weak pull-up reisistor enabled.
Input to the Crystal Oscillator Inverter and Input to the Internal Clock
Generator Circuits. Connect to DGND if unused.
Output from the Crystal Oscillator Inverter. Leave unconnected if unused.
General-Purpose Input and Output Port 1.7/PWM Output 3/I2C1 Data
Signal/Programmable Logic Array Input Element 6. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.
General-Purpose Input and Output Port 1.6/PWM Output 2/I2C1 Clock
Signal/Programmable Logic Array Input Element 5. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.
General-Purpose Input and Output Port 1.5/ADC Single-Ended or
Differential Analog Input 6/PWMTRIPINPUT/Programmable Logic Array
Output Element 4. By default, this pin is configured as a digital input with
a weak pull-up resistor enabled. When used as ADC input, the pull-up
resistor should be disabled manually.
General-Purpose Input and Output Port 1.4/ADC Single-Ended or Differential Analog Input 10/Programmable Logic Array Output Element 3.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.
Rev. H | Page 17 of 98
ADuC7023
Data Sheet
40LFCSP
34
Pin No.
3236LFCSP WLCSP
26
A3
Mnemonic
P1.3/ADC5/IRQ3/PLAI[4]
33
25
A2
P1.2/ADC4/IRQ2/PLAI[3]/ECLK/
14
12
F4
P1.1/SS/IRQ1/PWM1/PLAO[2]/T1
13
11
E4
P1.0/SCLK/PWM0/PLAO[1]
35
27
B3
VREF
40
1
32
1
A6
B6
AGND
AVDD
Description
General-Purpose Input and Output Port 1.3/ADC Single-Ended or
Differential Analog Input 5/External Interrupt Request 3/ Programmable
Logic Array Input Element 4.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.
General-Purpose Input and Output Port 1.2/ADC Single-Ended or
Differential Analog Input 4/External Interrupt Request 2/ Programmable
Logic Array Input Element 3/Input-Output for External Clock.
By default, this pin is configured as a digital input with a weak pull-up
resistor enabled. When used as ADC input, the pull-up resistor should be
disabled manually.
General-Purpose Input and Output Port 1.1/SPI Interface Slave Select
(Active Low)/External Interrupt Request 1/PWM Output 1/ Programmable
Logic Array Output Element 2/Timer 1 Input Clock. By default, this pin is
configured as a digital input with a weak pull-up resistor enabled.
General-Purpose Input and Output Port 1.0/SPI Interface Clock Signal/
PWM Output 0/Programmable Logic Array Output Element 1. By default,
this pin is configured as a digital input with a weak pull-up resistor enabled.
2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor
when using the internal reference.
Analog Ground. Ground reference point for the analog circuitry.
3.3 V Analog Power.
Rev. H | Page 18 of 98
Data Sheet
ADuC7023
1.2
0.5
1.0
0.4
0.8
0.3
0.6
0.2
0.4
0.1
0
–0.1
–0.2
–0.4
–0.3
–0.6
–0.4
–0.8
500
1000
3500
–1.0
4095
20
0.4
0
SINAD, THD AND PHSN OF ADC (dB)
0.6
0.2
0
–0.2
–0.4
–0.6
–0.8
500
1000
1500
2000 2500 3000
ADC CODES
SAMPLING RATE = 950kSPS
WORST CASE POSITIVE = 0.57, CODE = 4063
WORST CASE NEGATIVE = –0.90, CODE = 3356
3500
0.4
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
1500
2000 2500 3000
ADC CODES
SAMPLING RATE = 950kSPS
WORST CASE POSITIVE = 0.64, CODE = 3583
WORST CASE NEGATIVE = –0.61, CODE = 1830
3500
4095
08675-051
1000
4095
–40
–60
–80
–100
–200
20,000
40,000
60,000
FREQUENCY (Hz)
80,000
104,400
Figure 14. SINAD, THD, and PHSN of ADC , Internal 2.5 V Reference Used
0.5
500
3500
–20
0
0.6
0
1500
2000 2500 3000
ADC CODES
SAMPLING RATE = 950kSPS
WORST CASE POSITIVE = 1.09, CODE = 4032
WORST CASE NEGATIVE = –0.98, CODE = 3422
–400
4095
Figure 11. Typical INL, fADC = 950 kSPS, Internal Reference Used
–0.6
1000
08675-050
0
500
Figure 13. Typical INL, fADC = 950 kSPS, External 1.0 V Reference Used
Figure 10. Typical DNL, fADC = 950 kSPS, Internal Reference Used
–1.0
0
08675-053
1500
2000 2500 3000
ADC CODES
SAMPLING RATE = 950kSPS
WORST CASE POSITIVE = 0.63, CODE = 2364
WORST CASE NEGATIVE = –0.46, CODE = 2363
INL (LSB)
0
–0.2
0
DNL (LSB)
0.2
08675-052
INL (LSB)
0.6
08675-049
DNL (LSB)
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 12. Typical DNL, fADC = 950 kSPS, External 1.0 V Reference Used
Rev. H | Page 19 of 98
ADuC7023
Data Sheet
TERMINOLOGY
ADC SPECIFICATIONS
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise.
Integral Nonlinearity (INL)
The maximum deviation of any code from a straight line
passing through the endpoints of the ADC transfer function.
The endpoints of the transfer function are zero scale, a point
½ LSB below the first code transition, and full scale, a point
½ LSB above the last code transition.
The theoretical signal to (noise + distortion) ratio for an ideal
N-bit converter with a sine wave input is given by
Differential Nonlinearity (DNL)
The difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Total Harmonic Distortion
The ratio of the rms sum of the harmonics to the fundamental.
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus, for a 12-bit converter, this is 74 dB.
DAC SPECIFICATIONS
Offset Error
The deviation of the first code transition (0000 . . . 000) to
(0000 . . . 001) from the ideal, that is, +½ LSB.
Relative Accuracy
Otherwise known as endpoint linearity, relative accuracy is a
measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero error and full-scale error.
Gain Error
The deviation of the last code transition from the ideal AIN
voltage (full scale − 1.5 LSB) after the offset error has been
adjusted out.
Signal to (Noise + Distortion) Ratio
The measured ratio of signal to (noise + distortion) at the
output of the ADC. The signal is the rms amplitude of the
fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
Voltage Output Settling Time
The amount of time it takes the output to settle to within a
1 LSB level for a full-scale input change.
Rev. H | Page 20 of 98
Data Sheet
ADuC7023
OVERVIEW OF THE ARM7TDMI CORE
The ARM7® core is a 32-bit reduced instruction set computer
(RISC). It uses a single 32-bit bus for instruction and data. The
length of the data can be 8 bits, 16 bits, or 32 bits. The length of
the instruction word is 32 bits.
The ARM7TDMI is an ARM7 core with four additional features: T
support for the thumb (16-bit) instruction set, D support for
debug, M support for long multiplications, and I includes the
EmbeddedICE module to support embedded system debugging.
EXCEPTIONS
ARM supports five types of exceptions and a privileged
processing mode for each type. The five types of exceptions are:
THUMB MODE (T)
An ARM instruction is 32 bits long. The ARM7TDMI
processor supports a second instruction set that has been
compressed into 16 bits, called the Thumb® instruction set.
Faster execution from 16-bit memory and greater code density
can usually be achieved by using the Thumb instruction set
instead of the ARM instruction set, which makes the
ARM7TDMI core particularly suitable for embedded
applications.
However, the Thumb mode has two limitations. Thumb code
typically requires more instructions for the same job. As a
result, ARM code is usually best for maximizing the performance
of time critical code. Also, the Thumb instruction set does not
include some of the instructions needed for exception handling,
which automatically switches the core to ARM code for
exception handling.
See the ARM7TDMI user guide for details on the core
architecture, the programming model, and both the ARM
and ARM Thumb instruction sets.
LONG MULTIPLY (M)
The ARM7TDMI instruction set includes four extra instructions that perform 32-bit by 32-bit multiplication with a 64-bit
result, and 32-bit by 32-bit multiplication-accumulation
(MAC) with a 64-bit result. These results are achieved in fewer
cycles than required on a standard ARM7 core.
Normal interrupt or IRQ. This is provided to service
general-purpose interrupt handling of internal and
external events.
Fast interrupt or FIQ. This is provided to service data
transfers or communication channels with low latency.
FIQ has priority over IRQ.
Memory abort.
Attempted execution of an undefined instruction.
Software interrupt instruction (SWI). This can be used to
make a call to an operating system.
Typically, the programmer defines interrupt as IRQ, but for
higher priority interrupt, that is, faster response time, the
programmer can define interrupt as FIQ.
ARM REGISTERS
ARM7TDMI has a total of 37 registers: 31 general-purpose
registers and six status registers. Each operating mode has
dedicated banked registers.
When writing user-level programs, 15 general-purpose 32-bit
registers (R0 to R14), the program counter (R15), and the current
program status register (CPSR) are usable. The remaining registers
are only used for system-level programming and exception
handling.
When an exception occurs, some of the standard registers are
replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack
pointer (R13) and the link register (R14) as represented in
Figure 15. The fast interrupt mode has more registers (R8 to R12)
for fast interrupt processing. This means the interrupt processing
can begin without the need to save or restore these registers,
and thus save critical time in the interrupt handling process.
EmbeddedICE (I)
R0
EmbeddedICE provides integrated on-chip support for the
core. The EmbeddedICE module contains the breakpoint and
watchpoint registers that allow code to be halted for debugging
purposes. These registers are controlled through the JTAG test
port.
R1
When a breakpoint or watchpoint is encountered, the processor
halts and enters debug state. Once in a debug state, the
processor registers can be inspected as well as the Flash/EE,
SRAM, and memory mapped registers.
R8
USABLE IN USER MODE
SYSTEM MODES ONLY
R2
R3
R4
R5
R6
R7
R9
R10
R11
R12
R13
R14
R8_FIQ
R9_FIQ
R10_FIQ
R11_FIQ
R12_FIQ
R13_FIQ
R14_FIQ
R13_SVC
R14_SVC
R13_ABT
R14_ABT
R13_IRQ
R14_IRQ
R13_UND
R14_UND
R15 (PC)
USER MODE
SPSR_FIQ
FIQ
MODE
SPSR_SVC
SVC
MODE
SPSR_ABT
ABORT
MODE
SPSR_IRQ
IRQ
MODE
Figure 15. Register Organization
Rev. H | Page 21 of 98
SPSR_UND
UNDEFINED
MODE
08675-008
CPSR
ADuC7023
Data Sheet
More information relative to the model of the programmer and
the ARM7TDMI core architecture can be found in ARM7TDMI
technical and ARM architecture manuals available directly from
ARM Ltd.
INTERRUPT LATENCY
The worst-case latency for a fast interrupt request (FIQ)
consists of the following: the longest time the request can take
to pass through the synchronizer, the time for the longest
instruction to complete (the longest instruction is an LDM)
that loads all the registers including the PC, and the time for the
data abort and FIQ entry.
At the end of this time, the ARM7TDMI executes the instruction at 0x1C (FIQ interrupt vector address). The maximum
total time is 50 processor cycles, which is just under 1.2 μs in a
system using a continuous 41.78 MHz processor clock.
The maximum interrupt request (IRQ) latency calculation is
similar but must allow for the fact that FIQ has higher priority
and could delay entry into the IRQ handling routine for an
arbitrary length of time. This time can be reduced to 42 cycles if
the LDM command is not used. Some compilers have an option
to compile without using this command. Another option is to run
the part in thumb mode where the time is reduced to 22 cycles.
The minimum latency for FIQ or IRQ interrupts is a total of
five cycles, which consist of the shortest time the request can
take through the synchronizer, plus the time to enter the
exception mode.
The ARM7TDMI always runs in ARM (32-bit) mode when in
privileged modes, for example, when executing interrupt
service routines.
Rev. H | Page 22 of 98
Data Sheet
ADuC7023
MEMORY ORGANIZATION
The ADuC7023 incorporates two separate blocks of memory:
8 kB of SRAM and 64 kB of on-chip Flash/EE memory; 62 kB
of on-chip Flash/EE memory is available to the user, and the
remaining 2 kB are reserved for the factory configured boot
page. These two blocks are mapped as shown in Figure 16.
0xFFFFFFFF
MMRs
0xFFFF0000
RESERVED
0x0008FFFF
FLASH/EE
0x00080000
The total 64 kB of Flash/EE memory is organized as 32k × 16 bits;
31k × 16 bits is user space and 1 k × 16 bits is reserved for the
on-chip kernel. The page size of this Flash/EE memory is 512 bytes.
62 kilobytes of Flash/EE memory are available to the user as
code and nonvolatile data memory. There is no distinction
between data and program because ARM code shares the same
space. The real width of the Flash/EE memory is 16 bits, which
means that in ARM mode (32-bit instruction), two accesses to
the Flash/EE are necessary for each instruction fetch. It is,
therefore, recommended to use Thumb mode when executing
from Flash/EE memory for optimum access speed. The
maximum access speed for the Flash/EE memory is 41.78 MHz
in Thumb mode and 20.89 MHz in full ARM mode. More
details about Flash/EE access time are outlined later in the
Execution Time from SRAM and Flash/EE section.
SRAM
08675-009
RESERVED
0x00011FFF SRAM
0x00010000
0x0000FFFF REMAPPABLE MEMORY SPACE
0x00000000
(FLASH/EE OR SRAM)
Figure 16. Physical Memory Map
By default, after a reset, the Flash/EE memory is mirrored at
Address 0x00000000. It is possible to remap the SRAM at
Address 0x00000000 by clearing Bit 0 of the Remap MMR.
This remap function is described in more detail in the Flash/EE
Memory section.
MEMORY ACCESS
The ARM7 core sees memory as a linear array of the 232 byte
location where the different blocks of memory are mapped as
outlined in Figure 16.
The ADuC7023 memory organizations are configured in little
endian format, which means that the least significant byte is
located in the lowest byte address, and the most significant byte
is in the highest byte address.
BIT 0
BYTE 3
.
.
.
BYTE 2
.
.
.
BYTE 1
.
.
.
BYTE 0
.
.
.
B
A
9
8
7
6
5
4
0x00000004
3
2
1
0
0x00000000
0xFFFFFFFF
32 BITS
08675-010
BIT 31
FLASH/EE MEMORY
Eight kilobytes of SRAM are available to the user, organized as
2k × 32 bits, that is, two words. ARM code can run directly from
SRAM at 41.78 MHz, given that the SRAM array is configured as a
32-bit wide memory array. More details about SRAM access
time are outlined later in the Execution Time from SRAM and
Flash/EE section.
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
upper two pages of the memory array and accessed by indirect
addressing through the ARM7 banked registers.
The MMR space provides an interface between the CPU and
all on-chip peripherals. All registers, except the core registers,
reside in the MMR area. All shaded locations shown in Figure 18
are unoccupied or reserved locations and should not be
accessed by user software. Table 10 to Table 23 show the full
MMR memory map.
The access time for reading from or writing to an MMR depends
on the advanced microcontroller bus architecture (AMBA) bus
used to access the peripheral. The processor has two AMBA
buses: advanced high performance bus (AHB) used for system
modules and advanced peripheral bus (APB) used for lower
performance peripheral. Access to the AHB is one cycle, and
access to the APB is two cycles. All peripherals on the ADuC7023
are on the APB except the Flash/EE memory and the GPIOs.
Figure 17. Little Endian Format
Rev. H | Page 23 of 98
ADuC7023
Data Sheet
0xFFFFFFFF
0xFFFFF820
0xFFFFF800
FLASH CONTROL
INTERFACE
0xFFFFF46C
GPIO
0xFFFFF400
0xFFFF0FBF
PWM
0xFFFF0F80
0xFFFF0B54
PLA
0xFFFF0B00
0xFFFF0A14
SPI
0xFFFF0A00
0xFFFF0948
I2C1
0xFFFF0900
0xFFFF0848
I2C0
0xFFFF0800
0xFFFF0620
0xFFFF0600
DAC
0xFFFF0538
ADC
0xFFFF0500
0xFFFF0490
0xFFFF048C
0xFFFF0448
0xFFFF0440
0xFFFF0420
0xFFFF0404
0xFFFF0370
0xFFFF0360
0xFFFF0334
0xFFFF0320
0xFFFF0310
BAND GAP
REFERENCE
POWER SUPPLY
MONITOR
PLL AND
OSCILLATOR CONTROL
WATCHDOG
TIMER
GENERAL-PURPOSE
TIMER
TIMER0
0xFFFF0300
0xFFFF0220
0xFFFF0140
0xFFFF0000
REMAP AND
SYSTEM CONTROL
INTERRUPT
CONTROLLER
08675-011
0xFFFF0238
Figure 18. Memory Mapped Registers
Rev. H | Page 24 of 98
Data Sheet
ADuC7023
Table 10. IRQ Address Base = 0xFFFF0000
Address
0x0000
0x0004
0x0008
0x000C
0x0010
0x0014
Name
IRQSTA
IRQSIG
IRQEN
IRQCLR
SWICFG
IRQBASE
Byte
4
4
4
4
4
4
Access
Type
R
R
R/W
W
W
R/W
0x001C
IRQVEC
4
R
0x00000000
0x0020
IRQP0
4
R/W
0x00000000
0x0024
IRQP1
4
R/W
0x00000000
0x0028
IRQP2
4
R/W
0x00000000
0x002C
0x0030
0x0034
RESERVED
IRQCONN
IRQCONE
4
4
4
R/W
R/W
R/W
0x00000000
0x00000000
0x00000000
0x0038
0x003C
IRQCLRE
IRQSTAN
4
4
R/W
R/W
0x00000000
0x00000000
0x0100
0x0104
0x0108
0x010C
0x011C
0x013C
FIQSTA
FIQSIG
FIQEN
FIQCLR
FIQVEC
FIQSTAN
4
4
4
4
4
4
R
R
R/W
W
R
RW
0x00000000
Default Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
Description
Active IRQ source.
Current state of all IRQ sources (enabled and disabled).
Enabled IRQ sources.
MMR to disable IRQ sources.
Software interrupt configuration MMR.
Base address of all vectors. Points to start of a 64-byte memory block
which can contain up to 32 pointers to separate subroutine handlers.
This register contains the subroutine address for the currently active
IRQ source.
This register contains the interrupt priority setting for Interrupt Source 1
to Interrupt Source 7. An interrupt can have a priority setting of 0 to 7.
This register contains the interrupt priority setting for Interrupt Source 8
to Interrupt Source 15.
This register contains the interrupt priority setting for Interrupt Source 16 to
Interrupt Source 21.
Reserved.
Used to enable IRQ and FIQ interrupt nesting.
This register configures the external interrupt sources as rising edge,
falling edge, or level triggered.
Used to clear an edge level triggered interrupt source.
This register indicates the priority level of an interrupt that has just
caused an interrupt exception.
Active FIQ source.
Current state of all FIQ sources (enabled and disabled).
Enabled FIQ sources.
MMR to disable FIQ sources.
FIQ interrupt vector.
This register indicates the priority level of an FIQ that has just caused an
FIQ exception.
Table 11. System Control Address Base = 0xFFFF0200
Address
0x0220
0x0230
0x0234
0x0248
0x024C
Name
Remap2
RSTSTA
RSTCLR
RSTKEY1
RSTCFG
Byte
1
1
1
1
1
Access
Type
R/W
R/W
W
W
R/W
Default Value1
0x00
0x01
0x00
0xXX
0x00
0x0250
RSTKEY2
1
W
0xXX
1
2
Description
Remap control register.
RSTSTA status MMR.
RSTCLR MMR for clearing RSTSTA register.
0x76 should be written to this register before writing to RSTCFG.
This register allows the DAC and GPIO outputs to retain state after a
watchdog or software reset.
0xB1 should be written to this register after writing to RSTCFG.
N/A means not applicable.
Updated by kernel.
Rev. H | Page 25 of 98
ADuC7023
Data Sheet
Table 12. Timer Address Base = 0xFFFF0300
Address
0x0300
0x0304
0x0308
0x030C
0x0320
0x0324
0x0328
0x032C
0x0330
0x0360
0x0364
0x0368
0x036C
1
Name
T0LD
T0VAL
T0CON
T0CLRI
T1LD
T1VAL
T1CON
T1CLRI
T1CAP
T2LD
T2VAL
T2CON
T2CLRI
Byte
2
2
2
1
4
4
4
1
4
2
2
2
1
Access Type
R/W
R
R/W
W
R/W
R
R/W
W
R
R/W
R
R/W
W
Default Value1
0x0000
0xFFFF
0x0000
0xXX
0x00000000
0xFFFFFFFF
0x00000000
0xXX
0x00000000
0x0000
0xFFFF
0x0000
0xXX
Description
Timer0 load register.
Timer0 value register.
Timer0 control MMR.
Timer0 interrupt clear register.
Timer1 load register.
Timer1 value register
Timer1 control MMR.
Timer1 interrupt clear register.
Timer1 capture register.
Timer2 load register.
Timer2 value register.
Timer2 control MMR.
Timer2 interrupt clear register.
Default Value1
0xXXXX
0x00
0xXXXX
0xXXXX
0x21
0xXXXX
0xXXXX
0x0004
0xXXXX
0x0008
0x0000
Description
POWCON0 prewrite key.
Power control and core speed control register.
POWCON0 postwrite key.
PLLCON prewrite key.
PLL clock source selection MMR.
PLLCON postwrite key.
POWCON1 prewrite key.
Power control and core speed control register.
POWCON1 postwrite key.
Power supply monitor control register.
Comparator control register.
Default Value
0x0600
0x00
0x01
0x00
0x00000000
Description
ADC control MMR.
ADC positive channel selection register.
ADC negative channel selection register.
ADC status MMR.
ADC data output MMR.
N/A means not applicable.
Table 13. PLL/PSM Base Address = 0xFFFF0400
Address
0x0404
0x0408
0x040C
0x0410
0x0414
0x0418
0x0434
0x0438
0x043C
0x0440
0x0444
1
Name
POWKEY1
POWCON0
POWKEY2
PLLKEY1
PLLCON
PLLKEY2
POWKEY3
POWCON1
POWKEY4
PSMCON
CMPCON
Byte
2
1
2
2
1
2
2
2
2
2
2
Access
Type
W
R/W
W
W
R/W
W
W
R/W
W
R/W
R/W
N/A means not applicable.
Table 14. Reference Base Address = 0xFFFF0480
Address:
0x048C
Name:
REFCON
Byte:
1
Access type:
Read/write
Default value:
0x00
Description:
Reference control register.
Table 15. ADC Address Base = 0xFFFF0500
Address
0x0500
0x0504
0x0508
0x050C
0x0510
Name
ADCCON
ADCCP
ADCCN
ADCSTA
ADCDAT
Byte
2
1
1
1
4
Access
Type
R/W
R/W
R/W
R
R
Rev. H | Page 26 of 98
Data Sheet
Address
0x0514
0x0530
0x0534
0x0544
0x0548
Name
ADCRST
ADCGN
ADCOF
TSCON
TEMPREF
ADuC7023
Byte
1
2
2
1
2
Access
Type
R/W
R/W
R/W
R/W
R/W
Default Value
0x00
Factory configured
Factory configured
0x00
Factory configured
Description
ADC reset MMR.
ADC gain calibration MMR.
ADC offset calibration MMR.
Temperature sensor chopping enable register.
Temperature sensor reference value.
Default Value
0x00
0x00000000
0x00
0x00000000
0x00
0x00000000
0x00
0x00000000
0x00
0x0000
0x0000
Description
DAC0 control MMR.
DAC0 data MMR.
DAC1 control MMR.
DAC1 data MMR.
DAC2 control MMR.
DAC2 data MMR.
DAC3 control MMR.
DAC3 data MMR.
DAC Configuration MMR
DAC Key0 MMR
DAC Key1 MMR
Table 16. DAC Address Base = 0xFFFF0600
Address
0x0600
0x0604
0x0608
0x060C
0x0610
0x0614
0x0618
0x061C
0x0654
0x0650
0x0658
Name
DAC0CON
DAC0DAT
DAC1CON
DAC1DAT
DAC2CON
DAC2DAT
DAC3CON
DAC3DAT
DACBCFG
DACBKEY0
DACBKEY1
Byte
1
4
1
4
1
4
1
4
1
2
2
Access
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
Table 17. I2C0 Base Address = 0XFFFF0800
Address
0x0800
0x0804
0x0808
0x080C
0x0810
Name
I2C0MCON
I2C0MSTA
I2C0MRX
I2C0MTX
I2C0MCNT0
Byte
2
2
1
1
2
Access
Type
R/W
R
R
W
R/W
Default Value
0x0000
0x0000
0x00
0x00
0x0000
0x0814
I2C0MCNT1
1
R
0x00
0x0818
I2C0ADR0
1
R/W
0x00
0x081C
I2C0ADR1
1
R/W
0x00
0x0824
0x0828
0x082C
0x0830
0x0834
0x0838
0x083C
0x0840
0x0844
0x0848
0x084C
I2C0DIV
I2C0SCON
I2C0SSTA
I2C0SRX
I2C0STX
I2C0ALT
I2C0ID0
I2C0ID1
I2C0ID2
I2C0ID3
I2C0FSTA
2
2
2
1
1
1
1
1
1
1
2
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
0x1F1F
0x0000
0x0000
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0000
Description
I2C0 master control register.
I2C0 master status register.
I2C0 master receive register.
I2C0 master transmit register.
I2C0 master read count register. Write the number of required
bytes into this register prior to reading from a slave device.
I2C0 master current read count register. This register contains the
number of bytes already received during a read from slave sequence.
I2C0 address byte register. Write the required slave address in
here prior to communications.
I2C0 address byte register. Write the required slave address in
here prior to communications. Used in 10-bit mode only.
I2C0 clock control register. Used to configure the SCL frequency.
I2C0 slave control register.
I2C0 slave status register.
I2C0 slave receive register.
I2C0 slave transmit register.
I2C0 hardware general call recognition register.
I2C0 slave ID0 register. Slave bus ID register.
I2C0 slave ID1 register. Slave bus ID register.
I2C0 slave ID2 register. Slave bus ID register.
I2C0 slave ID3 register. Slave bus ID register.
I2C0 FIFO status register. Used in both master and slave modes.
Default Value
0x0000
0x0000
Description
I2C1 master control register.
I2C1 master status register.
Table 18. I2C1 Base Address = 0XFFFF0900
Address
0x0900
0x0904
Name
I2C1MCON
I2C1MSTA
Byte
2
2
Access
Type
R/W
R
Rev. H | Page 27 of 98
ADuC7023
Address
0x0908
0x090C
0x0910
Name
I2C1MRX
I2C1MTX
I2C1MCNT0
Data Sheet
Byte
1
1
2
Access
Type
R
W
R/W
Default Value
0x00
0x00
0x0000
Description
I2C1 master receive register.
I2C1 master transmit register.
I2C1 master read count register. Write the number of required bytes
into this register prior to reading from a slave device.
Rev. H | Page 28 of 98
Data Sheet
ADuC7023
Address
0x0914
Name
I2C1MCNT1
Byte
1
Access
Type
R
Default Value
0x00
0x0918
I2C1ADR0
1
R/W
0x00
0x091C
I2C1ADR1
1
R/W
0x00
0x0924
0x0928
0x092C
0x0930
0x0934
0x0938
0x093C
0x0940
0x0944
0x0948
0x094C
I2C1DIV
I2C1SCON
I2C1SSTA
I2C1SRX
I2C1STX
I2C1ALT
I2C1ID0
I2C1ID1
I2C1ID2
I2C1ID3
I2C1FSTA
2
2
2
1
1
1
1
1
1
1
2
R/W
R/W
R/W
R
W
R/W
R/W
R/W
R/W
R/W
R/W
0x1F1F
0x0000
0x0000
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x0000
Description
I2C1 master current read count register. This register contains the
number of bytes already received during a read from slave sequence.
I2C1 address byte register. Write the required slave address in
here prior to communications.
I2C1 address byte register. Write the required slave address in
here prior to communications. Used in 10-bit mode only.
I2C1 clock control register. Used to configure the SCL frequency.
I2C1 slave control register.
I2C1 slave status register.
I2C1 slave receive register.
I2C1 slave transmit register.
I2C1 hardware general call recognition register.
I2C1 slave ID0 register. Slave bus ID register.
I2C1 slave ID1 register. Slave bus ID register.
I2C1 slave ID2 register. Slave bus ID register.
I2C1 slave ID3 register. Slave bus ID register.
I2C1 FIFO status register. Used in both master and slave modes.
Default Value
0x0000
0x00
0xXX
0x00
0x0000
Description
SPI status MMR.
SPI receive MMR.
SPI transmit MMR.
SPI baud rate select MMR.
SPI control MMR.
Default Value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x00
0x00000000
0x00000000
0x00000000
0x00000000
0x00
Description
PLA Element 0 control register.
PLA Element 1 control register.
PLA Element 2 control register.
PLA Element 3 control register.
PLA Element 4 control register.
PLA Element 5 control register.
PLA Element 6 control register.
PLA Element 7 control register.
PLA Element 8 control register.
PLA Element 9 control register.
PLA Element 10 control register.
PLA Element 11 control register.
PLA Element 12 control register.
PLA Element 13 control register.
PLA Element 14 control register.
PLA Element 15 control register.
PLA clock select register.
PLA interrupt control register.
PLA ADC trigger control register.
PLA data in register.
PLA data out register.
PLA lock register.
Table 19. SPI Base Address = 0xFFFF0A00
Address
0x0A00
0x0A04
0x0A08
0x0A0C
0x0A10
Name
SPISTA
SPIRX
SPITX
SPIDIV
SPICON
Byte
2
1
1
1
2
Access
Type
R
R
W
R/W
R/W
Table 20. PLA Base Address = 0XFFFF0B00
Address
0x0B00
0x0B04
0x0B08
0x0B0C
0x0B10
0x0B14
0x0B18
0x0B1C
0x0B20
0x0B24
0x0B28
0x0B2C
0x0B30
0x0B34
0x0B38
0x0B3C
0x0B40
0x0B44
0x0B48
0x0B4C
0x0B50
0x0B54
Name
PLAELM0
PLAELM1
PLAELM2
PLAELM3
PLAELM4
PLAELM5
PLAELM6
PLAELM7
PLAELM8
PLAELM9
PLAELM10
PLAELM11
PLAELM12
PLAELM13
PLAELM14
PLAELM15
PLACLK
PLAIRQ
PLAADC
PLADIN
PLADOUT
PLALCK
Byte
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1
4
4
4
4
1
Access
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
W
Rev. H | Page 29 of 98
ADuC7023
Data Sheet
Table 21. PWM Base Address = 0xFFFF0F80
Address
0x0F80
Name
PWMCON1
Byte
2
Access
Type
R/W
Default Value
0x0012
0x0F84
0x0F88
0x0F8C
0x0F90
0x0F94
0x0F98
0x0F9C
0x0FA0
0x0FA4
0x0FA8
0x0FB0
0x0FB8
PWM0COM0
PWM0COM1
PWM0COM2
PWM0LEN
PWM1COM0
PWM1COM1
PWM1COM2
PWM1LEN
PWM2COM0
PWM2COM1
PWM2LEN
PWMCLRI
2
2
2
2
2
2
2
2
2
2
2
2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
Description
PWM Control Register 1. See the Pulse-Width Modulator section
for full details.
Compare Register 0 for PWM Output 0 and PWM Output 1.
Compare Register 1 for PWM Output 0 and PWM Output 1.
Compare Register 2 for PWM Output 0 and PWM Output 1.
Frequency control for PWM Output 0 and PWM Output 1.
Compare Register 0 for PWM Output 2 and PWM Output 3.
Compare Register 1 for PWM Output 2 and PWM Output 3.
Compare Register 2 for PWM Output 2 and PWM Output 3.
Frequency control for PWM Output 2 and PWM Output 3.
Compare Register 0 for PWM Output 4.
Compare Register 1 for PWM Output 4.
Frequency control for PWM Output 4.
PWM interrupt clear register. Writing any value to this register
clears a PWM interrupt source.
Table 22. GPIO Base Address = 0xFFFFF400
Address
0xF400
0xF404
0xF408
0xF420
0xF424
0xF428
0xF42C
0xF430
0xF434
0xF438
0xF43C
0xF440
0xF444
0xF448
0xF44C
Name
GP0CON
GP1CON
GP2CON
GP0DAT
GP0SET
GP0CLR
GP0PAR
GP1DAT
GP1SET
GP1CLR
GP1PAR
GP2DAT
GP2SET
GP2CLR
GP2PAR
Byte
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
Access
Type
R/W
R/W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
R/W
W
W
R/W
Default Value
0x00001111
0x00000000
0x00000000
0x000000XX
0x000000XX
0x000000XX
0x22220000
0x000000XX
0x000000XX
0x000000XX
0x22000022
0x000000XX
0x000000XX
0x000000XX
0x00000000
Description
GPIO Port0 control MMR.
GPIO Port1 control MMR.
GPIO Port2 control MMR.
GPIO Port0 data control MMR.
GPIO Port0 data set MMR.
GPIO Port0 data clear MMR.
GPIO Port0 pull-up disable MMR.
GPIO Port1 data control MMR.
GPIO Port1 data set MMR.
GPIO Port1 data clear MMR.
GPIO Port1 pull-up disable MMR.
GPIO Port2 data control MMR.
GPIO Port2 data set MMR.
GPIO Port2 data clear MMR.
GPIO Port2 pull-up disable MMR.
Default Value
0x20
0x0000
0x07
0xXXXX
0x0000
0xFFFFFF
0x00000000
0xFFFFFFFF
Description
Flash/EE status MMR.
Flash/EE control MMR.
Flash/EE control MMR.
Flash/EE data MMR.
Flash/EE address MMR.
Flash/EE LFSR MMR.
Flash/EE protection MMR.
Flash/EE protection MMR.
Table 23. Flash/EE Base Address = 0xFFFFF800
Address
0xF800
0xF804
0xF808
0xF80C
0xF810
0xF818
0xF81C
0xF820
Name
FEESTA
FEEMOD
FEECON
FEEDAT
FEEADR
FEESIGN
FEEPRO
FEEHIDE
Byte
1
2
1
2
2
3
4
4
Access
Type
R
R/W
R/W
R/W
R/W
R
R/W
R/W
Rev. H | Page 30 of 98
Data Sheet
ADuC7023
ADC CIRCUIT OVERVIEW
The converter accepts an analog input range of 0 V to VREF when
operating in single-ended mode. In fully differential mode, the
input signal must be balanced around a common-mode voltage
(VCM) in the 0 V to AVDD range with a maximum amplitude of
2 VREF (see Figure 19).
AVDD
VCM
2VREF
VCM
0
2VREF
08675-012
2VREF
Figure 19. Examples of Balanced Signals in Fully Differential Mode
A high precision, low drift, factory calibrated, 2.5 V reference is
provided on chip. An external reference can also be connected as
described later in the Band Gap Reference section.
Single or continuous conversion modes can be initiated in the
software. An external CONVSTART pin, an output generated
from the on-chip PLA, or a Timer0 or Timer1 overflow can
also be used to generate a repetitive trigger for ADC
conversions.
A voltage output from an on-chip band gap reference proportional to absolute temperature can also be routed through the
front-end ADC multiplexer. This temperature channel can be
selected as an ADC input. This facilitates an internal
temperature sensor channel that measures die temperature.
TRANSFER FUNCTION
Single-Ended Mode
1111 1111 1101
1111 1111 1100
1LSB =
FS
4096
0000 0000 0011
0000 0000 0010
0000 0000 0000
0V 1LSB
+FS – 1LSB
VOLTAGE INPUT
08675-013
0000 0000 0001
Figure 20. ADC Transfer Function in Single-Ended Mode
Fully Differential Mode
The amplitude of the differential signal is the difference between
the signals applied to the VIN+ and VIN– pins (that is, VIN+ − VIN−).
The maximum amplitude of the differential signal is, therefore,
−VREF to +VREF p-p (that is, 2 × VREF). This is regardless of the
common mode (CM). The common mode is the average of the
two signals, for example, (VIN+ + VIN–)/2, and is, therefore, the
voltage on which the two inputs are centered. This results in the
span of each input being CM ±VREF/2. This voltage has to be set
up externally, and its range varies with VREF (see the Driving the
Analog Inputs section).
The output coding is twos complement in fully differential mode
with 1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV when
VREF = 2.5 V. The output result is ±11 bits, but this is shifted by
one to the right. This allows the result in the ADCDAT MMR to
be declared as a signed integer when writing C code. The
designed code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … , FS −
3/2 LSB). The ideal input/output transfer characteristic is
shown in Figure 21.
SIGN
BIT
0 1111 1111 1110
0 1111 1111 1100
1LSB =
2 × VREF
4096
0 1111 1111 1010
In single-ended mode, the input range is 0 V to VREF. The
output coding is straight binary in single-ended mode with
0 0000 0000 0010
0 0000 0000 0000
1 1111 1111 1110
1 0000 0000 0100
1 0000 0000 0010
1 LSB = FS/4096, or
2.5 V/4096 = 0.61 mV, or
610 μV when VREF = 2.5 V
1 0000 0000 0000
0LSB
+VREF – 1LSB
–VREF + 1LSB
VOLTAGE INPUT (VIN+ – VIN–)
Figure 21. ADC Transfer Function in Differential Mode
The ideal code transitions occur midway between successive
integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … ,
FS − 3/2 LSB). The ideal input/output transfer characteristic
is shown in Figure 20.
Rev. H | Page 31 of 98
08675-014
VCM
1111 1111 1110
OUTPUT CODE
The ADC consists of a 12-bit successive approximation
converter based around two capacitor DACs. Depending on the
input signal configuration, the ADC can operate in one of two
different modes: fully differential mode (for small and balanced
signals) or single-ended mode (for any single-ended signals).
1111 1111 1111
OUTPUT CODE
The analog-to-digital converter (ADC) incorporates a fast,
multichannel, 12-bit ADC. It can operate from 2.7 V to 3.6 V
supplies and is capable of providing a throughput of up to
1 MSPS when the clock source is 41.78 MHz. This block
provides the user with a multichannel multiplexer, a differential
track-and-hold, an on-chip reference, and an ADC.
ADuC7023
Data Sheet
ACQ
TYPICAL OPERATION
When configured via the ADC control and channel selection
registers, the ADC converts the analog input and provides a
12-bit result in the ADC data register.
SIGN BITS
ADC BUSY
DATA
ADCDAT
0
12-BIT ADC RESULT
ADCSTA = 0
ADCSTA = 1
ADC INTERRUPT
Figure 22. ADC Result Format
The same format is used in DACxDAT, simplifying the software.
Current Consumption
The ADC in standby mode, that is, powered up but not
converting, typically consumes 640 μA. The internal reference
adds 140 μA. During conversion, the extra current is 0.3 μA
multiplied by the sampling frequency (in kHz).
Timing
Figure 23 gives details of the ADC timing. Users control the
ADC clock speed and the number of acquisition clocks in the
ADCCON MMR. By default, the acquisition time is eight
clocks, and the clock divider is two. The number of extra clocks
(such as bit trial or write) is set to 19, which gives a sampling
rate of 774 kSPS. For conversion on the temperature sensor, set
ADCCON = 0x37A3. When using multiple channels including
the temperature sensor, the timing settings revert to the userdefined settings after reading the temperature sensor channel.
Figure 23. ADC Timing
MMR INTERFACE
The ADC is controlled and configured via the eight MMRs
described in this section.
ADCCON Register
Name:
ADCCON
Address:
0xFFFF0500
Default value:
0x0600
Access:
Read/write
Function:
ADCCON is an ADC control register
that allows the programmer to enable the
ADC peripheral, select the mode of
operation of the ADC (either in singleended mode or fully differential mode),
and select the conversion type. This MMR
is described in Table 24.
Table 24. ADCCON MMR Bit Designations
Bit
15 to 14
13
Value
12 to 10
000
001
010
011
100
101
9 to 8
00
01
10
11
08675-016
16 15
CONVSTART
08675-015
27
WRITE
ADC CLOCK
The top four bits are the sign bits. The 12-bit result is placed
from Bit 16 to Bit 27 as shown in Figure 22. Note that in fully
differential mode, the result is represented in twos complement
format. In single-ended mode, the result is represented in
straight binary format.
31
BIT TRIAL
Description
Reserved.
Temperature sensor conversion enable. Set to 1 for temperature sensor conversions and single
software conversions. Set to 0 for normal ADC conversions.
ADC clock speed.
fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock
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