ADUC7025BSTZ62

Precision Analog Microcontroller 12-bit Analog I/O, ARM7TDMI® MCU ADuC7019/20/21/22/24/25/26/27 FEATURES Analog I/O Multichannel, 12-bit, 1 MSPS ADC Up to 16 ADC channels1 Fully differential and single-ended modes 0 to VREF analog input range 12-bit voltage output DACs Up to 4 DAC outputs available1 On-chip voltage reference On-chip temperature sensor (±3°C) Voltage comparator Microcontroller ARM7TDMI core, 16-bit/32-bit RISC architecture JTAG port supports code download and debug Clocking options Trimmed on-chip oscillator (±3%) External watch crystal External clock source up to 44 MHz 41.78 MHz PLL with programmable divider Memory 62 kB flash/EE memory, 8 kB SRAM In-circuit download, JTAG-based debug Software triggered in-circuit reprogrammability On-chip peripherals UART, 2 × I2C® and SPI® serial I/O Up to 40-pin GPIO port1 4 × general-purpose timers Wake-up and watchdog timers (WDT) Power supply monitor Three-phase, 16-bit PWM generator1 Programmable logic array (PLA) External memory interface, up to 512 kB1 Power Specified for 3 V operation Active mode: 11 mA @ 5 MHz; 40 mA @ 41.78 MHz Packages and temperature range From 40-lead 6 mm × 6 mm LFCSP to 80-lead LQFP1 Fully specified for –40°C to +125°C operation Tools Low-cost QuickStart™ development system Full third-party support APPLICATIONS Industrial control and automation systems Smart sensors, precision instrumentation Base station systems, optical networking FUNCTIONAL BLOCK DIAGRAM ADC0 MUX ADC11 TEMP SENSOR CMP0 CMP1 CMPOUT VREF OSC AND PLL PSM PLA THREEPHASE PWM GPIO BANDGAP REF 1MSPS 12-BIT ADC 12-BIT DAC 12-BIT DAC DAC0 DAC1 ADuC7026 12-BIT DAC 12-BIT DAC DAC2 DAC3 XCLKI XCLKO ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS 2k × 32 SRAM 31k × 16 FLASH/EEPROM SERIAL I/O UART, SPI, I2C PWM0H PWM0L PWM1H PWM1L PWM2H PWM2L Figure 1. 1 Depending on part model. See Ordering Guide for more information. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. 04955-001 RST POR 4 GENERAL PURPOSE TIMERS JTAG EXT. MEMORY INTERFACE ADuC7019/20/21/22/24/25/26/27 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 General Description ......................................................................... 4 Detailed Block Diagram .............................................................. 5 Specifications..................................................................................... 6 Timing Specifications .................................................................. 9 Absolute Maximum Ratings.......................................................... 16 ESD Caution................................................................................ 16 Pin Configurations and Function Descriptions ......................... 17 ADuC7019/ADuC7020/ADuC7021/ADuC7022 .................. 17 ADuC7024/ADuC7025 ............................................................. 20 ADuC7026/ADuC7027 ............................................................. 23 Typical Performance Characteristics ........................................... 27 Terminology .................................................................................... 30 ADC Specifications .................................................................... 30 DAC Specifications..................................................................... 30 Overview of the ARM7TDMI Core............................................. 31 Thumb Mode (T)........................................................................ 31 Long Multiply (M)...................................................................... 31 EmbeddedICE (I) ....................................................................... 31 Exceptions ................................................................................... 31 ARM Registers ............................................................................ 31 Interrupt Latency........................................................................ 32 Memory Organization ................................................................... 33 Memory Access........................................................................... 33 Flash/EE Memory....................................................................... 33 SRAM ........................................................................................... 33 Memory Mapped Registers ....................................................... 33 ADC Circuit Overview .................................................................. 37 Transfer Function....................................................................... 37 Typical Operation....................................................................... 38 MMRs Interface.......................................................................... 38 Converter Operation.................................................................. 40 Driving the Analog Inputs ........................................................ 42 Calibration................................................................................... 42 Temperature Sensor ................................................................... 42 Band Gap Reference................................................................... 42 Nonvolatile Flash/EE Memory ..................................................... 43 Programming.............................................................................. 43 Security ........................................................................................ 44 Flash/EE Control Interface ....................................................... 44 Execution Time from SRAM and Flash/EE............................ 46 Reset and Remap ........................................................................ 46 Other Analog Peripherals.............................................................. 48 DAC.............................................................................................. 48 Power Supply Monitor ............................................................... 49 Comparator ................................................................................. 50 Oscillator and PLL—Power Control........................................ 51 Digital Peripherals.......................................................................... 53 Three-Phase PWM..................................................................... 53 General-Purpose Input/Output................................................ 60 Serial Port Mux........................................................................... 62 UART Serial Interface................................................................ 62 Serial Peripheral Interface......................................................... 65 I2C Compatible Interfaces ......................................................... 67 Programmable Logic Array (PLA)........................................... 71 Processor Reference Peripherals................................................... 74 Interrupt System ......................................................................... 74 Timers .......................................................................................... 75 External Memory Interfacing ................................................... 79 Rev. A | Page 2 of 92 ADuC7019/20/21/22/24/25/26/27 Hardware Design Considerations .................................................83 Power Supplies.............................................................................83 Grounding and Board Layout Recommendations .................84 Clock Oscillator...........................................................................84 Power-on Reset Operation.........................................................85 Typical System Configuration ...................................................85 Development Tools .........................................................................86 PC-Based Tools ........................................................................... 86 In-Circuit Serial Downloader ................................................... 86 Outline Dimensions........................................................................ 87 Ordering Guide ........................................................................... 89 REVISION HISTORY 1/06—Rev. 0 to Rev. A Changes to Table 1 ............................................................................6 Added the Flash/EE Memory Reliability Section .......................43 Changes to Table 30 ........................................................................52 Changes to Serial Peripheral Interface .........................................66 Changes to Ordering Guide...........................................................90 10/05—Revision 0: Initial Version Rev. A | Page 3 of 92 ADuC7019/20/21/22/24/25/26/27 GENERAL DESCRIPTION The ADuC7019/7020/7021/7022/7024/7025/7026/7027 are fully integrated, 1 MSPS, 12-bit data acquisition systems incorporating high performance multichannel ADCs, 16-bit/32-bit MCUs and Flash/EE memory on a single chip. The ADC consists of up to 12 single-ended inputs. An additional four inputs are available but are multiplexed with the four DAC output pins. The four DAC outputs are only available on certain models (ADuC7020, and ADuC7026). However, in many cases where the DAC outputs are not present, these pins can still be used as additional ADC inputs, giving a maximum of 16 ADC input channels. The ADC can operate in single-ended or differential input modes. The ADC input voltage is 0 to VREF. Low-drift bandgap reference, temperature sensor, and voltage comparator complete the ADC peripheral set. Depending on the part model, up to four buffered voltage output DACs are available on-chip. The DAC output range is programmable to one of three voltage ranges. The devices operate from an on-chip oscillator and a PLL generating an internal high frequency clock of 41.78 MHz. This clock is routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an ARM7TDMI, 16-bit/32-bit RISC machine, which offers up to 41 MIPS peak performance. Eight kilobytes of SRAM and 62 kilobytes of nonvolatile Flash/EE memory are provided on-chip. The ARM7TDMI core views all memory and registers as a single linear array. On-chip factory firmware supports in-circuit serial download via the UART or I2C serial interface ports, while nonintrusive emulation is also supported via the JTAG interface. These features are incorporated into a low-cost QuickStart™ Development System supporting this MicroConverter® family. The parts operate from 2.7 V to 3.6 V and are specified over an industrial temperature range of −40°C to +125°C. When operating at 41.78 MHz, the power dissipation is typically 120 mW. The ADuC7019/7020/7021/7022/7024/7025/7026/7027 are available in a variety of memory models and packages. Rev. A | Page 4 of 92 ADuC7019/20/21/22/24/25/26/27 DETAILED BLOCK DIAGRAM DACGND 70 REFGND DACV DD GNDREF 8 72 71 67 73 74 53 26 25 54 28 27 37 75 69 ADC0 77 ADC1 78 ADC2/CMP0 79 ADC3/CMP1 80 ADC4 1 ADC5 2 ADC6 3 ADC7 4 ADC8 5 ADC9 6 ADC10 7 ADC11 76 ADCNEG 9 TEMP SENSOR MUX 12-BIT SAR ADC 1MSPS ADuC7026* ADC CONTROL DAC CONTROL 12-BIT VOLTAGE OUTPUTDAC 12-BIT VOLTAGE OUTPUTDAC 12-BIT VOLTAGE OUTPUTDAC 12-BIT VOLTAGE OUTPUTDAC BUF DACREF IOGND IOGND AGND AGND DGND IOVDD IOVDD AVDD AVDD LVDD RST 10 DAC0*/ADC12 BUF 11 DAC1*/ADC13 BUF 12 DAC2*/ADC14 BUF 13 DAC3*/ADC15 29 P3.0/AD0/PWM0H/PLAI[8] 62KBYTES FLASH/EE (31k × 16 BITS) ARM7TDMI THREEPHASE PWM 30 P3.1/AD1/PWM0L/PLAI[9] 31 P3.2/AD2/PWM1H/PLAI[10] 32 P3.3/AD3/PWM1L/PLAI[11] 38 P3.4/AD4/PWM2H/PLAI[12] 39 P3.5/AD5/PWM2L/PLAI[13] 46 P3.6/AD6/PWMTRIP/PLAI[14] DAC BM/P0.0/CMPOUT/PLAI[7]/MS2 20 MUX 8192 BYTES USER RAM CMPOUT/IRQ (2k × 32 BITS) MCU CORE WAKEUP/ RTC TIMER POWER SUPPLY MONITOR DOWNLOADER VREF 68 VREF 47 P3.7/AD7/PWMSYNC /PLAI[15] OSC BAND GAP REFERENCE PROG. CLOCK DIVIDER 44 XCLKO JTAG EMULATOR PLL 45 XCLKI 43 P0.7/ECLK/XCLK/SPM8/PLAO[4] P4.6/AD14/PLAO[14] 18 P4.7/AD15/PLAO[15] 19 PROG. LOGIC ARRAY SPI/I2C SERIAL INTERFACE UART SERIAL PORT SERIAL PORT MULTIPLEXER 55 56 63 64 65 66 62 61 60 59 58 57 52 51 42 14 15 23 22 34 POR 21 49 50 17 33 INTERRUPT CONTROLLER 35 36 48 24 16 40 IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 41 IRQ1/P0.5/ADCBUSY /PLAO[2]/MS0 P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P0.6/T1/MRST/PLAO[3]/AE P2.1/WS/PWM0H/PLAO[6] P2.2/RS/PWM0L/PLAO[7] P1.0/T1/SPM0/PLAI[0] TMS P2.4/PWM0H/MS0 P2.6/PWM1H/MS2 P1.1/SPM1/PLAI[1] P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P4.0/AD8/PLAO[8] P4.1/AD9/PLAO[9] P2.0/SPM9/PLAO[5]/CONVSTART P0.3/TRST/A16/ADC BUSY P4.2/AD10/PLAO[10] P4.3/AD11/PLAO[11] P4.4/AD12/PLAO[12] P4.5/AD13/PLAO[13] Figure 2. Rev. A | Page 5 of 92 04955-002 *SEE SELECTION TABLE FOR FEATURE AVAILABILITY ON DIFFERENT MODELS. P0.2/PWM2L/BHE P0.1/PWM2H/BLE P2.5/PWM0L/MS1 P2.7/PWM1L/MS3 TDI TDO TCK P2.3/AE ADuC7019/20/21/22/24/25/26/27 SPECIFICATIONS AVDD = IOVDD = 2.7 V to 3.6 V, VREF = 2.5 V internal reference, fCORE = 41.78 MHz, TA = 40°C to 125°C, unless otherwise noted. Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time DC Accuracy 1, 2 Resolution Integral Nonlinearity Differential Nonlinearity 3, 4 DC Code Distribution ENDPOINT ERRORS 5 Offset Error Offset Error Match Gain Error Gain Error Match DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk ANALOG INPUT Input Voltage Ranges Differential Mode Single-Ended Mode Leakage Current Input Capacitance ON-CHIP VOLTAGE REFERENCE Output Voltage Accuracy Reference Temperature Coefficient Power Supply Rejection Ratio Output Impedance Internal VREF Power-On Time EXTERNAL REFERENCE INPUT 7 Input Voltage Range Input Impedance DAC CHANNEL SPECIFICATIONS DC ACCURACY 8 Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error 9 Gain Error Mismatch Min Typ 5 12 ±0.6 ±1.0 ±0.5 +0.7/−0.6 1 ±1 ±1 ±2 ±1 69 −78 −75 −80 ±1.5 +1/−0.9 Max Unit μs Bits LSB LSB LSB LSB LSB LSB LSB LSB LSB dB dB dB dB fIN = 10 kHz sine wave, fSAMPLE = 1 MSPS Includes distortion and noise components Test Conditions/Comments Eight acquisition clocks and fADC/2 2.5 V internal reference 1.0 V external reference 2.5 V internal reference 1.0 V external reference ADC input is a dc voltage ±2 ±5 Measured on adjacent channels ±1 20 2.5 VCM 6 ±VREF/2 0 to VREF ±6 V V μA pF V mV ppm/°C dB Ω ms V kΩ RL = 5 kΩ, CL = 100 pF During ADC acquisition 0.47 μF from VREF to AGND TA = 25°C ±5 ±40 75 70 1 0.625 65 AVDD TA = 25°C 12 ±2 ±1 ±15 ±1 0.1 Bits LSB LSB mV % % Guaranteed monotonic 2.5 V internal reference % of full scale on DAC0 Rev. A | Page 6 of 92 ADuC7019/20/21/22/24/25/26/27 Parameter ANALOG OUTPUTS Output Voltage Range_0 Output Voltage Range_1 Output Voltage Range_2 Output Impedance DAC AC CHARACTERISTICS Voltage Output Settling Time Digital to Analog Glitch Energy COMPARATOR Input Offset Voltage Input Bias Current Input Voltage Range Input Capacitance Hysteresis4, 6 Response Time TEMPERATURE SENSOR Voltage Output at 25°C Voltage TC Accuracy POWER SUPPLY MONITOR (PSM) IOVDD Trip Point Selection Power Supply Trip Point Accuracy POWER-ON RESET GLITCH IMMUNITY ON RESET PIN3 WATCHDOG TIMER (WDT) Timeout Period FLASH/EE MEMORY Endurance 10 Data Retention 11 DIGITAL INPUTS Logic 1 Input Current Logic 0 Input Current Min Typ 0 to DACREF 0 to 2.5 0 to DACVDD 2 10 ±20 ±15 1 AGND 7 2 3 15 AVDD − 1.2 Max Unit V V V Ω μs nV-sec mV μA V pF mV μs Test Conditions/Comments DACREF range: DACGND to DACVDD 1 LSB change at major carry Hysteresis can be turned on or off via the CMPHYST bit in the CMPCON register 100 mV overdrive and configured with CMPRES = 11 780 −1.3 ±3 2.79 3.07 ±2.5 2.36 50 0 10,000 20 ±0.2 −40 −80 10 ±1 −60 −120 512 mV mV/°C °C V V % V μs sec cycles years μA μA μA pF V V V V All digital outputs excluding XCLKI and XCLKO ISOURCE = 1.6 mA ISINK = 1.6 mA Two selectable trip points Of the selected nominal trip point voltage TJ = 85°C All digital inputs excluding XCLKI and XCLKO VIH = VDD or VIH = 5 V VIL = 0 V; except TDI on ADuC7019/20/21/22/24/25 VIL = 0 V; TDI, on ADuC7019/20/21/22/24/25 All logic inputs excluding XCLKI and XCLKO Input Capacitance LOGIC INPUTS3 VINL, Input Low Voltage VINH, Input High Voltage LOGIC OUTPUTS VOH, Output High Voltage VOL, Output Low Voltage 12 CRYSTAL INPUTS XCLKI and XCLKO Logic Inputs, XCLKI Only VINL, Input Low Voltage VINH, Input High Voltage XCLKI Input Capacitance XCLKO Output Capacitance 0.8 2.0 2.4 0.4 1.1 1.7 20 20 V V pF pF Rev. A | Page 7 of 92 ADuC7019/20/21/22/24/25/26/27 Parameter INTERNAL OSCILLATOR MCU CLOCK RATE From 32 kHz Internal Oscillator From 32 kHz External Crystal Using an External Clock START-UP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay Element Propagation Delay POWER REQUIREMENTS 13, 14 Power Supply Voltage Range AVDD − AGND and IOVDD − IOGND Analog Power Supply Currents AVDD Current DACVDD Current 15 Digital Power Supply Current IOVDD Current in Normal Mode Min Typ 32.768 Max ±3 326 41.78 0.05 0.05 130 24 3.06 1.58 1.7 12 2.5 44 41.78 Unit kHz % kHz MHz MHz MHz ms ns μs ms ms ns ns Test Conditions/Comments CD = 7 CD = 0 TA = 85°C TA = 125°C Core clock = 41.78 MHz CD = 0 CD = 7 From input pin to output pin 2.7 200 400 3 3.6 V μA μA μA ADC in idle mode; all parts except ADuC7019 ADC in idle mode; ADuC7019 only 25 IOVDD Current in Pause Mode IOVDD Current in Sleep Mode Additional Power Supply Currents ADC DAC 1 2 3 7 11 40 25 250 600 2 0.7 700 10 15 45 30 400 1000 mA mA mA mA μA μA mA mA μA Code executing from Flash/EE CD = 7 CD = 3 CD = 0 (41.78 MHz clock) CD = 0 (41.78 MHz clock) TA = 85°C TA = 125°C @ 1 MSPS @ 62.5 kSPS per DAC All ADC channel specifications are guaranteed during normal MicroConverter core operation. Apply to all ADC input channels. Measured using the factory set default values in ADCOF and ADCGN. 4 Not production tested but supported by design and/or characterization data on production release. 5 Measured using the factory set default values in ADCOF and ADCGN using an external AD845 op amp as an input buffer stage as shown in Figure 47. Based on external ADC system components, the user may need to execute a system calibration to remove external endpoint errors and achieve these specifications (see the Calibration section). 6 The input signal can be centered on any dc common-mode voltage (VCM) as long as this value is within the ADC voltage input range specified. 7 When using an external reference input pin, the internal reference must be disabled by setting the LSB in the REFCON memory mapped register to 0. 8 DAC linearity is calculated using a reduced code range of 100 to 3995. 9 DAC gain error is calculated using a reduced code range of 100 to internal 2.5 V VREF. 10 Endurance is qualified as per JEDEC Standard 22 method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 11 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 method A117. Retention lifetime derates with junction temperature. 12 Test carried out with a maximum of eight I/O set to a low output level. 13 Power supply current consumption is measured in normal, pause, and sleep modes under the following conditions: Normal Mode: 3.6 V supply, Pause Mode: 3.6 V supply, Sleep Mode: 3.6 V supply. 14 IOVDD power supply current decreases typically by 2 mA during a flash/EE erase cycle. 15 On the ADuC7019/20/21/22, this current must be added to AVDD current. Rev. A | Page 8 of 92 ADuC7019/20/21/22/24/25/26/27 TIMING SPECIFICATIONS Table 2. External Memory Write Cycle Parameter CLK TMS_AFTER_CLKH TADDR_AFTER_CLKH TAE_H_AFTER_MS TAE THOLD_ADDR_AFTER_AE_L THOLD_ADDR_BEFORE_WR_L TWR_L_AFTER_AE_L TDATA_AFTER_WR_L TWR TWR_H_AFTER_CLKH THOLD_DATA_AFTER_WR_H TBEN_AFTER_AE_L TRELEASE_MS_AFTER_WR_H Min 0 4 ½ CLK (XMxPAR[14:12] + 1) x CLK ½ CLK + (!XMxPAR[10]) x CLK (!XMxPAR[8]) x CLK ½ CLK + (!XMxPAR[10] + !XMxPAR[8]) x CLK 8 (XMxPAR[7:4] + 1) x CLK 0 (!XMxPAR[8]) x CLK ½ CLK (!XMxPAR[8] + 1) x CLK 4 ns 12 ns Typ UCLK Max 4 8 Unit ns ns CLK CLK TMS_AFTER_CLKH MS TAE_H_AFTER_MS AE TWR TAE WR THOLD_DATA_AFTER_WR_H RD THOLD_ADDR_AFTER_AE_L THOLD_ADDR_BEFORE_WR_L TADDR_AFTER_CLKH A/D[15:0] FFFF 9ABC TDATA_AFTER_WR_L 5678 TBEN_AFTER_AE_L BEN0 BEN1 A16 04955-052 TWR_L_AFTER_AE_L TRELEASE_MS_AFTER_WR_H TWR_H_AFTER_CLKH 9ABE 1234 Figure 3. External Memory Write Cycle Rev. A | Page 9 of 92 ADuC7019/20/21/22/24/25/26/27 Table 3. External Memory Read Cycle Parameter CLK TMS_AFTER_CLKH TADDR_AFTER_ CLKH TAE_H_AFTER_MS TAE THOLD_ADDR_AFTER_AE_L TRD_L_AFTER_AE_L TDATA_AFTER_RD_L TRD TRD_H_AFTER_CLKH THOLD_DATA_AFTER_RD_H TRELEASE_MS_AFTER_RD_H Min 4 4 ½ CLK (XMxPAR[14:12] + 1) x CLK ½ CLK + (!XMxPAR[10]) x CLK ½ CLK + (!XMxPAR[10] + !XMxPAR[9]) x CLK 8 (XMxPAR[3:0] + 1) x CLK 0 (!XMxPAR[9]) x CLK CLK 4 ns 12 ns Typ UCLK Max 8 16 Unit ns ns CLK ECLK TMS_AFTER_CLKH GP0 TAE_H_AFTER_MS TAE TRD_L_AFTER_AE_L AE WR TRD RD THOLD_DATA_AFTER_RD_H TDATA_AFTER_RD_L TADDR_AFTER_CLKH A/D[15:0] BEN1 BEN0 A16 04955-053 TRELEASE_MS_AFTER_RD_H TRD_H_AFTER_CLKH THOLD_ADDR_AFTER_AE_L CDEF D14A 234A 89AB FFFF 234B Figure 4. External Memory Read Cycle Rev. A | Page 10 of 92 ADuC7019/20/21/22/24/25/26/27 Table 4. I2C Timing in Fast Mode (400 kHz) Parameter tL tH tSHD tDSU tDHD tRSU tPSU tBUF tR tF tSUP 1 Description SCLOCK low pulse width 1 SCLOCK high pulse width1 Start condition hold time Data setup time Data hold time Setup time for repeated start Stop condition setup time Bus-free time between a stop condition and a start condition Rise time for both CLOCK and SDATA Fall time for both CLOCK and SDATA Pulse width of spike suppressed Min 200 100 300 100 50 100 100 1.3 100 60 Slave Max Master Typ 1360 1140 251350 740 400 12.51350 400 200 20 300 100 50 Unit ns ns ns ns ns ns ns μs ns ns ns tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. tBUF SDATA (I/O) tSUP tR MSB LSB ACK MSB tDSU tPSU tSHD SCLK (I) PS STOP START CONDITION CONDITION 1 2–7 tDHD tH 8 tDSU tRSU 9 tF tDHD tR 1 S(R) REPEATED START Figure 5. I2C Compatible Interface Timing Rev. A | Page 11 of 92 04955-054 tL tSUP tF ADuC7019/20/21/22/24/25/26/27 Table 5. SPI Master Mode Timing (PHASE Mode = 1) Parameter tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF 1 2 Description SCLOCK low pulse width 1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge 2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max 25 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 Unit ns ns ns ns ns ns ns ns ns tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLOCK (POLARITY = 0) SCLOCK (POLARITY = 1) tSH tSL tSR tSF tDAV MOSI MSB tDF tDR BITS 6–1 LSB MISO MSB IN BITS 6–1 LSB IN 04955-055 tDSU tDHD Figure 6. SPI Master Mode Timing (PHASE Mode = 1) Rev. A | Page 12 of 92 ADuC7019/20/21/22/24/25/26/27 Table 6. SPI Master Mode Timing (PHASE Mode = 0) Parameter tSL tSH tDAV tDOSU tDSU tDHD tDF tDR tSR tSF 1 2 Description SCLOCK low pulse width 1 SCLOCK high pulse width1 Data output valid after SCLOCK edge Data output setup before SCLOCK edge Data input setup time before SCLOCK edge 2 Data input hold time after SCLOCK edge2 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Min Typ (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK Max 25 75 1 × tUCLK 2 × tUCLK 5 5 5 5 12.5 12.5 12.5 12.5 Unit ns ns ns ns ns ns ns ns ns ns tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. SCLOCK (POLARITY = 0) tSH tSL tSR SCLOCK (POLARITY = 1) tSF tDOSU MOSI MSB tDAV tDF tDR BITS 6–1 LSB MISO MSB IN BITS 6–1 LSB IN tDHD Figure 7. SPI Master Mode Timing (PHASE Mode = 0) Rev. A | Page 13 of 92 04955-056 tDSU ADuC7019/20/21/22/24/25/26/27 Table 7. SPI Slave Mode Timing (PHASE Mode = 1) Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tSFS 1 2 Description CS to SCLOCK edge 1 SCLOCK low pulse width 2 SCLOCK high pulse width2 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time CS high after SCLOCK edge Min 2 × tHCLK + 2 × tUCLK Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 25 1 × tUCLK 2 × tUCLK 5 5 5 5 0 12.5 12.5 12.5 12.5 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. CS tCS SCLOCK (POLARITY = 0) tSFS tSH tSL tSR SCLOCK (POLARITY = 1) tSF tDAV MISO MSB tDF tDR BITS 6–1 LSB MOSI MSB IN BITS 6–1 LSB IN 04955-057 tDSU tDHD Figure 8. SPI Slave Mode Timing (PHASE Mode = 1) Rev. A | Page 14 of 92 ADuC7019/20/21/22/24/25/26/27 Table 8. SPI Slave Mode Timing (PHASE Mode = 0) Parameter tCS tSL tSH tDAV tDSU tDHD tDF tDR tSR tSF tDOCS tSFS 1 2 Description CS to SCLOCK edge 1 SCLOCK low pulse width 2 SCLOCK high pulse width2 Data output valid after SCLOCK edge Data input setup time before SCLOCK edge1 Data input hold time after SCLOCK edge1 Data output fall time Data output rise time SCLOCK rise time SCLOCK fall time Data output valid after CS edge CS high after SCLOCK edge Min 2 × tHCLK + 2 × tUCLK Typ Max Unit ns ns ns ns ns ns ns ns ns ns ns ns (SPIDIV + 1) × tHCLK (SPIDIV + 1) × tHCLK 25 1 × tUCLK 2 × tUCLK 5 5 5 5 0 12.5 12.5 12.5 12.5 25 tUCLK = 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider. tHCLK depends on the clock divider or CD bits in PLLCON MMR. tHCLK = tUCLK/2CD. CS tCS SCLOCK (POLARITY = 0) tSFS tSH SCLOCK (POLARITY = 1) tSL tSR tSF tDAV tDOCS tDF MISO MSB tDR BITS 6–1 LSB MOSI MSB IN BITS 6–1 LSB IN 04955-058 tDSU tDHD Figure 9. SPI Slave Mode Timing (PHASE Mode = 0) Rev. A | Page 15 of 92 ADuC7019/20/21/22/24/25/26/27 ABSOLUTE MAXIMUM RATINGS AGND = REFGND = DACGND = GNDREF; TA = 25°C, unless otherwise noted. Table 9. Parameter AVDD to IOVDD AGND to DGND IOVDD to IOGND, AVDD to AGND Digital Input Voltage to IOGND Digital Output Voltage to IOGND VREF to AGND Analog Inputs to AGND Analog Outputs to AGND Operating Temperature Range Industrial Storage Temperature Range Junction Temperature θJA Thermal Impedance (40-pin CSP) θJA Thermal Impedance (64-pin CSP) θJA Thermal Impedance (64-pin LQFP) θJA Thermal Impedance (80-pin LQFP) Peak Solder Reflow Temperature SnPb Assemblies (10 sec to 30 sec) Pb-Free Assemblies (20 sec to 40 sec) Rating −0.3 V to +0.3 V −0.3 V to +0.3 V −0.3 V to +6 V −0.3 V to +5.3 V −0.3 V to IOVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V −0.3 V to AVDD + 0.3 V –40°C to +125°C –65°C to +150°C 150°C 26°C/W 24°C/W 47°C/W 38°C/W 240°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 16 of 92 ADuC7019/20/21/22/24/25/26/27 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS ADuC7019/ADuC7020/ADuC7021/ADuC7022 ADC2/CMP0 ADC1 ADC0 AVDD AGND VREF P4.2/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] P1.2/SPM2/PLAI[2] ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 AVDD AGND VREF P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] P1.2/SPM2/PLAI[2] 40 39 38 37 36 35 34 33 32 31 ADC3/CMP1 1 ADC4 2 GNDREF 3 4 DAC0/ADC12 5 DAC1/ADC13 6 DAC2/ADC14 7 DAC3/ADC15 TMS 8 9 TDI BM/P0.0/CMPOUT/PLAI[7] 10 PIN 1 INDICATOR ADuC7019/ ADuC7020 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART IRQ1/P0.5/ADCBUSY/PLAO[2] ADC4 1 ADC5 2 ADC6 3 ADC7 4 GNDREF 5 6 DAC0/ADC12 7 DAC1/ADC13 TMS 8 9 TDI BM/P0.0/CMPOUT/PLAI[7] 10 40 39 38 37 36 35 34 33 32 31 PIN 1 INDICATOR ADuC7021 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART IRQ1/P0.5/ADCBUSY/PLAO[2] 11 12 13 14 15 16 17 18 19 20 P0.6/T1/MRST/PLAO[3] TCK TDO IOGND IOVDD LVDD DGND P0.3/TRST/ADC BUSY RST IRQ0/P0.4/PWMTRIP/PLAO[1] 04955-064 P0.6/T1/MRST/PLAO[3] TCK TDO IOGND IOVDD LVDD DGND P0.3/TRST/ADC BUSY RST IRQ0/P0.4/PWMTRIP/PLAO[1] 11 12 13 14 15 16 17 18 19 20 Figure 10. ADuC7019/ADuC7020 40-Lead LFCSP_VQ Pin Configuration Figure 11. ADuC702140-Lead LFCSP_VQ Pin Configuration ADC5 1 ADC6 2 ADC7 3 ADC8 4 ADC9 5 GNDREF 6 TMS 7 8 TDI BM/P0.0/CMPOUT/PLAI[7] 9 P0.6/T1/MRST/PLAO[3] 10 40 39 38 37 36 35 34 33 32 31 ADC4 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 AVDD AGND VREF P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] PIN 1 INDICATOR ADuC7022 TOP VIEW (Not to Scale) 30 29 28 27 26 25 24 23 22 21 P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART TCK TDO IOGND IOVDD LVDD DGND P0.3/TRST/ADC BUSY RST IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2] 11 12 13 14 15 16 17 18 19 20 Figure 12. ADuC7022 40-Lead LFCSP_VQ Pin Configuration Rev. A | Page 17 of 92 04955-066 04955-065 ADuC7019/20/21/22/24/25/26/27 Table 10. Pin Function Descriptions (ADuC7019/ADuC7020/ADuC7021/ADuC7022) Pin No. 7019/7020 7021 38 37 39 38 40 39 1 40 2 ‒ ‒ ‒ ‒ ‒ 3 4 5 6 7 1 2 3 4 ‒ ‒ 5 6 7 ‒ ‒ 7022 36 37 38 39 40 1 2 3 4 5 6 ‒ ‒ ‒ ‒ Mnemonic ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 Description Single-Ended or Differential Analog Input 0. Single-Ended or Differential Analog Input 1. Single-Ended or Differential Analog Input 2/Comparator Positive Input. Single-Ended or Differential Analog Input 3 (Buffered Input on ADuC7019)/Comparator Negative Input. Single-Ended or Differential Analog Input 4. Single-Ended or Differential Analog Input 5. Single-Ended or Differential Analog Input 6. Single-Ended or Differential Analog Input 7. Single-Ended or Differential Analog Input 8. Single-Ended or Differential Analog Input 9. Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from IOGND and DGND. DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. DAC3 Voltage Output on ADuC7020. On the ADuC7019, a 10 nF capacitor needs to be connected between this pin and AGND/Single-Ended or Differential Analog Input 15. Test Mode Select, JTAG Test Port Input. Debug and download access. Test Data In, JTAG Test Port Input. Debug and download access. Multifunction I/O Pin. Boot Mode (BM). The ADuC7019/20/21/22 enter serial download mode if BM is low at reset and execute code if BM is pulled high at reset through a 1 kΩ resistor. General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7. Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/Programmable Logic Array Output Element 3. Test Clock, JTAG Test Port Input. Debug and download access. Test Data Out, JTAG Test Port Output. Debug and download access. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 μf capacitor to DGND only. Ground for Core Logic. General-Purpose Input and Output Port 0.3/Test Reset, JTAG Test Port Input/ ADCBUSY Signal Output. Reset Input, Active Low. Multifunction I/O Pin. External Interrupt Request 0, Active High/GeneralPurpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1. Multifunction I/O Pin. External Interrupt Request 1, Active High/GeneralPurpose Input andOutput Port 0.5/ADCBUSY Signa l Output/Programmable Logic Array Output Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/ Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC. Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/UART/ Programmable Logic Array Output Element 4. Output from the Crystal Oscillator Inverter. 8 9 10 8 9 10 7 8 9 TMS TDI BM/P0.0/CMPOUT/PLAI[7] 11 11 10 P0.6/T1/MRST/PLAO[3] 12 13 14 15 16 17 18 19 20 12 13 14 15 16 17 18 19 20 11 12 13 14 15 16 17 18 19 TCK TDO IOGND IOVDD LVDD DGND P0.3/TRST/ADCBUSY RST IRQ0/P0.4/PWMTRIP/PLAO[1] 21 21 20 IRQ1/P0.5/ADCBUSY/PLAO[2] 22 22 21 P2.0/SPM9/PLAO[5]/CONVSTART 23 23 22 P0.7/ECLK/XCLK/SPM8/PLAO[4] 24 24 23 XCLKO Rev. A | Page 18 of 92 ADuC7019/20/21/22/24/25/26/27 Pin No. 7019/7020 7021 25 25 26 27 28 26 27 28 7022 24 25 26 27 Mnemonic XCLKI P1.7/SPM7/PLAO[0] P1.6/SPM6/PLAI[6] P1.5/SPM5/PLAI[5]/IRQ3 Description Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/ Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0. General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10. 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. Analog Ground. Ground reference point for the analog circuitry. 3.3 V Analog Power. 29 29 28 P1.4/SPM4/PLAI[4]/IRQ2 30 31 32 33 34 35 36 37 30 31 32 33 ‒ 34 35 36 29 30 31 32 ‒ 33 34 35 P1.3/SPM3/PLAI[3] P1.2/SPM2/PLAI[2] P1.1/SPM1/PLAI[1] P1.0/T1/SPM0/PLAI[0] P4.2/PLAO[10] VREF AGND AVDD Rev. A | Page 19 of 92 ADuC7019/20/21/22/24/25/26/27 ADuC7024/ADuC7025 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 DACV DD AVDD AGND DACGND DAC REF VREF P4.5/PLAO[13] P4.4/PLAO[12] P4.3/PLAO[11] P4.2/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 TMS TDI P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMPOUT/PLAI[7] P0.6/T1/MRST/PLAO[3] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PIN 1 INDICATOR ADuC7024/ ADuC7025 TOP VIEW (Not to Scale) P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P4.1/PLAO[9] P4.0/PLAO[8] IOVDD IOGND P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P3.7/PWMSYNC/PLAI[15] P3.6/PWMTRIP/PLAI[14] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART TCK TDO IOGND IOVDD LVDD DGND P3.0/PWM0H/PLAI[8] P3.1/PWM0L/PLAI[9] P3.2/PWM1H/PLAI[10] P3.3/PWM1L/PLAI[11] P0.3/TRST/ADC BUSY RST P3.4/PWM2H/PLAI[12] P3.5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2] 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 13. ADuC7024/ADuC7025 64-Lead LFCSP_VQ Pin Configuration 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 DACV DD AVDD AGND DACGND DAC REF VREF P4.5/PLAO[13] P4.4/PLAO[12] P4.3/PLAO[11] P4.2/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 TMS TDI P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMPOUT/PLAI[7] P0.6/T1/MRST/PLAO[3] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIN 1 INDICATOR ADuC7024/ ADuC7025 TOP VIEW (Not to Scale) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P4.1/PLAO[9] P4.0/PLAO[8] IOVDD IOGND P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P3.7/PWMSYNC/PLAI[15] P3.6/PWMTRIP/PLAI[14] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART TCK TDO IOGND IOVDD LVDD DGND P3.0/PWM0H/PLAI[8] P3.1/PWM0L/PLAI[9] P3.2/PWM1H/PLAI[10] P3.3/PWM1L/PLAI[11] P0.3/TRST/ADC BUSY RST P3.4/PWM2H/PLAI[12] P3.5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2] 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 04955-067 04955-068 Figure 14. ADuC7024/ADuC7025 64-Lead LQFP Pin Configuration Rev. A | Page 20 of 92 ADuC7019/20/21/22/24/25/26/27 Table 11. Pin Function Descriptions (ADuC7024/ADuC7025 64-Lead CSP and ADuC7024/ADuC7025 64-Lead LQFP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Mnemonic ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 TMS TDI P4.6/PLAO[14] P4.7/PLAO[15] BM/P0.0/CMPOUT/PLAI[7] Description Single-Ended or Differential Analog Input 4. Single-Ended or Differential Analog Input 5. Single-Ended or Differential Analog Input 6. Single-Ended or Differential Analog Input 7. Single-Ended or Differential Analog Input 8. Single-Ended or Differential Analog Input 9. Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from IOGND and DGND. Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V. DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not present on the ADuC7025. DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not present on the ADuC7025. JTAG Test Port Input, Test Mode Select. Debug and download access. JTAG Test Port Input, Test Data In. Debug and download access General-Purpose Input and Output Port 4.6/Programmable Logic Array Output Element 14. General-Purpose Input and Output Port 4.7/Programmable Logic Array Output Element 15. Multifunction I/O Pin. Boot mode. The ADuC7024/ADuC7025 enter download mode if BM is low at reset and executes code if BM is pulled high at reset through a 1 kΩ resistor/General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7. Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/Programmable Logic Array Output Element 3. JTAG Test Port Input, Test Clock. Debug and download access. JTAG Test Port Output, Test Data Out. Debug and download access. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 μF capacitor to DGND only. Ground for Core Logic. General-Purpose Input and Output Port 3.0/PWM Phase 0 High-Side Output/Programmable Logic Array Input Element 8. General-Purpose Input and Output Port 3.1/PWM Phase 0 Low-Side Output/Programmable Logic Array Input Element 9. General-Purpose Input and Output Port 3.2/PWM Phase 1 High-Side Output/Programmable Logic Array Input Element 10. General-Purpose Input and Output Port 3.3/PWM Phase 1 Low-Side Output/Programmable Logic Array Input Element 11. General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output. Reset Input, Active Low. General-Purpose Input and Output Port 3.4/PWM Phase 2 High-Side Output/Programmable Logic Array Input 12. General-Purpose Input and Output Port 3.5/PWM Phase 2 Low-Side Output/Programmable Logic Array Input Element 13. Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1. Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC. Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output Element 4. Output from the Crystal Oscillator Inverter. Rev. A | Page 21 of 92 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 P0.6/T1/MRST/PLAO[3] TCK TDO IOGND IOVDD LVDD DGND P3.0/PWM0H/PLAI[8] P3.1/PWM0L/PLAI[9] P3.2/PWM1H/PLAI[10] P3.3/PWM1L/PLAI[11] P0.3/TRST/ADCBUSY RST P3.4/PWM2H/PLAI[12] P3.5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1] IRQ1/P0.5/ADCBUSY/PLAO[2] P2.0/SPM9/PLAO[5]/CONVSTART P0.7/ECLK/XCLK/SPM8/PLAO[4] 35 XCLKO ADuC7019/20/21/22/24/25/26/27 Pin No. 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Mnemonic XCLKI P3.6/PWMTRIP/PLAI[14] P3.7/PWMSYNC/PLAI[15] P1.7/SPM7/PLAO[0] P1.6/SPM6/PLAI[6] IOGND IOVDD P4.0/PLAO[8] P4.1/PLAO[9] P1.5/SPM5/PLAI[5]/IRQ3 P1.4/SPM4/PLAI[4]/IRQ2 P1.3/SPM3/PLAI[3] P1.2/SPM2/PLAI[2] P1.1/SPM1/PLAI[1] P1.0/T1/SPM0/PLAI[0] P4.2/PLAO[10] P4.3/PLAO[11] P4.4/PLAO[12] P4.5/PLAO[13] VREF DACREF DACGND AGND AVDD DACVDD ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 Description Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. General-Purpose Input and Output Port 3.6/PWM Safety Cut Off/Programmable Logic Array Input Element 14. General-Purpose Input and Output Port 3.7/PWM Synchronization Input Output/Programmable Logic Array Input Element 15. Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. General-Purpose Input and Output Port 4.0/Programmable Logic Array Output Element 8. General-Purpose Input and Output Port 4.1/Programmable Logic Array Output Element 9. Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0. General-Purpose Input and Output Port 4.2/Programmable Logic Array Output Element 10. General-Purpose Input and Output Port 4.3/Programmable Logic Array Output Element 11. General-Purpose Input and Output Port 4.4/Programmable Logic Array Output Element 12. General-Purpose Input and Output Port 4.5/Programmable Logic Array Output Element 13. 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. External Voltage Reference for the DACs. Range: DACGND to DACVDD. Ground for the DAC. Typically connected to AGND. Analog Ground. Ground reference point for the analog circuitry. 3.3 V Analog Power. 3.3 V Power Supply for the DACs. Typically connected to AVDD. Single-Ended or Differential Analog Input 0. Single-Ended or Differential Analog Input 1. Single-Ended or Differential Analog Input 2/Comparator Positive Input. Single-Ended or Differential Analog Input 3/Comparator Negative Input. Rev. A | Page 22 of 92 ADuC7019/20/21/22/24/25/26/27 ADuC7026/ADuC7027 ADC3/CMP1 ADC2/CMP0 ADC1 ADC0 ADC11 DACV DD AVDD AVDD AGND AGND DACGND DACREF VREF REFGND P4.5/AD13/PLAO[13] P4.4/AD12/PLAO[12] P4.3/AD11/PLAO[11] P4.2/AD10/PLAO[10] P1.0/T1/SPM0/PLAI[0] P1.1/SPM1/PLAI[1] ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 TMS TDI P0.1/PWM2H/BLE P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] BM/P0.0/CMPOUT/PLAI[7]/MS2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 PIN 1 INDICATOR ADuC7026/ ADuC7027 TOP VIEW (Not to Scale) 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P1.2/SPM2/PLAI[2] P1.3/SPM3/PLAI[3] P1.4/SPM4/PLAI[4]/IRQ2 P1.5/SPM5/PLAI[5]/IRQ3 P4.1/AD9/PLAO[9] P4.0/AD8/PLAO[8] IOVDD IOGND P1.6/SPM6/PLAI[6] P1.7/SPM7/PLAO[0] P2.2/RS/PWM0L/PLAO[7] P2.1/WS/PWM0H/PLAO[6] P2.7/PWM1L/MS3 P3.7/AD7/PWMSYNC /PLAI[15] P3.6/AD6/PWMTRIP/PLAI[14] XCLKI XCLKO P0.7/ECLK/XCLK/SPM8/PLAO[4] P2.0/SPM9/PLAO[5]/CONVSTART IRQ1/P0.5/ADCBUSY /PLAO[2]/MS0 P0.6/T1/MRST/PLAO[3]/AE TCK TDO P0.2/PWM2L/BHE IOGND IOVDD LVDD DGND P3.0/AD0/PWM0H/PLAI[8] P3.1/AD1/PWM0L/PLAI[9] P3.2/AD2/PWM1H/PLAI[10] P3.3/AD3/PWM1L/PLAI[11] P2.4/PWM0H/MS0 P0.3/TRST/A16/ADC BUSY P2.5/PWM0L/MS1 P2.6/PWM1H/MS2 RST P3.4/AD4/PWM2H/PLAI[12] P3.5/AD5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Figure 15. ADuC7026/ADuC7027 80-Lead LQFP Pin Configuration Table 12. Pin Function Descriptions (ADuC7026/ADuC7027) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 Mnemonic ADC4 ADC5 ADC6 ADC7 ADC8 ADC9 ADC10 GNDREF ADCNEG DAC0/ADC12 DAC1/ADC13 DAC2/ADC14 DAC3/ADC15 Description Single-Ended or Differential Analog Input 4. Single-Ended or Differential Analog Input 5. Single-Ended or Differential Analog Input 6. Single-Ended or Differential Analog Input 7. Single-Ended or Differential Analog Input 8. Single-Ended or Differential Analog Input 9. Single-Ended or Differential Analog Input 10. Ground Voltage Reference for the ADC. For optimal performance, the analog power supply should be separated from IOGND and DGND. Bias Point or Negative Analog Input of the ADC in Pseudo Differential Mode. Must be connected to the ground of the signal to convert. This bias point must be between 0 V and 1 V. DAC0 Voltage Output/Single-Ended or Differential Analog Input 12. DAC outputs are not present on the ADuC7027. DAC1 Voltage Output/Single-Ended or Differential Analog Input 13. DAC outputs are not present on the ADuC7027. DAC2 Voltage Output/Single-Ended or Differential Analog Input 14. DAC outputs are not present on the ADuC7027. DAC3 Voltage Output/Single-Ended or Differential Analog Input 15. DAC outputs are not present on the ADuC7027. Rev. A | Page 23 of 92 04955-069 ADuC7019/20/21/22/24/25/26/27 Pin No. 14 15 16 17 18 19 20 Mnemonic TMS TDI P0.1/PWM2H/BLE P2.3/AE P4.6/AD14/PLAO[14] P4.7/AD15/PLAO[15] BM/P0.0/CMPOUT/PLAI[7]/MS2 Description JTAG Test Port Input, Test Mode Select. Debug and download access. JTAG Test Port Input, Test Data In. Debug and download access. General-Purpose Input and Output Port 0.1/PWM Phase 2 High-Side Output/External Memory Byte Low Enable. General-Purpose Input and Output Port 2.3/External Memory Access Enable. General-Purpose Input and Output Port 4.6/External Memory Interface/Programmable Logic Array Output Element 14. General-Purpose Input and Output Port 4.7/External Memory Interface/Programmable Logic Array Output Element 15. Multifunction I/O Pin. Boot Mode. The ADuC7026/ADuC7027 enter UART download mode if BM is low at reset and execute code if BM is pulled high at reset through a 1 kΩ resistor/ General-Purpose Input and Output Port 0.0/Voltage Comparator Output/Programmable Logic Array Input Element 7/External Memory Select 2. Multifunction Pin, Driven Low After Reset. General-Purpose Output Port 0.6/Timer1 Input/Power-On Reset Output/Programmable Logic Array Output Element 3. JTAG Test Port Input, Test Clock. Debug and download access. JTAG Test Port Output, Test Data Out. Debug and download access. General-Purpose Input and Output Port 0.2/PWM Phase 2 Low-Side Output/External Memory Byte High Enable. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. 2.6 V Output of the On-Chip Voltage Regulator. This output must be connected to a 0.47 μF capacitor to DGND only. Ground for Core Logic. General-Purpose Input and Output Port 3.0/External Memory Interface/PWM Phase 0 HighSide Output/Programmable Logic Array Input Element 8. General-Purpose Input and Output Port 3.1/External Memory Interface/PWM Phase 0 LowSide Output/Programmable Logic Array Input Element 9. General-Purpose Input and Output Port 3.2/External Memory Interface/PWM Phase 1 HighSide Output/Programmable Logic Array Input Element 10. General-Purpose Input and Output Port 3.3/External Memory Interface/PWM Phase 1 LowSide Output/Programmable Logic Array Input Element 11. General-Purpose Input and Output Port 2.4/PWM Phase 0 High-Side Output/External Memory Select 0. General-Purpose Input and Output Port 0.3/JTAG Test Port Input, Test Reset/ADCBUSY Signal Output. General-Purpose Input and Output Port 2.5/PWM Phase 0 Low-Side Output/External Memory Select 1. General-Purpose Input and Output Port 2.6/PWM Phase 1 High-Side Output/External Memory Select 2. Reset Input, Active Low. General-Purpose Input and Output Port 3.4/External Memory Interface/PWM Phase 2 HighSide Output/Programmable Logic Array Input 12. General-Purpose Input and Output Port 3.5/External Memory Interface/PWM Phase 2 LowSide Output/Programmable Logic Array Input Element 13. Multifunction I/O Pin. External Interrupt Request 0, Active High/General-Purpose Input and Output Port 0.4/PWM Trip External Input/Programmable Logic Array Output Element 1/External Memory Select 1. Multifunction I/O Pin. External Interrupt Request 1, Active High/General-Purpose Input and Output Port 0.5/ADCBUSY Signal Output/Programmable Logic Array Output Element 2/External Memory Select 0. Serial Port Multiplexed. General-Purpose Input and Output Port 2.0/UART/Programmable Logic Array Output Element 5/Start Conversion Input Signal for ADC. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 P0.6/T1/MRST/PLAO[3]/AE TCK TDO P0.2/ PWM2L/BHE IOGND IOVDD LVDD DGND P3.0/AD0/PWM0H/PLAI[8] P3.1/AD1/PWM0L/PLAI[9] P3.2/AD2/PWM1H/PLAI[10] P3.3/AD3/PWM1L/PLAI[11] P2.4/PWM0H/MS0 P0.3/TRST/A16/ADCBUSY P2.5/PWM0L/MS1 P2.6/PWM1H/MS2 RST P3.4/AD4/PWM2H/PLAI[12] P3.5/AD5/PWM2L/PLAI[13] IRQ0/P0.4/PWMTRIP/PLAO[1]/MS1 41 IRQ1/P0.5/ADCBUSY/PLAO[2]/MS0 42 P2.0/SPM9/PLAO[5]/CONVSTART Rev. A | Page 24 of 92 ADuC7019/20/21/22/24/25/26/27 Pin No. 43 Mnemonic P0.7/ECLK/XCLK/SPM8/ PLAO[4] Description Serial Port Multiplexed. General-Purpose Input and Output Port 0.7/Output for External Clock Signal/Input to the Internal Clock Generator Circuits/UART/Programmable Logic Array Output Element 4. Output from the Crystal Oscillator Inverter. Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator Circuits. General-Purpose Input and Output Port 3.6/External Memory Interface/PWM Safety Cut Off/Programmable Logic Array Input Element 14. General-Purpose Input and Output Port 3.7/External Memory Interface/PWM Synchronization/Programmable Logic Array Input Element 15. General-Purpose Input and Output Port 2.7/PWM Phase 1 Low-Side Output/External Memory Select 3. General-Purpose Input and Output Port 2.1/External Memory Write Strobe/PWM Phase 0 High-Side Output/Programmable Logic Array Output Element 6. General-Purpose Input and Output Port 2.2/External Memory Read Strobe/PWM Phase 0 LowSide Output/Programmable Logic Array Output Element 7. Serial Port Multiplexed. General-Purpose Input and Output Port 1.7/UART, SPI/Programmable Logic Array Output Element 0. Serial Port Multiplexed. General-Purpose Input and Output Port 1.6/UART, SPI/Programmable Logic Array Input Element 6. Ground for GPIO. Typically connected to DGND. 3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator. General-Purpose Input and Output Port 4.0/External Memory Interface/Programmable Logic Array Output Element 8. General-Purpose Input and Output Port 4.1/External Memory Interface/Programmable Logic Array Output Element 9. Serial Port Multiplexed. General-Purpose Input and Output Port 1.5/UART, SPI/Programmable Logic Array Input Element 5/External Interrupt Request 3, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.4/UART, SPI/Programmable Logic Array Input Element 4/External Interrupt Request 2, Active High. Serial Port Multiplexed. General-Purpose Input and Output Port 1.3/UART, I2C1/Programmable Logic Array Input Element 3. Serial Port Multiplexed. General-Purpose Input and Output Port 1.2/UART, I2C1/Programmable Logic Array Input Element 2. Serial Port Multiplexed. General-Purpose Input and Output Port 1.1/UART, I2C0/Programmable Logic Array Input Element 1. Serial Port Multiplexed. General-Purpose Input and Output Port 1.0/Timer1 Input/UART, I2C0/Programmable Logic Array Input Element 0. General-Purpose Input and Output Port 4.2/External Memory Interface/Programmable Logic Array Output Element 10. General-Purpose Input and Output Port 4.3/External Memory Interface/Programmable Logic Array Output Element 11. General-Purpose Input and Output Port 4.4/External Memory Interface/Programmable Logic Array Output Element 12. General-Purpose Input and Output Port 4.5/External Memory Interface/Programmable Logic Array Output Element 13. Ground for the Reference. Typically connected to AGND. 2.5 V Internal Voltage Reference. Must be connected to a 0.47 μF capacitor when using the internal reference. External Voltage Reference for the DACs. Range: DACGND to DACVDD. Ground for the DAC. Typically connected to AGND. Analog Ground. Ground reference point for the analog circuitry. 3.3 V Analog Power. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71, 72 73, 74 XCLKO XCLKI P3.6/AD6/PWMTRIP/PLAI[14] P3.7/AD7/PWMSYNC/PLAI[15] P2.7/PWM1L/MS3 P2.1/WS/PWM0H/PLAO[6] P2.2/RS/PWM0L/PLAO[7] P1.7/SPM7/PLAO[0] P1.6/SPM6/PLAI[6] IOGND IOVDD P4.0/AD8/PLAO[8] P4.1/AD9/PLAO[9] P1.5/SPM5/PLAI[5]/IRQ3 P1.4/SPM4/PLAI[4]/IRQ2 P1.3/SPM3/PLAI[3] P1.2/SPM2/PLAI[2] P1.1/SPM1/PLAI[1] P1.0/T1/SPM0/PLAI[0] P4.2/AD10/PLAO[10] P4.3/AD11/PLAO[11] P4.4/AD12/PLAO[12] P4.5/AD13/PLAO[13] REFGND VREF DACREF DACGND AGND AVDD Rev. A | Page 25 of 92 ADuC7019/20/21/22/24/25/26/27 Pin No. 75 76 77 78 79 80 Mnemonic DACVDD ADC11 ADC0 ADC1 ADC2/CMP0 ADC3/CMP1 Description 3.3 V Power Supply for the DACs. Typically connected to AVDD. Single-Ended or Differential Analog Input 11. Single-Ended or Differential Analog Input 0. Single-Ended or Differential Analog Input 1. Single-Ended or Differential Analog Input 2/Comparator Positive Input. Single-Ended or Differential Analog Input 3/Comparator Negative Input. Rev. A | Page 26 of 92 ADuC7019/20/21/22/24/25/26/27 TYPICAL PERFORMANCE CHARACTERISTICS 1.0 0.8 0.6 0.4 0.2 (LSB) 1.0 fS = 774kSPS fS = 774kSPS 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1000 2000 ADC CODES 3000 4000 04955-075 (LSB) 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1000 2000 ADC CODES 3000 4000 04955-074 Figure 16. Typical INL Error, fS = 774 kSPS 1.0 1.0 Figure 19. Typical DNL Error, fS = 774 kSPS fS = 1MSPS 0.8 0.6 0.4 0.2 fS = 1MSPS 0.8 0.6 0.4 0.2 (LSB) 0 –0.2 –0.4 –0.6 04955-077 (LSB) 0 –0.2 –0.4 –0.6 –0.8 –1.0 0 1000 2000 ADC CODES 3000 4000 04955-076 –0.8 –1.0 0 1000 2000 ADC CODES 3000 4000 Figure 17. Typical INL Error, fS = 1 MSPS 1.0 0.9 0.8 0.7 WCP 0.6 0 –0.1 –0.2 –0.3 0 –0.1 –0.2 Figure 20. Typical DNL Error, fS = 1 MSPS 1.0 0.9 0.8 WCN –0.3 –0.4 0.7 0.6 0.5 WCP 0.4 0.3 0.2 0.1 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) 3.0 0 04955-071 (LSB) (LSB) (LSB) 0.5 –0.6 0.4 WCN 0.3 0.2 0.1 0 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) 3.0 –0.7 –0.8 –0.9 –1.0 –0.5 –0.6 –0.7 –0.8 04955-072 –0.9 –1.0 Figure 18. Typical Worst Case INL Error vs. VREF, fS = 774 kSPS Figure 21. Typical Worst Case DNL Error vs. VREF, fS = 774 kSPS Rev. A | Page 27 of 92 (LSB) –0.5 ADuC7019/20/21/22/24/25/26/27 9000 8000 7000 75 –76 70 SNR 65 –78 6000 –80 FREQUENCY SNR (dB) 5000 4000 3000 60 THD 55 –84 50 –82 2000 04955-073 1000 0 1161 1162 BIN 1163 40 1.0 1.5 2.0 2.5 EXTERNAL REFERENCE (V) 3.0 –88 Figure 22. Code Histogram Plot, fs = 774 kSPS, VIN = 0.7 V 0 Figure 25. Typical Dynamic Performance vs. VREF 1500 fS = 774kSPS, –20 –40 SNR = 69.3dB, THD = –80.8dB, PHSN = –83.4dB 1450 1400 1350 –60 1300 CODE (dB) –80 –100 –120 1250 1200 1150 1100 04955-078 1050 1000 –50 0 50 TEMPERATURE (°C) 100 150 –160 0 100 FREQUENCY (kHz) 200 Figure 23. Dynamic Performance, fS = 774 kSPS 20 Figure 26. On-Chip Temperature Sensor Voltage Output vs. Temperature 39.8 39.7 39.6 39.5 (mA) fS = 1MSPS, 0 –20 –40 SNR = 70.4dB, THD = –77.2dB, PHSN = –78.9dB (dB) –60 –80 –100 –120 –140 –160 04955-079 39.4 39.3 39.2 39.1 39.0 38.9 04955-080 0 50 100 FREQUENCY (kHz) 150 200 –40 0 25 85 TEMPERATURE (°C) 125 Figure 24. Dynamic Performance, fS = 1 MSPS Figure 27. Current Consumption vs. Temperature @ CD = 0 Rev. A | Page 28 of 92 04955-060 –140 04955-070 45 –86 THD (dB) ADuC7019/20/21/22/24/25/26/27 12.05 12.00 1.2 11.95 11.90 11.85 (mA) 1.4 1.0 0.8 (mA) 11.80 11.75 11.70 11.65 04955-081 0.6 0.4 11.60 11.55 –40 0 25 85 TEMPERATURE (°C) 125 0 –40 0 25 85 TEMPERATURE (°C) 125 Figure 28. Current Consumption vs. Temperature @ CD = 3 7.85 7.80 Figure 30. Current Consumption vs. Temperature in Sleep Mode 37.4 37.2 7.75 7.70 (mA) (mA) 37.0 7.65 7.60 7.55 7.50 36.8 36.6 36.4 04955-082 7.45 7.40 –40 0 25 85 TEMPERATURE (°C) 125 36.2 62.25 125.00 250.00 500.00 SAMPLING FREQUENCY (kSPS) 1000.00 Figure 29. Current Consumption vs. Temperature @ CD = 7 Figure 31. Current Consumption vs. ADC Speed Rev. A | Page 29 of 92 04955-084 04955-083 0.2 ADuC7019/20/21/22/24/25/26/27 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below the first code transition and full scale, a point ½ LSB above the last code transition. Differential Nonlinearity The difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Offset Error The deviation of the first code transition (0000 . . . 000) to (0000 . . . 001) from the ideal, that is, +½ LSB. Gain Error The deviation of the last code transition from the ideal AIN voltage (full scale − 1.5 LSB) after the offset error has been adjusted out. Signal to (Noise + Distortion) Ratio The measured ratio of signal to (noise + distortion) at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the rms sum of all nonfundamental signals up to half the sampling frequency (fS/2), excluding dc. The ratio is dependent upon the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal to (noise + distortion) ratio for an ideal N-bit converter with a sine wave input is given by Signal to (Noise + Distortion) = (6.02 N + 1.76) dB Thus, for a 12-bit converter, this is 74 dB. Total Harmonic Distortion The ratio of the rms sum of the harmonics to the fundamental. DAC SPECIFICATIONS Relative Accuracy Otherwise known as endpoint linearity, relative accuracy is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero error and full-scale error. Voltage Output Settling Time The amount of time it takes for the output to settle to within a 1 LSB level for a full-scale input change. Rev. A | Page 30 of 92 ADuC7019/20/21/22/24/25/26/27 OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8 bits, 16 bits, or 32 bits. The length of the instruction word is 32 bits. The ARM7TDMI is an ARM7 core with four additional features: • • • • T support for the thumb (16 bit) instruction set D support for debug M support for long multiplications I includes the embeddedICE module to support embedded system debugging When a breakpoint or watchpoint is encountered, the processor halts and enters debug state. Once in a debug state, the processor registers can be inspected as well as the Flash/EE, the SRAM, and the memory mapped registers. EXCEPTIONS ARM supports five types of exceptions and a privileged processing mode for each type. The five types of exceptions are: • Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of internal and external events. Fast interrupt or FIQ. This is provided to service data transfer or communication channel with low latency. FIQ has priority over IRQ. Memory abort. Attempted execution of an undefined instruction. Software interrupt instruction (SWI). This can be used to make a call to an operating system. THUMB MODE (T) An ARM instruction is 32 bits long. The ARM7TDMI processor supports a second instruction set that has been compressed into 16 bits, called the thumb instruction set. Faster execution from 16-bit memory and greater code density can usually be achieved by using the thumb instruction set instead of the ARM instruction set, which makes the ARM7TDMI core particularly suitable for embedded applications. However, the thumb mode has two limitations: • Thumb code usually uses more instructions for the same job. As a result, ARM code is usually best for maximizing the performance of the time-critical code. The thumb instruction set does not include some of the instructions needed for exception handling, which automatically switches the core to ARM code for exception handling. • • • • Typically, the programmer defines interrupt as IRQ, but for higher priority interrupt, that is, faster response time, the programmer can define interrupt as FIQ. ARM REGISTERS ARM7TDMI has a total of 37 registers: 31 general-purpose registers and six status registers. Each operating mode has dedicated banked registers. When writing user-level programs, 15 general-purpose 32-bit registers (R0 to R14), the program counter (R15) and the current program status register (CPSR) are usable. The remaining registers are only used for system-level programming and for exception handling. When an exception occurs, some of the standard registers are replaced with registers specific to the exception mode. All exception modes have replacement banked registers for the stack pointer (R13) and the link register (R14) as represented in Figure 32. The fast interrupt mode has more registers (R8 to R12) for fast interrupt processing. This means the interrupt processing can begin without the need to save or restore these registers, and thus save critical time in the interrupt handling process. • See the ARM7TDMI user guide for details on the core architecture, the programming model, and both the ARM and ARM thumb instruction sets. LONG MULTIPLY (M) The ARM7TDMI instruction set includes four extra instructions that perform 32-bit by 32-bit multiplication with 64-bit result, and 32-bit by 32-bit multiplication-accumulation (MAC) with 64-bit result. These results are achieved in fewer cycles than required on a standard ARM7 core. EMBEDDEDICE (I) EmbeddedICE provides integrated on-chip support for the core. The EmbeddedICE module contains the breakpoint and watchpoint registers that allow code to be halted for debugging purposes. These registers are controlled through the JTAG test port. Rev. A | Page 31 of 92 ADuC7019/20/21/22/24/25/26/27 R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 (PC) SPSR_IRQ SPSR_UND R8_FIQ R9_FIQ R10_FIQ R11_FIQ R12_FIQ R13_FIQ R14_FIQ R13_SVC R14_SVC R13_ABT R14_ABT R13_IRQ R14_IRQ R13_UND R14_UND USABLE IN USER MODE SYSTEM MODES ONLY INTERRUPT LATENCY The worst case latency for a fast interrupt request (FIQ) consists of the following: • • The longest time the request can take to pass through the synchronizer The time for the longest instruction to complete (the longest instruction is an LDM) that loads all the registers including the PC The time for the data abort entry The time for FIQ entry • SPSR_ABT • 04955-007 CPSR SPSR_FIQ FIQ MODE SPSR_SVC SVC MODE USER MODE ABORT MODE IRQ MODE UNDEFINED MODE Figure 32. Register Organization More information relative to the programmer’s model and the ARM7TDMI core architecture can be found in the following documents from ARM: • • DDI0029G, ARM7TDMI Technical Reference Manual DDI0100E, ARM Architecture Reference Manual At the end of this time, the ARM7TDMI executes the instruction at 0x1C (FIQ interrupt vector address). The maximum total time is 50 processor cycles, which is just under 1.2 μs in a system using a continuous 41.78 MHz processor clock. The maximum interrupt request (IRQ) latency calculation is similar, but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time. This time can be reduced to 42 cycles if the LDM command is not used. Some compilers have an option to compile without using this command. Another option is to run the part in thumb mode, where the time is reduced to 22 cycles. The minimum latency for FIQ or IRQ interrupts is a total of five cycles, which consist of the shortest time the request can take through the synchronizer, plus the time to enter the exception mode. Note that the ARM7TDMI always runs in ARM (32-bit) mode when in privileged modes, for example, when executing interrupt service routines. Rev. A | Page 32 of 92 ADuC7019/20/21/22/24/25/26/27 MEMORY ORGANIZATION The ADuC7019/7020/7021/7022/7024/7025/7026/7027 incorporate two separate blocks of memory: 8 kB of SRAM and 64 kB of on-chip Flash/EE memory. Sixty-two kilobytes of onchip Flash/EE memory is available to the user, and the remaining 2 kB are reserved for the factory configured boot page. These two blocks are mapped as shown in Figure 33. 0xFFFFFFFF MMRs 0xFFFF0000 RESERVED 0x40000FFFF EXTERNAL MEMORY REGION 3 0x40000000 RESERVED 0x30000FFFF EXTERNAL MEMORY REGION 2 0x30000000 RESERVED 0x20000FFFF EXTERNAL MEMORY REGION 1 0x20000000 RESERVED 0x10000FFFF EXTERNAL MEMORY REGION 0 0x10000000 RESERVED 0x0008FFFF FLASH/EE 0x00080000 RESERVED 04955-008 FLASH/EE MEMORY The total 64 kB of Flash/EE memory is organized as 32 k × 16 bits (31 k × 16 bits is user space and 1 k × 16 bits is reserved for the on-chip kernel). The page size of this Flash/EE memory is 512 bytes. Sixty-two kilobytes of Flash/EE memory are available to the user as code and nonvolatile data memory. There is no distinction between data and program as ARM code shares the same space. The real width of the Flash/EE memory is 16 bits, which means that in ARM mode (32-bit instruction), two accesses to the Flash/EE are necessary for each instruction fetch. It is therefore recommended to use thumb mode when executing from Flash/EE memory for optimum access speed. The maximum access speed for the Flash/EE memory is 41.78 MHz in thumb mode and 20.89 MHz in full ARM mode. More details about Flash/EE access time are outlined later in the Execution Time from SRAM and Flash/EE section of this data sheet. SRAM Eight kilobytes of SRAM are available to the user, organized as 2 k × 32 bits, that is, two words. ARM code can run directly from SRAM at 41.78 MHz, given that the SRAM array is configured as a 32-bit wide memory array. More details about SRAM access time are outlined later in the Execution Time from SRAM and Flash/EE section of this datasheet. 0x00011FFF SRAM 0x00010000 0x0000FFFF REMAPPABLE MEMORY SPACE (FLASH/EE OR SRAM) 0x00000000 Figure 33. Physical Memory Map Note that by default, after a reset, the Flash/EE memory is mirrored at address 0×00000000. It is possible to remap the SRAM at address 0×00000000 by clearing Bit 0 of the REMAP MMR. This remap function is described in more detail in the Flash/EE Memory section. MEMORY MAPPED REGISTERS The memory mapped register (MMR) space is mapped into the upper two pages of the memory array, and accessed by indirect addressing through the ARM7 banked registers. The MMR space provides an interface between the CPU and all on-chip peripherals. All registers, except the core registers, reside in the MMR area. All shaded locations shown in Figure 35 are unoccupied or reserved locations, and should not be accessed by user software. Table 13 shows the full MMR memory map. The access time for reading from or writing to an MMR depends on the advanced microcontroller bus architecture (AMBA) bus used to access the peripheral. The processor has two AMBA busses: advanced high performance bus (AHB) used for system modules, and advanced peripheral bus (APB) used for lower performance peripheral. Access to the AHB is one cycle, and access to the APB is two cycles. All peripherals on the ADuC7019/7020/7021/7022/7024/7025/7026/7027 are on the APB except the Flash/EE memory, the GPIOs, and the PWM. MEMORY ACCESS The ARM7 core sees memory as a linear array of 2 byte location where the different blocks of memory are mapped as outlined in Figure 33. The ADuC7019/7020/7021/7022/7024/7025/7026/7027 memory organizations are configured in little endian format, which means that the least significant byte is located in the lowest byte address, and the most significant byte is in the highest byte address. BIT 31 BYTE 3 . . . B 7 3 BYTE 2 . . . A 6 2 32 BITS BYTE 1 . . . 9 5 1 BIT 0 BYTE 0 . . . 8 4 0 0x00000004 0x00000000 04955-009 32 0xFFFFFFFF Figure 34. Little Endian Format Rev. A | Page 33 of 92 ADuC7019/20/21/22/24/25/26/27 0xFFFFFFFF 0xFFFFFC3C Table 13. Complete MMR List PWM 0xFFFFFC00 0xFFFFF820 0xFFFFF800 0xFFFFF46C FLASH CONTROL INTERFACE GPIO 0xFFFFF400 0xFFFF0B54 PLA 0xFFFF0B00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0948 Address Name Byte IRQ address base = 0xFFFF0000 0x0000 IRQSTA 4 0x0004 IRQSIG1 4 0x0008 IRQEN 4 0x000C IRQCLR 4 0x0010 SWICFG 4 0x0100 FIQSTA 4 0x0104 FIQSIG1 4 0x0108 FIQEN 4 0x010C FIQCLR 4 1 Access Type R R R/W W W R R R/W W Default Value 0x00000000 0x00XXX000 0x00000000 0x00000000 0x00000000 0x00000000 0x00XXX000 0x00000000 0x00000000 Page 74 74 74 74 75 74 75 75 75 Depends on the level on the external interrupt pins (P0.4, P0.5, P1.4, and P1.5). I2C1 0xFFFF0900 0xFFFF0848 I2C0 0xFFFF0800 0xFFFF0730 UART 0xFFFF0700 0xFFFF0620 System control address base = 0xFFFF0200 0x0220 REMAP1 1 R/W 0x00 0x0230 RSTSTA 1 R/W 0x01 0x0234 RSTCLR 1 W 0x00 1 47 47 47 Depends on model. DAC 0xFFFF0600 0xFFFF0538 ADC 0xFFFF0500 0xFFFF0490 0xFFFF048C 0xFFFF0448 0xFFFF0440 0xFFFF0420 0xFFFF0404 0xFFFF0370 0xFFFF0360 0xFFFF0350 0xFFFF0340 0xFFFF0334 0xFFFF0320 0xFFFF0310 BAND GAP REFERENCE POWER SUPPLY MONITOR PLL AND OSCILLATOR CONTROL WATCHDOG TIMER WAKE UP TIMER GENERAL PURPOSE TIMER Timer address base = 0xFFFF0300 0x0300 T0LD 2 R/W 0x0304 T0VAL 2 R 0x0308 T0CON 2 R/W 0x030C T0CLRI 1 W 0x0320 T1LD 4 R/W 0x0324 T1VAL 4 R 0x0328 T1CON 2 R/W 0x032C T1CLRI 1 W 0x0330 T1CAP 4 R/W 0x0340 T2LD 4 R/W 0x0344 T2VAL 4 R 0x0348 T2CON 2 R/W 0x034C T2CLRI 1 W 0x0360 T3LD 2 R/W 0x0364 T3VAL 2 R 0x0368 T3CON 2 R/W 0x036C T3CLRI 1 W PLL base address = 0xFFFF0400 0x0404 POWKEY1 2 0x0408 POWCON 2 0x040C POWKEY2 2 0x0410 PLLKEY1 2 0x0414 PLLCON 1 0x0418 PLLKEY2 2 0x0000 0xFFFF 0x0000 0xFF 0x00000000 0xFFFFFFFF 0x0000 0xFF 0x00000000 0x00000000 0xFFFFFFFF 0x0000 0xFF 0x0000 0xFFFF 0x0000 0x00 76 76 76 76 76 76 76 77 77 77 77 78 78 78 78 78 79 TIMER 0 0xFFFF0300 0xFFFF0238 0xFFFF0220 0xFFFF0110 0xFFFF0000 REMAP AND SYSTEM CONTROL 04955-010 INTERRUPT CONTROLLER W R/W W W R/W W 0x0000 0x0003 0x0000 0x0000 0x21 0x0000 52 52 52 52 52 52 Figure 35. Memory Mapped Registers PSM address base = 0xFFFF0440 0x0440 PSMCON 2 R/W 0x0444 CMPCON 2 R/W Reference address base = 0xFFFF0480 0x048C REFCON 1 R/W Rev. A | Page 34 of 92 0x0008 0x0000 49 50 0x00 42 ADuC7019/20/21/22/24/25/26/27 Access Address Name Byte Type ADC address base = 0xFFFF0500 0x0500 ADCCON 2 R/W 0x0504 ADCCP 1 R/W 0x0508 ADCCN 1 R/W 0x050C ADCSTA 1 R 0x0510 ADCDAT 4 R 0x0514 ADCRST 1 R/W 0x0530 ADCGN 2 R/W 0x0534 ADCOF 2 R/W DAC address base = 0xFFFF0600 0x0600 DAC0CON 1 R/W 0x0604 DAC0DAT 4 R/W 0x0608 DAC1CON 1 R/W 0x060C DAC1DAT 4 R/W 0x0610 DAC2CON 1 R/W 0x0614 DAC2DAT 4 R/W 0x0618 DAC3CON 1 R/W 0x061C DAC3DAT 4 R/W UART base address = 0xFFFF0700 0x0700 COMTX 1 R/W COMRX 1 R COMDIV0 1 R/W 0x0704 COMIEN0 1 R/W COMDIV1 1 R/W 0x0708 COMIID0 1 R 0x070C COMCON0 1 R/W 0x0710 COMCON1 1 R/W 0x0714 COMSTA0 1 R 0x0718 COMSTA1 1 R 0x071C COMSCR 1 R/W 0x0720 COMIEN1 1 R/W 0x0724 COMIID1 1 R 0x0728 COMADR 1 R/W 0x072C COMDIV2 2 R/W Default Value 0x0600 0x00 0x01 0x00 0x00000000 0x00 0x0200 0x0200 Page 39 39 40 40 40 40 40 40 Access Address Name Byte Type I2C0 base address = 0xFFFF0800 0x0800 I2C0MSTA 1 R 0x0804 I2C0SSTA 1 R 0x0808 I2C0SRX 1 R 0x080C I2C0STX 1 W 0x0810 I2C0MRX 1 R 0x0814 I2C0MTX 1 W 0x0818 I2C0CNT 1 R/W 0x081C I2C0ADR 1 R/W 0x0824 I2C0BYTE 1 R/W 0x0828 I2C0ALT 1 R/W 0x082C I2C0CFG 1 R/W 0x0830 I2C0DIV 2 R/W 0x0838 I2C0ID0 1 R/W 0x083C I2C0ID1 1 R/W 0x0840 I2C0ID2 1 R/W 0x0844 I2C0ID3 1 R/W 0x0848 I2C0CCNT 1 R/W 0x084C I2C0FSTA 2 R I2C1 base address = 0xFFFF0900 0x0900 I2C1MSTA 1 R 0x0904 I2C1SSTA 1 R 0x0908 I2C1SRX 1 R 0x090C I2C1STX 1 W 0x0910 I2C1MRX 1 R 0x0914 I2C1MTX 1 W 0x0918 I2C1CNT 1 R/W 0x091C I2C1ADR 1 R/W 0x0924 I2C1BYTE 1 R/W 0x0928 I2C1ALT 1 R/W 0x092C I2C1CFG 1 R/W 0x0930 I2C1DIV 2 R/W 0x0938 I2C1ID0 1 R/W 0x093C I2C1ID1 1 R/W 0x0940 I2C1ID2 1 R/W 0x0944 I2C1ID3 1 R/W 0x0948 I2C1CCNT 1 R/W 0x094C I2C1FSTA 2 R SPI base address = 0xFFFF0A00 0x0A00 SPISTA 1 0x0A04 SPIRX 1 0x0A08 SPITX 1 0x0A0C SPIDIV 1 0x0A10 SPICON 2 Default Value 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1F1F 0x00 0x00 0x00 0x00 0x01 0x0000 Page 68 68 69 69 69 69 69 69 69 69 70 70 70 70 70 70 70 71 0x00 0x00000000 0x00 0x00000000 0x00 0x00000000 0x00 0x00000000 48 48 48 48 48 48 48 48 0x00 0x00 0x00 0x00 0x00 0x01 0x00 0x00 0x60 0x00 0x00 0x04 0x01 0xAA 0x0000 63 63 63 63 63 63 63 64 64 64 64 65 65 65 64 0x00 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x1F1F 0x00 0x00 0x00 0x00 0x01 0x0000 68 68 69 69 69 69 69 69 69 69 69 70 70 70 70 70 70 70 R R W R/W R/W 0x00 0x00 0x00 0x1B 0x0000 66 66 66 66 66 Rev. A | Page 35 of 92 ADuC7019/20/21/22/24/25/26/27 Address Name Byte PLA base address = 0xFFFF0B00 0x0B00 PLAELM0 2 0x0B04 PLAELM1 2 0x0B08 PLAELM2 2 0x0B0C PLAELM3 2 0x0B10 PLAELM4 2 0x0B14 PLAELM5 2 0x0B18 PLAELM6 2 0x0B1C PLAELM7 2 0x0B20 PLAELM8 2 0x0B24 PLAELM9 2 0x0B28 PLAELM10 2 0x0B2C PLAELM11 2 0x0B30 PLAELM12 2 0x0B34 PLAELM13 2 0x0B38 PLAELM14 2 0x0B3C PLAELM15 2 0x0B40 PLACLK 1 0x0B44 PLAIRQ 4 0x0B48 PLAADC 4 0x0B4C PLADIN 4 0x0B50 PLADOUT 4 0x0B54 PLALCK 1 Access Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R W Default Value 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x00 0x00000000 0x00000000 0x00000000 0x00000000 0x00 Page 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 71 72 73 73 73 73 73 Access Address Name Byte Type GPIO base address = 0xFFFFF400 0xF400 GP0CON 4 R/W 0xF404 GP1CON 4 R/W 0xF408 GP2CON 4 R/W 0xF40C GP3CON 4 R/W 0xF410 GP4CON 4 R/W 0xF420 GP0DAT 4 R/W 0xF424 GP0SET 4 W 0xF428 GP0CLR 4 W 0xF42C GP0PAR 4 W 0xF430 GP1DAT 4 R/W 0xF434 GP1SET 4 W 0xF438 GP1CLR 4 W 0xF43C GP1PAR 4 W 0xF440 GP2DAT 4 R/W 0xF444 GP2SET 4 W 0xF448 GP2CLR 4 W 0xF450 GP3DAT 4 R/W 0xF454 GP3SET 4 W 0xF458 GP3CLR 4 W 0xF45C GP3PAR 4 W 0xF460 GP4DAT 4 R/W 0xF464 GP4SET 4 W 0xF468 GP4CLR 4 W Flash/EE base address = 0xFFFFF800 0xF800 FEESTA 1 R 0xF804 FEEMOD 2 R/W 0xF808 FEECON 1 R/W 0xF80C FEEDAT 2 R/W 0xF810 FEEADR 2 R/W 0xF818 FEESIGN 3 R 0xF81C FEEPRO 4 R/W 0xF820 FEEHIDE 4 R/W PWM base address = 0xFFFFFC00 0xFC00 PWMCON 2 R/W 0xFC04 PWMSTA 2 R/W 0xFC08 PWMDAT0 2 R/W 0xFC0C PWMDAT1 2 R/W 0xFC10 PWMCFG 2 R/W 0xFC14 PWMCH0 2 R/W 0xFC18 PWMCH1 2 R/W 0xFC1C PWMCH2 2 R/W 0xFC20 PWMEN 2 R/W 0xFC24 PWMDAT2 2 R/W Default Value 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x000000XX 0x000000XX 0x000000XX 0x20000000 0x000000XX 0x000000XX 0x000000XX 0x00000000 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x000000XX 0x00222222 0x000000XX 0x000000XX 0x000000XX Page 60 60 60 60 60 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 61 External memory base address = 0xFFFFF000 0xF000 XMCFG 1 R/W 0x00 0xF010 XM0CON 1 R/W 0x00 0xF014 XM1CON 1 R/W 0x00 0xF018 XM2CON 1 R/W 0x00 0xF01C XM3CON 1 R/W 0x00 0xF020 XM0PAR 2 R/W 0x70FF 0xF024 XM1PAR 2 R/W 0x70FF 0xF028 XM2PAR 2 R/W 0x70FF 0xF02C XM3PAR 2 R/W 0x70FF 80 80 80 80 80 80 80 80 80 0x20 0x0000 0x07 0xXXXX 0x0000 0xFFFFFF 0x00000000 0xFFFFFFFF 45 45 45 45 45 45 45 45 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 59 59 60 60 59 60 60 60 59 60 Rev. A | Page 36 of 92 ADuC7019/20/21/22/24/25/26/27 ADC CIRCUIT OVERVIEW The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 2.7 V to 3.6 V supplies and is capable of providing a throughput of up to 1 MSPS when the clock source is 41.78 MHz. This block provides the user with a multichannel multiplexer, differential track-and-hold, onchip reference, and ADC. The ADC consists of a 12-bit successive approximation converter based around two capacitor DACs. Depending on the input signal configuration, the ADC can operate in one of three different modes: • • • Fully differential mode, for small and balanced signals Single-ended mode, for any single-ended signals Pseudo differential mode, for any single-ended signals, taking advantage of the common-mode rejection offered by the pseudo differential input TRANSFER FUNCTION Pseudo Differential and Single-Ended Modes In pseudo differential or single-ended modes, the input range is 0 V to VREF. The output coding is straight binary in pseudo differential and single-ended modes with 1 LSB = FS/4096, or 2.5 V/4096 = 0.61 mV, or 610 μV when VREF = 2.5 V The ideal code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … , FS − 3/2 LSB). The ideal input/output transfer characteristic is shown in Figure 37. 1111 1111 1111 1111 1111 1110 1111 1111 1101 OUTPUT CODE 1111 1111 1100 1LSB = FS 4096 The converter accepts an analog input range of 0 to VREF when operating in single-ended mode or pseudo differential mode. In fully differential mode, the input signal must be balanced around a common-mode voltage VCM, in the range 0 V to AVDD, and with a maximum amplitude of 2 VREF (see Figure 36). AVDD VCM VCM 2VREF 2VREF 0000 0000 0011 0000 0000 0010 0000 0000 0001 0V 1LSB VOLTAGE INPUT +FS – 1LSB 04955-012 0000 0000 0000 Figure 37. ADC Transfer Function in Pseudo Differential Mode or Single-Ended Mode 04955-011 VCM 0 2VREF Fully Differential Mode The amplitude of the differential signal is the difference between the signals applied to the VIN+ and VIN– pins (that is, VIN+ – VIN–). The maximum amplitude of the differential signal is therefore –VREF to +VREF p-p (that is, 2 × VREF). This is regardless of the common mode (CM). The common mode is the average of the two signals, for example, (VIN+ + VIN–)/2, and is therefore the voltage that the two inputs are centered on. This results in the span of each input being CM ± VREF/2. This voltage has to be set up externally and its range varies with VREF (see the Driving the Analog Inputs section). The output coding is twos complement in fully differential mode with 1 LSB = 2 VREF/4096 or 2 × 2.5 V/4096 = 1.22 mV when VREF = 2.5 V. The designed code transitions occur midway between successive integer LSB values (that is, 1/2 LSB, 3/2 LSB, 5/2 LSB, … , FS – 3/2 LSB). The ideal input/output transfer characteristic is shown in Figure 38. Figure 36. Examples of Balanced Signals in Fully Differential Mode A high precision, low drift, and factory calibrated 2.5 V reference is provided on-chip. An external reference can also be connected as described later in the Band Gap Reference section. Single or continuous conversion modes can be initiated in the software. An external CONVSTART pin, an output generated from the on-chip PLA, or a Timer0 or Timer1 overflow can also be used to generate a repetitive trigger for ADC conversions. A voltage output from an on-chip band gap reference proportional to absolute temperature can also be routed through the front-end ADC multiplexer, effectively an additional ADC channel input. This facilitates an internal temperature sensor channel, which measures die temperature to an accuracy of ±3°C. Rev. A | Page 37 of 92 ADuC7019/20/21/22/24/25/26/27 SIGN BIT 0 1111 1111 1110 0 1111 1111 1100 0 1111 1111 1010 1LSB = ACQ BIT TRIAL WRITE 2 × VREF 4096 ADC CLOCK OUTPUT CODE 0 0000 0000 0010 0 0000 0000 0000 1 1111 1111 1110 CONVSTART ADCBUSY 1 0000 0000 0100 1 0000 0000 0010 04955-013 ADCDAT DATA Figure 38. ADC Transfer Function in Differential Mode ADC INTERRUPT TYPICAL OPERATION Once configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register. The top 4 bits are the sign bits. The 12-bit result is placed from Bit 16 to Bit 27 as shown in Figure 39. Again, it should be noted that in fully differential mode, the result is represented in twos complement format, and in pseudo differential and singleended modes, the result is represented in straight binary format. 31 27 16 15 0 04955-014 Figure 40. ADC Timing ADuC7019 The ADuC7019 is identical to the ADuC7020 except for one buffered ADC channel, ADC3, and it has only three DACs. The output buffer of the fourth DAC is internally connected to the ADC3 channel as shown in Figure 41. ADuC7019 MUX ADC3 DAC3 ADC15 04955-016 1MSPS 12-BIT ADC 12-BIT DAC SIGN BITS 12-BIT ADC RESULT Figure 39. ADC Result Format Figure 41. ADC3 Buffered Input The same format is used in DAC×DAT, simplifying the software. Current Consumption The ADC in standby mode, that is, powered up but not converting, typically consumes 640 μA. The internal reference adds 140 μA. During conversion, the extra current is 0.3 μA multiplied by the sampling frequency (in kHz). Figure 31 shows the current consumption versus the sampling frequency of the ADC. Note that the DAC3 output pin must be connected to a 10 nF capacitor to AGND. This channel should be used to measure dc voltages only. ADC calibration might be necessary on this channel. MMRS INTERFACE The ADC is controlled and configured via the eight MMRs described in this section. Timing Figure 40 gives details of the ADC timing. Users have control on the ADC clock speed and on the number of acquisition clocks in the ADCCON MMR. By default, the acquisition time is eight clocks and the clock divider is two. The number of extra clocks (such as bit trial or write) is set to 19, which gives a sampling rate of 774 kSPS. For conversion on temperature sensor, the ADC acquisition time is automatically set to 16 clocks and the ADC clock divider is set to 32. ADCCON Register Name ADCCON Address 0xFFFF0500 Default Value 0x0600 Access R/W ADCCON is an ADC control register that allows the programmer to enable the ADC peripheral, select the mode of operation of the ADC (either in single-ended mode, pseudo differential mode, or fully differential mode), and select the conversion type. This MMR is described in Table 14. Rev. A | Page 38 of 92 04955-015 1 0000 0000 0000 0LSB +VREF – 1LSB –VREF + 1LSB VOLTAGE INPUT (VIN+ – VIN–) ADCSTA = 0 ADCSTA = 1 ADuC7019/20/21/22/24/25/26/27 Table 14. ADCCON MMR Bit Designations Bit 15:13 12:10 Value Description Reserved. ADC clock speed. fADC/1. This divider is provided to obtain 1 MSPS ADC with an external clock