Triple-Channel Digital Isolators
ADuM1310/ADuM1311
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
APPLICATIONS
ADuM1310
16 VDD2
VDD1
1
GND1
2
VIA
3
ENCODE
DECODE
14 VOA
VIB
4
ENCODE
DECODE
13 VOB
VIC
5
ENCODE
DECODE
12 VOC
NC
6
11 NC
DISABLE
7
10 CTRL2
GND1
8
9
04904-001
15 GND2
GND2
Figure 1. ADuM1310
ADuM1311
16 VDD2
VDD1
1
GND1
2
VIA
3
ENCODE
DECODE
14 VOA
VIB
4
ENCODE
DECODE
13 VOB
VOC
5
DECODE
ENCODE
12 VIC
NC
6
11 NC
CTRL1
7
10 CTRL2
GND1
8
9
General-purpose multichannel isolation
SPI interface/data converter isolation
RS-232/RS-422/RS-485 transceiver
Industrial field bus isolation
15 GND2
GND2
04904-002
Low power operation
5 V operation
1.7 mA per channel maximum at 0 Mbps to 2 Mbps
4.0 mA per channel maximum at 2 Mbps to 10 Mbps
3 V operation
1.0 mA per channel maximum at 0 Mbps to 2 Mbps
2.1 mA per channel maximum at 2 Mbps to 10 Mbps
Bidirectional communication
3 V/5 V level translation
Schmitt trigger inputs
High temperature operation: 105°C
Up to 10 Mbps data rate (NRZ)
Programmable default output state
High common-mode transient immunity: >25 kV/μs
16-lead, RoHS-compliant, SOIC wide body package
8.1 mm external creepage
Safety and regulatory approvals
UL recognition: 3750 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
VIORM = 560 V peak working voltage
Figure 2. ADuM1311
GENERAL DESCRIPTION
The ADuM1310/ADuM13111 are 3-channel digital isolators
based on Analog Devices, Inc., iCoupler® technology. Combining high speed CMOS and monolithic air core transformer
technology, these isolation components provide outstanding
performance characteristics superior to alternatives such as
optocoupler devices.
By avoiding the use of LEDs and photodiodes, iCoupler devices
remove the design difficulties commonly associated with optocouplers. The typical optocoupler concerns regarding uncertain
current transfer ratios, maximum operating temperature, and
lifetime effects are eliminated with the simple iCoupler digital
interfaces and stable performance characteristics. The need for
external drivers and other discrete components is eliminated
with these iCoupler products. Furthermore, iCoupler devices
consume one-tenth to one-sixth the power of optocouplers at
1
comparable signal data rates. The iCoupler also offers higher
channel densities and more options for channel directionality.
The ADuM1310/ADuM1311 isolators provide three
independent isolation channels in a variety of channel
configurations and data rates up to 10 Mbps (see the Ordering
Guide). All models operate with the supply voltage on either
side ranging from 2.7 V to 5.5 V, providing compatibility with
lower voltage systems as well as enabling voltage translation
functionality across the isolation barrier. All products allow the
user to predetermine the default output state in the absence of input
VDD1 power with a simple control pin. Unlike other optocoupler
alternatives, the ADuM1310/ADuM1311 isolators have a patented
refresh feature that ensures dc correctness in the absence of input
logic transitions and during power-up/ power-down conditions.
Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents pending.
Rev. K
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Technical Support
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ADuM1310/ADuM1311
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Recommended Operating Conditions .................................... 11
Applications ....................................................................................... 1
Absolute Maximum Ratings ......................................................... 12
Functional Block Diagrams ............................................................. 1
ESD Caution................................................................................ 12
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ......................... 13
Revision History ............................................................................... 2
Typical Performance Characteristics ........................................... 16
Specifications..................................................................................... 3
Applications Information .............................................................. 18
Electrical Characteristics—5 V Operation................................ 3
PC Board Layout ........................................................................ 18
Electrical Characteristics—3 V Operation................................ 5
Propagation Delay-Related Parameters ................................... 18
Electrical Characteristics—Mixed 5 V/3 V or 3 V/5 V
Operation....................................................................................... 7
DC Correctness and Magnetic Field Immunity ..................... 18
Package Characteristics ............................................................. 10
Insulation Lifetime ..................................................................... 20
Regulatory Information ............................................................. 10
Outline Dimensions ....................................................................... 21
Insulation and Safety-Related Specifications .......................... 10
Ordering Guide .......................................................................... 21
Power Consumption .................................................................. 19
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
Insulation Characteristics.......................................................... 11
REVISION HISTORY
6/15—Rev. J to Rev. K
1/07—Rev. E to Rev. F
Changes to Table 5 and Table 6 ..................................................... 10
Added ADuM1311 ............................................................. Universal
Changes to Typical Performance Characteristics Section ........ 16
Changes to Ordering Guide .......................................................... 20
9/14—Rev. I to Rev. J
Changes to Features Section............................................................ 1
Changes to Table 5 and Table 6 ..................................................... 10
4/14—Rev. H to Rev. I
Change to Table 5 ........................................................................... 10
3/12—Rev. G to Rev. H
Created Hyperlink for Safety and Regulatory Approvals
Entry in Features Section................................................................. 1
Change to PC Board Layout Section............................................ 18
Updated Outline Dimensions ....................................................... 21
10/06—Rev. D to Rev. E
Removed ADuM1410 ........................................................ Universal
Updated Format .................................................................. Universal
Change to Figure 3 ......................................................................... 10
Changes to Table 10 ....................................................................... 10
Changes to Application Information Section ............................. 12
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
3/06—Rev. C to Rev. D
Added Note 1; Changes to Figure 2 ................................................1
Changes to Absolute Maximum Ratings ..................................... 11
6/07—Rev. F to Rev. G
Updated VDE Certification Throughout ...................................... 1
Changes to Features and Applications ........................................... 1
Changes to DC Specifications in Table 1 ....................................... 3
Changes to DC Specifications in Table 2 ....................................... 5
Changes to DC Specifications in Table 3 ....................................... 7
Changes to Regulatory Information Section .............................. 10
Added Table 10 ............................................................................... 12
Added Insulation Lifetime Section .............................................. 19
11/05—Revision C: Initial Version
Rev. K | Page 2 of 24
Data Sheet
ADuM1310/ADuM1311
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 5 V. All voltages are relative to their respective grounds.
Table 1.
Parameter
DC SPECIFICATIONS
ADuM1310, Total Supply Current,
Three Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1311, Total Supply Current,
Three Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
For All Models
Input Currents
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
IDD1 (Q)
2.4
3.2
mA
IDD2 (Q)
1.2
1.6
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
IDD1 (10)
IDD2 (10)
6.6
2.1
9.0
3.0
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
IDD1 (Q)
2.2
2.8
mA
IDD2 (Q)
1.8
2.4
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
IDD1 (10)
IDD2 (10)
4.5
3.5
5.7
4.3
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
+0.01
+10
µA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2,
0 V ≤ VDISABLE ≤ VDD1
IIA, IIB, IIC, ICTRL1,
ICTRL2, IDISABLE
−10
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
VIH
VIL
VOAH, VOBH, VOCH
2.0
Logic Low Output Voltages
VOAL, VOBL, VOCL
SWITCHING SPECIFICATIONS
ADuM131xARWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Propagation Delay Skew5
Channel-to-Channel Matching6
ADuM131xBRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
0.8
(VDD1 or VDD2) − 0.1
(VDD1 or VDD2) − 0.4
5.0
4.8
0.0
0.2
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD
1000
1
20
100
40
50
50
PW
tPHL, tPLH
PWD
0.1
0.4
100
10
20
30
50
5
5
tPSK
30
Rev. K | Page 3 of 24
V
V
V
V
V
V
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
ns
Mbps
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ns
Mbps
ns
ns
ps/°C
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
ADuM1310/ADuM1311
Parameter
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
For All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output7
Common-Mode Transient Immunity
at Logic Low Output7
Refresh Rate
Input Enable Time8
Input Disable Time8
Input Supply Current per Channel,
Quiescent9
Output Supply Current per Channel,
Quiescent9
Input Dynamic Supply Current
per Channel10
Output Dynamic Supply Current per
Channel10
Data Sheet
Symbol
tPSKCD
Min
Typ
tPSKOD
Max
5
Unit
ns
Test Conditions/Comments
CL = 15 pF, CMOS signal levels
6
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
tR/tF
|CMH|
25
2.5
35
ns
kV/µs
|CML|
25
35
kV/µs
fr
tENABLE
tDISABLE
IDDI (Q)
1.2
0.50
2.0
5.0
0.73
Mbps
µs
µs
mA
IDDO (Q)
0.38
0.53
mA
IDDI (D)
0.12
IDDO (D)
0.04
VIA, VIB, VIC = 0 V or VDD1
VIA, VIB, VIC = 0 V or VDD1
mA/
Mbps
mA/
Mbps
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 13).
9
IDDx (Q) is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
the same orientation as Channel A must be included to account for the total current consumed.
10
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1
Rev. K | Page 4 of 24
Data Sheet
ADuM1310/ADuM1311
ELECTRICAL CHARACTERISTICS—3 V OPERATION
2.7 V ≤ VDD1 ≤ 3.6 V, 2.7 V ≤ VDD2 ≤ 3.6 V; all minimum/maximum specifications apply over the entire recommended operation range,
unless otherwise noted; all typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.0 V. All voltages are relative to their respective ground.
Table 2.
Parameter
DC SPECIFICATIONS
ADuM1310, Total Supply Current,
Three Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
ADuM1311, Total Supply Current,
Three Channels1
DC to 2 Mbps
VDD1 Supply Current
VDD2 Supply Current
10 Mbps (BRWZ Grade Only)
VDD1 Supply Current
VDD2 Supply Current
For All Models
Input Currents
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
IDD1 (Q)
IDD2 (Q)
1.2
0.8
1.6
1.0
mA
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
IDD1 (10)
IDD2 (10)
3.4
1.1
4.9
1.3
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
IDD1 (Q)
IDD2 (Q)
1.0
0.9
1.6
1.4
mA
DC to 1 MHz logic signal frequency
DC to 1 MHz logic signal frequency
IDD1 (10)
IDD2 (10)
2.5
1.9
3.5
2.6
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
+0.01
+10
µA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2,
0 V ≤ VDISABLE ≤ VDD1
IIA, IIB, IIC, ICTRL1,
ICTRL2, IDISABLE
−10
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
VIH
VIL
VOAH, VOBH, VOCH
1.6
Logic Low Output Voltages
VOAL, VOBL, VOCL
SWITCHING SPECIFICATIONS
ADuM131xARWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Propagation Delay Skew5
Channel-to-Channel Matching6
ADuM131xBRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
0.4
(VDD1 or VDD2) − 0.1 3.0
(VDD1 or VDD2) − 0.4 2.8
0.0
0.2
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD
0.1
0.4
1000
1
20
100
40
50
50
PW
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
ns
Mbps
ns
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
30
5
ns
Mbps
ns
ns
ps/°C
ns
ns
tPSKOD
6
ns
tPHL, tPLH
PWD
100
V
V
V
V
V
V
10
20
30
50
5
5
Rev. K | Page 5 of 24
ADuM1310/ADuM1311
Parameter
For All Models
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output7
Common-Mode Transient Immunity
at Logic Low Output7
Refresh Rate
Input Enable Time8
Input Disable Time8
Input Supply Current per Channel,
Quiescent9
Output Supply Current per Channel,
Quiescent9
Input Dynamic Supply Current
per Channel10
Output Dynamic Supply Current
per Channel10
Data Sheet
Symbol
Min
Typ
tR/tF
|CMH|
25
|CML|
25
Max
Unit
Test Conditions/Comments
2.5
35
ns
kV/µs
35
kV/µs
CL = 15 pF, CMOS signal levels
VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
fr
tENABLE
tDISABLE
IDDI (Q)
1.1
2.0
5.0
0.25
0.38
Mbps
µs
µs
mA
IDDO (Q)
0.19
0.33
mA
IDDI (D)
0.07
IDDO (D)
0.02
VIA, VIB, VIC = 0 V or VDD1
VIA, VIB, VIC = 0 V or VDD1
mA/
Mbps
mA/
Mbps
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 13).
9
IDDx (Q) is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
the same orientation as Channel A must be included to account for the total current consumed.
10
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1
Rev. K | Page 6 of 24
Data Sheet
ADuM1310/ADuM1311
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3 V OR 3 V/5 V OPERATION
5 V/3 V operation: 4.5 V ≤ VDD1 ≤ 5.5 V, 2.7 V ≤ VDD2 ≤ 3.6 V; 3 V/5 V operation: 2.7 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V; all
minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted; all typical specifications
are at TA = 25°C; VDD1 = 3.0 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.0 V. All voltages are relative to their respective ground.
Table 3.
Parameter
DC SPECIFICATIONS
ADuM1310, Total Supply Current,
Three Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
Symbol
Min
Logic High Input Threshold
VDDX = 5 V Operation
VDDX = 3 V Operation
3.2
mA
1.2
1.6
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
0.8
1.0
mA
1.2
1.6
mA
6.5
3.4
8.2
4.9
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
1.1
1.9
1.3
2.2
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
2.2
2.8
mA
1.0
1.6
mA
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
0.9
1.4
mA
1.8
2.4
mA
4.5
2.5
5.7
3.5
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
1.9
3.5
2.6
4.3
mA
mA
5 MHz logic signal frequency
5 MHz logic signal frequency
+0.01
+10
µA
0 V ≤ VIA, VIB, VIC ≤ VDD1 or VDD2,
0 V ≤ VCTRL1, VCTRL2 ≤ VDD1 or VDD2,
0 V ≤ VDISABLE ≤ VDD1
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
IDD2 (10)
IDD1 (Q)
IDD2 (Q)
3 V/5 V Operation
10 Mbps (BRWZ Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
For All Models
Input Currents
2.4
IDD1 (10)
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
Test Conditions/Comments
IDD2 (Q)
3 V/5 V Operation
10 Mbps (BRWZ Grade Only)
VDD1 Supply Current
5 V/3 V Operation
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
3 V/5 V Operation
ADuM1311, Total Supply Current,
Three Channels1
DC to 2 Mbps
VDD1 Supply Current
5 V/3 V Operation
Max Unit
IDD1 (Q)
3 V/5 V Operation
VDD2 Supply Current
5 V/3 V Operation
Typ
DC to 1 MHz logic signal
frequency
DC to 1 MHz logic signal
frequency
IDD1 (10)
IDD2 (10)
IIA, IIB, IIC, ICTRL1, −10
ICTRL2, IDISABLE
VIH
2.0
1.6
V
V
Rev. K | Page 7 of 24
ADuM1310/ADuM1311
Parameter
Logic Low Input Threshold
VDDX = 5 V Operation
VDDX = 3 V Operation
Logic High Output Voltages
Logic Low Output Voltages
SWITCHING SPECIFICATIONS
ADuM131xARWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion |tPLH − tPHL|4
Propagation Delay Skew5
Channel-to-Channel Matching6
ADuM131xBRWZ
Minimum Pulse Width2
Maximum Data Rate3
Propagation Delay4
Pulse Width Distortion, |tPLH − tPHL|4
Change vs. Temperature
Propagation Delay Skew5
Channel-to-Channel Matching,
Codirectional Channels6
Channel-to-Channel Matching,
Opposing-Directional Channels6
For All Models
Output Rise/Fall Time (10% to 90%)
5 V/3 V Operation
3 V/5 V Operation
Common-Mode Transient
Immunity at Logic High Output7
Common-Mode Transient
Immunity at Logic Low Output7
Refresh Rate
5 V/3 V Operation
3 V/5 V Operation
Input Enable Time8
Input Disable Time8
Input Supply Current per Channel,
Quiescent9
VDDX = 5 V Operation
VDDX = 3 V Operation
Output Supply Current per
Channel, Quiescent9
VDDX = 5 V Operation
VDDX = 3 V Operation
Input Dynamic Supply Current per
Channel10
VDDX = 5 V Operation
VDDX = 3 V Operation
Data Sheet
Symbol
VIL
Min
Typ
Max Unit
0.8
0.4
VOAH, VOBH, VOCH (VDD1 or VDD2) − 0.1 (VDD1 or VDD2)
(VDD1 or VDD2) − 0.4 (VDD1 or VDD2) − 0.2
VOAL, VOBL, VOCL
0.0
0.1
0.2
0.4
PW
tPHL, tPLH
PWD
tPSK
tPSKCD/OD
1
25
PW
V
V
V
V
V
V
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
100
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
tPSK
tPSKCD
30
5
tPSKOD
6
ns
tPHL, tPLH
PWD
60
5
5
tR/tF
|CMH|
25
2.5
2.5
35
|CML|
25
35
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
1000 ns
Mbps
100 ns
40
ns
50
ns
50
ns
ns
Mbps
ns
ns
ps/°C
ns
ns
10
20
Test Conditions/Comments
CL = 15 pF, CMOS signal levels
ns
ns
kV/µs VIx = VDD1 or VDD2, VCM = 1000 V,
transient magnitude = 800 V
kV/µs VIx = 0 V, VCM = 1000 V,
transient magnitude = 800 V
fr
1.2
1.1
tENABLE
tDISABLE
2.0
5.0
Mbps
Mbps
µs
VIA, VIB, VIC, VID = 0 V or VDD1
µs
VIA, VIB, VIC, VID = 0 V or VDD1
IDDI (Q)
IDDI (Q)
0.50
0.25
0.73 mA
0.38 mA
IDDO (Q)
IDDO (Q)
IDDI (D)
0.38
0.19
0.53 mA
0.33 mA
0.12
0.07
Rev. K | Page 8 of 24
mA/
Mbps
mA/
Mbps
Data Sheet
Parameter
Output Dynamic Supply Current
per Channel10
VDDX = 5 V Operation
VDDX = 3 V Operation
ADuM1310/ADuM1311
Symbol
IDDI (D)
Min
Typ
0.04
0.02
Max Unit
Test Conditions/Comments
mA/
Mbps
mA/
Mbps
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total VDD1 and VDD2 supply currents as a function of data rate for ADuM1310/ADuM1311 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH propagation delay is
measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal.
5
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate
that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Input enable time is the duration from when VDISABLE is set low until the output states are guaranteed to match the input states in the absence of any input data logic
transitions. If an input data logic transition within a given channel does occur within this time interval, the output of that channel reaches the correct state within the
much shorter duration, as determined by the propagation delay specifications within this data sheet. Input disable time is the duration from when VDISABLE is set high
until the output states are guaranteed to reach their programmed output levels, as determined by the CTRL2 logic state (see Table 13).
9
IDDx (Q) is the quiescent current drawn from the corresponding supply by a single channel. To calculate the total quiescent current, an additional inaccessible channel in
the same orientation as Channel A must be included to account for the total current consumed.
10
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
1
Rev. K | Page 9 of 24
ADuM1310/ADuM1311
Data Sheet
PACKAGE CHARACTERISTICS
Table 4.
Parameter
Resistance (Input-to-Output)1
Capacitance (Input-to-Output)1
Input Capacitance2
IC Junction-to-Case Thermal Resistance
Side 1
Side 2
1
2
Symbol
RI-O
CI-O
CI
Min
θJCI
θJCO
Typ
1012
2.2
4.0
Max
33
28
Unit
Ω
pF
pF
Test Conditions/Comments
°C/W
°C/W
Thermocouple located at center of package underside
f = 1 MHz
The device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM1310/ADuM1311 have been approved by the organizations listed in Table 5. See Table 10 and the Insulation Lifetime section
for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 5.
UL
Recognized Under 1577
Component Recognition
Program1
Single Protection, 3750 V rms
Isolation Voltage
File E214100
1
2
CSA
Approved under CSA
Component Acceptance
Notice 5A
Basic insulation per CSA
60950-1-03 and IEC 60950-1,
800 V rms (1131 V peak)
maximum working voltage
Reinforced insulation per
CSA 60950-1-03 and IEC
60950-1, 400 V rms
(566 V peak) maximum
working voltage
File 205078
CQC
Approved under CQC11-4715432012
VDE
Certified according to DIN V VDE V
0884-10 (VDE V 0884-10): 2006-122
Basic insulation per GB4943.1-2011
Reinforced insulation, 560 V peak
Basic insulation, 415 V rms
(588 V peak) maximum working
voltage, tropical climate, altitude ≤
5000 m
File: CQC14001114897
File 2471900-4880-0001
In accordance with UL 1577, each ADuM1310/ADuM1311 is proof-tested by applying an insulation test voltage ≥4500 V rms for 1 sec (current leakage detection limit = 8.1 μA).
In accordance with DIN V VDE V 0884-10, each ADuM1310/ADuM1311 is proof-tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial
discharge detection limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 6.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L(I01)
Value
3750
7.7 min
Unit
V rms
mm
Minimum External Tracking (Creepage)
L(I02)
8.1 min
mm
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
0.017 min
>400
II
mm
V
Rev. K | Page 10 of 24
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Data Sheet
ADuM1310/ADuM1311
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 INSULATION CHARACTERISTICS
The ADuM1310/ADuM1311 isolators are suitable for reinforced electrical isolation within the safety limit data only. Maintenance of the
safety data is ensured by protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval for 560 V peak
working voltage.
Table 7.
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method B1
Input-to-Output Test Voltage, Method A
After Environmental Tests Subgroup 1
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Highest Allowable Overvoltage
Safety-Limiting Values
VIORM × 1.875 = VPR, 100% production test, tm = 1 sec,
partial discharge < 5 pC
VIORM × 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC
Symbol
Characteristic
Unit
VIORM
VPR
I to IV
I to III
I to II
40/105/21
2
560
1050
V peak
V peak
896
672
V peak
V peak
VTR
4000
V peak
TS
IS1
IS2
RS
150
265
335
>109
°C
mA
mA
Ω
VPR
VIORM × 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC
Transient overvoltage, tTR = 10 sec
Maximum value allowed in the event of a failure;
see Figure 3
VIO = 500 V
350
RECOMMENDED OPERATING CONDITIONS
300
Table 8.
Parameter
Operating Temperature
Supply Voltages1
Input Signal Rise and Fall Times
250
SIDE 2
200
Symbol
TA
VDD1, VDD2
Min
−40
2.7
Max
+105
5.5
1.0
Unit
°C
V
ms
150
1
SIDE 1
100
50
All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to external
magnetic fields.
04904-005
SAFETY-LIMITING CURRENT (mA)
Case Temperature
Side 1 Current
Side 2 Current
Insulation Resistance at TS
Test Conditions/Comments
0
0
50
150
100
CASE TEMPERATURE (°C)
200
Figure 3. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. K | Page 11 of 24
ADuM1310/ADuM1311
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is
a stress rating only; functional operation of the product at
these or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Table 9.
Parameter
Storage Temperature (TST) Range
Ambient Operating Temperature
(TA) Range
Supply Voltages (VDD1, VDD2)1
Input Voltage
(VIA, VIB, VIC, VDISABLE, VCTRL1, VCTRL2)1, 2
Output Voltage (VOA, VOB, VOC)1, 2
Average Output Current per Pin3
Side 1 (IO1)
Side 2 (IO2)
Common-Mode Transients 4
Rating
−65°C to +150°C
−40°C to +105°C
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
ESD CAUTION
−0.5 V to VDDO + 0.5 V
−18 mA to +18 mA
−22 mA to +22 mA
−100 kV/µs to +100 kV/µs
All voltages are relative to their respective ground.
VDDI and VDDO refer to the supply voltages on the input and output sides of
a given channel, respectively. See the PC Board Layout section.
3
See Figure 3 for maximum rated current values for various temperatures.
4
Refers to common-mode transients across the insulation barrier.
Common-mode transients exceeding the absolute maximum ratings may
cause latch-up or permanent damage.
1
2
Table 10. Maximum Continuous Working Voltage1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Max
565
Unit
V peak
Constraint
50-year minimum lifetime
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
1131
560
V peak
V peak
Maximum approved working voltage per IEC 60950-1
Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Rev. K | Page 12 of 24
Data Sheet
ADuM1310/ADuM1311
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1
*GND1 2
VIA 3
16 VDD2
15 GND2*
14 VOA
ADuM1310 13 VOB
TOP VIEW
VIC 5 (Not to Scale) 12 VOC
VIB 4
NC 6
DISABLE 7
*GND1 8
11 NC
10 CTRL2
9
GND2*
04904-003
NC = NO CONNECT
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
Figure 4. ADuM1310 Pin Configuration
Table 11. ADuM1310 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
VDD1
GND1
VIA
VIB
VIC
NC
DISABLE
8
9
10
GND1
GND2
CTRL2
11
12
13
14
15
16
NC
VOC
VOB
VOA
GND2
VDD2
Description
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Input C.
No Connection.
Input Disable. Disables the isolator inputs and halts the dc refresh circuits. Outputs take on the logic state
determined by CTRL2.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Default Output Control. Controls the logic state the outputs take on when the input power is off. VOA, VOB, and
VOC outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA, VOB, and VOC outputs are low when
CTRL2 is low and VDD1 is off. When VDD1 power is on, this pin has no effect.
No Connection.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. K | Page 13 of 24
ADuM1310/ADuM1311
Data Sheet
VDD1 1
16
VDD2
*GND1 2
15
GND2*
VIA 3
14
VOA
VIB 4
ADuM1311
VOB
TOP VIEW
VOC 5 (Not to Scale) 12 VIC
13
NC 6
11
NC
CTRL1 7
10
CTRL2
*GND1 8
9
GND2*
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
04904-004
NC = NO CONNECT
Figure 5. ADuM1311 Pin Configuration
Table 12. ADuM1311 Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
Mnemonic
VDD1
GND1
VIA
VIB
VOC
NC
CTRL1
8
9
10
GND1
GND2
CTRL2
11
12
13
14
15
16
NC
VIC
VOB
VOA
GND2
VDD2
Description
Supply Voltage for Isolator Side 1, 2.7 V to 5.5 V.
Ground 1. Ground reference for Isolator Side 1.
Logic Input A.
Logic Input B.
Logic Output C.
No Connection.
Default Output Control. Controls the logic state the outputs take on when the input power is off. VOC output is
high when CTRL1 is high or disconnected and VDD2 is off. VOC output is low when CTRL1 is low and VDD2 is off.
When VDD2 power is on, this pin has no effect.
Ground 1. Ground reference for Isolator Side 1.
Ground 2. Ground reference for Isolator Side 2.
Default Output Control. Controls the logic state the outputs take on when the input power is off. VOA and VOB
outputs are high when CTRL2 is high or disconnected and VDD1 is off. VOA and VOB outputs are low when CTRL2
is low and VDD1 is off. When VDD1 power is on, this pin has no effect.
No Connection.
Logic Input C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2.
Supply Voltage for Isolator Side 2, 2.7 V to 5.5 V.
Rev. K | Page 14 of 24
Data Sheet
ADuM1310/ADuM1311
Table 13. Truth Table (Positive Logic)
VIx
Input1
H
L
X
CTRLx
Input2
X
X
H or
NC
L
VDISABLE
State3
L or NC
L or NC
H
VDDI
State4
Powered
Powered
X
VDDO
State5
Powered
Powered
Powered
VOx
Output
H
L
H
H
X
Powered
L
X
H or
NC
X
Unpowered
Powered
H
X
L
X
Unpowered
Powered
L
X
X
X
Powered
Unpowered
Z
X
Description
Normal operation, data is high.
Normal operation, data is low.
Inputs disabled. Outputs are in the default state determined by
CTRLx.
Inputs disabled. Outputs are in the default state determined by
CTRLx.
Input unpowered. Outputs are in the default state determined by
CTRLx. Outputs return to input state within 1 µs of VDDI power
restoration. See the pin function descriptions (Table 11 and Table 12)
for more details.
Input unpowered. Outputs are in the default state determined by
CTRLx. Outputs return to input state within 1 µs of VDDI power
restoration. See the pin function descriptions (Table 11 and Table 12)
for more details.
Output unpowered. Output pins are in high impedance state.
Outputs return to input state within 1 µs of VDDO power restoration.
See the pin function descriptions (Table 11 and Table 12) for more
details.
VIx and VOx refer to the input and output signals of a given channel (A, B, or C).
CTRLx refers to the default output control signal on the input side of a given channel (A, B, or C).
3
Available only on the ADuM1310.
4
VDDI refers to the power supply on the input side of a given channel (A, B, or C).
5
VDDO refers to the power supply on the output side of a given channel (A, B, or C).
1
2
Rev. K | Page 15 of 24
ADuM1310/ADuM1311
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
6
2.0
5V
CURRENT (mA)
4
1.0
3V
3V
2
0
0
2
4
6
DATA RATE (Mbps)
8
04904-009
0.5
04904-006
CURRENT/CHANNE L (mA)
5V
1.5
0
0
10
2
6
4
DATA RATE (Mbps)
8
10
Figure 9. Typical ADuM1310 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Figure 6. Typical Supply Current per Input Channel vs. Data Rate
for 5 V and 3 V Operation
6
1.0
0.9
5V
0.7
4
CURRENT (mA)
CURRENT/CHANNE L (mA)
0.8
0.6
0.5
0.4
3V
5V
2
0.3
3V
0.1
0
0
2
4
6
DATA RATE (Mbps)
8
04904-010
04904-007
0.2
0
0
10
2
4
6
DATA RATE (Mbps)
8
10
Figure 10. Typical ADuM1310 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
Figure 7. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
6
1.4
1.0
5V
0.8
0.6
5V
4
CURRENT (mA)
3V
3V
2
0.4
04904-008
0.2
0
0
2
4
6
DATA RATE (Mbps)
8
04904-011
CURRENT/CHANNE L (mA)
1.2
0
0
10
2
4
6
DATA RATE (Mbps)
8
10
Figure 11. Typical ADuM1311 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
Figure 8. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
Rev. K | Page 16 of 24
Data Sheet
ADuM1310/ADuM1311
6
5V
2
3V
04904-012
CURRENT (mA)
4
0
0
2
4
6
DATA RATE (Mbps)
8
10
Figure 12. Typical ADuM1311 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
Rev. K | Page 17 of 24
ADuM1310/ADuM1311
Data Sheet
APPLICATIONS INFORMATION
PC BOARD LAYOUT
The ADuM1310/ADuM1311 digital isolator requires no
external interface circuitry for the logic interfaces. Power supply
bypassing is strongly recommended at the input and output
supply pins (see Figure 13). Bypass capacitors are most
conveniently connected between Pin 1 and Pin 2 for VDD1 and
between Pin 15 and Pin 16 for VDD2. The capacitor value should
be between 0.01 μF and 0.1 μF. The total lead length between
both ends of the capacitor and the input power supply pin
should not exceed 20 mm. Bypassing between Pin 1 and Pin 8
and between Pin 9 and Pin 16 should be considered, unless
both ground pins on each package are connected together close
to the package.
VDD2
GND2
VOA
VOB
VOC/VIC
ADuM1310/
ADuM1311
NC
DISABLE/CTRL1
GND1
NC
CTRL2
GND2
04904-013
VDD1
GND1
VIA
VIB
VIC/VOC
Figure 13. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, care
should be taken to ensure that board coupling across the isolation
barrier is minimized. Furthermore, the board layout should be
designed so that any coupling that does occur equally affects all
pins on a given component side. Failure to ensure this can cause
voltage differentials between pins exceeding the device’s
absolute maximum ratings, thereby leading to latch-up or
permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition may
differ from the propagation delay time of a low-to-high transition.
INPUT (VIx)
50%
OUTPUT (VOx)
tPHL
04904-014
tPLH
50%
Figure 14. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and is an indication of how
accurately the input signal’s timing is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM1310/ADuM1311 component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM1310/
ADuM1311 components operating under the same conditions.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder via the
transformer. The decoder is bistable and is therefore either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than about 5 μs, the input
side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default state (see Table 13)
by the watchdog timer circuit.
The magnetic field immunity of the ADuM1310/ADuM1311 is
determined by the changing magnetic field, which induces a
voltage in the transformer’s receiving coil large enough to either
falsely set or reset the decoder. The following analysis defines
the conditions under which this can occur. The 3 V operating
condition of the ADuM1310/ADuM1311 is examined because
it represents the most susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ/dt) ∑ π rn2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM1310/
ADuM1311 and an imposed requirement that the induced
voltage be, at most, 50% of the 0.5 V margin at the decoder, a
maximum allowable magnetic field at a given frequency can be
calculated. The result is shown in Figure 15.
Rev. K | Page 18 of 24
Data Sheet
ADuM1310/ADuM1311
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
100
Note that, at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces can
induce error voltages sufficient to trigger succeeding circuitry.
Care should be taken in the layout of such traces to avoid this
possibility.
10
1
POWER CONSUMPTION
The supply current at a given channel of the ADuM1310/
ADuM1311 isolator is a function of the supply voltage, the
channel data rate, and the channel output load.
0.1
0.01
04904-015
0.001
1k
For each input channel, the supply current is given by
100M
10k
100k
1M
10M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 15. Maximum Allowable External Magnetic Flux Density
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM1310/ADuM1311 transformers. Figure 16 expresses
these allowable current magnitudes as a function of frequency
for selected distances. As shown, the ADuM1310/ADuM1311 is
extremely immune and can be affected only by extremely large
currents operated at high frequency very close to the component.
For the 1 MHz example noted, a 0.5 kA current would have to
be placed 5 mm away from the ADuM1310/ ADuM1311 to
affect the component’s operation.
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
10k
100k
1M
10M
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
f > 0.5 fr
IDDO = IDDO (Q)
f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
−3
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half the input
data rate, expressed in units of Mbps.
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. The ADuM1310/
ADuM1311 contains an internal data channel that is not
available to the user. This channel is in the same orientation as
Channel A and consumes quiescent current. The contribution
of this channel must be included in the total quiescent current
calculation for each supply. Figure 6 and Figure 7 show perchannel supply currents as a function of data rate for an
unloaded output condition. Figure 8 shows per-channel supply
current as a function of data rate for a 15 pF output condition.
Figure 9 through Figure 12 show total VDD1 and VDD2 supply
current as a function of data rate for ADuM1310/ADuM1311
channel configurations.
04904-016
MAXIMUM ALLOWABLE CURRENT (kA)
1000
1k
f ≤ 0.5 fr
For each output channel, the supply current is given by
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurred during a transmitted pulse
(and had the worst-case polarity), it would reduce the received
pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing
threshold of the decoder.
0.01
IDDI = IDDI (Q)
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 16. Maximum Allowable Current
for Various Current-to-ADuM1310/ADuM1311 Spacings
Rev. K | Page 19 of 24
ADuM1310/ADuM1311
Data Sheet
Note that the voltage presented in Figure 18 is shown as
sinusoidal for illustration purposes only. It is meant to represent
any voltage waveform varying between 0 V and some limiting
value. The limiting value can be positive or negative, but the
voltage cannot cross 0 V.
The insulation lifetime of the ADuM1310/ADuM1311 depends
on the voltage waveform type imposed across the isolation
barrier. The iCoupler insulation structure degrades at different
rates depending on whether the waveform is bipolar ac,
unipolar ac, or dc. Figure 17, Figure 18, and Figure 19 illustrate
these different isolation voltage waveforms.
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
RATED PEAK VOLTAGE
04904-017
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in Table 10
summarize the peak voltage for 50 years of service life for a
bipolar ac operating condition and the maximum CSA/VDE
approved working voltages. In many cases, the approved
working voltage is higher than 50-year service life voltage.
Operation at these high working voltages can lead to shortened
insulation life in some cases.
0V
Figure 17. Bipolar AC Waveform
RATED PEAK VOLTAGE
04904-018
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog
Devices carries out an extensive set of evaluations to determine
the lifetime of the insulation structure within the ADuM1310/
ADuM1311.
In the case of unipolar ac or dc voltage, the stress on the
insulation is significantly lower. This allows operation at higher
working voltages while still achieving a 50-year service life. The
working voltages listed in Table 10 can be applied while
maintaining the 50-year minimum lifetime provided the voltage
conforms to either the unipolar ac or dc voltage case. Any crossinsulation voltage waveform that does not conform to Figure 18
or Figure 19 should be treated as a bipolar ac waveform, and its
peak voltage should be limited to the 50-year lifetime voltage
value listed in Table 10.
0V
Figure 18. Unipolar AC Waveform
RATED PEAK VOLTAGE
04904-019
INSULATION LIFETIME
0V
Figure 19. DC Waveform
Rev. K | Page 20 of 24
Data Sheet
ADuM1310/ADuM1311
OUTLINE DIMENSIONS
10.50 (0.4134)
10.10 (0.3976)
9
16
7.60 (0.2992)
7.40 (0.2913)
1.27 (0.0500)
BSC
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
10.65 (0.4193)
10.00 (0.3937)
8
0.51 (0.0201)
0.31 (0.0122)
0.75 (0.0295)
45°
0.25 (0.0098)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
8°
0°
0.33 (0.0130)
0.20 (0.0079)
COMPLIANT TO JEDEC STANDARDS MS-013-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1.27 (0.0500)
0.40 (0.0157)
03-27-2007-B
1
Figure 20. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body (RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Number
of Inputs,
Model1
VDD1 Side
ADuM1310ARWZ
3
ADuM1310ARWZ-RL 3
Number
of Inputs,
VDD2 Side
0
0
Maximum Maximum
Data Rate Propagation
(Mbps)
Delay, 5 V (ns)
1
100
1
100
Maximum
Pulse Width
Distortion (ns)
40
40
ADuM1310BRWZ
3
ADuM1310BRWZ-RL 3
0
0
10
10
50
50
5
5
ADuM1311ARWZ
2
ADuM1311ARWZ-RL 2
1
1
1
1
100
100
40
40
ADuM1311BRWZ
2
ADuM1311BRWZ-RL 2
1
1
10
10
50
50
5
5
1
Z = RoHS Compliant Part.
Rev. K | Page 21 of 24
Temperature
Package Description
Range
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W, 13” Tape
and Reel
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W, 13” Tape
and Reel
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W, 13” Tape
and Reel
−40°C to +105°C 16-Lead SOIC_W
−40°C to +105°C 16-Lead SOIC_W, 13” Tape
and Reel
Package
Option
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
RW-16
ADuM1310/ADuM1311
Data Sheet
NOTES
Rev. K | Page 22 of 24
Data Sheet
ADuM1310/ADuM1311
NOTES
Rev. K | Page 23 of 24
ADuM1310/ADuM1311
Data Sheet
NOTES
©2005–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04904-0-6/15(K)
Rev. K | Page 24 of 24
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