ADUM4136BRWZ

Single-/Dual-Supply, High Voltage Isolated IGBT Gate Driver ADuM4136 Data Sheet FEATURES GENERAL DESCRIPTION 4 A peak drive output capability Output power device resistance: 5 V 2.5 V ≤ VDD1 − VSS1 ≤ 5 V VDD1 − VSS1 > 5 V Tested at 5 mA Tested at 5 mA Tested at 250 mA Tested at 1 A Tested at 250 mA Tested at 1 A Tested at 250 mA VDD2 = 12 V, 2 Ω gate resistance CL = 2 nF, VDD2 = 15 V, RGON2 = RGOFF2 = 3.9 Ω ADuM4136 Data Sheet Parameter Propagation Delay3 Propagation Delay Skew4 Output Rise/Fall Time (10% to 90%) Blanking Capacitor Discharge Switch Masking Time to Report Desaturation Fault to FAULT Pin Common-Mode Transient Immunity (CMTI) Static CMTI5 Dynamic CMTI6 Symbol tDHL, tDLH tPSK tR/tF tDESAT_DELAY tREPORT |CM| Min 40 Typ 55 11 213 16 312 1.3 Max 68 15 22.9 615 2 100 100 Unit ns ns ns ns μs Test Conditions/Comments CL = 2 nF, VDD2 = 15 V, RGON2 = RGOFF2 = 3.9 Ω CL = 2 nF, RGON2 = RGOFF2 = 3.9 Ω CL = 2 nF, VDD2 = 15 V, RGON2 = RGOFF2 = 3.9 Ω kV/μs kV/μs VCM = 1500 V VCM = 1500 V 1 The minimum pulse width is the shortest pulse width at which the specified timing parameter is guaranteed. See the Power Dissipation section. tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOUT signal. tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOUT signal. See Figure 22 for waveforms of propagation delay parameters. 4 tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See Figure 22 for waveforms of propagation delay parameters. 5 Static common-mode transient immunity is defined as the largest dv/dt between VSS1 and VSS2 with inputs held either high or low such that the output voltage remains either above 0.8 × VDD2 for output high, or 0.8 V for output low. Operation with transients above the recommended levels can cause momentary data upsets. 6 Dynamic common-mode transient immunity is defined as the largest dv/dt between VSS1 and VSS2 with the switching edge coincident with the transient test pulse. Operation with transients above the recommended levels can cause momentary data upsets. 2 3 PACKAGE CHARACTERISTICS Table 2. Parameter Resistance (Input Side to High-Side Output)1 Capacitance (Input Side to High-Side Output)1 Input Capacitance Junction to Ambient Thermal Resistance Junction to Case Thermal Resistance 1 Symbol RI-O CI-O CI θJA θJC Min Typ 1012 2.0 4.0 75.4 35.4 Max Unit Ω pF pF °C/W °C/W Test Conditions/Comments 4-layer printed circuit board (PCB) 4-layer PCB The device is considered a two-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. REGULATORY INFORMATION The ADuM4136 is pending approval by the organizations listed in Table 3. Table 3. UL (Pending) Recognized under UL 1577 Component Recognition Program1 Single Protection, 5000 V rms Isolation Voltage File E214100 1 2 CSA (Pending) Approved under CSA Component Acceptance Notice 5A VDE (Pending) Certified according to VDE0884-102 Basic insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed.+A1+A2, 780 V rms (1103 V peak) maximum working voltage CSA 60950-1-07+A1+A2 and IEC 60950-1 Second Ed.+A1+A2, 390 V rms (551 V peak) maximum working voltage File 205078 Basic insulation, 849 V peak File 2471900-4880-0001 In accordance with UL 1577, each ADuM4136 is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA). In accordance with DIN V VDE V 0884-10, each ADuM4136 is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection limit = 5 pC). An asterisk (*) marking branded on the component designates DIN V VDE V 0884-10 approval. INSULATION AND SAFETY RELATED SPECIFICATIONS Table 4. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 5000 7.8 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 7.8 min mm Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group CTI 0.026 min >400 II mm V Rev. 0 | Page 4 of 16 Test Conditions/Comments 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Insulation distance through insulation DIN IEC 112/VDE 0303 Part 1 Material Group (DIN VDE 0110, 1/89, Table 1) Data Sheet ADuM4136 DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS Maintenance of the safety data is ensured by protective circuits. The asterisk (*) marking on the package denotes DIN V VDE V 0884-10 approval for a 560 V peak working voltage. Table 5. VDE Characteristics Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 150 V rms For Rated Mains Voltage ≤ 300 V rms For Rated Mains Voltage ≤ 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input to Output Test Voltage, Method B1 Input to Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Safety Limiting Values Maximum Junction Temperature Safety Total Dissipated Power Insulation Resistance at TS Test Conditions/Comments VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VPEAK = 12.8 kV, 1.2 μs rise time, 50 μs, 50% fall time Maximum value allowed in the event of a failure (see Figure 2) VIO = 500 V SAFE OPERATING POWER (W) 3.0 Symbol Characteristic Unit VIORM Vpd (m) I to IV I to III I to II 40/105/21 2 849 1592 V peak V peak Vpd (m) 1274 V peak Vpd (m) 1019 V peak VIOTM VIOSM 8000 8000 V peak V peak TS PS RS 150 2.77 >109 °C W Ω RECOMMENDED OPERATING CONDITIONS 2.5 Table 6. 2.0 1.5 1.0 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 13575-002 0.5 Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN V VDE V 0884-10 Parameter Operating Temperature Range (TA) Supply Voltages VDD11 VDD22 VDD2 − VSS22 VSS22 Input Signal Rise/Fall Time Static Common Mode Transient Immunity3 Dynamic Common Mode Transient Immunity4 1 Value −40°C to +125°C 2.5 V to 6 V 12 V to 35 V 12 V to 35 V −15 V to 0 V 1 ms −100 kV/μs to +100 kV/μs −100 kV/μs to +100 kV/μs Referenced to VSS1. Referenced to GND2. Static common-mode transient immunity is defined as the largest dv/dt between VSS1 and VSS2 with inputs held either high or low such that the output voltage remains either above 0.8 × VDD2 for output high, or 0.8 V for output low. Operation with transients above recommended levels can cause momentary data upsets. 4 Dynamic common-mode transient immunity is defined as the largest dv/dt between VSS1 and VSS2 with the switching edge coincident with the transient test pulse. Operation with transients above recommended levels can cause momentary data upsets. 2 3 Rev. 0 | Page 5 of 16 ADuM4136 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 8. Maximum Continuous Working Voltage1 Table 7. Parameter Storage Temperature Range (TST) Junction Operating Temperature Range (TJ) Supply Voltage VDD1 to VSS1 VDD2 to GND2 VSS2 to GND2 VDD2 − VSS2 Input Voltage VDESAT1 VI+,2 VI−,2 RESET2 Output Voltage VOUT3 Common-Mode Transients (|CM|) Rating −55°C to +150°C −40°C to +125°C −0.3 V to +6.5 V −0.3 V to +40 V −20 V to +0.3 V 40 V Parameter 60 Hz AC Voltage Value 600 V rms DC Voltage 1092 V peak Constraint 20-year lifetime at 0.1% failure rate, zero average voltage Limited by the creepage of the package, Pollution Degree 2, Material Group II2, 3 1 See the Insulation Lifetime section for details. Other pollution degree and material group requirements yield a different limit. 3 Some system level standards allow components to use the printed wiring board (PWB) creepage values. The supported dc voltage may be higher for those standards. 2 −0.3 V to VDD2 + 0.3 V −0.3 V to +6.5 V −0.3 V to VDD2 + 0.3 V −150 kV/μs to +150 kV/μs ESD CAUTION 1 Referenced to GND2. Referenced to VSS1. 3 Referenced to VSS2. 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 9. Truth Table (Positive Logic)1 VI+ Input L L H H X X L X X 1 2 3 VI− Input L H L H X X L X X RESET Pin H H H H H H H L3 X READY Pin H H H H L Unknown L Unknown L FAULT Pin H H H H Unknown L Unknown H3 Unknown L is low, H is high, and X is don’t care. VGATE is the voltage of the gate being driven. Time dependent value. See Figure 22 for details on timing. Rev. 0 | Page 6 of 16 VDD1 State Powered Powered Powered Powered Powered Powered Unpowered Powered Powered VDD2 State Powered Powered Powered Powered Powered Powered Powered Powered Unpowered VGATE2 L L H L L L L L Unknown Data Sheet ADuM4136 VI+ 1 16 GND2 VI– 2 15 VSS2 VDD1 3 14 DESAT 13 VDD2 12 VDD2 FAULT 6 11 VOUT READY 7 10 VSS2 VSS1 8 9 VSS2 VSS1 4 RESET 5 ADuM4136 TOP VIEW (Not to Scale) 13575-003 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 3. Pin Configuration Table 10. Pin Function Descriptions Pin No. 1 2 3 4 5 6 Mnemonic V I+ V I− VDD1 VSS1 RESET FAULT 7 READY 8 9 10 11 12 13 14 VSS1 VSS2 VSS2 VOUT VDD2 VDD2 DESAT 15 16 VSS2 GND2 Description Positive Logic CMOS Input Drive Signal. Negative Logic CMOS Input Drive Signal. Input Supply Voltage on Primary Side, 2.5 V to 6 V. The supply that is connected to this pin must be referenced to VSS1. Ground Reference for Primary Side. CMOS Input. When a fault exists, bring this pin low to clear the fault. RESET has an internal 300 kΩ pull-down resistor. Open-Drain Logic Output. Connect this pin to a pull-up resistor to read the signal. A low state on this pin indicates when a desaturation fault has occurred. The presence of a fault condition precludes the gate drive output from going high. Open-Drain Logic Output. Connect this pin to a pull-up resistor to read the signal. A high state on this pin indicates that the device is functional and ready to operate as a gate driver. If READY is low, the gate drive output is precluded from going high. Ground Reference for Primary Side. Negative Supply for Secondary Side, −15 V to 0 V. The supply that is connected to this pin must be referenced to GND2. Negative Supply for Secondary Side, −15 V to 0 V. The supply that is connected to this pin must be referenced to GND2. Gate Drive Output Current Path for the Device. Secondary Side Input Supply Voltage, 12 V to 35 V. The supply that is connected to this pin must be referenced to GND2. Secondary Side Input Supply Voltage, 12 V to 35 V. The supply that is connected to this pin must be referenced to GND2. Detection of Desaturation Condition. Connect this pin to an external current source or a pull-up resistor. A fault on this pin asserts a fault on the FAULT pin on the primary side. Until the fault is cleared on the primary side, the gate drive is suspended. During a fault condition, a smaller turn-off FET slowly brings the gate voltage down. Negative Supply for Secondary Side, −15 V to 0 V. The supply that is connected to this pin must be referenced to GND2. Ground Reference for Secondary Side. Connect this pin to the emitter of the IGBT or the source of the MOSFET being driven. Rev. 0 | Page 7 of 16 ADuM4136 Data Sheet TYPICAL PERFORMANACE CHARACTERISTICS CH1 = VI+ (2V/DIV) CH1 = VI+ (2V/DIV) 1 1 CH2 = VGATE (5V/DIV) CH2 = VGATE (5V/DIV) 2 CH2 5V 100ns/DIV 10GS/s 100ps/PT A CH1 1.68V CH1 2V CH2 5V 100ns/DIV 10GS/s 100ps/PT A CH1 1.68V Figure 4. Input to Output Waveform, 2 nF Load, 5.1 Ω Series Gate Resistor, VDD1 = +5 V, VDD2 = +15 V, VSS2 = −5 V Figure 7. Input to Output Waveform, 2 nF Load, 4.0 Ω Series Gate Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = 0 V CH1 = VI+ (2V/DIV) CH1 = VI+ (2V/DIV) 1 13575-007 CH1 2V 13575-004 2 1 CH2 = VGATE (5V/DIV) CH2 = VGATE (5V/DIV) 2 CH2 5V 100ns/DIV 10GS/s 100ps/PT A CH1 1.68V CH1 2V CH2 5V 100ns/DIV 10GS/s 100ps/PT A CH1 1.68V 13575-008 CH1 2V 13575-005 2 Figure 5. Input to Output Waveform, 2 nF Load, 5.1 Ω Series Gate Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = 0 V Figure 8. Input to Output Waveform, 2 nF Load, 2.0 Ω Series Gate Resistor, VDD1 = +5 V, VDD2 = +15 V, VSS2 = −5 V CH1 = VI+ (2V/DIV) CH1 = VI+ (2V/DIV) 1 1 CH2 = VGATE (5V/DIV) CH2 = VGATE (5V/DIV) 2 CH2 5V 100ns/DIV 10GS/s 100ps/PT A CH1 1.68V CH1 2V Figure 6. Input to Output Waveform, 2 nF Load, 4.0 Ω Series Gate Resistor, VDD1 = +5 V, VDD2 = +15 V, VSS2 = −5 V CH2 5V 100ns/DIV 10GS/s 100ps/PT A CH1 1.68V Figure 9. Input to Output Waveform, 2 nF Load, 2.0 Ω Series Gate Resistor, VDD1 = 5 V, VDD2 = 15 V, VSS2 = 0 V Rev. 0 | Page 8 of 16 13575-009 CH1 2V 13575-006 2 Data Sheet ADuM4136 80 4.0 VDD1 = 3.3V 70 PROPAGATION DELAY (ns) VDD1 = 5.0V 3.5 3.0 VDD1 = 2.5V 2.0 1.5 1.0 tDLH 40 30 20 200 300 400 500 600 700 800 900 1000 0 12 18 20 22 24 26 28 30 Figure 13. Propagation Delay vs. Output Supply Voltage (VDD2), VDD1 = 5 V 60 30 50 25 tF RISE/FALL TIME (ns) VDD2 = 20V 40 VDD2 = 15V VDD2 = 12V 20 10 20 tR 15 10 0 100 200 300 400 500 600 700 800 900 1000 FREQUENCY (kHz) 0 12 14 16 18 20 22 24 26 28 30 VDD2 (V) Figure 11. IDD2 Current vs. Frequency, Duty = 50%, 2 nF Load, VSS2 = 0 V 13575-014 5 13575-011 0 16 VDD2 (V) Figure 10. IDD1 Current vs. Frequency, Duty = 50%, VI+ = VDD1 30 14 13575-013 100 13575-010 0 FREQUENCY (kHz) IDD2 (mA) 50 10 0.5 0 tDHL Figure 14. Rise/Fall Time vs. VDD2, VDD2 − VSS2 = 12 V, VDD1 = 5 V, 2 nF Load, RG = 5.1 Ω 80 CH1 = VI+ (5V/DIV) 70 PROPAGATION DELAY (ns) 1 2 CH2 = VGATE (5V/DIV) CH3 = VDD2 (10V/DIV) 60 tDHL 50 tDLH 40 30 20 10 CH1 5V CH3 10V CH2 5V A CH3 10µs/DIV 100MS/s 100ns/PT 8.8V 13575-012 3 0 2.5 2.8 3.3 3.8 4.3 4.8 5.3 5.8 INPUT SUPPLY VOLTAGE (V) Figure 15. Propagation Delay vs. Input Supply Voltage, VDD2 − VSS2 = 12 V Figure 12. Typical VDD2 Startup to Output Valid Rev. 0 | Page 9 of 16 13575-015 IDD1 (mA) 2.5 60 ADuM4136 Data Sheet 80 800 700 SOURCE RESISTANCE tDHL 60 600 tDLH 500 RDSON (mΩ) 50 40 30 SINK RESISTANCE 400 300 20 200 10 100 –20 0 20 40 60 80 100 0 –40 13575-016 0 –40 120 AMBIENT TEMPERATURE (°C) Figure 16. Propagation Delay vs. Ambient Temperature, VDD2 = 5 V, VDD2 − VSS2 = 12 V –20 0 20 40 60 80 100 13575-019 PROPAGATION DELAY (ns) 70 120 TEMPERATURE (°C) Figure 19. Output On Resistance (RDSON) vs. Temperature, VDD2 = 15 V, Tested at 1 A CH1 = VI+ (5V/DIV) CH2 = VGATE (10V/DIV) 1 CH1 = VI+ (5V/DIV) 1 2 CH3 = FAULT (5V/DIV) 2 CH2 = VGATE (5V/DIV) 3 CH3 = RESET (5V/DIV) 3 CH2 10V CH4 5V 500ns/DIV 2.5GS/s 400ps/PT A CH1 1.1V 13575-017 CH4 = DESAT (5V/DIV) CH1 5V CH3 5V Figure 17. Example Desaturation Event and Reporting A CH3 3.3V 10 9 700 PEAK OUTPUT CURRENT (A) SOURCE RESISTANCE 600 RDSON (mΩ) 500ns/DIV 2.5GS/s 400ps/PT Figure 20. Example RESET to Output Valid 800 500 SINK RESISTANCE 400 300 200 100 8 PEAK SINK IOUT 7 6 PEAK SOURCE IOUT 5 4 3 2 1 –20 0 20 40 60 TEMPERATURE (°C) 80 100 120 0 12.0 13575-018 0 –40 CH2 5V Figure 18. Output On Resistance (RDSON) vs. Temperature, VDD2 = 15 V, Tested at 250 mA 14.5 17.0 19.5 22.0 OUTPUT SUPPLY VOLTAGE (V) 24.5 13575-021 CH1 5V CH3 5V 13575-020 4 Figure 21. Peak Output Current vs. Output Supply Voltage, 2.4 Ω Series Resistance (IOUT is the Current Going Into/Out Of the Device Gate) Rev. 0 | Page 10 of 16 Data Sheet ADuM4136 APPLICATIONS INFORMATION PCB LAYOUT Desaturation Detection The ADuM4136 IGBT gate driver requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins. Use a small ceramic capacitor with a value between 0.01 μF and 0.1 μF to provide a good high frequency bypass. On the output power supply pin, VDD2, it is recommended to add a 10 μF capacitor to provide the charge required to drive the gate capacitance at the ADuM4136 outputs. On the output supply pin, avoid the use of vias on the bypass capacitor or employ multiple vias to reduce the inductance in the bypassing. The total lead length between both ends of the smaller capacitor and the input or output power supply pin must not exceed 5 mm. Occasionally, component failures or faults occur with the circuitry connected to the IGBT connected to the ADuM4136. Examples include shorts in the inductor/motor windings or shorts to power/ground buses. The resulting excess in current flow causes the IGBT to come out of saturation. To detect this condition and to reduce the likelihood of damage to the FET, a threshold circuit is used on the ADuM4136. If the DESAT pin exceeds the typical desaturation threshold (VDESAT, TH) of 9.2 V while the high-side driver is on, the ADuM4136 enters the failure state and turns the IGBT off. At this time, the FAULT pin is brought low. An internal current source of 537 μA (typical) is provided, as well as the option to boost the charging current using external current sources or pull-up resistors. PROPAGATION DELAY RELATED PARAMETERS Propagation delay describes the time required for a logic signal to propagate through a component. The propagation delay to a low output can differ from the propagation delay to a high output. The ADuM4136 specifies tDLH as the time between the rising input high logic threshold (VIH) to the output rising 10% threshold (see Figure 22). Likewise, the falling propagation delay (tDHL) is defined as the time between the input falling logic low threshold (VIL) and the output falling 90% threshold. The rise and fall times are dependent on the loading conditions and are not included in the propagation delay, which is the industry standard for gate drivers. The ADuM4136 has a built-in blanking time to prevent false triggering while the IGBT first turns on. The time between desaturation detection and reporting a desaturation fault to the FAULT pin is less than 2 μs (tREPORT). Bring RESET low to clear the fault. There is a 500 ns (minimum) debounce (tDEB_RESET) on the RESET pin. The time, tDESAT_DELAY, shown in Figure 23, provides approximately 312 ns (typical) of masking time that keeps the internal switch that grounds the blanking capacitor tied low for the initial portion of the IGBT on time. DESAT EVENT 90% V I+ OUTPUT 10% VGATE VIH tDESAT_DELAY = 300ns INPUT VIL DESAT SWITCH tDHL tR tF ON OFF 13575-022 tDLH ON OFF ON