Isolated, Half Bridge Gate Driver with
Adjustable Dead Time, 4 A Output
ADuM4221
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS
Switching power supplies
Isolated IGBT/MOSFET gate drives
Industrial inverters
Gallium nitride (GaN)/silicon carbide (SiC) compatible
VIA 1
ADuM4221
UVLO
VIB 2
TSD
15 VOA
DECODE
AND
LOGIC
ENCODE
16 VDDA
14 GNDA
VDD1 3
UVLO
GND1 4
DISABLE 5
13 NC
CONTROL
LOGIC
12 NC
UVLO
DT 6
NC 7
DECODE
AND
LOGIC
ENCODE
VDD1 8
TSD
11 VDDB
10 VOB
9 GNDB
17219-001
4 A peak current ( 5 V
2.5 V ≤ VDD1 ≤ 5 V
VDD1 > 5 V
V
V
V
V
V
V
V
V
V
V
V
V
Grade A
Grade B
Grade C
Grade A
Grade B
Grade C
Grade A
Grade B
Grade C
IDD2 (Q)
IIA, IIB
−1
VIH
0.7 × VDD1
3.5
VIL
VVDD1UV+
VVDD1UV−
VVDD1UVH
VVDDAUV+,
VVDDBUV+
VDDA and VDDB Negative Going Threshold
VVDDAUV−,
VVDDBUV−
VDDA and VDDB Hysteresis
VVDDAUVH,
VVDDBUVH
TSD
Positive Edge
Hysteresis
Drive Strength
Pull-Down Negative Metal Oxide
Semiconductor (NMOS) On Resistance
Typ
2.3
4.1
6.9
10.8
2.45
2.35
0.1
4.4
7.3
11.3
4.2
7.1
11.1
0.2
0.2
0.2
2.5
4.5
7.5
11.6
TTSD_POS
TTSD_HYST
155
30
RDSON_N
0.6
1.6
Ω
Tested at 250 mA, VDDx = 15 V
Pull-Up Positive Metal Oxide
Semiconductor (PMOS) On Resistance
RDSON_P
0.6
0.8
1.6
1.8
Ω
Ω
Tested at 1 A, VDDx = 15 V
Tested at 250 mA, VDDx = 15 V
IPEAK
0.8
4
1.8
Peak Current
Ω
A
Tested at 1 A, VDDx = 15 V
VDDA,VDDB = 15 V, 2 Ω gate resistance
Rev. 0 | Page 3 of 19
°C
°C
ADuM4221
Parameter
SWITCHING SPECIFICATIONS
Pulse Width
Data Sheet
Symbol
Min
Typ
Max
50
Propagation Delay1
Rising Edge
Falling Edge
Time to Disable
Time to Enable
Delay Skew2
Pulse Width Distortion
tDLH
tDHL
tDIS
tEN
tPSK
tPWD
Channel to Channel Matching3
tPSKCD
Output Rise and Fall Time (10% to 90%)
tR/tF
Adjustable Dead Time
DT
19
21
21
19
25
30
25
25
Unit
Test Conditions
ns
Load capacitance (CL) = 2.2 nF,
VDD1 = 5 V, VDDA and VDDB = 15 V,
external gate resistor (RG) = 5.1 Ω
CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, and RG = 5.1Ω
5
33
44
44
33
22
16
ns
ns
ns
ns
ns
ns
1.5
10
ns
14
25
34
ns
1809
742
48
2320
938
62
2831
1135
76
ns
ns
ns
CL = 2.2 nF, RG = 5.1 Ω
CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, RG = 5.1 Ω
CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, see Figure 19
CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, RG = 5.1 Ω, see Figure 26
CL = 2.2 nF, VDD1 = 5 V, VDDA and
VDDB = 15 V, RG = 5.1 Ω
Dead time resistor (RDT) = 500 kΩ
RDT = 200 kΩ
RDT = 10 kΩ
1
tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% level of the VOx signal. tDHL propagation delay is
measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See Figure 26 for the waveforms of the propagation delay
parameters.
2
tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output
load within the recommended operating conditions. See Figure 26 for the waveforms of the propagation delay parameters.
3
Channel to channel matching is the absolute value of the difference in propagation delays between two channels on a single device.
PACKAGE CHARACTERISTICS
Table 2.
Parameter
Resistance (Input to Output)1
Capacitance (Input to Output)1
Input Capacitance2
IC Junction to Ambient Thermal Resistance
1
2
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1013
2.2
4.0
45
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package underside
The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
Rev. 0 | Page 4 of 19
Data Sheet
ADuM4221
REGULATORY INFORMATION
The ADuM4221 is pending approval by the organizations listed in Table 3.
Table 3.
UL (Pending)
Recognized Under 1577 Component
Recognition Program1
Single Protection, 5700 V rms
Isolation Voltage
File E214100
1
2
CSA (Pending)
Approved under CSA Component
Acceptance Notice 5A
IEC 62368, Third Edition
Basic insulation at 830 V rms
(1173 V peak)
Reinforced insulation at 415 V rms
(586 V peak)
IEC 60601-1, Edition 3.1
Reinforced insulation (2 MOPP),
250 V rms (353V peak)
CSA 61010-1-12 and IEC 61010-1,
Third Edition
Basic insulation at 300 V rms mains,
800 V secondary (1089 V peak)
Reinforced insulation at
300 V rms mains,
400 V secondary (565 V peak)
File 205078
VDE (Pending)
Certified according to DIN VDE V
0884-11 (VDE V 0884-11):2017-012
Basic insulation, 900 V peak,
VIOSM = 9850 V peak
Reinforced insulation, 849 V peak,
VIOSM = 8000 V peak
CQC (Pending)
Certified by
CQC11-471543-2012
GB4943.1-2011
File 2471900-4880-0003
File (pending)
Basic insulation at
800 V rms (1131 V peak)
Reinforced insulation at
400 V rms (565 V peak)
In accordance with UL 1577, each ADuM4221 is proof tested by applying an insulation test voltage ≥ 6840 V rms for 1 sec.
In accordance with DIN VDE V 0884-11, each ADuM4221 is proof tested by applying an insulation test voltage ≥ 1592 V peak for 1 sec (partial discharge detection limit =
5 pC). The * marking branded on the component designates DIN VDE V 0884-11 approval.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 4.
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Symbol
L (I01)
Value
5700
8.3
Unit
V rms
mm
Minimum External Tracking (Creepage)
L (I02)
8.3
mm
Minimum Clearance in the Plane of the Printed Circuit
Board, PCB (PCB Clearance)
L (PCB)
8.3
mm
CTI
25.5
>600
I
μm
V
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Material Group
Rev. 0 | Page 5 of 19
Test Conditions/Comments
1-minute duration
Measured from input terminals to output
terminals, shortest distance through air
Measured from input terminals to output
terminals, shortest distance path along body
Measured from input terminals to output
terminals, shortest distance through air,
line of sight, in the PCB mounting plane
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
ADuM4221
Data Sheet
DIN V VDE V 0884-11 (VDE V 0884-11) INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation only within the safety limit data. Protective circuits ensure maintenance of the safety data.
Table 5. VDE Characteristics
Description
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 600 V rms
Climatic Classification
Pollution Degree per DIN VDE 0110, Table 1
Maximum Repetitive Peak Isolation Voltage
Input to Output Test Voltage, Method B1
Test Conditions/Comments
VIORM × 1.875 = Vpd (m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Input to Output Test Voltage, Method A
After Environmental Tests Subgroup 1
Characteristic
Unit
VIORM
Vpd (m)
I to IV
I to IV
I to IV
40/105/21
2
849
1592
V peak
V peak
1274
V peak
1019
V peak
8000
V peak
9850
V peak
8000
V peak
150
2.77
>109
°C
W
Ω
Vpd (m)
VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
After Input and/or Safety Test Subgroup 2
and Subgroup 3
Maximum Rated Transient Isolation Voltage
Surge Isolation Voltage
Basic
VIOTM
VIOSM
V peak = 12.8 kV, 1.2 µs rise time, 50 µs,
50% fall time
V peak = 12.8 kV, 1.2 µs rise time, 50 µs,
50% fall time
Maximum value allowed in the event of a
failure (see Figure 2)
Reinforced
Safety Limiting Values
Maximum Junction Temperature
Total Power Dissipation at 25°C
Insulation Resistance at TS
TS
PS
RS
VIO = 500 V
3.0
RECOMMENDED OPERATING CONDITIONS
2.5
Table 6.
2.0
1.5
1.0
0.5
0
0
50
100
150
AMBIENT TEMPERATURE (°C)
200
17219-002
SAFE OPERATING PVDD1 , PVDDA ,
OR PVDDB POWER (W)
Symbol
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on
Case Temperature, per DIN V VDE V 0884-11
Parameter
TJ
Supply Voltages
VDD11
VDDA and VDDB2
Common-Mode Transient Immunity
Static3
Dynamic4
Dead Time Resistor Range
Value
−40°C to +125°C
2.5 V to 6.5 V
4.5 V to 35 V
−150 kV/µs to +150 kV/µs
−150 kV/µs to +150 kV/µs
10 kΩ to 500 kΩ
Referenced to GND1.
Referenced to GNDA,GNDB.
3
Static common-mode transient immunity is defined as the largest dv/dt
between GND1 and GNDA and GNDB with the inputs held either high or low
such that the output voltage remains either above 0.8 × VDDA and VDDB for
output high or 0.8 V for output low. Operation with transients above
recommended levels can cause momentary data upsets.
4
Dynamic common-mode transient immunity is defined as the largest dv/dt
between GND1 and GNDA and GNDB with the switching edge coincident with
the transient test pulse. Operation with transients above recommended
levels can cause momentary data upsets.
1
2
Rev. 0 | Page 6 of 19
Data Sheet
ADuM4221
ABSOLUTE MAXIMUM RATINGS
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
TA = 25°C, unless otherwise noted.
Table 7.
Parameter
Voltage Ranges
Supply
VDD1
VDDA and VDDB
Input1 (VIA, VIB, and DISABLE)
Output2
VOA
VOB
VOA Transient for 200 ns
VOB Transient for 200 ns
Temperature Range
Storage (TST)
TJ
Common-Mode Transients3 (CMH, CML)
Rating
−0.2 V to +7 V
−0.3 V to +40 V
−0.3 V to +7 V
THERMAL RESISTANCE
−0.3 V to VDDA + 0.3 V
−0.3 V to VDDB + 0.3 V
−2 V to VDDA + 0.3 V
−2 V to VDDB + 0.3 V
Thermal performance is directly linked to the PCB design and
operating environment. Careful attention to PCB thermal
design is required.
θJA is the junction to ambient thermal resistance, and ΨJT is the
junction to top characterization parameter.
Table 8. Thermal Resistance
−55°C to +150°C
−40°C to +125°C
−200 kV/µs to
+200 kV/µs
Package Type1
RI-16-2
1
Rating assumes VDD1 is above 2.5 V. VIA and VIB are rated up to 6.5 V when VDD1
is unpowered.
2
Referenced to GND2, maximum of 40 V.
3
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum rating can cause latch-up
or permanent damage.
θJA
45
ΨJT
16.67
Unit
°C/W
4-layer PCB.
1
ESD CAUTION
Table 9. Maximum Continuous Working Voltage 1
Parameter
AC Voltage
Bipolar Waveform
Basic Insulation
Reinforced Insulation
DC Voltage
Basic Insulation
Reinforced Insulation
1
Rating
Unit
Constraint
900
849
V peak
V peak
20 year minimum insulation lifetime per VDE-0884-11
20 year minimum insulation lifetime per VDE-0884-11
1660
V peak
830
V peak
Lifetime limited by package creepage maximum approved working voltage per IEC 60664-1,
Pollution Degree 2, Material Group I
Lifetime limited by package creepage maximum approved working voltage per IEC 60664-1,
Pollution Degree 2, Material Group I
Refers to the continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Rev. 0 | Page 7 of 19
ADuM4221
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIA 1
16 VDDA
VIB 2
15 VOA
VDD1 3
14 GNDA
GND1 4
ADuM4221
13 NC
DISABLE 5
TOP VIEW
(Not to Scale)
12 NC
DT 6
11 VDDB
NC 7
10 VOB
9 GNDB
NOTES
1. NC = NO CONNECT.
DO NOT CONNECT TO THESE PINS.
17219-003
VDD1 8
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. 1
1
2
3, 8
4
5
6
Mnemonic
VIA
VIB
VDD1
GND1
DISABLE
DT
7, 12, 13
9
10
11
14
15
16
NC
GNDB
VOB
VDDB
GNDA
VOA
VDDA
1
Description
Logic Input A.
Logic Input B.
Input Supply Voltage.
Ground Reference for Input Logic Signals.
Input Disable. The DISABLE pin disables the isolator inputs and refresh circuits.
Dead Time Control Input. The resistor connected from the DT pin to ground sets the dead time between the
output transitions.
No Connect. Do not connect to these pins.
Ground Reference for Output B.
Output B.
Output B Supply Voltage.
Ground Reference for Output A.
Output A.
Output A Supply Voltage.
Pin 3 and Pin 8 are internally connected. Connecting both the VDD1 pins to the VDD1 input supply is recommended.
Table 11. Truth Table (Positive Logic with Dead Time)
DISABLE 1
Low
VIA Input1
Low
VIB Input1
Low
VDD1 State
Powered
VDDA and VDDB State
Powered
VOA Output
Low
VOB Output
Low
Low
Low
High
Powered
Powered
Low
High
Low
High
Low
Powered
Powered
High
Low
Low
High
High
Powered
Powered
Low
Low
High
X
X
X
X
X
Powered
Unpowered
Powered
Powered
Low
Low
Low
Low
X
X
X
Powered
Unpowered
Low
Low
1
X means don’t care.
Rev. 0 | Page 8 of 19
Notes
Output transition begins
after dead time expires
Output transition begins
after dead time expires
Output transition begins
after dead time expires
Output transition begins
after dead time expires
Device is disabled
Output returns to input state
after VDD1 power restoration
Output remains low
Data Sheet
ADuM4221
TYPICAL PERFORMANCE CHARACTERISTICS
VIB
VOx
VIA
2
1
3
VIx
VOB
4
VOA
3
M40.0ns
A CH1
T
159.800ns
2.04V
CH1 2.00V
CH3 5.00V
CH2 2.00V
CH4 5.00V
3
3
VALUE MEAN MIN
MAX
STD DEV
962.2ns 961.6n 961.6n 962.2n 353.6p
34.27ns 34.21n 34.15n 34.27n 82.50p
4
4
M2.00µs
A CH1
T
16.0000µs
2.84V
17219-007
CH1 2.00V
CH3 5.00V
17219-004
1
Figure 4. Output Waveform for 2 nF Load and 3.9 Ω Series Gate Resistor
with 15 V Output Supply
Figure 7. Dead Time Operation Between Input and Output with 200 kΩ Dead
Time Resistor and One Input Held High
VOx
VDD1
3
3
VIx
VOx
4
M40.0ns
A CH1
T
159.800ns
2.04V
Figure 5. Output Waveform for 2 nF Load and 0 Ω Series Gate Resistor
with 15 V Output Supply
VIB
VIA
VOB
VOA
CH3 2.00V
CH4 5.00V
3
VALUE
14.33µs
4
M400µs
A CH4
T
4.00000µs
5.50V
MEAN MIN
MAX
STD DEV
14.33µ 14.33µ 14.33µ 0.000
17219-008
CH1 2.00V
CH3 5.00V
17219-005
1
Figure 8. Typical VDD1 Delay to Output Waveform, VIx = VDD1
VDD2
1, 2
3
VOx
4
3, 4
3
4
VALUE
252.1ns
252.9ns
4
3
M400ns
A CH1
T
0.0000s
2.84V
MEAN MIN
MAX
STD DEV
163.8n –37.90n 252.1n 120.6n
165.4n –22.80n 254.0n 121.5n
M400µs
A CH4
T
4.00000µs
5.50V
CH3 5.00V
CH4 5.00V
3
VALUE MEAN MIN
MAX
STD DEV
13.84µs 13.84µ 13.84µ 13.84µ 0.000
4
Figure 9. Typical VDD2 Delay to Output Waveform, VIx = VDD1
(VDD2 Refers to VDDA or VDDB)
Figure 6. Dead Time Operation Between Input and Output with 50 kΩ
Dead Time Resistor
Rev. 0 | Page 9 of 19
17219-009
CH2 2.00V
CH4 5.00V
17219-006
CH1 2.00V
CH3 5.00V
ADuM4221
Data Sheet
6.0
5.0
VDD1 = 3.3V
VDD1 = 5V
5.5
VDD2 = 5V
VDD2 = 10V
VDD2 = 15V
4.5
5.0
4.0
4.5
3.5
3.5
IDD2 (mA)
IDD1 (mA)
4.0
3.0
2.5
2.0
3.0
2.5
2.0
1.5
1.5
1.0
1.0
0
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (kHz)
0
17219-010
0
10
20
30
40
50
60
70
80
90
100
DUTY CYCLE (%)
Figure 10. VDD1 Current (IDD1) vs. Frequency for VDD1 = 3.3 V and VDD1 = 5 V,
50% Duty Cycle
Figure 13. IDD2 vs. Duty Cycle for VDD2 = 5 V, VDD2 = 10 V, and VDD2 = 15 V,
VDD1 = 5 V (VDD2 Refers to VDDA or VDDB)
40
30
VDD2 = 5V
VDD2 = 10V
VDD2 = 15V
35
RISE TIME
FALL TIME
25
RISE AND FALL TIME (ns)
30
25
IDD2 (mA)
0
17219-013
0.5
0.5
20
15
10
20
15
10
5
0
100
200
300
400
500
600
700
800
900
1000
FREQUENCY (kHz)
0
–40
17219-011
0
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 11. VDD2 Current (IDD2) vs. Frequency for VDD2 = 5 V, VDD2 = 10 V, and
VDD2 = 15 V, 50% Duty Cycle, 2 nF Load (VDD2 Refers to VDDA or VDDB)
Figure 14. Rise and Fall Time vs. Temperature with a 3.9 Ω Series Gate
Resistor for a 2 nF Load and a 15 V Output Supply
30
10
VDD1 = 2.5V
VDD1 = 5V
9
RISE TIME
FALL TIME
25
RISE AND FALL TIME (ns)
8
7
6
5
4
3
2
20
15
10
5
0
0
10
20
30
40
50
60
70
80
90
100
DUTY CYCLE (%)
Figure 12. IDD1 vs. Duty Cycle for VDD1 = 2.5 V and VDD1 = 5 V,
VDD2 = 15 V (VDD2 Refers to VDDA or VDDB)
0
5
10
15
20
25
OUTPUT SUPPLY VOLTAGE (V)
30
35
17219-015
1
17219-012
IDD1 (mA)
–20
17219-014
5
Figure 15. Rise and Fall Time vs. Output Supply Voltage with a 3.9 Ω Series
Gate Resistor for a 2 nF Load
Rev. 0 | Page 10 of 19
Data Sheet
15
30
25
20
15
10
5
0
20
40
60
80
100
120
TEMPERATURE (°C)
6
3
15
CHANNEL TO CHANNEL MATCHING (ns)
30
25
20
15
10
5
RISING
FALLING
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
INPUT SUPPLY VOLTAGE (V)
24
28
32
36
3
PEAK OUTPUT CURRENT (A)
7
25
20
15
10
–20
0
20
40
60
80
100
120
Figure 20. Channel to Channel Matching vs. Temperature, Rising and
Falling, VDD2 = 15 V (VDD2 Refers to VDDA or VDDB)
35
30
CHANNEL TO CHANNEL RISING
CHANNEL TO CHANNEL FALLING
6
8
SOURCE CURRENT
SINK CURRENT
6
5
4
3
2
1
RISING
FALLING
12
16
20
24
28
OUTPUT SUPPLY VOLTAGE (V)
32
36
0
17219-018
8
20
9
40
4
16
TEMPERATURE (°C)
Figure 17. Propagation Delay vs. Input Supply Voltage, Rising and Falling,
VDD2 = 15 V (VDD2 Refers to VDDA or VDDB)
5
12
12
0
–40
17219-017
0
2.5
8
Figure 19. Channel to Channel Matching vs. Output Supply Voltage,
Rising and Falling
35
0
4
OUTPUT SUPPLY VOLTAGE (V)
40
PROPAGATION DELAY (ns)
9
0
Figure 16. Propagation Delay vs. Temperature
PROPAGATION DELAY (ns)
12
17219-120
–20
17219-016
0
–40
CHANNEL TO CHANNEL RISING
CHANNEL TO CHANNEL FALLING
Figure 18. Propagation Delay vs. Output Supply Voltage, Rising and
Falling, VDD1 = 5 V
0
5
10
15
20
25
30
OUTPUT SUPPLY VOLTAGE (V)
35
40
17219-121
PROPAGATION DELAY (ns)
35
17219-019
RISING
FALLING
CHANNEL TO CHANNEL MATCHING (ns)
40
ADuM4221
Figure 21. Peak Output Current vs. Output Supply Voltage with a 2.2 Ω
Series Gain Resistor
Rev. 0 | Page 11 of 19
ADuM4221
0.9
0.8
1.6
0.7
1.4
RDS(ON) (Ω)
0.6
0.5
0.4
1.2
1.0
0.8
0.3
0.6
0.2
0.4
0.1
0.2
0
4
8
NMOS
PMOS
1.8
12
16
20
24
28
OUTPUT SUPPLY VOLTAGE (V)
32
36
0
–40
17219-122
RDS(ON) (Ω)
2.0
NMOS
PMOS
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 22. Output Resistance (RDS(ON)) vs. Output Supply Voltage for
NMOS and PMOS, VDD1 = 5 V
Figure 23. RDS(ON) vs. Temperature for NMOS and PMOS
Rev. 0 | Page 12 of 19
17219-123
1.0
Data Sheet
Data Sheet
ADuM4221
THEORY OF OPERATION
Gate drivers are required where fast rise times of switching
device gates are desired. The gate signal for most enhancement
type power devices is referred to a source or emitter node. The
gate driver must have the ability to follow this source or emitter
node, necessitating isolation between the controlling signal and
the output of the gate driver in topologies where the source or
emitter nodes swing, such as a half bridge. Gate switching times
are a function of the drive strength of the gate driver. Buffer
stages before a CMOS output reduce the total delay time and
increase the final drive strength of the driver.
The ADuM4221 achieves isolation between the control side and
output side of the gate driver by means of a high frequency carrier
that transmits data across the isolation barrier using iCoupler chip
scale transformer coils separated by layers of polyimide isolation.
The encoding scheme used by the ADuM4221 is a positive logic
on/off keying (OOK), a high signal transmitted by the presence of
the carrier frequency across the iCoupler chip scale transformer
coils. Positive logic encoding ensures that a low signal is seen on
the output when the input side of the gate driver is unpowered.
A low state is the most common safe state in enhancement
mode power devices, driving in situations where shoot through
conditions can exist. The architecture is designed for high
common-mode transient immunity and high immunity to
electrical noise and magnetic interference. Radiated emissions
are minimized with a spread spectrum OOK carrier and other
techniques such as differential coil layout. Figure 24 illustrates
the encoding used by the ADuM4221.
REGULATOR
REGULATOR
TRANSMITTER
RECEIVER
VOUT
GND1
GND2
Figure 24. Operational Block Diagram of OOK Encoding (VIN Is the Input Voltage, and VOUT Is the Output Voltage.)
Rev. 0 | Page 13 of 19
17219-020
VIN
ADuM4221
Data Sheet
APPLICATIONS INFORMATION
PCB LAYOUT
The ADuM4221 requires no external interface circuitry for the
logic interfaces. Power supply bypassing is required at the input
and output supply pins, as shown in Figure 25. Use a small ceramic
capacitor with a value between 0.01 μF and 0.1 μF to provide a
good high frequency bypass. On the output power supply pin,
VDDA or VDDB, it is also recommended to add a 10 μF capacitor
to provide the charge required to drive the gate capacitance at
the ADuM4221 outputs. On the output supply pin, avoid the
use of vias with a bypass capacitor or use multiple vias to
reduce the inductance in the bypassing. The total lead length
between both ends of the smaller capacitor and the input or
output power supply pin must be as short as possible.
VIA
VDDA
VIB
VOA
VDD1
GNDA
GND1
NC
DISABLE
NC
NC
PEAK CURRENT RATING
The ADuM4221 has two output channels, and each channel
connects to the gate of the power device through an external
series gate resistor. The output driver MOSFETs of the gate
driver IC can source or sink more than 6 A (per VOA and VOB). In
a practical application, to control the drive strength and to spread
the power dissipation of driving the gate to outside of the gate
driver IC, standard external series gate resistors are used. The
output current of the gate driver is shown in Figure 21 of the
Typical Performance Characteristics section.
TSD
VDDB
NC
Propagation delay skew is the maximum amount that the
propagation delay differs between multiple components
operating under the same conditions.
PROTECTION FEATURES
VOB
VDD1
GNDB
17219-021
DT
Channel to channel matching is the maximum amount that the
propagation delay differs between channels within a single
component.
Figure 25. Recommended PCB Layout
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay parameter describes the time it takes a logic
signal to propagate through a component. The propagation delay
to a logic low output can differ from the propagation delay to a
logic high output. The ADuM4221 specifies the rising edge
propagation delay (tDLH) as the time between the rising input high
logic threshold (VIH) to the output rising (tR) 10% threshold
(see Figure 26). Likewise, the falling edge propagation delay
(tDHL) is the time between the input falling logic low threshold
(VIL) and the output falling (tF) 90% threshold. The rise and fall
times are dependent on the loading conditions and are not
included in the propagation delay, which is the industry
standard for gate drivers.
90%
OUTPUT
10%
If the internal temperature of the ADuM4221 exceeds 155°C
(typical), the device enters TSD. During the TSD time, the gate
drive is disabled. When TSD occurs, the device does not leave
TSD until the internal temperature drops below 125°C
(typical), at which time, the device exits shutdown.
UVLO
The ADuM4221 has UVLO protections for both the primary
and secondary side of the device. If either the primary or
secondary side voltages are below the falling edge UVLO, the
device outputs a low signal. After the ADuM4221 is powered
above the rising edge UVLO threshold, the device outputs the
signal found at the input. To account for small voltage source
ripple, hysteresis is built into the UVLO. The primary side
UVLO thresholds are common among all models.
OUTPUT LOAD CHARACTERISTICS
The output signals depend on the characteristics of the output
load, which is typically an N channel MOSFET. The driver output
response to an N channel MOSFET load with a gate voltage
(VGATE) can be modeled with a switch output resistance (RSW),
an inductance due to the PCB trace (LTRACE), a series gate resistor
(RGATE), and a gate to source capacitance (CGS), as shown in
Figure 27.
VIH
VIA
VIL
tDLH
tR
tF
Figure 26. Propagation Delay Parameters
17219-022
tDHL
ADuM4221
VOA RSW
RGATE
LTRACE
VGATE
CGS
17219-023
INPUT
Figure 27. Resistor, Inductor, and Capacitor (RLC) Model of the Gate of an
N Channel MOSFET
Rev. 0 | Page 14 of 19
Data Sheet
ADuM4221
(RSW
2400
2100
1800
1500
1200
900
600
L
1
× TRACE
+ RGATE )
CGS
300
0
Output ringing is reduced by adding a series gate resistance to
dampen the response. The waveforms in Figure 4 show a correctly
damped example with a 2 nF load and a 3.9 Ω external series gate
resistor. The waveforms in Figure 5 show an underdamped
example with a 2 nF load and a 0 Ω external series gate resistor.
0
50
100
150
200
250
350
300
400
RDT (kΩ)
450
500
17219-124
=
Q
between the DT pin and ground (see Figure 30). The relation
between RDT and the obtained dead time is shown in Figure 28.
DEAD TIME (ns)
RSW is the switch resistance of the internal driver output, which
is approximately 2 Ω. RGATE is the intrinsic gate resistance of the
MOSFET and any external series resistance. A MOSFET that
requires a 4 A gate driver has a typical intrinsic gate resistance of
approximately 1 Ω and a CGS of between 2 nF and 10 nF. LTRACE
is the inductance of the PCB trace, typically a value of 5 nH or
less for a well designed layout with a short and wide connection
from the ADuM4221 output to the gate of the MOSFET. The
following equation defines the Q factor of the RLC circuit, which
indicates how the output responds to a step change. For a well
damped output, Q is less than 1.
Figure 28. Dead Time vs. Dead Time Resistor
Use the following equation, to calculate the required amount of
dead time:
DT (ns) ≈ 5 × RDT (kΩ)
ADJUSTABLE DEAD TIME CONTROL
The ADuM4221 includes overlap protection such that the gate
driver outputs (VOA and VOB) cannot simultaneously go high even
if both inputs are high. Additionally, the ADuM4221 also has a
dead time control pin (DT) that can adjust the delay between the
output high-side and low-side transitions by using a single resistor
The VOx pin reacts to the VIx pin depending on the dead time
value set by the RDT resistor. The DT pin controls the edge
transitions between VOA and VOB. Dead time only affects the
rising edge transition of the gate drive signal, and dead time
operation is shown in Figure 29.
VIH
VIA
VIL
VIH
VIB
VIL
DT
DT
90%
VOA
10%
DT
DT
90%
17219-029
VOB
10%
Figure 29. Dead Time Operation for Different Input Transitions
Rev. 0 | Page 15 of 19
ADuM4221
Data Sheet
BOOT STRAPPED, HALF BRIDGE OPERATION
The ADuM4221 is well suited for operating two output gate
signals referenced to separate grounds, as in the case for a half
bridge configuration. Because isolated auxiliary supplies are often
expensive, it is beneficial to reduce the amount of supplies.
One method to reduce power supplies is to use a boot strapped
configuration for the high-side supply of the ADuM4221.
In this topology, the decoupling capacitor (CA) acts as the
energy storage for the high-side supply and is filled whenever
VIA
1
the low-side switch is closed, bringing GNDA to GNDB (see
Figure 30). During the CA charging time, control the dv/dt of
the VDDA voltage to reduce the possibility of glitches on the
output. To control the dv/dt of the VDDA voltage, introduce a
series resistance (RBOOT) into the CA charging path.
Note that in Figure 30, DBOOT is the bootstrapped diode, CDD1
is the decoupling capacitor on the input side, and CB is the
decoupling capacitor for the driver low-side supply.
ADuM4221
VIB
2
VDD1
DECODE
15
VDD1
CDD1
3
14
4
13
5
12
GND1
RGA
DBOOT
CA
GNDA
NC
DT
VDD1
VOA
VBUS
NC
DISABLE
RDT
RBOOT
6
DELAY
7
ENCODE
NC
11
DECODE
10
VDD1
9
8
VDDB
VOB
VDDB
CB
GNDB
NC = NO CONNECT
Figure 30. Circuit of Bootstrapped Half Bridge Operation
Rev. 0 | Page 16 of 19
RGB
17219-024
VDD1
ENCODE
VDDA
16
Data Sheet
ADuM4221
Alternately, use the gate charge as follows:
PDISS = QG × (VDD2 − GND2) × fSW
where QG is the total gate charge of the device being driven.
This power dissipation is shared between the internal on
resistances of the internal gate driver switches and the external
gate resistances, RGON and RGOFF. The ratio of the internal gate
resistances to the total series resistance allows the calculation of
losses seen within the ADuM4221device.
PDISS_ADuM4221 = PDISS × 0.5(RDSON_P/(RGON + RDSON_P) +
0.5(RDSON_N/(RGOFF + RDSON_N))
Take the power dissipation found inside the chip and multiply
it by θJA to see the rise above ambient temperature that the
ADuM4221 experiences, then multiplied this value by two
because there are two channels.
TADuM4221 = θJA × 2 × PDISS_ADuM4221 + TA
For the device to remain within specification, TADuM4221 must
not exceed 125°C. If TADuM4221 exceeds the TSD rising edge, the
device enters TSD, and the output remains low until the TSD
falling edge is crossed.
10
1
0.1
0.01
0.001
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
17219-026
where:
CEST = CISS × 5.
fSW is the switching frequency of the IGBT.
100
Figure 31. Maximum Allowable External Magnetic Flux Density
1k
DISTANCE = 1m
100
10
DISTANCE = 100mm
1
DISTANCE = 5mm
0.1
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 32. Maximum Allowable Current for Various Current to
ADuM4221 Spacings
Rev. 0 | Page 17 of 19
17219-027
PDISS = CEST × (VDD2 − GND2)2 × fSW
The ADuM4221 is resistant to external magnetic fields. The
limitation on the ADuM4221 magnetic field immunity is set by
the condition in which the induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset
the decoder. The following analysis defines the conditions under
which falsely sets or resets of the decoder can occur (see Figure 31
and Figure 32).
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSITY (kgauss)
When driving a MOSFET or IGBT gate, the driver must dissipate
power. This power is not insignificant and can lead to TSD if
considerations are not made. The gate of an IGBT can be
approximately simulated as a capacitive load. Due to Miller
capacitance and other nonlinearities, it is common practice to
take the stated input capacitance of a given MOSFET or IGBT,
CISS, and multiply this capacitance by a factor of 3 to 5 to arrive
at a conservative estimate of the approximate load being driven.
With this value, the estimated total power dissipation in the
system due to the switching action is given by
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
MAXIMUM ALLOWABLE CURRENT (kA)
POWER DISSIPATION
ADuM4221
Data Sheet
The voltage presented in Figure 34 is shown as sinusoidal for
illustration purposes only. This voltage is meant to represent
any voltage waveform varying between 0 V and some limiting
value. The limiting value can be positive or negative, but the
voltage cannot cross 0 V.
The values detailed in Table 9 summarize the peak voltage for
20 years of service life for a bipolar ac operating condition,
and the maximum CSA and VDE approved working voltages.
In many cases, the approved working voltage is higher than
the 20 year service life voltage. Operation at these high working
voltages can lead to shortened insulation life in some cases.
The insulation lifetime of the ADuM4221 depends on the
voltage waveform type imposed across the isolation barrier.
The iCoupler insulation structure degrades at different rates
depending on whether the waveform is bipolar ac, unipolar ac,
or dc. Figure 33, Figure 34, and Figure 35 illustrate these
different isolation voltage waveforms.
A bipolar ac voltage environment is the worst condition for
iCoupler products and is the 20 year operating lifetime that
Rev. 0 | Page 18 of 19
RATED PEAK VOLTAGE
17219-033
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage.
0V
Figure 33. Bipolar AC Waveform
RATED PEAK VOLTAGE
17219-034
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of
the voltage waveform applied across the insulation. In addition
to the testing performed by regulatory agencies, Analog Devices
carries out an extensive set of evaluations to determine the
lifetime of the insulation structure within the ADuM4221.
Analog Devices recommends for the maximum working
voltage. In the case of unipolar ac or dc voltage, the stress on
the insulation is significantly lower. Unipolar ac or dc voltage
operation allows operation at higher working voltages while
still achieving a 20 year service life. Any cross insulation voltage
waveform that does not conform to Figure 34 or Figure 35 must
be treated as a bipolar ac waveform, and its peak voltage must
be limited to the 20 year lifetime voltage value listed in Table 9.
0V
Figure 34. Unipolar AC Waveform
RATED PEAK VOLTAGE
17219-035
INSULATION LIFETIME
0V
Figure 35. DC Waveform
Data Sheet
ADuM4221
OUTLINE DIMENSIONS
12.95
12.80
12.65
9
16
7.60
7.50
7.40
1
10.55
10.30
10.05
8
PIN 1
INDICATOR
TOP VIEW
2.44
2.24
0.33
0.23
END VIEW
SEATING
PLANE
1.27 BSC
0.49
0.35
8°
0°
1.27
0.41
12-13-2017-B
PKG-004586
0.25
0.10
COPLANARITY
0.10
SIDE VIEW
0.76
45°
0.25
0.25 BSC
GAGE
PLANE
2.64
2.50
2.36
COMPLIANT TO JEDEC STANDARDS MS-013-AC
Figure 36. 16-Lead Standard Small Outline Package with Increased Creepage [SOIC_IC]
(RI-16-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADuM4221ARIZ
ADuM4221ARIZ-RL
Inputs
VIA, VIB
VIA, VIB
Minimum
Output Voltage (V)
4.5
4.5
Adjustable
Dead Time
Yes
Yes
Temperature
Range
−40°C to +125°C
−40°C to +125°C
ADuM4221BRIZ
ADuM4221BRIZ-RL
VIA, VIB
VIA, VIB
7.5
7.5
Yes
Yes
−40°C to +125°C
−40°C to +125°C
ADuM4221CRIZ
ADuM4221CRIZ-RL
VIA, VIB
VIA, VIB
11.6
11.6
Yes
Yes
−40°C to +125°C
−40°C to +125°C
EVAL-ADuM4221EBZ
1
Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D17219-7/20(0)
Rev. 0 | Page 19 of 19
Package
Description
16-Lead SOIC_IC
16-Lead SOIC_IC,
13” Tape and Reel
16-Lead SOIC_IC
16-Lead SOIC_IC,
13” Tape and Reel
16-Lead SOIC_IC
16-Lead SOIC_IC,
13” Tape and Reel
Evaluation Board
Package
Option
RI-16-2
RI-16-2
Ordering
Quantity
1
1,000
RI-16-2
RI-16-2
1
1,000
RI-16-2
RI-16-2
1
1,000
工商网监
湘ICP备2023018690号
