1 kV RMS Quad-Channel Digital Isolators
ADuM7440/ADuM7441/ADuM7442
Data Sheet
FEATURES
GENERAL DESCRIPTION
Small, 16-lead QSOP
1000 V rms isolation rating
Safety and regulatory approvals
UL recognition
UL 1577: 1000 V rms for 1 minute
Low power operation
5 V operation
2.25 mA per channel maximum at 0 Mbps to 1 Mbps
11.5 mA per channel maximum at 25 Mbps
3.3 V operation
1.5 mA per channel maximum at 0 Mbps to 1 Mbps
8.25 mA per channel maximum at 25 Mbps
Bidirectional communication
Up to 25 Mbps data rate (NRZ)
3 V/5 V level translation
High temperature operation: 105°C
High common-mode transient immunity: >15 kV/μs
The ADuM7440/ADuM7441/ADuM74421 are 4-channel digital
isolators based on the Analog Devices, Inc., iCoupler® technology.
Combining high speed CMOS and monolithic air core transformer
technologies, these isolation components provide outstanding
performance characteristics superior to the alternatives, such as
optocoupler devices and other integrated couplers.
The ADuM7440/ADuM7441/ADuM7442 family of quad 1 kV
digital isolation devices is packaged in a small 16-lead QSOP.
While most 4-channel isolators come in 16-lead wide SOIC
packages, the ADuM7440/ADuM7441/ADuM7442 free almost
70% of board space and yet can still withstand high isolation
voltage and meet UL regulatory requirements. In addition to the
space savings, the ADuM7440/ADuM7441/ADuM7442 offer a
lower price than 2.5 kV or 5 kV isolators where only functional
isolation is needed.
This family, like many Analog Devices isolators, offers very low
power consumption, consuming one-tenth to one-sixth the
power of comparable isolators at comparable data rates up to
25 Mbps. Despite the low power consumption, all models of the
ADuM7440/ADuM7441/ADuM7442 provide low pulse width
distortion ( 0.8 VDD. The common-mode voltage slew rates apply to both rising and falling
common-mode voltage edges.
Rev. D | Page 3 of 20
ADuM7440/ADuM7441/ADuM7442
Data Sheet
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 4.
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew1
Channel Matching
Codirectional
Opposing-Direction
Jitter
1
Min
Symbol
tPHL, tPLH
PWD
A Grade
Typ
Max
1
85
25
60
10
5
PW
tPSK
Min
37
250
C Grade
Typ
Max
25
66
5
51
2
3
40
20
tPSKCD
tPSKOD
10
25
30
3
4
2
2
5
7
Unit
Test Conditions/Comments
Mbps
ns
ns
ps/°C
ns
ns
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Within PWD limit
ns
ns
ns
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
Table 5.
Parameter
SUPPLY CURRENT
ADuM7440
ADuM7441
ADuM7442
Symbol
1 Mbps—A, C Grades
Min
Typ
Max
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
3.0
1.8
2.8
2.5
2.2
2.2
Min
25 Mbps—C Grade
Typ
Max
3.8
2.3
3.5
3.3
2.7
2.8
20
4.0
14
5.5
10
8.4
Unit
28
5.0
20
7.5
13
11
Test Conditions/Comments
mA
mA
mA
mA
mA
mA
Table 6. For All Models
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Input Current per Channel
Supply Current per Channel
Quiescent Input Supply Current
Quiescent Output Supply Current
Dynamic Input Supply Current
Dynamic Output Supply Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity1
Refresh Rate
1
Symbol
Min
VIH
VIL
VOH
0.7 VDDx
−10
IDDI(Q)
IDDO(Q)
IDDI(D)
IDDO(D)
tR/tF
|CM|
fr
Max
0.3 VDDx
VDDx − 0.2
VDDx − 0.4
VOL
II
Typ
15
3.3
3.1
0.0
0.2
+0.01
0.1
0.4
+10
Unit
Test Conditions/Comments
V
V
V
V
V
V
µA
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
0 V ≤ VIx ≤ VDDx
0.50
0.41
0.18
0.02
mA
mA
mA/Mbps
mA/Mbps
2.8
20
ns
kV/µs
1.1
Mbps
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both
rising and falling common-mode voltage edges.
Rev. D | Page 4 of 20
Data Sheet
ADuM7440/ADuM7441/ADuM7442
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 5 V, VDD2 = 3.3 V. Minimum/maximum specifications apply over the entire recommended
operation range of 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V; and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 7.
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew1
Channel Matching
Codirectional
Opposing-Direction
Jitter
1
Min
Symbol
tPHL, tPLH
PWD
A Grade
Typ
Max
1
80
25
55
10
5
PW
tPSK
C Grade
Typ
Max
Min
30
250
25
55
5
42
2
3
40
20
tPSKCD
tPSKOD
10
25
30
2
3
2
2
5
6
Unit
Test Conditions/Comments
Mbps
ns
ns
ps/°C
ns
ns
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Within PWD limit
ns
ns
ns
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
Table 8.
Parameter
SUPPLY CURRENT
ADuM7440
ADuM7441
ADuM7442
Symbol
1 Mbps—A, C Grades
Min
Typ
Max
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
4.4
1.6
3.7
2.2
3.2
2.0
25 Mbps—C Grade
Min
Typ
Max
5.5
2.1
5.0
2.8
3.9
2.6
28
3.5
19
5.2
15
7.8
Unit
35
4.5
27
7.0
20
12
Test Conditions/Comments
mA
mA
mA
mA
mA
mA
Table 9. For All Models
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Input Current per Channel
Supply Current per Channel
Quiescent Input Supply Current
Quiescent Output Supply Current
Dynamic Input Supply Current
Dynamic Output Supply Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity1
Refresh Rate
1
Symbol
Min
VIH
VIL
VOH
0.7 VDDx
VDDx − 0.1
VDDx − 0.4
−10
IDDI(Q)
IDDO(Q)
IDDI(D)
IDDO(D)
tR/tF
|CM|
fr
Max
0.3 VDDx
VOL
II
Typ
15
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.1
0.4
+10
Unit
Test Conditions/Comments
V
V
V
V
V
V
µA
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
0 V ≤ VIx ≤ VDDx
0.77
0.40
0.26
0.02
mA
mA
mA/Mbps
mA/Mbps
2.5
20
ns
kV/µs
1.2
Mbps
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both
rising and falling common-mode voltage edges.
Rev. D | Page 5 of 20
ADuM7440/ADuM7441/ADuM7442
Data Sheet
ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 3.3 V, VDD2 = 5 V. Minimum/maximum specifications apply over the entire recommended
operation range of 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +105°C, unless otherwise noted. Switching specifications
are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 10.
Parameter
SWITCHING SPECIFICATIONS
Data Rate
Propagation Delay
Pulse Width Distortion
Change vs. Temperature
Pulse Width
Propagation Delay Skew1
Channel Matching
Codirectional
Opposing-Direction
Jitter
1
Symbol
Min
tPHL, tPLH
PWD
A Grade
Typ
Max
1
80
25
55
10
5
PW
tPSK
250
C Grade
Typ
Max
Min
31
25
60
5
46
2
3
40
20
tPSKCD
tPSKOD
10
25
30
2
3
2
2
5
7
Unit
Test Conditions/Comments
Mbps
ns
ns
ps/°C
ns
ns
Within PWD limit
50% input to 50% output
|tPLH − tPHL|
Within PWD limit
ns
ns
ns
tPSK is the magnitude of the worst-case difference in tPHL or tPLH that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
Table 11.
Parameter
SUPPLY CURRENT
ADuM7440
ADuM7441
ADuM7442
Symbol
1 Mbps—A, C Grades
Min
Typ
Max
IDD1
IDD2
IDD1
IDD2
IDD1
IDD2
2.7
2.5
2.5
3.6
2.0
3.2
3.3
3.3
3.3
4.6
2.4
4.0
Symbol
Min
VIH
VIL
VOH
0.7 VDDx
25 Mbps—C Grade
Min
Typ
Max
18
5.7
12
8.0
8.9
12
24
8.0
20
11
13
15
Unit
Test Conditions/Comments
mA
mA
mA
mA
mA
mA
Table 12. For All Models
Parameter
DC SPECIFICATIONS
Logic High Input Threshold
Logic Low Input Threshold
Logic High Output Voltages
Logic Low Output Voltages
Input Current per Channel
Supply Current per Channel
Quiescent Input Supply Current
Quiescent Output Supply Current
Dynamic Input Supply Current
Dynamic Output Supply Current
AC SPECIFICATIONS
Output Rise/Fall Time
Common-Mode Transient Immunity1
Refresh Rate
1
VDDx − 0.1
VDDx − 0.4
−10
IDDI(Q)
IDDO(Q)
IDDI(D)
IDDO(D)
tR/tF
|CM|
fr
Max
0.3 VDDx
VOL
II
Typ
VDDx
VDDx − 0.2
0.0
0.2
+0.01
0.50
0.61
0.17
0.03
15
0.1
0.4
+10
0.60
0.73
Unit
Test Conditions/Comments
V
V
V
V
V
V
µA
IOx = −20 µA, VIx = VIxH
IOx = −4 mA, VIx = VIxH
IOx = 20 µA, VIx = VIxL
IOx = 4 mA, VIx = VIxL
0 V ≤ VIx ≤ VDDx
mA
mA
mA/Mbps
mA/Mbps
2.5
20
ns
kV/µs
1.1
Mbps
10% to 90%
VIx = VDDx, VCM = 1000 V,
transient magnitude = 800 V
|CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD. The common-mode voltage slew rates apply to both
rising and falling common-mode voltage edges.
Rev. D | Page 6 of 20
Data Sheet
ADuM7440/ADuM7441/ADuM7442
PACKAGE CHARACTERISTICS
Table 13.
Parameter
Resistance (Input-to-Output)1
Capacitance (Input-to-Output)1
Input Capacitance2
IC Junction-to-Ambient Thermal
Resistance
1
2
Symbol
RI-O
CI-O
CI
θJA
Min
Typ
1013
2
4.0
76
Max
Unit
Ω
pF
pF
°C/W
Test Conditions/Comments
f = 1 MHz
Thermocouple located at center of package
underside
The device is considered a 2-terminal device: Pin 1 through Pin 8 are shorted together and Pin 9 through Pin 16 are shorted together.
Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM7440/ADuM7441/ADuM7442 are approved by the organization listed in Table 14. See Table 18 and the Insulation Lifetime
section for recommended maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 14.
UL
Recognized under UL 1577 Component Recognition Program1
Single Protection, 1000 V rms Isolation Voltage
File E214100
1
In accordance with UL 1577, each ADuM7440/ADuM7441/ADuM7442 is proof tested by applying an insulation test voltage ≥1200 V rms for 1 sec (current leakage
detection limit = 5 µA).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 15.
Symbol
L(I01)
Value
1000
3.8
Unit
V rms
mm min
Minimum External Tracking (Creepage)
L(I02)
2.8
mm min
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index)
Isolation Group
CTI
2.6
>175
IIIa
μm min
V
Test Conditions/Comments
1-minute duration
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
350
RECOMMENDED OPERATING CONDITIONS
300
Table 16.
Parameter
Operating Temperature
Supply Voltages1
Input Signal Rise and Fall Times
250
200
150
1
100
50
0
0
50
100
150
CASE TEMPERATURE (°C)
200
Symbol
TA
VDD1, VDD2
Min
−40
3.0
Max
+105
5.5
1.0
Unit
°C
V
ms
All voltages are relative to their respective ground. See the DC Correctness
and Magnetic Field Immunity section for information on immunity to external
magnetic fields.
08340-007
SAFETY-LIMITING CURRENT (mA)
Parameter
Rated Dielectric Insulation Voltage
Minimum External Air Gap (Clearance)
Figure 4. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per DIN V VDE V 0884-10
Rev. D | Page 7 of 20
ADuM7440/ADuM7441/ADuM7442
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 17.
Parameter
Storage Temperature (TST) Range
Ambient Operating Temperature (TA)
Supply Voltages (VDD1, VDD2)
Input Voltages (VIA, VIB, VIC, VID)1, 2
Output Voltages (VOA, VOB, VOC, VOD)1, 2
Average Output Current per Pin3
Side 1 (IO1)
Side 2 (IO2)
Common-Mode Transients3
Rating
−65°C to +150°C
−40°C to +105°C
−0.5 V to +7.0 V
−0.5 V to VDDI + 0.5 V
−0.5 V to VDDO + 0.5 V
ESD CAUTION
−10 mA to +10 mA
−10 mA to +10 mA
−100 kV/μs to +100 kV/μs
1
VDDI and VDDO refer to the supply voltages on the input and output sides of a
given channel, respectively. See the Printed Circuit Board (PCB) Layout section.
2
See Figure 4 for maximum rated current values for various temperatures.
3
Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause
latch-up or permanent damage.
Table 18. Maximum Continuous Working Voltage1
Parameter
AC Voltage, Bipolar Waveform
AC Voltage, Unipolar Waveform
Basic Insulation
DC Voltage
Basic Insulation
1
Max
420
Unit
V peak
Constraint
50-year minimum lifetime
420
V peak
50-year minimum lifetime
420
V peak
50-year minimum lifetime
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Table 19. Truth Table (Positive Logic)
VIx Input1
H
L
X
VDDI State2
Powered
Powered
Unpowered
VDDO State3
Powered
Powered
Powered
VOx Output1
H
L
H
X
Powered
Unpowered
Z
Description
Normal operation; data is high.
Normal operation; data is low.
Input unpowered. Outputs are in the default high state. Outputs return to
input state within 1 μs of VDDI power restoration. See the pin function
descriptions (Table 20 through Table 22) for more details.
Output unpowered. Output pins are in high impedance state. Outputs
return to input state within 1 μs of VDDO power restoration. See the pin function
descriptions (Table 20 through Table 22) for more details.
1
VIx and VOx refer to the input and output signals of a given channel (A, B, C, or D).
VDDI refers to the power supply on the input side of a given channel (A, B, C, or D).
3
VDDO refers to the power supply on the output side of a given channel (A, B, C, or D).
2
Rev. D | Page 8 of 20
Data Sheet
ADuM7440/ADuM7441/ADuM7442
VDD1A 1
16
VDD2A
GND1* 2
15
GND2*
VIA 3
ADuM7440
14
VOA
VIB 4
TOP VIEW
(Not to Scale)
13
VOB
12
VOC
VID 6
11
VOD
VDD1B 7
10
VDD2B
GND1* 8
9
GND2*
VIC 5
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
08340-004
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. ADuM7440 Pin Configuration
Table 20. ADuM7440 Pin Function Descriptions
Pin No.
1
Mnemonic
VDD1A
2
GND1
3
4
5
6
7
VIA
VIB
VIC
VID
VDD1B
8
GND1
9
GND2
10
VDD2B
11
12
13
14
15
VOD
VOC
VOB
VOA
GND2
16
VDD2A
Description
Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic
bypass capacitor of value 0.01 μF to 0.1 μF between VDD1A (Pin 1) and GND1 (Pin 2).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Input D.
Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic
bypass capacitor of value 0.01 μF to 0.1 μF between VDD1B (Pin 7) and GND1 (Pin 8).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic
bypass capacitor of value 0.01 μF to 0.1 μF between VDD2B (Pin 10) and GND2 (Pin 9).
Logic Output D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a
ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD2A (Pin 16) and GND2 (Pin 15).
Rev. D | Page 9 of 20
Data Sheet
VDD1A 1
16
VDD2A
GND1* 2
15
GND2*
VIA 3
ADuM7441
14
VOA
VIB 4
TOP VIEW
(Not to Scale)
13
VOB
12
VOC
VOD 6
11
VID
VDD1B 7
10
VDD2B
GND1* 8
9
GND2*
VIC 5
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
08340-005
ADuM7440/ADuM7441/ADuM7442
Figure 6. ADuM7441 Pin Configuration
Table 21. ADuM7441 Pin Function Descriptions
Pin No.
1
Mnemonic
VDD1A
2
GND1
3
4
5
6
7
VIA
VIB
VIC
VOD
VDD1B
8
GND1
9
GND2
10
VDD2B
11
12
13
14
15
VID
VOC
VOB
VOA
GND2
16
VDD2A
Description
Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic
bypass capacitor of value 0.01 μF to 0.1 μF between VDD1A (Pin 1) and GND1 (Pin 2).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Logic Input A.
Logic Input B.
Logic Input C.
Logic Output D.
Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic
bypass capacitor of value 0.01 μF to 0.1 μF between VDD1B (Pin 7) and GND1 (Pin 8).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic
bypass capacitor of value 0.01 μF to 0.1 μF between VDD2B (Pin 10) and GND2 (Pin 9).
Logic Input D.
Logic Output C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a
ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD2A (Pin 16) and GND2 (Pin 15).
Rev. D | Page 10 of 20
ADuM7440/ADuM7441/ADuM7442
VDD1A 1
16
VDD2A
GND1* 2
15
GND2*
VIA 3
ADuM7442
14
VOA
VIB 4
TOP VIEW
(Not to Scale)
13
VOB
12
VIC
VOD 6
11
VID
VDD1B 7
10
VDD2B
GND1* 8
9
GND2*
VOC 5
*PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. CONNECTING BOTH
TO GND1 IS RECOMMENDED. PIN 9 AND PIN 15 ARE INTERNALLY
CONNECTED. CONNECTING BOTH TO GND2 IS RECOMMENDED.
08340-006
Data Sheet
Figure 7. ADuM7442 Pin Configuration
Table 22. ADuM7442 Pin Function Descriptions
Pin No.
1
Mnemonic
VDD1A
2
GND1
3
4
5
6
7
VIA
VIB
VOC
VOD
VDD1B
8
GND1
9
GND2
10
VDD2B
11
12
13
14
15
VID
VIC
VOB
VOA
GND2
16
VDD2A
Description
Supply Voltage A for Isolator Side 1 (3.0 V to 5.5 V). Pin 1 must be connected externally to Pin 7. Connect a ceramic
bypass capacitor of value 0.01 μF to 0.1 μF between VDD1A (Pin 1) and GND1 (Pin 2).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Logic Input A.
Logic Input B.
Logic Output C.
Logic Output D.
Supply Voltage B for Isolator Side 1 (3.0 V to 5.5 V). Pin 7 must be connected externally to Pin 1. Connect a ceramic
bypass capacitor of value 0.01 μF to 0.1 μF between VDD1B (Pin 7) and GND1 (Pin 8).
Ground 1. Ground reference for Isolator Side 1. Pin 2 and Pin 8 are internally connected, and connecting both to GND1 is
recommended.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Supply Voltage B for Isolator Side 2 (3.0 V to 5.5 V). Pin 10 must be connected externally to Pin 16. Connect a ceramic
bypass capacitor of value 0.01 μF to 0.1 μF between VDD2B (Pin 10) and GND2 (Pin 9).
Logic Input D.
Logic Input C.
Logic Output B.
Logic Output A.
Ground 2. Ground reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected, and connecting both to GND2 is
recommended.
Supply Voltage A for Isolator Side 2 (3.0 V to 5.5 V). Pin 16 must be connected externally to Pin 10. Connect a
ceramic bypass capacitor of value 0.01 μF to 0.1 μF between VDD2A (Pin 16) and GND2 (Pin 15).
Rev. D | Page 11 of 20
ADuM7440/ADuM7441/ADuM7442
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
10
35
30
8
CURRENT (mA)
CURRENT (mA)
25
6
5V
4
3V
5V
20
15
3V
10
2
0
5
10
15
20
25
30
0
08340-015
DATA RATE (Mbps)
10
15
20
25
30
Figure 11. Typical ADuM7440 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
10
4
8
CURRENT (mA)
3
CURRENT (mA)
5
DATA RATE (Mbps)
Figure 8. Typical Supply Current per Input Channel vs. Data Rate
for 5 V and 3 V Operation
2
5V
6
5V
4
3V
1
2
3V
0
5
10
15
20
25
30
DATA RATE (Mbps)
0
08340-016
0
0
0
5
10
15
20
25
30
DATA RATE (Mbps)
Figure 9. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3 V Operation (No Output Load)
08340-019
0
08340-018
5
Figure 12. Typical ADuM7440 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
4
35
30
25
CURRENT (mA)
CURRENT (mA)
3
5V
2
3V
20
5V
15
3V
10
1
0
5
10
15
20
25
30
0
DATA RATE (Mbps)
0
5
10
15
20
25
30
DATA RATE (Mbps)
Figure 13. Typical ADuM7441 VDD1 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Figure 10. Typical Supply Current per Output Channel vs. Data Rate
for 5 V and 3 V Operation (15 pF Output Load)
Rev. D | Page 12 of 20
08340-020
0
08340-017
5
ADuM7440/ADuM7441/ADuM7442
25
8
20
CURRENT (mA)
10
6
5V
4
3V
5V
10
5
0
5
10
15
20
25
30
DATA RATE (Mbps)
Figure 14. Typical ADuM7441 VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
0
0
5
10
15
20
DATA RATE (Mbps)
25
30
08340-022
0
15
3V
2
08340-021
CURRENT (mA)
Data Sheet
Figure 15. Typical ADuM7442 VDD1 or VDD2 Supply Current vs. Data Rate
for 5 V and 3 V Operation
Rev. D | Page 13 of 20
ADuM7440/ADuM7441/ADuM7442
Data Sheet
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD (PCB) LAYOUT
VDD2A
GND2
VOA
VOB
VOC/VIC
VOD/VID
VDD2B
GND2
VDD1A
GND1
VIA
VIB
VIC/VOC
VID/VOD
VDD1B
GND1
08340-014
The ADuM7440/ADuM7441/ADuM7442 digital isolators
require no external interface circuitry for the logic interfaces.
Power supply bypassing is strongly recommended at the input
and output supply pins (see Figure 16). A total of four bypass
capacitors should be connected between Pin 1 and Pin 2 for
VDD1A, between Pin 7 and Pin 8 for VDD1B, between Pin 9 and
Pin 10 for VDD2B, and between Pin 15 and Pin 16 for VDD2A.
Supply VDD1A Pin 1 and VDD1B Pin 7 should be connected
together and supply VDD2B Pin 10 and VDD2A Pin 16 should be
connected together. The capacitor values should be between
0.01 μF and 0.1 μF. The total lead length between both ends of
the capacitor and the power supply pin should not exceed 20 mm.
Figure 16. Recommended Printed Circuit Board Layout
In applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, users should design the board layout so that any
coupling that does occur equally affects all pins on a given
component side. Failure to ensure this can cause voltage differentials
between pins exceeding the absolute maximum ratings of the
device, thereby leading to latch-up or permanent damage.
See the AN-1109 Application Note for board layout guidelines.
PROPAGATION DELAY-RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-tooutput propagation delay time for a high-to-low transition may
differ from the propagation delay time of a low-to-high transition.
INPUT (VIx)
50%
OUTPUT (VOx)
tPHL
08340-008
tPLH
50%
Figure 17. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values and an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM7440/ADuM7441/ADuM7442 component.
Propagation delay skew refers to the maximum amount the
propagation delay differs between multiple ADuM7440/
ADuM7441/ADuM7442 components operating under the
same conditions.
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent to the decoder using the
transformer. The decoder is bistable and is, therefore, either set
or reset by the pulses, indicating input logic transitions. In the
absence of logic transitions at the input for more than ~1 μs, a
periodic set of refresh pulses indicative of the correct input state
is sent to ensure dc correctness at the output. If the decoder
receives no internal pulses of more than approximately 5 μs, the
input side is assumed to be unpowered or nonfunctional, in which
case the isolator output is forced to a default high state by the
watchdog timer circuit.
The magnetic field immunity of the ADuM7440/ADuM7441/
ADuM7442 is determined by the changing magnetic field,
which induces a voltage in the transformer’s receiving coil large
enough to either falsely set or reset the decoder. The following
analysis defines the conditions under which this can occur. The
3 V operating condition of the ADuM7440/ADuM7441/
ADuM7442 is examined because it represents the most
susceptible mode of operation.
The pulses at the transformer output have an amplitude greater
than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus
establishing a 0.5 V margin in which induced voltages can be
tolerated. The voltage induced across the receiving coil is given by
V = (−dβ / dt) ∑ π rn2; n = 1, 2, … , N
where:
β is magnetic flux density (gauss).
rn is the radius of the nth turn in the receiving coil (cm).
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM7440/
ADuM7441/ADuM7442 and an imposed requirement that the
induced voltage be, at most, 50% of the 0.5 V margin at the
decoder, a maximum allowable magnetic field at a given
frequency can be calculated. The result is shown in Figure 18.
Rev. D | Page 14 of 20
ADuM7440/ADuM7441/ADuM7442
1000
POWER CONSUMPTION
The supply current at a given channel of the ADuM7440/
ADuM7441/ADuM7442 isolator is a function of the supply
voltage, the data rate of the channel, and the output load of the
channel.
100
10
1
For each input channel, the supply current is given by
0.1
0.01
0.001
1k
10M
10k
1M
100k
MAGNETIC FIELD FREQUENCY (Hz)
100M
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.5 kgauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurred during a transmitted pulse
(and was of the worst-case polarity), it would reduce the
received pulse from >1.0 V to 0.75 V, still well above the 0.5 V
sensing threshold of the decoder.
The preceding magnetic flux density values correspond to
specific current magnitudes at given distances from the
ADuM7440/ADuM7441/ADuM7442 transformers. Figure 19
shows these allowable current magnitudes as a function of
frequency for selected distances. As shown, the ADuM7440/
ADuM7441/ADuM7442 are extremely immune and can be
affected only by extremely large currents operated at high
frequency very close to the component. For the 1 MHz example
noted previously, a 1.2 kA current would have to be placed
5 mm away from the ADuM7440/ADuM7441/ADuM7442 to
affect the operation of the component.
IDDI = IDDI (D) × (2f − fr) + IDDI (Q)
f > 0.5 fr
f ≤ 0.5 fr
IDDO = (IDDO (D) + (0.5 × 10 ) × CL × VDDO) × (2f − fr) + IDDO (Q)
f > 0.5 fr
−3
where:
IDDI (D), IDDO (D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL is the output load capacitance (pF).
VDDO is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half the input
data rate, expressed in Mbps.
fr is the input stage refresh rate (Mbps).
IDDI (Q), IDDO (Q) are the specified input and output quiescent
supply currents (mA).
To calculate the total VDD1 and VDD2 supply current, the supply
currents for each input and output channel corresponding to
VDD1 and VDD2 are calculated and totaled. Figure 8 and Figure 9
show per-channel supply currents as a function of data rate for
an unloaded output condition. Figure 10 shows the per-channel
supply current as a function of data rate for a 15 pF output
condition. Figure 11 through Figure 15 show the total VDD1 and
VDD2 supply current as a function of data rate for ADuM7440/
ADuM7441/ADuM7442 channel configurations.
INSULATION LIFETIME
1000
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation. In addition to
the testing performed by the regulatory agencies, Analog Devices
carries out an extensive set of evaluations to determine the
lifetime of the insulation structure within the ADuM7440/
ADuM7441/ADuM7442.
100
10
1
0.1
DISTANCE = 5mm
DISTANCE = 100mm
DISTANCE = 1m
1k
10k
10M
100k
1M
MAGNETIC FIELD FREQUENCY (Hz)
100M
08340-010
MAXIMUM ALLOWABLE CURRENT (kA)
f ≤ 0.5 fr
IDDO = IDDO (Q)
Figure 18. Maximum Allowable External Magnetic Flux Density
0.01
IDDI = IDDI (Q)
For each output channel, the supply current is given by
08340-009
MAXIMUM ALLOWABLE MAGNETIC FLUX (kgauss)
Data Sheet
Figure 19. Maximum Allowable Current for Various
Current-to-ADuM7440/ADuM7441/ADuM7442 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces can
induce error voltages sufficiently large enough to trigger the
thresholds of succeeding circuitry. Take care in the layout of
such traces to avoid this possibility.
Analog Devices performs accelerated life testing using voltage
levels higher than the rated continuous working voltage.
Acceleration factors for several operating conditions are
determined. These factors allow calculation of the time to
failure at the actual working voltage. The values shown in
Table 18 summarize the peak voltage for 50 years of service life
for a bipolar ac operating condition and the maximum CSA
approved working voltages. In many cases, the approved working
voltage is higher than 50-year service life voltage. Operation at
these high working voltages can lead to shortened insulation life
in some cases.
Rev. D | Page 15 of 20
ADuM7440/ADuM7441/ADuM7442
Data Sheet
Note that the voltage presented in Figure 21 is shown as sinusoidal
for illustration purposes only. It is meant to represent any voltage
waveform varying between 0 V and some limiting value. The
limiting value can be positive or negative, but the voltage cannot
cross 0 V.
In the case of unipolar ac or dc voltage, the stress on the insulation
is significantly lower. This allows operation at higher working
voltages while still achieving a 50-year service life. The working
voltages listed in Table 18 can be applied while maintaining the
50-year minimum lifetime provided the voltage conforms to
either the unipolar ac or dc voltage case. Any cross-insulation
voltage waveform that does not conform to Figure 21 or
Figure 22 should be treated as a bipolar ac waveform, and its
peak voltage should be limited to the 50-year lifetime voltage
value listed in Table 18.
Rev. D | Page 16 of 20
08340-011
0V
Figure 20. Bipolar AC Waveform
RATED PEAK VOLTAGE
08340-012
Bipolar ac voltage is the most stringent environment. The goal
of a 50-year operating lifetime under the ac bipolar condition
determines the Analog Devices recommended maximum
working voltage.
RATED PEAK VOLTAGE
0V
Figure 21. Unipolar AC Waveform
RATED PEAK VOLTAGE
08340-013
The insulation lifetime of the ADuM7440/ADuM7441/
ADuM7442 depends on the voltage waveform type imposed
across the isolation barrier. The iCoupler insulation structure
degrades at different rates depending on whether the waveform
is bipolar ac, unipolar ac, or dc. Figure 20, Figure 21, and Figure 22
illustrate these different isolation voltage waveforms.
0V
Figure 22. DC Waveform
Data Sheet
ADuM7440/ADuM7441/ADuM7442
OUTLINE DIMENSIONS
0.197 (5.00)
0.193 (4.90)
0.189 (4.80)
9
1
8
0.158 (4.01)
0.154 (3.91)
0.150 (3.81)
0.010 (0.25)
0.006 (0.15)
0.069 (1.75)
0.053 (1.35)
0.065 (1.65)
0.049 (1.25)
0.010 (0.25)
0.004 (0.10)
COPLANARITY
0.004 (0.10)
0.244 (6.20)
0.236 (5.99)
0.228 (5.79)
0.025 (0.64)
BSC
0.012 (0.30)
0.008 (0.20)
SEATING
PLANE
8°
0°
0.020 (0.51)
0.010 (0.25)
0.050 (1.27)
0.016 (0.41)
0.041 (1.04)
REF
COMPLIANT TO JEDEC STANDARDS MO-137-AB
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
09-12-2014-A
16
Figure 23. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Number
of Inputs,
Model1
VDD1 Side
ADuM7440ARQZ
4
ADuM7440ARQZ-RL7 4
Number
of Inputs,
VDD2 Side
0
0
Maximum
Data Rate
(Mbps)
1
1
Maximum
Propagation
Delay, 5 V (ns)
75
75
Maximum
Pulse Width
Distortion (ns)
25
25
Temperature
Range
−40°C to +105°C
−40°C to +105°C
ADuM7440CRQZ
ADuM7440CRQZ-RL7
4
4
0
0
25
25
50
50
5
5
−40°C to +105°C
−40°C to +105°C
ADuM7441ARQZ
ADuM7441ARQZ-RL7
3
3
1
1
1
1
75
75
25
25
−40°C to +105°C
−40°C to +105°C
ADuM7441CRQZ
ADuM7441CRQZ-RL7
3
3
1
1
25
25
50
50
5
5
−40°C to +105°C
−40°C to +105°C
ADuM7442ARQZ
ADuM7442ARQZ-RL7
2
2
2
2
1
1
75
75
25
25
−40°C to +105°C
−40°C to +105°C
ADuM7442CRQZ
ADuM7442CRQZ-RL7
2
2
2
2
25
25
50
50
5
5
−40°C to +105°C
−40°C to +105°C
1
Z = RoHS Compliant Part.
Rev. D | Page 17 of 20
Package
Description
16-Lead QSOP
16-Lead QSOP,
7” Tape and Reel
16-Lead QSOP
16-Lead QSOP,
7” Tape and Reel
16-Lead QSOP
16-Lead QSOP,
7” Tape and Reel
16-Lead QSOP
16-Lead QSOP,
7” Tape and Reel
16-Lead QSOP
16-Lead QSOP,
7” Tape and Reel
16-Lead QSOP
16-Lead QSOP,
7” Tape and Reel
Package
Option
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
ADuM7440/ADuM7441/ADuM7442
Data Sheet
NOTES
Rev. D | Page 18 of 20
Data Sheet
ADuM7440/ADuM7441/ADuM7442
NOTES
Rev. D | Page 19 of 20
ADuM7440/ADuM7441/ADuM7442
Data Sheet
NOTES
©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08340-0-10/15(D)
Rev. D | Page 20 of 20
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