ADV7182BCPZ

10-Bit, SDTV Video Decoder with Differential Inputs ADV7182 Data Sheet FEATURES RoviTM (Macrovision) copy protection detection NTSC/PAL/SECAM autodetection 8-bit ITU-R BT.656 YCrCb 4:2:2 output and HS, VS, or FIELD Full-featured VBI data slicer with teletext support (WST) Power-down mode and ultralow sleep mode current Two-wire serial MPU interface (I2C compatible) Single 1.8 V supply possible Automotive qualified models available −40°C to +105°C automotive temperature grade −40°C to +85°C industrial qualified temperature grade 32-lead, 5 mm × 5 mm, RoHS-compliant LFCSP Worldwide NTSC/PAL/SECAM color demodulation support One 10-bit analog-to-digital converter (ADC), 4× oversampling per channel for CVBS, Y/C mode, and YPrPb Four analog video input channels with on-chip antialiasing filter CVBS (composite), Y/C (S-Video), and YPrPb (component) video input support Fully differential, pseudo differential, and single-ended CVBS video input support Up to 4 V common-mode input range solution Excellent common-mode rejection capabilities Five-line adaptive comb filters and CTI/DNR video enhancement TBC functionality provided by adaptive digital line length tracking (ADLLT), signal processing, and enhanced first in, first out (FIFO) management Integrated automatic gain control (AGC) with adaptive peak white mode Video fast switch capability Adaptive contrast enhancement (ACE) Down dither (8 bits to 6 bits) APPLICATIONS Automotive infotainment DVRs for video security Media players FUNCTIONAL BLOCK DIAGRAM CLOCK PROCESSING BLOCK AIN3 AIN4 AA FILTER 2 AA FILTER 3 DIGITAL PROCESSING BLOCK + SHA – 2D COMB ADC VBI SLICER COLOR DEMOD AA FILTER 4 VS/FIELD/SFL HS I2C/CONTROL REFERENCE ADV7182 SCLK SDATA ALSB RESET PWRDWN 8-BIT PIXEL DATA P7 TO P0 INTRQ 11001-001 AIN2 10-BIT ADC LLC ACE DOWN-DITHER DIFFERENTIAL OR SINGLE-ENDED ANALOG VIDEO INPUTS MUX BLOCK AIN1 ADLLT PROCESSING FIFO AA FILTER 1 PLL OUTPUT BLOCK XTALP XTALN Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADV7182 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 SD Luma Path ............................................................................. 20 Applications ....................................................................................... 1 SD Chroma Path ......................................................................... 20 Functional Block Diagram .............................................................. 1 ACE and Dither Processing Blocks .......................................... 21 Revision History ............................................................................... 3 Sync Processing .......................................................................... 21 General Description ......................................................................... 4 VBI Data Recovery..................................................................... 21 Overview of the Analog Front End ............................................ 4 General Setup .............................................................................. 21 Overview of the Standard Definition Processor ...................... 5 Color Controls ............................................................................ 23 Specifications..................................................................................... 6 Free-Run Operation ................................................................... 25 Electrical Characteristics ............................................................. 6 Clamp Operation........................................................................ 26 Video Specifications ..................................................................... 7 Luma Filter .................................................................................. 27 Timing Specifications .................................................................. 8 Chroma Filter.............................................................................. 30 Analog Specifications ................................................................... 9 Gain Operation ........................................................................... 31 Thermal Specifications ................................................................ 9 Chroma Transient Improvement (CTI) .................................. 35 Absolute Maximum Ratings.......................................................... 10 Digital Noise Reduction (DNR) and Luma Peaking Filter ... 36 ESD Caution ................................................................................ 10 Comb Filters................................................................................ 37 Pin Configuration and Function Descriptions ........................... 11 IF Filter Compensation ............................................................. 39 Power Supply Sequencing .............................................................. 12 Adaptive Contrast Enhancement (ACE) ................................. 39 Optimal Power-Up Sequence ................................................... 12 Dither Function .......................................................................... 40 Simplified Power-Up Sequence ................................................ 12 AV Code Insertion and Controls ............................................. 41 Universal Power Supply ............................................................. 12 Synchronization Output Signals............................................... 42 Input Networks ............................................................................... 13 Sync Processing .......................................................................... 49 Single-Ended Input Network .................................................... 13 VBI Data Decode ....................................................................... 49 Differential Input Network ....................................................... 13 I2C Readback Registers .............................................................. 57 Short-to-Battery Protection Section ........................................ 13 ITU-R BT.656 Tx Configuration .................................................. 61 Analog Front End ........................................................................... 14 MPU Port Description ................................................................... 62 Input Configuration ................................................................... 14 Register Access............................................................................ 63 Analog Input Muxing ................................................................ 14 Register Programming............................................................... 63 Antialiasing Filters ..................................................................... 16 I2C Sequencer .............................................................................. 63 Global Control Registers ............................................................... 17 I2C Register Maps ........................................................................... 64 Power-Saving Modes .................................................................. 17 PCB Layout Recommendations.................................................... 94 Reset Control .............................................................................. 17 Analog Interface Inputs ............................................................. 94 Global Pin Control ..................................................................... 17 Power Supply Decoupling ......................................................... 94 Global Status Register .................................................................... 19 VREFN and VREFP ................................................................... 94 Identification ............................................................................... 19 Digital Outputs (Both Data and Clocks) ................................ 94 Status 1 ......................................................................................... 19 Digital Inputs .............................................................................. 94 Status 2 ......................................................................................... 19 Typical Circuit Connection ........................................................... 95 Status 3 ......................................................................................... 19 Outline Dimensions ....................................................................... 96 Autodetection Result.................................................................. 19 Ordering Guide .......................................................................... 96 Video Processor .............................................................................. 20 Automotive Products ................................................................. 96 Rev. C | Page 2 of 96 Data Sheet ADV7182 REVISION HISTORY 9/14—Rev. B to Rev. C Changes to Input Networks Section .............................................13 Changes to Analog Interface Inputs Section ...............................94 Changes to Figure 50 ......................................................................95 7/14—Rev. A to Rev. B Changes to Features Section ............................................................ 1 Moved Revision History ................................................................... 3 Changes to General Description Section ....................................... 4 Changes to Table 2 and Table Summary Statement ...................... 6 Changes to Table 3 Summary Statement ........................................ 7 Change to Table 4 Summary Statement ......................................... 8 Change to Table 5 Summary Statement ......................................... 9 Changes to Table 7 ..........................................................................10 Changes to Power Supply Sequencing Section and Figure 5.....12 Changes to Input Networks Section and Figure 7 ......................13 Change to Antialiasing Filters Section .........................................16 Changes to Global Pin Control Section .......................................17 Changes to Table 16 ........................................................................19 Changes to Free-Run Operation Section .....................................25 Changes to Clamp Operation Section ..........................................26 Changes to Chroma Filter Section ................................................30 Changes to Gain Operation Section ............................................. 32 Changes to Comb Filters Section .................................................. 37 Changed Pixel Port Configuration Section to ITU-R BT.565 Tx Configuration Section, Moved Polarity LLC Pin Section, Added Figure 45; Renumbered Sequentially............................................ 61 Changes to Table 91 ........................................................................ 62 Changes to Header Row and Address 0x11, Table 95 ................ 68 Change to Header Row, Table 96 .................................................. 83 Changes to Ordering Guide ........................................................... 96 3/13—Rev. 0 to Rev. A Change to Features Section.............................................................. 1 Changes to General Description Section ....................................... 4 Changes to Free Run Operation Section and Table 33, Added Luma Ramp Test Pattern Section, VS_COAST_MODE[1:0], Address 0xF9[3:2] Section, and Table 34, Renumbered Sequentially ...................................................................................... 24 Changes to Register 0x14, Table 94 .............................................. 72 Changes to Register 0xF9, Table 94 .............................................. 82 1/13—Revision 0: Initial Version Rev. C | Page 3 of 96 ADV7182 Data Sheet GENERAL DESCRIPTION The ADV7182 automatically detects and converts standard analog baseband video signals compatible with worldwide NTSC, PAL, and SECAM standards into a 4:2:2 component video data stream. This video data stream is compatible with the 8-bit ITU-R BT.656 interface standard. External HS, VS, and FIELD signals can provide timing references for LCD controllers and other video ASICs. The accurate 10-bit analog-to-digital conversion provides professional quality video performance for consumer applications with true 8-bit data resolution. The analog video inputs accept both single-ended, pseudo-differential, and fully differential composite video signals as well as S-Video and YPbPr video signals, supporting a wide range of consumer and automotive video sources. The ADV7182 along with an external resistor divider provide a common-mode input range of 4 V, enabling the removal of large signal, common-mode transients present on the video lines. Common-mode rejection (CMR) values of up to 80 dB can be achieved without the need for external amplifier circuitry. The AGC and clamp restore circuitry allow an input video signal peak-to-peak range to 1.0 V at the analog video input pin of the ADV7182. Alternatively, these can be bypassed for manual settings. The ADV7182 can be protected from short-to-battery (STB) events with standard ac coupling capacitors. The ADV7182 is programmed via a two-wire, serial bidirectional port (I2C® compatible) and is fabricated in a 1.8 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7182 is provided in a space-saving LFCSP surface-mount, RoHS compliant package. The ADV7182 is available in an automotive grade that is rated over the −40°C to +105°C temperature range. This makes the ADV7182 ideal for automive applications. The ADV7182 is also available in a −40°C to +85°C temperature range, making it ideal for industrial applications. The ADV7182 is a versatile one-chip multiformat video decoder that automatically detects PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video. The ADV7182 can receive composite signals in either single-ended or differential modes. This makes the ADV7182 ideal for automotive applications. OVERVIEW OF THE ANALOG FRONT END The ADV7182 analog front end (AFE) comprises a single high speed, 10-bit ADC that digitizes the analog video signal before applying it to the standard definition processor. The AFE employs differential channels to the ADC to ensure high performance in mixed-signal applications and to enable differential CVBS to be connected directly to the ADV7182. The front end also includes a 4-channel input mux that enables multiple composite video signals to be applied to the ADV7182. Current clamps are positioned in front of the ADC to ensure that the video signal remains within the range of the converter. A resistor divider network is required before each analog input channel to ensure that the input signal is kept within the range of the ADC (see Figure 23). The choice of this resistor divider ratio provides a common-mode range of up to 4 V. Fine clamping of the video signal is performed downstream by digital fine clamping within the ADV7182. Table 1 shows the three ADC clocking rates that are determined by the video input format to be processed. These clock rates ensure 4× oversampling per channel for CVBS, Y/C, and YPrPb modes. The ADV7182 has a fully differential AFE. This allows for inherent small and large signal noise rejection, improved electromagnetic interference (EMI), and the ability to absorb ground bounce. Support is offered for both true differential and pseudodifferential signals. Table 1. ADC Clock Rates Input Format CVBS Y/C (S-Video)2 YPrPb2 1 2 ADC Clock Rate (MHz)1 57.27 114 172 Oversampling Rate per Channel 4× 4× 4× Based on a 28.63636 MHz clock input to the ADV7182. See INSEL[4:0] in Table 95 for writes needed to set Y/C (S-Video) and YPrPb modes. The ADV7182 converts these analog video formats into a digital 8-bit ITU-R BT.656 video stream. The digital video output stream of the ADV7182 interfaces easily to a wide range of MPEG encoders, codecs, mobile video processors, and Analog Devices, Inc., digital video encoders, such as the ADV7391. External HS, VS, and FIELD signals provide timing references for LCD controllers and other video ASICs. Rev. C | Page 4 of 96 Data Sheet ADV7182 OVERVIEW OF THE STANDARD DEFINITION PROCESSOR The ADV7182 is capable of decoding a large selection of baseband video signals in composite (both single-ended and differential), S-Video, and component formats. The video standards supported by the video processor include PAL B/PAL D/PAL I/PAL G/PAL H, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/NTSC J, NTSC 4.43, and SECAM B/SECAM D/SECAM G/SECAM K/SECAM L. The ADV7182 can automatically detect the video standard and process it accordingly. The ADV7182 has a five-line, superadaptive, 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to the video standard and signal quality without requiring user intervention. Video user controls such as brightness, contrast, saturation, and hue are also available with the ADV7182. The ADV7182 implements a patented ADLLT™ algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7182 to track and decode poor quality video sources such as VCRs and noisy sources from tuner outputs, VCD players, and camcorders. The ADV7182 contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. The ACE offers improved visual detail using an algorithm that automatically varies contrast levels to enhance picture detail. This enables the contrast in dark areas of an image to be increased without saturating the bright areas of an image. This is particularly useful in automotive applications, where it can be important to be able to discern objects in shaded areas. Down dithering from eight bits to six bits enables ease of design for standard LCD panels. The video processor can process a variety of VBI data services, such as closed captioning (CCAP), wide screen signaling (WSS), copy generation management system (CGMS), and teletext data slicing for world standard teletext (WST). Data is transmitted via the 8-bit video output port as ancillary data packets (ANC). The ADV7182 is fully Macrovision® certified; detection circuitry enables Type I, Type II, and Type III protection levels to be identified and reported to the user. The decoder is also fully robust to all Macrovision signal inputs. Rev. C | Page 5 of 96 ADV7182 Data Sheet SPECIFICATIONS ELECTRICAL CHARACTERISTICS AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Table 2. Parameter STATIC PERFORMANCE Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage (DVDDIO = 3.3 V) Input High Voltage (DVDDIO = 1.8 V) Input Low Voltage (DVDDIO = 3.3 V) Input Low Voltage (DVDDIO = 1.8 V) Crystal Inputs Input Leakage Current Input Leakage Current (SDATA, SCLK) Input Leakage Current (PWRDWN, ALSB) Input Capacitance DIGITAL OUTPUTS Output High Voltage (DVDDIO = 3.3 V) Output High Voltage (DVDDIO = 1.8 V) Output Low Voltage (DVDDIO = 3.3 V) Output Low Voltage (DVDDIO = 1.8 V) High Impedance Leakage Current Output Capacitance POWER REQUIREMENTS 1, 2 Digital I/O Power Supply PLL Power Supply Analog Power Supply Digital Power Supply Digital I/O Supply Current PLL Supply Current Analog Supply Current Digital Supply Current Symbol Test Conditions/Comments N INL DNL CVBS mode CVBS mode VIH VIH VIL VIL VIH VIL IIN IIN IIN CIN Typ Max Unit 10 Bits LSB LSB 2 −0.6/+0.6 2 1.2 0.4 +10 +15 +48 10 V V V V V V µA µA µA pF 0.4 0.2 10 20 V V V V µA pF 0.8 0.4 1.2 −10 −10 −10 VOH VOH VOL VOL ILEAK COUT ISOURCE = 0.4 mA ISOURCE = 0.4 mA ISINK = 3.2 mA ISINK = 1.6 mA DVDDIO PVDD AVDD DVDD IDVDDIO IPVDD IAVDD IDVDD Min 2.4 1.4 1.62 1.71 1.71 1.71 Single-ended CVBS input Differential CVBS input Single-ended CVBS fast switch Differential CVBS fast switch Y/C input YPrPb input Single-ended CVBS input Differential CVBS input Single-ended CVBS fast switch Differential CVBS fast switch Y/C input YPrPb input Rev. C | Page 6 of 96 3.3 1.8 1.8 1.8 3 12 47 69 47 69 60 75 60 66 60 66 60 60 3.63 1.89 1.89 1.89 V V V V mA mA mA mA mA mA mA mA mA mA mA mA mA mA Data Sheet ADV7182 Parameter POWER DOWN PERFORMANCE1 Digital I/O Supply Power-Down Current PLL Supply Power-Down Current Analog Supply Power-Down Current Digital Supply Power-Down Current Total Power Dissipation in Power-Down Mode 1 2 Symbol Test Conditions/Comments Min Typ IDVDDIO IPVDD IAVDD IDVDD Max Unit 73 38 0.15 368 1 µA µA µA µA mW Guaranteed by characterization. Typical current consumption values are recorded with nominal voltage supply levels and an SMPTEBAR test pattern. VIDEO SPECIFICATIONS Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Table 3. Parameter NONLINEAR SPECIFICATIONS 1 Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front-End Crosstalk Common-Mode Rejection 2 LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range fSC Subcarrier Lock Range Color Lock-In Time Sync Depth Range Color Burst Range Vertical Lock Time Autodetection Switch Speed 3 Fast Switch Speed 4 LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy Symbol Test Conditions/Comments Min DP DG LNL CVBS input, modulate five-step CVBS input, modulate five-step CVBS input, five-step 0.9 0.5 2.0 Degrees % % Luma ramp Luma flat field 57 58 60 75 dB dB dB dB CMR Typ −5 40 Max +5 70 2 100 100 % Hz kHz Lines % % Fields Lines ms 1 1 % % ±1.3 60 20 5 CVBS, 1 V input CVBS, 1 V input 1 Unit 200 200 These specifications apply for all CVBS input types (NTSC, PAL, SECAM) as well as for single-ended and differential CVBS inputs. The common-mode rejection (CMR) of this circuit design is critically dependent on the external resistor matching on its inputs. This measurement was performed with 0.1% tolerant resistors, a common-mode voltage of 1 V, and a common-mode frequency of 10 kHz. 3 This is the time that it takes the ADV7182 to detect which video format is present at its input, for example, PAL I or NTSC M. 4 This is the time that it takes the ADV7182 to switch from one (single-ended or differential) analog input to another, for example, switching from AIN1 to AIN2. 2 Rev. C | Page 7 of 96 ADV7182 Data Sheet TIMING SPECIFICATIONS Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Table 4. Parameter SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability I2C PORT SCLK Frequency SCLK Minimum Pulse Width High SCLK Minimum Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDATA Setup Time SCLK and SDATA Rise Times SCLK and SDATA Fall Times Setup Time for Stop Condition RESET FEATURE RESET Pulse Width Symbol Test Conditions/Comments Min Typ Max Unit ±50 MHz ppm 28.63636 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 1.3 0.6 0.6 100 300 300 0.6 5 CLOCK OUTPUTS LLC Mark Space Ratio DATA AND CONTROL OUTPUTS Data Output Transitional Time t9:t10 ms 45:55 t11 55:45 Negative clock edge to start of valid data (tACCESS = t10 − t11) End of valid data to negative clock edge (tHOLD = t9 + t12) t12 Timing Diagrams t3 t5 t3 SDATA t1 t6 t4 t7 11001-003 SCLK t2 t8 Figure 2. I2C Timing t9 t10 OUTPUT LLC t11 11001-004 t12 OUTPUTS P0 TO P7, HS, VS/FIELD/SFL Figure 3. Pixel Port and Control Output Timing Rev. C | Page 8 of 96 kHz µs µs µs µs ns ns ns µs % duty cycle 3.8 ns 6.9 ns Data Sheet ADV7182 ANALOG SPECIFICATIONS Guaranteed by characterization. AVDD, DVDD, and PVDD = 1.71 V to 1.89 V; DVDDIO = 1.62 V to 3.63 V, specified at operating temperature range, unless otherwise noted. Table 5. Parameter CLAMP CIRCUITRY External Clamp Capacitor Input Impedance Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current Test Conditions/Comments Min Typ Max 0.1 10 0.32 0.32 7 7 Clamps switched off Unit µF MΩ mA mA µA µA THERMAL SPECIFICATIONS Table 6. Parameter THERMAL CHARACTERISTICS Junction-to-Ambient Thermal Resistance (Still Air) Junction-to-Case Thermal Resistance Symbol Test Conditions/Comments θJA 4-layer printed circuit board (PCB) with solid ground plane, 32-lead LFCSP 4-layer PCB with solid ground plane, 32-lead LFCSP θJC Rev. C | Page 9 of 96 Min Typ Max Unit 32.5 °C/W 2.3 °C/W ADV7182 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 7. Parameter1 AVDD to GND DVDD to GND PVDD to GND DVDDIO to GND PVDD to DVDD AVDD to DVDD Digital Inputs Voltage Digital Outputs Voltage Analog Inputs to Ground Maximum Junction Temperature (TJ max) Storage Temperature Range Infrared Reflow Soldering (20 sec) 1 Rating 2.2 V 2.2 V 2.2 V 4V −0.9 V to +0.9 V −0.9 V to +0.9 V GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to DVDDIO + 0.3 V GND − 0.3 V to AVDD + 0.3 V 140°C This device is a high performance integrated circuit with an ESD rating of