ADV7184

Multiformat SDTV Video Decoder with Fast Switch Overlay Support ADV7184 FEATURES Multiformat video decoder supports NTSC-(J, M, 4.43), PAL-(B/D/G/H/I/M/N), SECAM Integrates four 54 MHz, 10-bit ADCs SCART fast blank support Clocked from a single 28.63636 MHz crystal Line-locked clock-compatible (LLC) Adaptive digital line length tracking (ADLLT™), signal processing, and enhanced FIFO management give mini TBC functionality 5-line adaptive comb filters Proprietary architecture for locking to weak, noisy, and unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated AGC with adaptive peak white mode Macrovision® copy protection detection CTI (chroma transient improvement) DNR (digital noise reduction) Multiple programmable analog input formats CVBS (composite video) S-Video (Y/C) YPrPb component (VESA, MII, SMPTE, and Betacam) 12 analog video input channels Integrated antialiasing filters Automatic NTSC/PAL/SECAM identification Programmable interrupt request output pin Digital output formats (8-bit or 16-bit) ITU-R BT.656 YCrCb 4:2:2 output + HS, VS, and FIELD 0.5 V to 1.6 V analog signal input range Differential gain: 0.5% typ Differential phase: 0.5° typ Programmable video controls Peak white/hue/brightness/saturation/contrast Integrated on-chip video timing generator Free-run mode (generates stable video output with no I/P) VBI decode support for closed captioning (including XDS), WSS, CGMS, Gemstar® 1×/2×, Teletext, VITC, VPS Power-down mode 2-wire serial MPU interface (I2C®-compatible) 3.3 V analog, 1.8 V digital core; 3.3 V IO supply Industrial temperature grade: –40°C to +85°C 80-lead LQFP Pb-free package APPLICATIONS DVD recorders Video projectors HDD-based PVRs/DVDRs LCD TVs Set-top boxes Security systems Digital televisions AVR receivers GENERAL DESCRIPTION The ADV7184 integrated video decoder automatically detects and converts a standard analog baseband television signal, which is compatible with worldwide standards NTSC, PAL, and SECAM, into 4:2:2 component video data-compatible with 16-bit or 8-bit CCIR601/CCIR656. The advanced and highly flexible digital output interface enables performance video decoding and conversion in linelocked clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security and surveillance cameras, and professional systems. The 10-bit accurate ADC provides professional quality video performance and is unmatched. This allows true 8-bit resolution in the 8-bit output mode. The 12 analog input channels accept standard composite, S-Video, and YPrPb video signals in an extensive number of combinations. AGC and clamp restore circuitry allow an input video signal peak-to-peak range of 0.5 V to 1.6 V. Alternatively, these can be bypassed for manual settings. The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise, accurate sampling and digital filtering. The line locked clock output allows the output data rate, timing signals, and output clock signals to be synchronous, asynchronous, or line locked even with ±5% line length variation. The output control signals allow glueless interface connections in almost any application. The ADV7184 modes are set up over a 2-wire, serial, bidirectional port (I2Ccompatible). SCART and overlay functionality are enabled by the ADV7184’s ability to simultaneously process CVBS and standard definition RGB signals. Signal mixing is controlled by the fast blank pin. The ADV7184 is fabricated in a 3.3 V CMOS process. Its monolithic CMOS construction ensures greater functionality with lower power dissipation. The ADV7184 is packaged in a small 80-lead LQFP Pb-free package. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved. ADV7184 TABLE OF CONTENTS Introduction ...................................................................................... 4 Analog Front End ......................................................................... 4 Standard Definition Processor (SDP)........................................ 4 Electrical Characteristics ................................................................. 5 Video Specifications..................................................................... 6 Timing Specifications .................................................................. 7 Analog Specifications................................................................... 7 Thermal Specifications ................................................................ 8 Timing Diagrams.......................................................................... 8 Absolute Maximum Ratings............................................................ 9 Package Thermal Performance................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Analog Front End ........................................................................... 12 Analog Input Muxing ................................................................ 12 Manual Input Muxing................................................................ 14 XTAL Clock Input Pin Functionality....................................... 15 28.63636 MHz Crystal Operation ............................................ 15 Antialiasing Filters ..................................................................... 15 SCART and Fast Blanking......................................................... 15 Fast Blank Control...................................................................... 16 Readback of FB Pin Status......................................................... 18 Global Control Registers ............................................................... 19 Power-Save Modes...................................................................... 19 Reset Control .............................................................................. 19 Global Pin Control ..................................................................... 19 Global Status Registers................................................................... 21 Standard Definition Processor (SDP).......................................... 22 SD Luma Path ............................................................................. 22 SD Chroma Path......................................................................... 22 Sync Processing........................................................................... 23 VBI Data Recovery..................................................................... 23 General Setup.............................................................................. 23 Color Controls ............................................................................ 25 Clamp Operation........................................................................ 27 Luma Filter .................................................................................. 28 Chroma Filter.............................................................................. 31 Gain Operation........................................................................... 31 Chroma Transient Improvement (CTI) .................................. 34 Digital Noise Reduction (DNR), and Luma Peaking Filter .. 35 Comb Filters................................................................................ 36 AV Code Insertion and Controls ............................................. 39 Synchronization Output Signals............................................... 40 Sync Processing .......................................................................... 48 VBI Data Decode ....................................................................... 48 I2C Readback registers ............................................................... 57 Pixel Port Configuration ............................................................... 71 MPU Port Description................................................................... 72 Register Accesses ........................................................................ 73 Register Programming............................................................... 73 I2C Sequencer.............................................................................. 73 I2C Register Maps ........................................................................... 74 User Map ..................................................................................... 74 User Sub Map.............................................................................. 90 I2C Programming Examples.......................................................... 99 Mode 1 CVBS Input................................................................... 99 Mode 2 S-Video Input ............................................................. 100 Mode 3 525i/625i YPrPb Input .............................................. 101 Mode 4 SCART—S-Video or CVBS Autodetect.................. 102 Mode 5 SCART Fast Blank—CVBS and RGB...................... 103 Mode 6 SCART RGB input (Static Fast Blank)—CVBS and RGB ............................................................................................ 104 Rev. 0 | Page 2 of 108 ADV7184 PCB Layout Recommendations ................................................. 105 Analog Interface Inputs........................................................... 105 Power Supply Decoupling ....................................................... 105 PLL ............................................................................................. 105 Digital Outputs (Both Data and Clocks) .............................. 105 Digital Inputs.............................................................................106 XTAL And Load Capacitor Values Selection ........................106 Typical Circuit Connection ......................................................... 107 Outline Dimensions......................................................................108 Ordering Guide .........................................................................108 REVISION HISTORY 7/05—Revision 0: Initial Version Rev. 0 | Page 3 of 108 ADV7184 INTRODUCTION The ADV7184 is a high quality, single chip, multiformat video decoder that automatically detects and converts PAL, NTSC, and SECAM standards in the form of composite, S-Video, and component video into a digital ITU-R BT.656 format. The advanced and highly flexible digital output interface enables performance video decoding and conversion in line-locked clock-based systems. This makes the device ideally suited for a broad range of applications with diverse analog video characteristics, including tape-based sources, broadcast sources, security and surveillance cameras, and professional systems. STANDARD DEFINITION PROCESSOR (SDP) The ADV7184 is capable of decoding a large selection of baseband video signals in composite, S-Video, and component formats. The video standards supported include PAL B/D/I/G/H, PAL60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC 4.43, and SECAM B/D/G/K/L. The ADV7184 can automatically detect the video standard and process it accordingly. The ADV7184 has a 5-line, superadaptive, 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal. This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality without user intervention. Video user controls such as brightness, contrast, saturation, and hue are also available within the ADV7184. The ADV7184 implements a patented adaptive digital linelength tracking (ADLLT) algorithm to track varying video line lengths from sources such as a VCR. ADLLT enables the ADV7184 to track and decode poor quality video sources such as VCRs, noisy sources from tuner outputs, VCD players, and camcorders. The ADV7184 contains a chroma transient improvement (CTI) processor that sharpens the edge rate of chroma transitions, resulting in sharper vertical transitions. The ADV7184 can process a variety of VBI data services, such as closed captioning (CC), wide screen signaling (WSS), copy generation management system (CGMS), Gemstar 1×/2×, extended data service (XDS), and teletext. The ADV7184 is fully Macrovision certified; detection circuitry enables Type I, II, and III protection levels to be identified and reported to the user. The decoder is also fully robust to all Macrovision signal inputs. ANALOG FRONT END The ADV7184 analog front end includes four 10-bit ADCs that digitize the analog video signal before applying it to the standard definition processor. The analog front end uses differential channels to each ADC to ensure high performance in mixed-signal applications. The front end also includes a 12-channel input mux that enables multiple video signals to be applied to the ADV7184. Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter. Fine clamping of the video signals is performed downstream by digital fine clamping within the ADV7184. The ADCs are configured to run in 4× oversampling mode. The ADV7184 has optional antialiasing filters on each of the four input channels. The filters are designed for SD video with approximately 6 MHz bandwidth. SCART and overlay functionality are enabled by the ADV7184’s ability to simultaneously process CVBS and Standard Definition RGB signals. Signal mixing is controlled by the Fast Blank pin. FUNCTIONAL BLOCK DIAGRAM ANTI CLAMP ALIAS FILTER AIN1– AIN12 12 INPUT MUX ANTI CLAMP ALIAS FILTER ANTI ALIAS FILTER 10 A/D 10 A/D 10 A/D 10 DECIMATION AND 10 DOWNSAMPLING 10 FILTERS 10 CVBS/Y LUMA FILTER LUMA RESAMPLE 10 A/D DATA PREPROCESSOR STANDARD DEFINITION PROCESSOR LUMA 2D COMB Y (5H MAX) 16 FSC RECOVERY CVBS CHROMA C DEMOD Cr Cb R G COLORSPACE CONVERSION B SYNC EXTRACT RESAMPLE CONTROL CHROMA Cr 2D COMB Cb (4H MAX) HS 8 8 PIXEL DATA P15-P8 P7-P0 CVBS S-VIDEO YPrPb SCART - (RGB + CVBS) CLAMP ANTI CLAMP ALIAS FILTER OUTPUT FORMATTER CHROMA FILTER CHROMA RESAMPLE FAST BLANK OVERLAY CONTROL AND AV CODE INSERTION VS FIELD SYNC PROCESSING AND CLOCK GENERATION FB SYNC AND CLK CONTROL Y Cr Cb LLC1 LLC2 ADV7184 VBI DATA RECOVERY SCLK SDA ALSB SERIAL INTERFACE CONTROL AND VBI DATA MACROVISION DETECTION GLOBAL CONTROL STANDARD AUTODETECTION SYNTHESIZED LLC CONTROL FREE RUN OUTPUT CONTROL SFL CONTROL AND DATA INT Figure 1. Rev. 0 | Page 4 of 108 05479-001 ADV7184 ELECTRICAL CHARACTERISTICS At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V, nominal input range 1.6 V. Operating temperature range, unless otherwise noted. Table 1. Parameter STATIC PERFORMANCE 1, 2, 3 Resolution (Each ADC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage 4 Input Low Voltage 5 Input Current Input Capacitance9 DIGITAL OUTPUTS Output High Voltage 8 Output Low Voltage8 High Impedance Leakage Current Output Capacitance9 POWER REQUIREMENTS 9 Digital Core Power Supply Digital I/O Power Supply PLL Power Supply Analog Power Supply Digital Core Supply Current Digital I/O Supply Current PLL Supply Current Analog Supply Current Power-Down Current Power-Up Time 1 2 3 Symbol N INL DNL VIH VIL IIN CIN VOH VOL ILEAK COUT DVDD DVDDIO PVDD AVDD IDVDD IDVDDIO IPVDD IAVDD IPWRDN tPWRUP Test Conditions Min Typ Max 10 ±3 -0.99/2.5 Unit Bits LSB LSB V V μA μA pF V V μA pF V V V V mA mA mA mA mA mA ms BSL at 54 MHz BSL at 54 MHz 2 Pins listed in Note 6 All other pins 7 –50 –10 –0.6/+0.7 −0.5/+0.5 0.8 +50 +10 10 ISOURCE = 0.4 mA ISINK = 3.2 mA 2.4 0.4 10 20 1.65 3.0 1.71 3.15 1.8 3.3 1.8 3.3 105 4 11 99 269 0.65 20 2 3.6 1.89 3.45 CVBS input 10 YPrPb input 11 All ADC linearity tests performed at input range of full scale – 12.5%, and at zero scale +12.5%. Max INL and DNL specifications obtained with part configured for component video input. Temperature range TMIN to TMAX, –40°C to +85°C. The min/max specifications are guaranteed over this range. 4 To obtain specified VIH level on Pin 29, Register 0x13 (write only) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00, then VIH on Pin 29 = 1.2 V. 5 To obtain specified VIL level on Pin 29, Register 0x13 (write only) must be programmed with value 0x04. If Register 0x13 is programmed with value 0x00, then VIL on Pin 29 = 0.4 V. 6 Pins: 36 and 79. 7 Excluding all “TEST” pins (TEST0 to TEST12) 8 VOH and VOL levels obtained using default drive strength value (0xD5) in register subaddress 0xF4. 9 Guaranteed by characterization. 10 ADC0 powered on only. 11 All four ADCs powered on. Rev. 0 | Page 5 of 108 ADV7184 VIDEO SPECIFICATIONS At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted. Table 2. Parameter 1, 2 NONLINEAR SPECIFICATIONS Differential Phase Differential Gain Luma Nonlinearity NOISE SPECIFICATIONS SNR Unweighted Analog Front End Crosstalk LOCK TIME SPECIFICATIONS Horizontal Lock Range Vertical Lock Range Fsc Subcarrier Lock Range Color Lock In Time Sync Depth Range 3 Color Burst Range Vertical Lock Time Autodetection Switch Speed CHROMA SPECIFICATIONS Hue Accuracy Color Saturation Accuracy Color AGC Range Chroma Amplitude Error Chroma Phase Error Chroma Luma Intermodulation LUMA SPECIFICATIONS Luma Brightness Accuracy Luma Contrast Accuracy 1 2 Symbol DP DG LNL Test Conditions CVBS I/P, modulate 5-step CVBS I/P, modulate 5-step CVBS I/P, 5-step Luma ramp Luma flat field Min Typ 0.5 0.5 0.5 Max 0.7 0.7 0.7 Unit Degree % % dB dB dB 54 56 56 58 60 +5 70 ±1.3 60 –5 40 20 5 2 100 HUE CL_AC 5 0.5 0.4 0.2 CVBS, 1 V I/P CVBS, 1 V I/P 1 1 1 1 200 200 % Hz Hz Lines % % Fields Lines Degree % % % Degree % % % 400 Temperature range TMIN to TMAX, –40°C to +85°C. The min/max specifications are guaranteed over this range. Guaranteed by characterization. 3 Nominal sync depth is 300 mV at 100% sync depth range. Rev. 0 | Page 6 of 108 ADV7184 TIMING SPECIFICATIONS At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted. Table 3. Parameter 1, 2 SYSTEM CLOCK AND CRYSTAL Nominal Frequency Frequency Stability I2C PORT 3 SCLK Frequency SCLK Min Pulse Width High SCLK Min Pulse Width Low Hold Time (Start Condition) Setup Time (Start Condition) SDA Setup Time SCLK and SDA Rise Time SCLK and SDA Fall Time Setup Time for Stop Condition RESET FEATURE Reset Pulse Width CLOCK OUTPUTS LLC1 Mark Space Ratio LLC1 Rising to LLC2 Rising LLC1 Rising to LLC2 Falling DATA AND CONTROL OUTPUTS Data Output Transitional Time 4 Data Output Transitional Time4 Propagation Delay to Hi-Z Max Output Enable Access Time Min Output Enable Access Time 1 2 Symbol Test Conditions Min Typ 28.63636 Max Unit MHz ppm kHz μs μs μs μs ns ns ns μs ms ±50 400 t1 t2 t3 t4 t5 t6 t7 t8 0.6 1.3 0.6 0.6 100 300 300 0.6 5 t9:t10 t11 t12 t13 t14 t15 t16 t17 Negative clock edge to start of valid data; (tACCESS = t10 – t13) End of valid data to negative clock edge; (tHOLD = t9 + t14) 6 7 4 45:55 1 1 3.6 2.4 55:45 % duty cycle ns ns ns ns ns ns ns Temperature range TMIN to TMAX, –40°C to +85°C. The min/max specifications are guaranteed over this range. Guaranteed by characterization. 3 TTL input values are 0 V to 3 V, with rise/fall times ≤3 ns, measured between the 10% and 90% points. 4 Timing figures obtained using default drive strength value (0xD5) in register subaddress 0xF4. ANALOG SPECIFICATIONS At AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. Operating temperature range, unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p. Table 4. Parameter 1, 2 CLAMP CIRCUITRY External Clamp Capacitor Input Impedance 3 Input impedance of Pin 40 (FB) Large Clamp Source Current Large Clamp Sink Current Fine Clamp Source Current Fine Clamp Sink Current 1 2 3 Symbol Test Conditions Min Typ 0.1 10 20 0.75 0.75 17 17 Max Unit μF MΩ kΩ mA mA μA μA Clamps switched off Temperature range TMIN to TMAX, –40°C to +85°C. The min/max specifications are guaranteed over this range. Guaranteed by characterization. Except Pin 40 (FB). Rev. 0 | Page 7 of 108 ADV7184 THERMAL SPECIFICATIONS Table 5. Parameter Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance (Still Air) Symbol θJC θJA Test Conditions 4-layer PCB with solid ground plane 4-layer PCB with solid ground plane Min Typ 7.6 38.1 Max Unit °C/W °C/W TIMING DIAGRAMS t3 SDA t5 t3 t6 SCLK t1 05479-002 t2 t7 t4 t8 Figure 2. I2C Timing t9 OUTPUT LLC 1 t10 t11 OUTPUT LLC 2 t12 t13 OUTPUTS P0–P15, VS, HS, FIELD, SFL 05479-003 t14 Figure 3. Pixel Port and Control Output Timing OE t15 P0–P15, HS, VS, FIELD, SFL t17 05479-004 t16 Figure 4. OE Timing Rev. 0 | Page 8 of 108 ADV7184 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter AVDD to AGND DVDD to DGND PVDD to AGND DVDDIO to DGND DVDDIO to AVDD PVDD to DVDD DVDDIO to PVDD DVDDIO to DVDD AVDD to PVDD AVDD to DVDD Digital Inputs Voltage to DGND Digital Output Voltage to DGND Analog Inputs to AGND Maximum Junction Temperature (TJ max) Storage Temperature Range Infrared Reflow Soldering (20 sec) Rating 4V 2.2 V 2.2 V 4V –0.3 V to +0.3 V –0.3 V to +0.3 V –0.3V to +2 V –0.3V to +2 V –0.3V to +2 V –0.3V to +2 V –0.3V to DVDDIO + 0.3 V –0.3V to DVDDIO + 0.3 V AGND – 0.3 V to AVDD + 0.3 V 125°C –65°C to +150°C 260°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL PERFORMANCE To reduce power consumption the user is advised to turn off any unused ADCs when using the part. The junction temperature must always stay below the maximum junction temperature (TJ max) of 125°C. The following equation shows how to calculate the junction temperature: TJ = TA Max + (θJA × WMax) where: TA Max = 85°C. θJA = 30°C/W. Wmax = ((AVDD × IAVDD) + (DVDD × IDVDD) + (DVDDIO × IDVDDIO) + (PVDD × IPVDD)). ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 9 of 108 ADV7184 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET TEST1 TEST6 TEST0 TEST4 TEST7 TEST5 DGND FIELD 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VS 1 HS 2 DGND 3 DVDDIO 4 P11 5 P10 6 P9 7 P8 8 DGND 9 DVDD 10 INT 11 SFL 12 TEST2 13 DGND 14 DVDDIO 15 TEST8 16 TEST12 17 TEST11 18 P7 19 P6 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PIN 1 AIN12 60 59 58 57 56 55 54 DVDD SCLK ALSB AIN6 SDA P12 P13 P14 P15 OE AIN5 AIN11 AIN4 AIN10 AGND CAPC2 CAPC1 AGND CML REFOUT AVDD CAPY2 CAPY1 AGND AIN3 AIN9 AIN2 AIN8 AIN1 AIN7 ADV7184 TOP VIEW (Not to Scale) 53 52 51 50 49 48 47 46 45 44 43 42 41 TEST10 TEST3 XTAL1 TEST9 ELPF P5 P4 P3 P2 P1 P0 DVDD PWRDN DGND PVDD XTAL AGND LLC2 LLC1 FB Figure 5. 80-Lead LQFP Pin Configuration Table 7. Pin Function Descriptions Pin No. 3, 9, 14, 31, 71 39, 47, 53, 56 4, 15 10, 30, 72 50 38 42, 44, 46, 58, 60, 62, 41, 43, 45, 57, 59, 61 11 40 70, 78, 13, 25, 69, 63, 35, 34, 18, 17 77, 65 16 33, 32, 24, 23, 22, 21, 20, 19, 8, 7, 6, 5, 76, 75, 74, 73 2 1 80 Mnemonic DGND AGND DVDDIO DVDD AVDD PVDD AIN1 to AIN12 Type G G P P P P I Function Digital Ground. Analog Ground. Digital I/O Supply Voltage (3.3 V). Digital Core Supply Voltage (1.8 V). Analog Supply Voltage (3.3 V). PLL Supply Voltage (1.8 V). Analog Video Input Channels. INT FB TEST0 to TEST5, TEST9 to TEST12 TEST6 to TEST7 TEST8 P0 to P15 O I Interrupt Request Output. Interrupt occurs when certain signals are detected on the input video. See the User Sub Map register details in Table 103. Fast Blank. FB is a fast switch overlay input that switches between CVBS and RGB analog I/P signals. Leave these pins unconnected. O Tie to AGND Tie to DVDDIO Video Pixel Output Port. HS VS FIELD O O O Horizontal Synchronization Output Signal. Vertical Synchronization Output Signal. Field Synchronization Output Signal. Rev. 0 | Page 10 of 108 05479-005 ADV7184 Pin No. 67 68 66 64 27 26 Mnemonic SDA SCLK ALSB RESET LLC1 LLC2 Type I/O I I I O O Function I2C Port Serial Data Input/Output Pin. I2C Port Serial Clock Input (Max Clock Rate of 400 kHz). This pin selects the I2C address for the ADV7184. ALSB set to Logic 0 sets the address for a write as 0x40; set to Logic 1 sets the address as 0x42. System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset the ADV7184 circuitry. Line-Locked Clock 1. Line-locked output clock for the pixel data output by the ADV7184. Nominally 27 MHz, but varies up or down according to video line length. Line-Locked Clock 2. This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7184. Nominally 13.5 MHz, but varies up or down according to video line length. This is the input pin for the 28.63636 MHz crystal, or can be overdriven by an external 3.3 V, 28.63636 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal. This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7184. In crystal mode, the crystal must be a fundamental crystal. Logic 0 on this pin places the ADV7184 in a power-down mode. Refer to the I2C Register Maps section for more options on power-down modes for the ADV7184. When set to Logic 0, OE enables the pixel output bus, P15 to P0 of the ADV7184. Logic 1 on the OE pin places P15 through P0, HS, VS, and SFL/SYNC_OUT into a high impedance state. The recommended external loop filter must be connected to this ELPF pin, as shown in Figure 50. Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock the subcarrier frequency when this decoder is connected to any Analog Devices, Inc. digital video encoder. Internal Voltage Reference Output. Refer to Figure 50 for a recommended capacitor network for this pin. The CML pin is a common-mode level for the internal ADCs. Refer to Figure 50 for a recommended capacitor network for this pin. ADC’s Capacitor Network. Refer to Figure 50 for a recommended capacitor network for these pins. ADC’s Capacitor Network. Refer to Figure 50 for a recommended capacitor network for these pins. 29 XTAL I 28 XTAL1 O 36 79 PWRDN OE I I 37 12 ELPF SFL I O 51 52 48, 49 54, 55 REFOUT CML CAPY1, CAPY2 CAPC1, CAPC2 O O I I Rev. 0 | Page 11 of 108 ADV7184 ANALOG FRONT END ANALOG INPUT MUXING RGB_IP_SEL INSEL[3:0] AIN10 AIN11 AIN12 AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN5 AIN6 ADC_SW_MAN_EN PRIM_MODE[3:0] SDM_SEL[1:0] INTERNAL MAPPING FUNCTIONS AIN1 AIN7 AIN2 AIN8 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 AIN3 AIN9 AIN4 AIN10 AIN5 AIN11 AIN6 AIN12 AIN2 AIN8 AIN5 AIN11 AIN6 AIN12 AIN4 1 0 ADC0_SW[3:0] ADC0 1 0 ADC1_SW[3:0] ADC1 1 0 ADC2_SW[3:0] ADC2 1 AIN4 AIN7 0 ADC3_SW[3:0] ADC3 Figure 6. Internal Pin Connections The ADV7184 has an integrated analog muxing section that allows connecting more than one source of video signal to the decoder. Figure 6 outlines the overall structure of the input muxing provided in the ADV7184. As seen in Figure 6, the analog input muxes can be controlled in two ways: • By functional registers (INSEL). Using INSEL[3:0] simplifies the setup of the muxes, and minimizes crosstalk between channels by pre-assigning the input channels. This is referred to as ADI-recommended input muxing. By an I2C manual override (ADC_SW_MAN_EN, ADC0_SW, ADC1_SW, ADC2_SW, ADC3_SW). This is provided for applications with special requirements, such as number/combinations of signals, which would not be served by the pre-assigned input connections. This is referred to as manual input muxing. YES CONNECTING ANALOG SIGNALS TO ADV7184 ADI RECOMMENDED INPUT MUXING; SEE TABLES 8 AND 9 NO • SET SDM_SEL[1:0] AND INSEL[3:0] FOR REQUIRED MUXING CONFIGURATION SET SDM_SEL[1:0] AND INSEL[3:0] TO CONFIGURE ADV7184 TO DECODE VIDEO FORMAT: CVBS: 00, 0000 YC: 00, 0110 YPrPb: 00, 1001 SCART (CVBS/RGB): 00, 1111 SET SDM_SEL[1:0] FOR S-VIDEO/CVBS AUTODETECT Refer to Figure 7 for an overview of the two methods of controlling input muxing. Figure 7. Input Muxing Overview Rev. 0 | Page 12 of 108 05479-007 USE MANUAL INPUT MUXING (ADC_SW_MAN_EN, ADC0_SW, ADC1_SW, ADC2_SW, ADC3_SW) 05479-006 ADV7184 ADI Recommended Input Muxing A maximum of 12 CVBS inputs can be connected and decoded by the ADV7184. As seen in Figure 5, this means the sources must be connected to adjacent pins on the IC. This calls for a careful design of the PCB layout, for example, ground shielding between all signals routed through tracks that are physically close together. SDM_SEL[1:0], S-Video and CVBS Autodetect Mode Select, Address 0x69 [1:0] The SDM_SEL bits decide on input routing and whether INSEL[3:0] is used to govern I/P routing decision. The CVBS/YC autodetection feature is enabled using SDM_SEL = 11. Table 8. SDM_SEL[1:0] SDM_SEL[1:0] 00 01 10 11 Mode As per INSEL[3:0] CVBS YC YC/CVBS auto Analogue Video Inputs As per INSEL[3:0] AIN11 Y = AIN10 C = AIN12 CVBS = AIN11 Y = AIN11 C = AIN12 INSEL[3:0] Input Selection, Address 0x00 [3:0] The INSEL bits allow the user to select an input channel as well as the input format. Depending on the PCB connections, only a subset of the INSEL modes is valid. The INSEL[3:0] not only switches the analog input muxing, it also configures the standard definition processor core to process CVBS (Comp), S-Video (Y/C), or component (YPbPr/RGB) format. ADI-recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity. Table 10 summarizes how the PCB layout should connect analog video signals to the ADV7184. It is strongly recommended to connect any unused analog input pins to AGND to act as a shield. Connect inputs AIN7 to AIN11 to AGND when only six input channels are used. This improves the quality of the sampling due to better isolation between the channels. AIN12 is not under the control of INSEL[3:0]. It can be routed to ADC0/ADC1/ADC2 only by manual muxing. See Table 11 for details. Table 9. Input Channel Switching Using INSEL[3:0] INSEL[3:0] 0000 (default) 0001 Analog Input Pins CVBS1 = AIN1 B = AIN4 or AIN71 R = AIN5 or AIN81 G = AIN6 or AIN91 CVBS2 = AIN2 B = AIN4 or AIN71 R = AIN5 or AIN81 G = AIN6 or AIN91 CVBS3 = AIN3 B = AIN4 or AIN71 R = AIN5 or AIN81 G = AIN6 or AIN91 CVBS4 = AIN4 B = AIN7 R = AIN8 G = AIN9 CVBS1 = AIN5 B = AIN7 R = AIN8 G = AIN9 CVBS1 = AIN6 B = AIN7 R = AIN8 G = AIN9 Y1 = AIN1 C1 = AIN4 Y2 = AIN2 C2 = AIN5 Description Video Format SCART (CVBS and R, G, B) INSEL[3:0] 1000 1001 SCART (CVBS and R, G, B) 1010 SCART (CVBS and R, G, B) 1011 Analog Input Pins Y3 = AIN3 C3 = AIN6 Y1 = AIN1 PB1 = AIN4 PR1 = AIN5 Y2 = AIN2 PB2 = AIN3 PR2 = AIN6 CVBS7 = AIN7 B = AIN4 R = AIN5 G = AIN6 CVBS8 = AIN8 B = AIN4 R = AIN5 G = AIN6 CVBS9 = AIN9 B = AIN4 R = AIN5 G = AIN6 CVBS10 = AIN10 B = AIN4 or AIN71 R = AIN5 or AIN81 G = AIN6 or AIN91 CVBS11 = AIN11 B = AIN4 or AIN71 R = AIN5 or AIN81 G = AIN6 or AIN91 Description Video Format YC YPrPb YPrPb SCART (CVBS and R, G, B) 0010 0011 SCART (CVBS and R, G, B) 1100 SCART (CVBS and R, G, B) 0100 SCART (CVBS and R, G, B) 1101 SCART (CVBS and R, G, B) 0101 SCART (CVBS and R, G, B) 1110 SCART (CVBS and R, G, B) 0110 0111 YC YC 1111 SCART (CVBS and R, G, B) 1 Selectable via RGB_IP_SEL. Rev. 0 | Page 13 of 108 ADV7184 RGB_IP_SEL, Address 0xF1 [0] For SCART input, R, G and B signals can be input on either AIN4, AIN5, and AIN6 or on AIN7, AIN8, and AIN9. 0 (default)—B is input on AIN4, R is input on AIN 5, and G is input on AIN6. 1—B is input on AIN7, R is input on AIN 8, and G is input on AIN9. registers (ADC0/ADC1/ACD2/ADC3_SW) contradict each other, the ADC0/ADC1/ADC2 /ADC3_SW settings apply and INSEL is ignored. Manual input muxing controls only the analog input muxes. INSEL[3:0] still has to be set so the follow-on blocks process the video data in the correct format. This means INSEL must still be used to tell the ADV7184 whether the input signal is of component, YC, or CVBS format. Restrictions in the channel routing are imposed by the analog signal routing inside the IC; every input pin cannot be routed to each ADC. Refer to Figure 6 for an overview on the routing capabilities inside the chip. The four mux sections can be controlled by the reserved control signal buses ADC0/ADC1/ ADC2/ADC3_SW[3:0]. Table 11 explains the control words used. MANUAL INPUT MUXING By accessing a set of manual override muxing registers, the analog input muxes of the ADV7184 can be controlled directly. This is referred to as manual input muxing. Manual input muxing overrides other input muxing control bits, for example, INSEL. Manual muxing is activated by setting the ADC_SW_MAN_EN bit. It affects only the analog switches in front of the ADCs. This means if the settings of INSEL and the manual input muxing Table 10. Input Channel Assignments Input Channel AIN7 AIN1 AIN8 AIN2 AIN9 AIN3 AIN10 AIN4 AIN11 AIN5 AIN12 AIN6 Pin No. 41 42 43 44 45 46 57 58 59 60 61 62 CVBS7 CVBS1 CVBS8 CVBS2 CVBS9 CVBS3 CVBS10 CVBS4 CVBS11 CVBS5 Not Available CVBS6 ADI-Recommended Input Muxing Control INSEL[3:0] SCART1-B YC1-Y YPrPb1-Y SCART2-CVBS SCART1-R YC2-Y YPrPb2-Y SCART1-G YC3-Y YPrPb2-Pb YC1-C YC2-C YC3-C YPrPb1-Pb YPrPb1-Pr YPrPb2-Pr SCART2-B SCART1-CVBS SCART2-R SCART2-G Table 11. Manual Mux Settings for All ADCs (ADC_SW_MAN_EN = 1) ADC0_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC0 Connected To No Connection AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 No Connection No Connection AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 No Connection ADC1_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC1 Connected To No Connection No Connection No Connection AIN3 AIN4 AIN5 AIN6 No Connection No Connection No Connection No Connection AIN9 AIN10 AIN11 AIN12 No Connection ADC2_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC2 Connected To No Connection No Connection AIN2 No Connection No Connection AIN5 AIN6 No Connection No Connection No Connection AIN8 No Connection No Connection AIN11 AIN12 No Connection ADC3_sw[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 ADC3 Connected To No Connection No Connection No Connection No Connection AIN4 No Connection No Connection No Connection No Connection AIN7 No Connection No Connection No Connection No Connection No Connection No Connection Rev. 0 | Page 14 of 108 ADV7184 ADC_SW_MAN_EN, Manual Input Muxing Enable, Address 0xC4 [7] ADC0_sw[3:0], ADC0 Mux Configuration, Address 0xC3 [3:0] ADC1_sw[3:0], ADC1 Mux Configuration, Address 0xC3 [7:4] ADC2_sw[3:0], ADC2 Mux Configuration, Address 0xC4 [3:0] ADC3_sw[3:0], ADC3 Mux Configuration, Address 0xF3 [7:4] See Table 11. AA_FILT_EN[2], Address 0xF3 [2] 0 (default)—The filter on channel 2 is disabled. 1—The filter on channel 2 is enabled. AA_FILT_EN[3], Address 0xF3 [3] 0 (default)—The filter on channel 3 is disabled. 1—The filter on channel 3 is enabled. RESPONSE OF AA FILTER WITH CALIBRATED CAPACITORS 0 –2 –4 –6 –8 –10 –12 –14 –16 –18 –20 –22 –24 –26 –28 –30 –32 –34 –36 –38 –40 –42 –44 –46 –48 –50 –52 1M 10M 100M 1G FREQUENCY (Hz) XTAL CLOCK INPUT PIN FUNCTIONALITY XTAL_TTL_SEL, Address 0x13 [2] ATTENUATION (dB) The XTAL pad is normally part of the crystal oscillator circuit, powered from a 1.8 V supply. For optimal clock generation, the slice level of the input buffer of this circuit is at approximately half the supply voltage. This makes it incompatible with TLL level signals. 0 (default)—A crystal is used to generate the ADV7184’s clock. 1—An external TTL level clock is supplied. A different input buffer can be selected, which slices at TTL-compatible levels. This inhibits operation of the crystal oscillator and, therefore, can only be used when a clock signal is applied. 28.63636 MHZ CRYSTAL OPERATION EN28XTAL, Address 0x1D [6] The ADV7184 can operate on two different base crystal frequencies. Selecting one over the other can be desirable in systems in which board crosstalk between different components leads to undesirable interference between video signals. It is recommended by ADI to use an XTAL of frequency 28.63636 MHz to clock the ADV7184. The programming examples at the end of this datasheet presume 28.63636 MHz crystal is used. 0 (default)—XTAL frequency is 27 MHz. 1—XTAL frequency is 28.63636 MHz. Figure 8. Frequency Response of Internal ADV7184 Antialiasing Filters SCART AND FAST BLANKING The ADV7184 can support simultaneous processing of CVBS and RGB standard definition signals to enable SCART compatibility and overlay functionality. This function is available when INSEL[3:0] is set appropriately (see Table 9). Timing extraction is always performed by the ADV7184 on the CVBS signal. However, a combination of the CVBS and RGB inputs can be mixed and output under control of I2C registers and the fast blank (FB) pin. Four basic modes are supported: Static Switch Mode The FB pin is not used. The timing is extracted from the CVBS signal, and either the CVBS content or RGB content can be output under the control of CVBS_RGB_SEL. This mode allows the selection of a full-screen picture from either source. Overlay is not possible in static switch mode. Fixed Alpha Blending The FB pin is not used. The timing is extracted from the CVBS signal, and an alpha blended combination of the video from the CVBS and RGB sources is output. This alpha blending is applied to the full screen. The alpha blend factor is selected with the I2C signal MAN_ALPHA[6:0]. Overlay is not possible in fixed alpha blending mode. ANTIALIASING FILTERS The ADV7184 has optional antialiasing filters on each of the four input channels. The filters are designed for SD video with approximately 6 MHz bandwidth. A plot of the filter response is shown in Figure 8. The filters can be individually enabled via I2C under the control of AA_FILT_EN[3:0]. AA_FILT_EN[0], Address 0xF3 [0] 0 (default)—The filter on channel 0 is disabled. 1—The filter on channel 0 is enabled. AA_FILT_EN[1], Address 0xF3 [1] 0 (default)—The filter on channel 1 is disabled. 1—The filter on channel 1 is enabled. Rev. 0 | Page 15 of 108 05479-008 ADV7184 Dynamic Switching (Fast Mux) Source selection is under the control of the fast blank (FB) pin. This enables dynamic multiplexing between the CVBS and RGB sources. With default settings, when Logic 1 is applied to the FB pin the RGB source is selected; when Logic 0 is applied to the FB pin the CVBS source is selected. This mode is suitable for the overlay of subtitles, teletext, or other material. Typically, the CVBS source carries the main picture and the RGB source has the overlay data. Dynamic Switching with Edge-Enhancement This provides the same functionality as the dynamic switching mode, but with ADI proprietary edge-enhancement algorithms that improve the visual appearance of transitions for signals from a wide variety of sources. The switched or blended data is output from the ADV7184 in the standard output formats (see Table 99). FAST BLANK CONTROL FB_MODE[1:0], Address 0xED [1:0] FB_MODE controls which of the fast blank modes is selected. Table 12. FB_MODE[1:0] function FB_MODE[1:0] 00 (default) 01 10 11 Description Static Switch Mode. Fixed Alpha Blending. Dynamic Switching (Fast Mux). Dynamic Switching with Edge Enhancement. Static Mux Selection Control CVBS_RGB_SEL, Address 0xED [2] CVBS_RGB_SEL controls whether the video from the CVBS or the RGB source is selected for output from the ADV7184. 0 (default)—Data from the CVBS source is selected for output. 1—Data from the RGB source is selected for output. System Diagram A block diagram of the ADV7184 fast blanking configuration is shown in Figure 9. The CVBS signal is processed by the ADV7184 and converted to YPrPb. The RGB signals are processed by a color space converter (CSC) and samples are converted to YPrPb. Both sets of YPrPb signals are input to the sub-pixel blender, which can be configured to operate in any of the four modes outlined above. The fast blank position resolver determines the time position of the FB to a very high accuracy (12C) VIDEO DATA PROCESSING BLOCK 05479-012 FSC RECOVERY Figure 12. Block Diagram of the Standard Definition Processor A block diagram of the ADV7184’s standard definition processor (SDP) is shown in Figure 12. The SDP block can handle standard definition video in CVBS, YC, and YPrPb formats. It can be divided into a luminance and a chrominance path. If the input video is of a composite type (CVBS), both processing paths are fed with the CVBS input. SD CHROMA PATH The input signal is processed by the following blocks: • • Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal. Chroma Demodulation. This block uses a color subcarrier (Fsc) recovery unit to regenerate the color subcarrier for any modulated chroma scheme. The demodulation block then performs an AM demodulation for PAL and NTSC, and an FM demodulation for SECAM. Chroma Filter Block. This block contains a chroma decimation filter (CAA) with a fixed response, and some shaping filters (CSH) that have selectable responses. Gain Control. Automatic gain control (AGC) can operate on several different modes, including gain based on the color subcarrier’s amplitude, gain based on the depth of the horizontal sync pulse on the luma channel, or fixed manual gain. Chroma Resample. The chroma data is digitally resampled to keep it perfectly aligned with the luma data. The resampling is done to correct for static and dynamic linelength errors of the incoming video signal. Chroma 2D Comb. The two-dimensional, 5-line, superadaptive comb filter provides high quality YC separation in case the input signal is CVBS. AV Code Insertion. At this point, the demodulated chroma (Cr and Cb) signal is merged with the retrieved luma values. AV codes (as per ITU-R. BT-656) can be inserted. SD LUMA PATH The input signal is processed by the following blocks: • • Digital Fine Clamp. This block uses a high precision algorithm to clamp the video signal. Luma Filter Block. This block contains a luma decimation filter (YAA) with a fixed response, and some shaping filters (YSH) that have selectable responses. Luma Gain Control. The automatic gain control (AGC) can operate on a variety of different modes, including gain based on the depth of the horizontal sync pulse, peak white mode, and fixed manual gain. Luma Resample. To correct for line-length errors as well as dynamic line-length changes, the data is digitally resampled. Luma 2D Comb. The two-dimensional comb filter provides YC separation. AV Code Insertion. At this point, the decoded luma (Y) signal is merged with the retrieved chroma values. AV codes (as per ITU-R. BT-656) can be inserted. • • • • • • • • • Rev. 0 | Page 22 of 108 ADV7184 SYNC PROCESSING The ADV7184 extracts syncs embedded in the video data stream. There is currently no support for external HS/VS inputs. The sync extraction has been optimized to support imperfect video sources, such as videocassette recorders with head switches. The actual algorithm used employs a coarse detection based on a threshold crossing, followed by a more detailed detection using an adaptive interpolation algorithm. The raw sync information is sent to a line-length measurement and prediction block. The output of this block is then used to drive the digital resampling section to ensure that the ADV7184 outputs 720 active pixels per line. The sync processing on the ADV7184 also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video. • • VSYNC Processor. This block provides extra filtering of the detected VSYNCs to give improved vertical lock. HSYNC Processor. The HSYNC processor is designed to filter incoming HSYNCs that have been corrupted by noise, providing much improved performance for video signals with stable time base but poor SNR. GENERAL SETUP Video Standard Selection The VID_SEL[3:0] register allows the user to force the digital core into a specific video standard. Under normal circumstances, this should not be necessary. The VID_SEL[3:0] bits default to an autodetection mode that supports PAL, NTSC, SECAM, and variants thereof. The Autodetection of SD Modes section describes the autodetection system. Autodetection of SD Modes To guide the autodetect system, individual enable bits are provided for each of the supported video standards. Setting the relevant bit to 0 inhibits the standard from being automatically detected . Instead, the system picks the closest of the remaining enabled standards. The results of the autodetection can be read back via the status registers. See the Global Status Registers section for more information. VID_SEL[3:0], Address 0x00 [7:4] Table 24. VID_SEL Function VID_SEL[3:0] 0000 (default) 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description Autodetect (PAL-BGHID) NTSC-J (without pedestal), SECAM. Autodetect (PAL-BGHID) NTSC-M (with pedestal), SECAM. Autodetect (PAL-N) (pedestal) NTSC-J (without pedestal), SECAM. Autodetect (PAL-N) (pedestal) NTSC-M (with pedestal), SECAM. NTSC-J (1). NTSC-M (1). PAL 60. NTSC-4.43 (1). PAL-BGHID. PAL-N (= PAL-BGHID (with pedestal)). PAL-M (without pedestal). PAL-M. PAL-combination N. PAL-combination N (with pedestal). SECAM. SECAM (with pedestal). VBI DATA RECOVERY The ADV7184 can retrieve the following information from the input video: • • • • • • • Wide-screen signaling (WSS) Copy generation management system (CGMS) Closed caption (CC) Macrovision protection presence Gemstar-compatible data slicing Teletext VITC/VPS The ADV7184 is also capable of automatically detecting the incoming video standard with respect to • • • Color subcarrier frequency Field rate Line rate AD_SEC525_EN Enable Autodetection of SECAM 525 Line Video, Address 0x07 [7] 0 (default)—Disables the autodetection of a 525-line system with a SECAM style, FM-modulated color component. 1—Enables autodetection. AD_SECAM_EN Enable Autodetection of SECAM, Address 0x07 [6] 0—Disables the autodetection of SECAM. 1 (default)—Enables autodetection. Rev. 0 | Page 23 of 108 The SDP can configure itself to support PAL-BGHID, PAL-M/N, PAL-combination N, NTSC-M, NTSC-J, SECAM 50 Hz/60 Hz, NTSC-4.43, and PAL-60. ADV7184 AD_N443_EN Enable Autodetection of NTSC-443, Address 0x07 [5] 0—Disables the autodetection of NTSC style systems with a 4.43 MHz color subcarrier. 1 (default)—Enables autodetection. AD_P60_EN Enable Autodetection of PAL-60, Address 0x07 [4] 0—Disables the autodetection of PAL systems with a 60 Hz field rate. 1 (default)—Enables autodetection. AD_PALN_EN Enable Autodetection of PAL-N, Address 0x07 [3] 0—Disables the detection of the PAL N standard. 1 (default)—Enables autodetection. AD_PALM_EN Enable Autodetection of PAL-M, Address 0x07 [2] 0—Disables the autodetection of PAL M. 1 (default)—Enables autodetection. AD_NTSC_EN Enable Autodetection of NTSC, Address 0x07 [1] 0—Disables the autodetection of standard NTSC. 1 (default)—Enables autodetection. AD_PAL_EN Enable Autodetection of PAL, Address 0x07 [0] 0—Disables the autodetection of standard PAL. 1 (default)—Enables autodetection. Second, there was a design change in Analog Devices encoders from ADV717x to ADV719x. The older versions used the SFL (GenLock Telegram) bit directly, while the later ones invert the bit prior to using it. The reason for this is that the inversion compensated for the 1-line delay of an SFL (GenLock Telegram) transmission. As a result, ADV717x encoders need the PAL switch bit in the SFL (GenLock Telegram) to be 1 for NTSC to work. Also, the ADV7190/ADV7191/ADV7194 encoders need the PAL switch bit in the SFL to be 0 to work in NTSC. If the state of the PAL switch bit is wrong, a 180° phase shift occurs. In a decoder/encoder back-to-back system in which SFL is used, this bit must be set up properly for the specific encoder used. SFL_INV Address 0x41 [6] 0 (default)—Makes the part SFL-compatible with ADV7190/ ADV7191/ADV7194 and ADV73xx encoders. 1—Makes the part SFL-compatible with ADV717x encoders. Lock-Related Controls Lock information is presented to the user through Bits [1:0] of the Status 1 register. See the STATUS_1[7:0], Address 0x10 [7:0] section. Figure 13 outlines the signal flow and the controls available to influence the way the lock status information is generated. SRLS Select Raw Lock Signal, Address 0x51 [6] Using the SRLS bit, the user can choose between two sources for determining the lock status (per Bits [1:0] in the Status 1 register). The time_win signal is based on a line-to-line evaluation of the horizontal synchronization pulse of the incoming video. It reacts quite quickly. The free_run signal evaluates the properties of the incoming video over several fields, and takes vertical synchronization information into account. 0 (default)—Selects the free_run signal. 1—Selects the time_win signal. Subcarrier Frequency Lock Inversion The SFL_INV bit controls the behavior of the PAL switch bit in the SFL (GenLock Telegram) data stream. It was implemented to solve some compatibility issues with video encoders. It solves two problems. First, the PAL switch bit is only meaningful in PAL. Some encoders (including Analog Devices encoders) also look at the state of this bit in NTSC. SELECT THE RAW LOCK SIGNAL SRLS TIME_WIN FREE_RUN FSC LOCK TAKE FSC LOCK INTO ACCOUNT FSCLE 1 0 1 FILTER THE RAW LOCK SIGNAL CIL[2:0], COL[2:0] 0 COUNTER INTO LOCK COUNTER OUT OF LOCK MEMORY STATUS 1 [0] STATUS 1 [1] 05479-013 Figure 13. Lock-Related Signal Path Rev. 0 | Page 24 of 108 ADV7184 FSCLE Fsc Lock Enable, Address 0x51 [7] The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits [1:0] in STATUS_1. This bit must be set to 0 when operating in YPrPb component mode to generate a reliable HLOCK status bit. 0 (default)—Makes the overall lock status dependent on the horizontal sync lock only. 1—Makes the overall lock status dependent on horizontal sync lock and Fsc lock. VS_Coast[1:0], Address 0xF9 [3:2] These bits are used to set VS free-run (coast) frequency. Table 25. VS_COAST[1:0] function VS_COAST [1:0] 00 (default) 01 10 11 Description Auto coast mode—follows VS frequency from last video input Forces 50 Hz coast mode Forces 60 Hz coast mode Reserved ST_NOISE_VLD, HS Tip Noise Measurement Valid, Address 0xDE [3] (read only) 0—The ST_NOISE[10:0] measurement is not valid 1 (default)—The ST_NOISE[10:0] measurement is valid. ST_NOISE[10:0] HS Tip Noise Measurement, Address 0xDE [2:0], 0xDF [7:0] The ST_NOISE[10:0] measures, over four fields, a readback value of the average of the noise in the HSYNC tip. ST_NOISE_VLD must be 1 for this measurement to be valid. 1 bit of ST_NOISE[10:0] = 1 ADC code. 1 bit of ST_NOISE[10:0] = 1.6 V/4096 = 390.625 μV. COLOR CONTROLS These registers allow the user to control the picture appearance, including control of the active data in the event of video being lost. These controls are independent of any other controls. For instance, brightness control is independent of picture clamping, although both controls affect the signal’s dc level. CON[7:0] Contrast Adjust, Address 0x08 [7:0] This register allows the user to adjust the contrast of the picture. Table 28. CON Function CON[7:0] 0x80 (default) 0x00 0xFF Description Gain on luma channel = 1 Gain on luma channel = 0 Gain on luma channel = 2 CIL[2:0] Count Into Lock, Address 0x51 [2:0] CIL[2:0] determines the number of consecutive lines for which the into-lock condition must be true before the system switches into the locked state, and reports this via STATUS_1[1:0]. It counts the value in lines of video. Table 26. CIL Function CIL[2:0] 000 001 010 011 100 (default) 101 110 111 Description 1 2 5 10 100 500 1000 100000 SD_SAT_Cb[7:0] SD Saturation Cb Channel, Address 0xE3 [7:0] This register allows the user to control the gain of the Cb channel only. The user can adjust the saturation of the picture. Table 29. SD_SAT_Cb Function SD_SAT_Cb[7:0] 0x80 (default) 0x00 0xFF Description Gain on Cb channel = 1 Gain on Cb channel = 0 Gain on Cb channel = 2 COL[2:0] Count Out of Lock, Address 0x51 [5:3] COL[2:0] determines the number of consecutive lines for which the out of lock condition must be true before the system switches into unlocked state, and reports this via STATUS_0[1:0]. It counts the value in lines of video. Table 27. COL Function COL[2:0] 000 001 010 011 100 (default) 101 110 111 Description 1 2 5 10 100 500 1000 100000 SD_SAT_Cr[7:0] SD Saturation Cr Channel, Address 0xE4 [7:0] This register allows the user to control the gain of the Cr channel only. The user can adjust the saturation of the picture. Table 30. SD_SAT_Cr Function SD_SAT_Cr[7:0] 0x80 (default) 0x00 0xFF Description Gain on Cr channel = 1 Gain on Cr channel = 0 Gain on Cr channel = 2 Rev. 0 | Page 25 of 108 ADV7184 SD_OFF_Cb[7:0] SD Offset Cb Channel, Address 0xE1 [7:0] This register allows the user to select an offset for data on the Cb channel only and adjust the hue of the picture. There is a functional overlap with the HUE [7:0] register. Table 31.SD_OFF_Cb Function SD_OFF_Cb[7:0] 0x80 (default) 0x00 0xFF Description 0 mV offset applied to the Cb channel −568 mV offset applied to the Cb channel +568 mV offset applied to the Cb channel DEF_Y[5:0] Default Value Y, Address 0x0C [7:2] If the ADV7184 loses lock on the incoming video signal or if there is no input signal, the DEF_Y[5:0] bits allow the user to specify a default luma value to be output. The register is used under the following conditions: • If DEF_VAL_AUTO_EN bit is set to high and the ADV7184 loses lock to the input video signal. This is the intended mode of operation (automatic mode). The DEF_VAL_EN bit is set, regardless of the lock status of the video decoder. This is a forced mode that may be useful during configuration. • SD_OFF_Cr [7:0] SD Offset Cr Channel, Address 0xE2 [7:0] This register allows the user to select an offset for data on the Cr channel only and adjust the hue of the picture. There is a functional overlap with the HUE [7:0] register. Table 32. SD_OFF_Cr Function SD_OFF_Cr[7:0] 0x80 (default) 0x00 0xFF Description 0 mV offset applied to the Cr channel −568 mV offset applied to the Cr channel +568 mV offset applied to the Cr channel The DEF_Y[5:0] values define the 6 MSBs of the output video. The remaining LSBs are padded with 0s. For example, in 8-bit mode, the output is Y[7:0] = {DEF_Y[5:0], 0, 0}. The value for Y is set by the DEF_Y[5:0] bits. A value of 0x0D produces a blue color in conjunction with the DEF_C[7:0] default setting. Register 0x0C has a default value of 0x36. DEF_C[7:0] Default Value C, Address 0x0D [7:0] BRI[7:0] Brightness Adjust, Address 0x0A [7:0] This register controls the brightness of the video signal. It allows the user to adjust the brightness of the picture. Table 33. BRI Function BRI[7:0] 0x00 (default) 0x7F 0x80 Description Offset of the luma channel = 0 mV Offset of the luma channel = +204 mV Offset of the luma channel = −204 mV The DEF_C[7:0] register complements the DEF_Y[5:0] value. It defines the 4 MSBs of Cr and Cb values to be output if • • The DEF_VAL_AUTO_EN bit is set to high and the ADV7184 can’t lock to the input video (automatic mode). DEF_VAL_EN bit is set to high (forced output). HUE[7:0] Hue Adjust, Address 0x0B [7:0] This register contains the value for the color hue adjustment. It allows the user to adjust the hue of the picture. HUE[7:0] has a range of ±90°, with 0x00 equivalent to an adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°. The hue adjustment value is fed into the AM color demodulation block. Therefore, it only applies to video signals that contain chroma information in the form of an AM modulated carrier (CVBS or Y/C in PAL or NTSC). It does not affect SECAM and does not work on component video inputs (YPrPb). Table 34. HUE Function HUE[7:0] 0x00 (default) 0x7F 0x80 Description Phase of the chroma signal = 0° Phase of the chroma signal = +90° Phase of the chroma signal = −90° The data that is finally output from the ADV7184 for the chroma side is Cr[7:0] = {DEF_C[7:4], 0, 0, 0, 0}, Cb[7:0] = {DEF_C[3:0], 0, 0, 0, 0}. The values for Cr and Cb are set by DEF_C[7:0] bits. A value of 0x7C produces a blue color in conjunction with the DEF_Y[5:0] default setting. DEF_VAL_EN Default Value Enable, Address 0x0C [0] This bit forces the use of the default values for Y, Cr, and Cb. Refer to the descriptions for DEF_Y and DEF_C for additional information. In this mode, the decoder also outputs a stable 27 MHz clock, HS, and VS. 0 (default)—Outputs a colored screen determined by userprogrammable Y, Cr, and Cb values when the decoder freeruns. Free-run mode is turned on and off by the DEF_VAL_AUTO_EN bit. 1—Forces a colored screen output determined by userprogrammable Y, Cr, and Cb values. This overrides picture data even if the decoder is locked. Rev. 0 | Page 26 of 108 ADV7184 DEF_VAL_AUTO_EN Default Value Automatic Enable, Address 0x0C [1] This bit enables the automatic use of the default values for Y, Cr, and Cb when the ADV7184 cannot lock to the video signal. 0—Disables free-run mode. If the decoder is unlocked, it outputs noise. 1 (default)—Enables free-run mode. A colored screen set by the user-programmable Y, Cr, and Cb values is displayed when the decoder loses lock. The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid ADC input window so that the analog-to-digital conversion can take place. It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits the ADC range. After digitization, the digital fine clamp block corrects for any remaining variations in dc level. Since the dc level of an input video signal refers directly to the brightness of the picture transmitted, it is important to perform a fine clamp with high accuracy; otherwise, brightness variations may occur. Furthermore, dynamic changes in the dc level almost certainly lead to visually objectionable artifacts, and must therefore be prohibited. The clamping scheme must be able to acquire a newly connected video signal with a completely unknown dc level, and it must maintain the dc level during normal operation. To quickly acquire an unknown video signal, the large current clamps may be activated. It is assumed that the amplitude of the video signal at this point is of a nominal value. Control of the coarse and fine current clamp parameters is automatically performed by the decoder. Standard definition video signals may have excessive noise on them. In particular, CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise (>100 mV). A voltage clamp would be unsuitable for this type of video signal. Instead, the ADV7184 uses a set of four current sources that can cause coarse (>0.5 mA) and fine ( the VDP CCAP can be updated at the next occurrence of CCAP). Back to step 2. 2 The following read-only bits contain data detection information from the VDP module from the time the status bit has been last cleared or unmasked. VDP_CCAPD_Q Address 0x4E [0], User Sub Map 0 (default)—CCAP data has not been detected. 1—CCAP data has been detected. VDP_CGMS_WSS_CHNGD_Q Address 0x4E [2], User Sub Map 2. 3. 0 (default)—CGMS or WSS data has not been detected. 1—CGM or WSS data has been detected. VDP_GS_VPS_PDC_UTC_CHNG_Q Address 0x4E [4], User Sub Map 4. 5. 6. 0 (default)—Gemstar, PDC, UTC, or VPS data has not been detected. 1—Gemstar, PDC, UTC, or VPS data has been detected. VDP_VITC_Q Address 0x4E [6], User Sub Map, read only 0 (default)—VITC data has not been detected. 1—VITC data has been detected. Interrupt Status Clear Register Details 7. Interrupt Mask Register Details The following bits set the interrupt mask on the signal from the VDP VBI data slicer. VDP_CCAPD_MSKB Address 0x50 [0], User Sub Map It is not necessary to write 0 to these write-only bits as they automatically reset when they are set (self-clearing). VDP_CCAPD_CLR Address 0x4F [0], User Sub Map 0 (default)—Disables interrupt on VDP_CCAPD_Q signal. 1—Enables interrupt on VDP_CCAPD_Q signal. VDP_CGMS_WSS_CHNGD_MSKB Address 0x50 [2], User Sub Map 1—Clears VDP_CCAP_Q bit. VDP_CGMS_WSS_CHNGD_CLR Address 0x4F [2], User Sub Map 0 (default)—Disables interrupt on VDP_CGMS_WSS_ CHNGD_Q signal. 1—Enables interrupt on VDP_CGMS_WSS_CHNGD_Q signal. VDP_GS_VPS_PDC_UTC_CHNG_MSKB Address 0x50 [4], User Sub Map 1—Clears VDP_CGMS_WSS_CHNGD_Q bit. VDP_GS_VPS_PDC_UTC_CHNG_CLR Address 0x4F [4], User Sub Map 1—Clears VDP_GS_VPS_PDC_UTC_CHNG_Q bit. VDP_VITC_CLR Address 0x4F [6], User Sub Map 1—Clears VDP_VITC_Q bit. 0 (default)—Disables interrupt on VDP_GS_VPS_PDC_UTC_CHNG_Q signal. 1—Enables interrupt on VDP_GS_VPS_PDC_UTC_CHNG_Q signal. Rev. 0 | Page 56 of 108 ADV7184 I2C READBACK REGISTERS Teletext Because teletext is a high data rate standard, the decoded bytes are available only as ancillary data. However, a TTX_AVL bit has been provided in I2C so that the user can check whether or not the VDP has detected teletext. Note that the TTXT_AVL bit is a plain status bit and does not use the protocol identified in the I2C Interface section. TTXT_AVL Teletext Detected Status bit, Address 0x78 [7], User Sub Map, Read Only WST_PKT_DECOD_DISABLE Disable Hamming Decoding of Bytes in WST, Address 0x60 [3], User Sub Map 0—Enables hamming decoding of WST packets 1 (default)—Disables hamming decoding of WST packets. For hamming coded bytes, the dehammed nibbles are output along with some error information from the hamming decoder as follows. • • Input Hamming Coded byte: {D3, P3, D2, P2, D1, P1, D0, P0} (bits in decoded order) Output Dehammed byte: {E1, E0, 0, 0, D3’, D2’, D1’, D0’} (Di’ – corrected bits, Ei error info). 0—Teletext was not detected. 1—Teletext was detected. WST Packet Decoding Table 74. Explanation of Error Bits in the Dehammed Output Byte E[1:0] 00 01 10 11 Error Information No errors detected Error in P4 Double error Single error found and corrected Output Data Bitsin Nibble OK OK BAD OK For WST ONLY, the VDP decodes the Magazine and Row address of WST teletext packets and further decodes the packet’s 8x4 hamming coded words. This feature can be disabled using WST_PKT_ DECOD_ DISABLE bit (Bit 3, register 0x60, User Sub Map). The feature is valid for WST only. Table 75 describes the different WST packets that are decoded. Table 75. WST Packet Description Packet Header Packet (X/00) Byte 1Pst Byte 2Pnd Byte 3rd Byte 4th Byte 5th to 10th Byte 11th to 42nd Byte 1st Byte 2nd Byte 3rd to 42nd Byte 1st Byte 2nd Byte 3rd Byte 4th Byte to 10th Byte 11th to 23rd Byte 24th to 42nd Byte 1st Byte 2nd Byte 3rd Byte 4th Byte to 10th Byte 11th to 23rd Byte 24th to 42nd Byte 1st Byte 2nd Byte 3rd Byte 4th to 42nd Byte Description Mag No. – Dehammed Byte 4. Row No. – Dehammed Byte 5. Page No. – Dehammed Byte 6. Page No. – Dehammed Byte 7. Control Bytes – Dehammed Byte 8 to Byte 13. Raw data bytes. Mag No. – Dehammed Byte 4. Row No. – Dehammed Byte 5. Raw data bytes. Mag No. – Dehammed Byte 4. Row No. – Dehammed Byte 5. Desig Code. – Dehammed Byte 6. Dehammed Initial Teletext Page Byte 7 to Byte 12. UTC bytes – Dehammed Bytes 13 to Byte 25. Raw status bytes. Mag No. – Dehammed Byte 4. Row No. – Dehammed Byte 5. Desig Code. – Dehammed Byte 6. Dehammed Initial Teletext Page Byte 7 to Byte 12. PDC bytes – Dehammed Byte 13 to Byte 25. Raw status bytes. Mag No. – Dehammed Byte 4. Row No. – Dehammed Byte 5. Desig Code. – Dehammed Byte 6. Raw data bytes. Text Packets (X/01 to X/25) 8/30 (Format 1) packet Desig Code = 0000 or 0001 UTC 8/30 (Format 2) packet Desig Code = 0010 or 0011 PDC X/26, X/27, X/28, X/29, X/30, X/31 1 1 For X/26, X/28 and M/29, further decoding needs 24x18 hamming decoding. Not supported at present. Rev. 0 | Page 57 of 108 ADV7184 CGMS and WSS The CGMS and WSS data packets convey the same type of information for different video standards. WSS is for PAL and CGMS is for NTSC and hence the CGMS and WSS readback registers are shared. WSS is bi-phase coded; the VDP does a biphase decoding to produce the 14 raw WSS bits in the CGMS/WSS readback I2C registers and sets the CGMS_WSS_AVL bit. CGMS_WSS_CLEAR CGMS/WSS Clear, Address 0x78 [2], User Sub Map, Write Only, Self Clearing CCAP Two bytes of decoded closed caption data are available in the I2C registers. The field information of the decoded CCAP data can be obtained from the CC_EVEN_FIELD bit (register 0x78). CC_CLEAR Closed Caption Clear, Address 0x78 [0] User Sub Map, Write Only, Self Clearing 1—Re-initializes the CCAP readback registers. CC_AVL Closed Caption Available, Address 0x78 [0], User Sub Map, Read Only 1—Re-initializes the CGMS/WSS readback registers. CGMS_WSS_AVL CGMS/WSS Available Bit, Address 0x78 [2], User Sub Map, Read Only 0—Closed captioning was not detected. 1—Closed captioning was detected. CC_EVEN_FIELD Address 0x78 [1], User Sub Map, Read Only 0—CGMS/WSS was not detected. 1—CGMS/WSS was detected. CGMS_WSS_DATA_0[3:0] Address 0x7D [3:0] CGMS_WSS_DATA_1[7:0] Address 0x7E [7:0] CGMS_WSS_DATA_2[7:0] Address 0x7F [7:0] Identifies the field from which the CCAP data was decoded. 0—Closed captioning detected on an ODD field. 1—Closed captioning was detected on an EVEN field. VDP_CCAP_DATA_0 Address 0x79 [7:0], User Sub Map, Read Only User Sub Map, read only. These bits hold the decoded CGMS or WSS data. Refer to Figure 37 and Figure 38 for the I2C to WSS and CGMS bit mapping. Decoded Byte 1 of CCAP data. VDP_CCAP_DATA_1 Address 0x7A [7:0], User Sub Map, Read Only Decoded Byte 2 of CCAP data. VDP_CGMS_WSS_DATA_2 0 RUN-IN SEQUENCE VDP_CGMS_WSS_ DATA_1[5:0] 0 1 2 3 4 5 ACTIVE VIDEO 1 2 3 4 5 6 7 START CODE 11.0μs 42.5μs 05479-037 38.4μs Figure 37. WSS Waveform +100 IRE REF +70 IRE 0 VDP_CGMS_WSS_DATA_2 1 2 3 4 5 6 7 0 VDP_CGMS_WSS_DATA_1 1 2 3 4 5 6 7 VDP_CGMS_WSS_ DATA_0[3:0] 0 1 2 3 0 IRE 49.1μs ± 0.5μs CRC SEQUENCE 05479-038 –40 IRE 11.2μs 2.235μs ± 20ns Figure 38. CGMS Waveform Rev. 0 | Page 58 of 108 ADV7184 Table 76. CGMS Readback Registers 1 Signal Name CGMS_WSS_DATA_0[3:0] CGMS_WSS_DATA_1[7:0] CGMS_WSS_DATA_2[7:0] 1 Register Location VDP_CGMS_WSS_DATA_0 [3:0] VDP_CGMS_WSS_DATA_1 [7:0] VDP_CGMS_WSS_DATA_2 [7:0] Address (User Sub Map) 125 0x7D 126 0x7E 127 0x7F The register is a readback register; default value does not apply. 10.5 ± 0.25μs 12.91μs 7 CYCLES OF 0.5035MHz (CLOCK RUN-IN) 50 IRE S T A R T 0123456 701234567 P A R I T Y P A R I T Y 40 IRE 27.382μs 33.764μs Figure 39.CCAP Waveform and Decoded Data Correlation Table 77. CCAP Readback Registers 1 Signal Name CCAP_BYTE_1[7:0] CCAP_BYTE_2[7:0] 1 Register Location VDP_CCAP_DATA_0[7:0] VDP_CCAP_DATA_1[7:0] Address (User Sub Map) 121 0x79 122 0x7A The register is a readback register; default value does not apply. BIT0, BIT1 BIT88, BIT89 VITC WAVEFORM Figure 40. VITC Waveform and Decoded Data Correlation VITC VITC has a sync sequence of 10 in between each data byte. The VDP strips these syncs from the data stream to give out only the data bytes. The VITC results are available in VDP_VITC_DATA_0 to VDP_VITC_DATA_8 registers (Register 0x92 to Register 0x9A, User Sub Map). The VITC has a CRC byte at the end; the in-between syncs are also used in this CRC calculation. Since the in-between syncs are not given out, the CRC is also calculated internally. The calculated CRC is also available for the user in VITC_CALC_CRC register (Resister 0x9B, User Sub Map). Once the VDP completes decoding the VITC line, the VITC_DATA and VITC_CALC_CRC registers are updated and VITC_AVL bit is set. VITC_CLEAR VITC Clear, Address 0x78 [6], User Sub Map, Write Only, Self Clearing 1—Re-initializes the VITC readback registers. VITC_AVL VITC Available, Address 0x78 [6], User Sub Map 0—VITC data was not detected. 1—VITC data was detected. VITC Readback Registers See Figure 40 for the I2C to VITC bit mapping. Rev. 0 | Page 59 of 108 05479-040 TO 05479-039 REFERENCE COLOR BURST (9 CYCLES) FREQUENCY = FSC = 3.579545MHz AMPLITUDE = 40 IRE 10.003μs VDP_CCAP_DATA_0 VDP_CCAP_DATA_1 ADV7184 Table 78. VITC Readback Registers 1 Signal Name VITC_DATA_0[7:0] VITC_DATA_1[7:0] VITC_DATA_2[7:0] VITC_DATA_3[7:0] VITC_DATA_4[7:0] VITC_DATA_5[7:0] VITC_DATA_6[7:0] VITC_DATA_7[7:0] VITC_DATA_8[7:0] VITC_CALC_CRC[7:0] 1 Register Location VDP_VITC_DATA_0[7:0] VDP_VITC_DATA_1[7:0] VDP_VITC_DATA_2[7:0] VDP_VITC_DATA_3[7:0] VDP_VITC_DATA_4[7:0] VDP_VITC_DATA_5[7:0] VDP_VITC_DATA_6[7:0] VDP_VITC_DATA_7[7:0] VDP_VITC_DATA_8[7:0] VDP_VITC_CALC_CRC[7:0] (VITC bits [9:2]) (VITC bits [19:12]) (VITC bits [29:22]) (VITC bits [39:32]) (VITC bits [49:42]) (VITC bits [59:52]) (VITC bits [69:62]) (VITC bits [79:72]) (VITC bits [89:82]) Address (User Sub Map) 146 0x92 147 0x93 148 0x94 149 0x95 150 0x96 151 0x97 152 0x98 153 0x99 154 0x9A 155 0x9B The register is a readback register; default value does not apply. VPS/PDC/UTC/GEMSTAR The readback registers for VPS, PDC and UTC have been shared. Gemstar is a high data rate standard and so is available only through the ancillary stream; however, for evaluation purposes any one line of Gemstar is available through I2C registers sharing the same register space as PDC, UTC, and VPS. Thus only one standard out of VPS, PDC, UTC, and Gemstar can be read through the I2C at a time. The user has to program I2C_GS_VPS_PDC_UTC[1:0] (register address 0x9C, User Sub Map)to identify the data that should be made available in the I2C registers. I2C_GS_VPS_PDC_UTC (VDP) [1:0] Address 0x9C [6:5], User Sub Map VPS The VPS data bits are bi-phase decoded by the VDP. The decoded data is available in both the ancillary stream and in the I2C readback registers. VPS decoded data is available in the VDP_GS_VPS_PDC_UTC_0 to VDP_VPS_PDC_UTC_12 registers (addresses 0x84 – 0x90, User Sub Map). The GS_VPS_ PDC_UTC_AVL bit is set if the user had programmed I2C_GS_VPS_PDC_UTC to 01, as explained in Table 79. GEMSTAR Specifies which standard result to be available for I2C readback. Table 79. I2C_GS_VPS_PDC_UTC[1:0] Function I2C_GS_VPS_PDC_UTC[1:0] 00 (default) 01 10 11 Description Gemstar 1x/2x. VPS. PDC. UTC. The Gemstar decoded data is made available in the ancillary stream and any one line of Gemstar is also available in I2C registers for evaluation purposes. In order to obtain Gemstar results in I2C registers, the user has to program I2C_GS_VPS_PDC_UTC to 00, as explained in Table 79. VDP supports auto detection of Gemstar standard between Gemstar 1× or Gemstar 2× and decodes accordingly. For this auto detection mode to work the user has to set AUTO_DETECT_GS_TYPE I2C bit (register 0x61, User Sub Map) and program the decoder to decode Gemstar 2× on the required lines through line programming. The type of Gemstar decoded can be determined by observing the bit GS_DATA_TYPE bit (Register 0x78, User Sub Map). AUTO_DETECT_GS_TYPE, Address 0x61 [4], User Sub Map GS_PDC_VPS_UTC_CLEAR GS/PDC/VPS/UTC Clear, Address 0x78 [4], User Sub Map, Write Only, Self Clearing 1—Re-initializes the GS/PDC/VPS/UTC data readback registers. GS_PDC_VPS_UTC_AVL GS/PDC/VPS/UTC Available , Address 0x78 [4], User Sub Map, Read Only 0 (default)—Disables autodetection of Gemstar type. 1—Enables autodetection. GS_DATA_TYPE, Address 0x78 [5], User Sub Map, Read Only 0—One of GS, PDC, VPS or UTC data was not detected. 1—One of GS, PDC, VPS, or UTC data was detected. VDP_GS_VPS_PDC_UTC Readback Registers Identifies the decoded Gemstar data type. 0—Gemstar 1× mode is detected. Read 2 data bytes from 0x84. 1—Gemstar 2× mode is detected. Read 4 data bytes from 0x84. The Gemstar data that is available in the I2C register could be from any line of the input video on which Gemstar was decoded. To read the Gemstar data on a particular video line, the user should use the Manual Configuration as described in Table 65 and Table 66 and enable Gemstar decoding on the required line only. Rev. 0 | Page 60 of 108 See Table 80. ADV7184 Table 80. GS /VPS/PDC/UTC Readback Registers 1 Signal Name GS_VPS_PDC_UTC_BYTE_0[7:0] GS_VPS_PDC_UTC_BYTE_1[7:0] GS_VPS_PDC_UTC_BYTE_2[7:0] GS_VPS_PDC_UTC_BYTE_3[7:0] VPS_PDC_UTC_BYTE_4[7:0] VPS_PDC_UTC_BYTE_5[7:0] VPS_PDC_UTC_BYTE_6[7:0] VPS_PDC_UTC_BYTE_7[7:0] VPS_PDC_UTC_BYTE_8[7:0] VPS_PDC_UTC_BYTE_9[7:0] VPS_PDC_UTC_BYTE_10[7:0] VPS_PDC_UTC_BYTE_11[7:0] VPS_PDC_UTC_BYTE_12[7:0] 1 Register Location VDP_GS_VPS_PDC_UTC_0[7:0] VDP_GS_VPS_PDC_UTC_1[7::0] VDP_GS_VPS_PDC_UTC_2[7:0] VDP_GS_VPS_PDC_UTC_3[7:0] VDP_VPS_PDC_UTC_4[7:0] VDP_VPS_PDC_UTC_5[7:0] VDP_VPS_PDC_UTC_6[7:0] VDP_VPS_PDC_UTC_7[7:0] VDP_VPS_PDC_UTC_8[7:0] VDP_VPS_PDC_UTC_9[7:0] VDP_VPS_PDC_UTC_10[7:0] VDP_VPS_PDC_UTC_11[7:0] VDP_VPS_PDC_UTC_12[7:0] Address (User Sub Map) Dec Hex 132d 0x84 133d 0x85 134d 0x86 135d 0x87 136d 0x88 137d 0x89 138d 0x8A 139d 0x8B 140d 0x8C 141d 0x8D 142d 0x8E 143d 0x8F 144d 0x90 The register is a readback register; default value does not apply. PDC/UTC The block is configured via I2C in the following ways: • • • GDECEL[15:0] allows data recovery on selected video lines on even fields to be enabled and disabled. GDECOL[15:0] enables the data recovery on selected lines for odd fields. GDECAD configures the way in which data is embedded in the video data stream. PDC and UTC are data transmitted through teletext packet 8/30 format 2 (magazine 8, row 30, design_code 2 or 3), and packet 8/30 format 1 (magazine 8, row 30, design_code 0 or 1). Hence, if PDC or UTC data is to be read through I2C, the corresponding teletext standard (WST or PAL System B) should be decoded by VDP. The whole teletext decoded packet is output on the ancillary data stream. The user can look for the magazine number, row number and design_code and qualify the data as PDC, UTC or none of these. If PDC/UTC packets have been identified, Byte 0 to Byte 12 are updated to the GS_VPS_PDC_UTC_0 to VPS_PDC_UTC_12 registers, and the GS_VPS_PDC_UTC_AVL bit set. The full packet data is also available in the ancillary data format. Note that the data available in the I C register depends on the status of the WST_PKT_DECODE_DISABLE bit (Bit 3, subaddress 0x60, User Sub Map). 2 The recovered data is not available through I2C, but is inserted into the horizontal blanking period of an ITU-R BT656compatible data stream. The data format is intended to comply with the recommendation by the International Telecommunications Union, ITU-R BT.1364. For more information, see the ITU website at www.itu.ch. See Figure 41. GDE_SEL_OLD_ADF, Address 0x4C [3], User Map VBI System 2 The user has an option of using a different VBI data slicer called VBI System 2. This data slicer is used to decode Gemstar and Closed Caption VBI signals only. Using this system, the Gemstar data is only available in the ancillary data stream. A special mode enables one line of data to be read back via I2C. For details on how to get I2C readback when using the VBI System 2 data slicer, see the ADI applications note on ADV7184 VBI processing. The ADV7184 has a new ancillary data output block that can be used by the VDP data slicer and the VBI System 2 data slicer. The new ancillary data formatter is used by setting GDE_SEL_OLD_ADF = 0 (this is the default setting). If this bit is set low, refer to Table 69 and Table 70 for information about how the data is packaged in the ancillary data stream. To use the old ancillary data formatter (to be backwardcompatible with the ADV7183B), set GDE_SEL_OLD_ADF = 1. The ancillary data format in this section refers to the ADV7183Bcompatible ancillary data formatter. 0 (default)—Enables new ancillary data system (for use with VDP and VBI System 2). 1—Enables old ancillary data system (for use with VBI System 2 only; ADV7183B-compatible). Gemstar Data Recovery The Gemstar-compatible data recovery block (GSCD) supports 1× and 2× data transmissions. In addition, it can serve as a closed caption decoder. Gemstar-compatible data transmissions can occur only in NTSC. Closed caption data can be decoded in both PAL and NTSC. Rev. 0 | Page 61 of 108 ADV7184 The format of the data packet depends on the following criteria: • • Transmission is 1× or 2×. Data is output in 8-bit or 4-bit format (see the description of the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] bit). Data is closed caption (CCAP) or Gemstar-compatible. Entries within the packet are as follows: • • Fixed preamble sequence of 0x00, 0xFF, 0xFF. Data identification word (DID). The value for the DID marking a Gemstar or CCAP data packet is 0x140 (10-bit value). Secondary data identification word (SDID), which contains information about the video line from which data was retrieved, whether the Gemstar transmission was of 1× or 2× format, and whether it was retrieved from an even or odd field. Data count byte, giving the number of user data-words that follow. User data section. Optional padding to ensure that the length of the user data-word section of a packet is a multiple of four bytes (requirement as set in ITU-R BT.1364). Checksum byte. • • Data packets are output if the corresponding enable bit is set (see the GDECEL[15:0] and GDECOL[15:0] descriptions), and if the decoder detects the presence of data. This means that for video lines where no data has been decoded, no data packet is output even if the corresponding line enable bit is set. Each data packet starts immediately after the EAV code of the preceding line. Figure 41 and Table 81 show the overall structure of the data packet. • • • • Table 81 lists the values within a generic data packet that is output by the ADV7184 in 8-bit format. DATA IDENTIFICATION SECONDARY DATA IDENTIFICATION DATA COUNT OPTIONAL PADDING BYTES CHECK SUM 05479-045 00 FF FF DID SDID USER DATA PREAMBLE FOR ANCILLARY DATA USER DATA (4 OR 8 WORDS) Figure 41. Gemstar and CCAP Embedded Data Packet (Generic) Table 81. Generic Data Output Packet Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D[9] 0 1 1 0 EP EP EP EP EP EP EP EP EP EP CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 0 0 0 0 CS[7] D[6] 0 1 1 1 2X 0 0 0 0 0 0 0 0 0 CS[6] CS[5] D[5] 0 1 1 0 0 D[4] 0 1 1 0 0 D[3] 0 1 1 0 line[3:0] DC[1] D[2] 0 1 1 0 DC[0] D[1] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 CS[2] 0 D[0] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count (DC) User data-words User data-words User data-words User data-words User data-words User data-words User data-words User data-words Checksum word1[7:4] word1[3:0] word2[7:4] word2[3:0] word3[7:4] word3[3:0] word4[7:4] word4[3:0] CS[4] CS[3] Rev. 0 | Page 62 of 108 ADV7184 Table 82. Data Byte Allocation 2× 1 1 0 0 Raw Information Bytes Retrieved from the Video Line 4 4 2 2 GDECAD 0 1 0 1 User Data-Words (Including Padding) 8 4 4 4 Padding Bytes 0 0 0 2 DC[1:0] 10 01 01 01 Gemstar Bit Names • DID. The data identification value is 0x140 (10-bit value). Care has been taken that in 8-bit systems, the two LSBs do not carry vital information. EP and EP. The EP bit is set to ensure even parity on the data-word D[8:0]. Even parity means there is always an even number of 1s within the D[8:0] bit arrangement. This includes the EP bit. EP describes the logic inverse of EP and is output on D[9]. The EP is output to ensure that the reserved codes of 00 and FF cannot happen. EF. Even field identifier. EF = 1 indicates that the data was recovered from a video line on an even field. 2X. This bit indicates whether the data sliced was in Gemstar 1× or 2× format. A high indicates 2× format. line[3:0]. This entry provides a code that is unique for each of the possible 16 source lines of video from which Gemstar data may have been retrieved. Refer to Table 91 and Table 92. DC[1:0]. Data count value. The number of UDWs in the packet divided by 4. The number of UDWs in any packet must be an integral number of 4. Padding is required at the end, if necessary, as set in ITU-R BT.1364. See Table 82. The 2X bit determines whether the raw information retrieved from the video line was 2 or 4 bytes. The state of the GDECAD bit affects whether the bytes are transmitted straight (that is, two bytes transmitted as two bytes) or whether they are split into nibbles (that is, two bytes transmitted as four half bytes). Padding bytes are then added where necessary. • CS[8:2]. The checksum is provided to determine the integrity of the ancillary data packet. It is calculated by summing up D[8:2] of DID, SDID, the data count byte, and all UDWs, and ignoring any overflow during the summation. Since all data bytes that are used to calculate the checksum have their 2 LSBs set to 0, the CS[1:0] bits are also always 0. CS[8] describes the logic inversion of CS[8]. The value CS[8] is included in the checksum entry of the data packet to ensure that the reserved values of 0x00 and 0xFF do not occur. Table 83 to Table 88 outline the possible data packages. Gemstar 2× Format, Half-Byte Output Mode • • • • Half-byte output mode is selected by setting CDECAD = 0; fullbyte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. Gemstar 1× Format • Half-byte output mode is selected by setting CDECAD = 0, fullbyte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. • Rev. 0 | Page 63 of 108 ADV7184 Table 83. Gemstar 2× Data, Half-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 D[9] 0 1 1 0 EP EP EP EP EP EP EP EP EP EP CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 0 0 0 0 CS[7] D[6] 0 1 1 1 1 0 0 0 0 0 0 0 0 0 CS[6] CS[5] D[5] 0 1 1 0 0 D[4] 0 1 1 0 0 D[3] 0 1 1 0 line[3:0] 1 D[2] 0 1 1 0 0 D[1] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words User data-words User data-words User data-words User data-words Checksum Gemstar word1[7:4] Gemstar word1[3:0] Gemstar word2[7:4] Gemstar word2[3:0] Gemstar word3[7:4] Gemstar word3[3:0] Gemstar word4[7:4] Gemstar word4[3:0] CS[4] CS[3] CS[2] Table 84. Gemstar 2× Data, Full-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] 0 1 1 1 1 0 D[5] 0 1 1 0 0 D[4] D[3] 0 0 1 1 1 1 0 0 line[3:0] 0 0 D[2] 0 1 1 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum CS[8] CS[8] CS[7] Gemstar word1[7:0] Gemstar word2[7:0] Gemstar word3[7:0] Gemstar word4[7:0] CS[6] CS[5] CS[4] CS[3] CS[2] Table 85. Gemstar 1× Data, Half-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP EP EP EP EP CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] CS[5] D[5] 0 1 1 0 0 D[4] 0 1 1 0 0 D[3] 0 1 1 0 line[3:0] 0 D[2] 0 1 1 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum Gemstar word1[7:4] Gemstar word1[3:0] Gemstar word2[7:4] Gemstar word2[3:0] CS[4] CS[3] CS[2] Rev. 0 | Page 64 of 108 ADV7184 Table 86. Gemstar 1× Data, Full-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] 0 1 1 1 0 0 D[5] 0 1 1 0 0 D[4] 0 1 1 0 0 D[3] 0 1 1 0 line[3:0] 0 D[2] 0 1 1 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words UDW padding 0x200 UDW padding 0x200 Checksum 1 1 CS[8] 0 0 CS[8] 0 0 CS[7] Gemstar word1[7:0] Gemstar word2[7:0] 0 0 0 0 0 0 CS[6] CS[5] CS[4] 0 0 CS[3] 0 0 CS[2] Table 87. NTSC CCAP Data, Half-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP EP EP EP EP CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] CS[5] D[5] 0 1 1 0 1 0 D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 1 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[2] CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum CCAP word1[7:4] CCAP word1[3:0] CCAP word2[7:4] CCAP word2[3:0] CS[4] CS[3] Table 88. NTSC CCAP Data, Full-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] 0 1 1 1 0 0 D[5] 0 1 1 0 1 0 D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 1 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words UDW padding 0x200 UDW padding 0x200 Checksum 1 1 CS[8] 0 0 CS[8] 0 0 CS[7] CCAP word1[7:0] CCAP word2[7:0] 0 0 0 0 CS[6] CS[5] 0 0 CS[4] 0 0 CS[3] 0 0 CS[2] Rev. 0 | Page 65 of 108 ADV7184 Table 89. PAL CCAP Data, Half-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP EP EP EP EP CS[8] D[8] 0 1 1 1 EP EP EP EP EP EP CS[8] D[7] 0 1 1 0 EF 0 0 0 0 0 CS[7] D[6] 0 1 1 1 0 0 0 0 0 0 CS[6] CS[5] D[5] 0 1 1 0 1 0 D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[2] CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data count User data-words User data-words User data-words User data-words Checksum CCAP word1[7:4] CCAP word1[3:0] CCAP word2[7:4] CCAP word2[3:0] CS[4] CS[3] Table 90. PAL CCAP Data, Full-Byte Mode Byte 0 1 2 3 4 5 6 7 8 9 10 D[9] 0 1 1 0 EP EP D[8] 0 1 1 1 EP EP D[7] 0 1 1 0 EF 0 D[6] 0 1 1 1 0 0 D[5] 0 1 1 0 1 0 D[4] 0 1 1 0 0 0 D[3] 0 1 1 0 1 0 D[2] 0 1 1 0 0 1 D[1] 0 1 1 0 0 0 0 0 0 0 CS[1] D[0] 0 1 1 0 0 0 0 0 0 0 CS[0] Description Fixed preamble Fixed preamble Fixed preamble DID SDID Data Count User data-words User data-words UDW padding 200h UDW padding 200h Checksum 1 1 CS[8] 0 0 CS[8] 0 0 CS[7] CCAP word1[7:0] CCAP word2[7:0] 0 0 0 0 CS[6] CS[5] 0 0 CS[4] 0 0 CS[3] 0 0 CS[2] NTSC CCAP Data Half-byte output mode is selected by setting CDECAD = 0, the full-byte mode is enabled by CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. The data packet formats are shown in Table 87 and Table 88. Only closed caption data can be embedded in the output data stream. NTSC closed caption data is sliced on Line 21d on even and odd fields. The corresponding enable bit has to be set high. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] and GDECOL[15:0] Gemstar Decoding Odd Lines, Address 0x4A [7:0]; Address 0x4B [7:0] sections. PAL CCAP Data See the GDECEL[15:0] Gemstar Decoding Even Lines, Address 0x48 [7:0]; Address 0x49 [7:0] and GDECOL[15:0] Gemstar Decoding Odd Lines, Address 0x4A [7:0]; Address 0x4B [7:0] sections. GDECEL[15:0] Gemstar Decoding Even Lines, Address 0x48 [7:0]; Address 0x49 [7:0] The 16 bits of the GDECEL[15:0] are interpreted as a collection of 16 individual line decode enable signals. Each bit refers to a line of video in an even field. Setting the bit enables the decoder block trying to find Gemstar or closed caption-compatible data on that particular line. Setting the bit to 0 prevents the decoder from trying to retrieve data. See Table 91 and Table 92. To retrieve closed caption data services on NTSC (Line 284), GDECEL[11] must be set. To retrieve closed caption data services on PAL (Line 335), GDECEL[14] must be set. The default value of GDECEL[15:0] is 0x0000. This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the even field. The user should only enable Gemstar slicing on lines where VBI data is expected. Half-byte output mode is selected by setting CDECAD = 0, fullbyte output mode is selected by setting CDECAD = 1. See the GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] section. Table 89and Table 90 list the bytes of the data packet. Only closed caption data can be embedded in the output data stream. PAL closed caption data is sliced from Line 22 and Line 335. The corresponding enable bits have to be set. Rev. 0 | Page 66 of 108 ADV7184 Table 91. NTSC Line Enable Bits and Corresponding Line Numbering Line[3:0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Line Number (ITU-R BT.470) 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 273 (10) 274 (11) 275 (12) 276 (13) 277 (14) 278 (15) 279 (16) 280 (17) 281 (18) 282 (19) 283 (20) 284 (21) 285 (22) 286 (23) 287 (24) 288 (25) Enable Bit GDECOL[0] GDECOL[1] GDECOL[2] GDECOL[3] GDECOL[4] GDECOL[5] GDECOL[6] GDECOL[7] GDECOL[8] GDECOL[9] GDECOL[10] GDECOL[11] GDECOL[12] GDECOL[13] GDECOL[14] GDECOL[15] GDECEL[0] GDECEL[1] GDECEL[2] GDECEL[3] GDECEL[4] GDECEL[5] GDECEL[6] GDECEL[7] GDECEL[8] GDECEL[9] GDECEL[10] GDECEL[11] GDECEL[12] GDECEL[13] GDECEL[14] GDECEL[15] Comment Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar or closed caption Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar Gemstar or closed caption Gemstar Gemstar Gemstar Gemstar GDECOL[15:0] Gemstar Decoding Odd Lines, Address 0x4A [7:0]; Address 0x4B [7:0] The 16 bits of the GDECOL[15:0] form a collection of 16 individual line decode enable signals. See Table 91 and Table 92. To retrieve closed caption data services on NTSC (Line 21), GDECOL[11] must be set. To retrieve closed caption data services on PAL (Line 22), GDECOL[14] must be set. The default value of GDEC0L[15:0] is 0x0000. This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the odd field. The user should only enable Gemstar slicing on lines where VBI data is expected. GDECAD Gemstar Decode Ancillary Data Format, Address 0x4C [0] The decoded data from Gemstar-compatible transmissions or closed caption transmission is inserted into the horizontal blanking period of the respective line of video. A potential problem can arise if the retrieved data bytes have the value 0x00 or 0xFF. In an ITU-R BT.656-compatible data stream, those values are reserved and used only to form a fixed preamble. The GDECAD bit allows the data to be inserted into the horizontal blanking period in two ways: • Insert all data straight into the data stream, even the reserved values of 0x00 and 0xFF, if they occur. This may violate the output data format specification ITU-R BT.1364. Split all data into nibbles and insert the half-bytes over double the number of cycles in a 4-bit format. • 0 (default)—The data is split into half-bytes and inserted. 1—The data is output straight in 8-bit format. Rev. 0 | Page 67 of 108 ADV7184 Table 92. PAL Line Enable Bits and Corresponding Line Numbering Line[3:0] 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 Line Number (ITU-R BT.470) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 321 (8) 322 (9) 323 (10) 324 (11) 325 (12) 326 (13) 327 (14) 328 (15) 329 (16) 330 (17) 331 (18) 332 (19) 333 (20) 334 (21) 335 (22) 336 (23) Enable Bit GDECOL[0] GDECOL[1] GDECOL[2] GDECOL[3] GDECOL[4] GDECOL[5] GDECOL[6] GDECOL[7] GDECOL[8] GDECOL[9] GDECOL[10] GDECOL[11] GDECOL[12] GDECOL[13] GDECOL[14] GDECOL[15] GDECEL[0] GDECEL[1] GDECEL[2] GDECEL[3] GDECEL[4] GDECEL[5] GDECEL[6] GDECEL[7] GDECEL[8] GDECEL[9] GDECEL[10] GDECEL[11] GDECEL[12] GDECEL[13] GDECEL[14] GDECEL[15] Comment Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Closed caption Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Not valid Closed caption Not valid The active video content (luminance magnitude) over a line of video is summed together. At the end of a line, this accumulated value is compared with a threshold and a decision is made as to whether or not a particular line is black. The threshold value needed may depend on the type of input signal; some control is provided via LB_TH[4:0]. Detection at the Start of a Field The ADV7184 expects a section of at least six consecutive black lines of video at the top of a field. Once those lines are detected, register LB_LCT[7:0] reports back the number of black lines that were actually found. By default, the ADV7184 starts looking for those black lines in sync with the beginning of active video, for example, straight after the last VBI video line. LB_SL[3:0] allows the user to set the start of letterbox detection from the beginning of a frame on a line-by-line basis. The detection window closes in the middle of the field. Detection at the End of a Field The ADV7184 expects at least six continuous lines of black video at the bottom of a field before reporting the number of lines actually found via the LB_LCB[7:0] value. The activity window for letterbox detection (end of field) starts in the middle of an active field. Its end is programmable via LB_EL[3:0]. Detection at the Midrange Some transmissions of wide screen video include subtitles within the lower black box. If the ADV7184 finds at least two black lines followed by some more nonblack video, for example, the subtitle, followed by the remainder of the bottom black block, it reports a midcount via LB_LCM[7:0]. If no subtitles are found, LB_LCM[7:0] reports the same number as LB_LCB[7:0]. There is a 2-field delay in the reporting of any line count parameters. There is no letterbox detected bit. Read the LB_LCT[7:0] and LB_LCB[7:0] register values to conclude whether or not the letterbox-type video is present in software. LB_LCT[7:0] Letterbox Line Count Top, Address 0x9B [7:0]; LB_LCM[7:0] Letterbox Line Count Mid, Address 0x9C [7:0]; LB_LCB[7:0] Letterbox Line Count Bottom, Address 0x9D [7:0] Table 93. LB_LCx Access Information 1 Signal Name LB_LCT[7:0] LB_LCM[7:0] LB_LCB[7:0] 1 Letterbox Detection Incoming video signals may conform to different aspect ratios (16:9 wide screen or 4:3 standard). For certain transmissions in the wide screen format, a digital sequence (WSS) is transmitted with the video signal. If a WSS sequence is provided, the aspect ratio of the video can be derived from the digitally decoded bits WSS contains. In the absence of a WSS sequence, letterbox detection may be used to find wide screen signals. The detection algorithm examines the active video content of lines at the start and end of a field. If black lines are detected, this may indicate that the currently shown picture is in wide screen format. Address 0x9B 0x9C 0x9D This register is a readback register; default value does not apply. Rev. 0 | Page 68 of 108 ADV7184 LB_TH[4:0] Letterbox Threshold Control, Address 0xDC [4:0] Table 94. LB_TH Function LB_TH[4:0] 01100 (default) 01101 to 10000 00000 to 01011 AMPLITUDE (dB) 6 4 Description Default threshold for detection of black lines. Increase threshold (need larger active video content before identifying nonblack lines). Decrease threshold (even small noise levels can cause the detection of nonblack lines). 2 0 –2 –4 –6 LB_SL[3:0] Letterbox Start Line, Address 0xDD [7:4] The LB_SL[3:0] bits are set at 0100 by default. For an NTSC signal, this window is from Line 23 to Line 286. By changing the bits to 0101, the detection window starts on Line 24 and ends on Line 287. LB_EL[3:0] Letterbox End Line, Address 0xDD [3:0] –8 3.0 3.5 4.0 4.5 5.0 5.5 6.0 FREQUENCY (MHz) Figure 43. PAL IF Compensation Filter Responses See Table 102 for programming details. I2C Interrupt System The ADV7184 has a comprehensive interrupt register set. This map is located in the User Sub Map. See Table 103 for details of the interrupt register map. Figure 46 describes how to access this map. Interrupt Request Output Operation The LB_EL[3:0] bits are set at 1101 by default. This means that letterbox detection window ends with the last active video line. For an NTSC signal, this window is from Line 262 to Line 525. By changing the bits to 1100, the detection window starts on Line 261 and ends on Line 254. IF Compensation Filter IFFILTSEL[2:0] IF Filter Select Address 0xF8 [2:0] When an interrupt event occurs, the interrupt pin INTRQ goes low with a programmable duration given by INTRQ_DUR_SEL[1:0] INTRQ_DURSEL[1:0], Interrupt Duration Select Address 0x40 [7:6], User Sub Map Table 95. INTRQ_DUR_SEL INTRQ_DURSEL[1:0] 00 (default) 01 10 11 Description 3 XTAL periods. 15 XTAL periods. 63 XTAL periods. Active until cleared. The IFFILTSEL[2:0] register allows the user to compensate for SAW filter characteristics on a composite input as would be observed on tuner outputs. Figure 42 and Figure 43 show IF filter compensation for NTSC and PAL. The options for this feature are as follows: • • • Bypass mode (default) NTSC—consists of three filter characteristics PAL—consists of three filter characteristics 6 4 2 AMPLITUDE (dB) When the active-until-cleared interrupt duration is selected, and the event that caused the interrupt is no longer in force, the interrupt persists until it is masked or cleared. For example, if the ADV7184 loses lock, an interrupt is generated and the INTRQ pin goes low. If the ADV7184 returns to the locked state, INTRQ continues to drive low until the SD_LOCK bit is either masked or cleared. 0 –2 –4 –6 –8 –10 –12 2.0 05479-046 2.5 3.0 3.5 4.0 4.5 5.0 FREQUENCY (MHz) Figure 42. NTSC IF Compensation Filter Responses Rev. 0 | Page 69 of 108 05479-047 ADV7184 Interrupt Drive Level Multiple Interrupt Events The ADV7184 resets with open drain enabled and all interrupts masked off. Therefore INTRQ is in a high impedance state after reset. 01 or 10 has to be written to INTRQ_OP_SEL[1:0] for a logic level to be driven out from the INTRQ pin. It is also possible to write to a register in the ADV7184 that manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ. INTRQ_OP_SEL[1:0], Interrupt Duration Select Address 0x40 [1:0], User Sub Map Table 96. INTRQ_OP_SEL INTRQ_OP_SEL[1:0] 00 (default) 01 10 11 Description Open drain. Drive low when active. Drive high when active. Reserved. If interrupt event 1 occurs and then interrupt event 2 occurs before the system controller has cleared or masked interrupt event 1, the ADV7184 does not generate a second interrupt signal. The system controller should check all unmasked interrupt status bits since more than one may be active. Macrovision Interrupt Selection Bits The user can select between pseudo sync pulse and color stripe detection as follows: MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection Bits Address 0x40 [5:4], User Sub Map Table 97. MV_INTRQ_SEL MV_INTRQ_SEL [1:0] 00 01 (default) 10 11 Description Reserved. Pseudo sync only. Color stripe only. Either pseudo sync or color stripe. Additional information relating to the interrupt system is detailed in Table 104. Rev. 0 | Page 70 of 108 ADV7184 PIXEL PORT CONFIGURATION The ADV7184 has a very flexible pixel port that can be configured in a variety of formats to accommodate downstream ICs. Table 98 and Table 99 summarize the various functions that the ADV7184’s pins can have in different modes of operation. The ordering of components (Cr vs. Cb, CHA/B/C, for example) can be changed. Refer to the SWPC Swap Pixel Cr/Cb, Address 0x27 [7] section. Table 98 indicates the default positions for the Cr/Cb components. OF_SEL[3:0] Output Format Selection, Address 0x03 [5:2] SWPC Swap Pixel Cr/Cb, Address 0x27 [7] 0 (default)—No swapping is allowed. 1—The Cr and Cb values can be swapped. LLC_PAD_SEL[2:0] LLC1 Output Selection, Address 0x8F [6:4] The following I2C write allows the user to select between LLC1 (nominally at 27 MHz) and LLC2 (nominally at 13.5 MHz). The LLC2 signal is useful for LLC2-compatible wide bus (16-bit) output modes. See the OF_SEL[3:0] Output Format Selection, Address 0x03 [5:2] section for additional information. The LLC2 signal and data on the data bus are synchronized. By default, the rising edge of LLC1/LLC2 is aligned with the Y data; the falling edge occurs when the data bus holds C data. The polarity of the clock, and therefore the Y/C assignments to the clock edges, can be altered by using the Polarity LLC pin. 000 (default)—The output is nominally 27 MHz LLC on the LLC1 pin. 101—The output is nominally 13.5 MHz LLC on the LLC1 pin. The modes in which the ADV7184 pixel port can be configured are under the control of OF_SEL[3:0]. See Table 99 for details. The default LLC frequency output on the LLC1 pin is approximately 27 MHz. For modes that operate with a nominal data rate of 13.5 MHz (0001, 0010), the clock frequency on the LLC1 pin stays at the higher rate of 27 MHz. For information on outputting the nominal 13.5 MHz clock on the LLC1 pin, see the LLC_PAD_SEL[2:0] LLC1 Output Selection, Address 0x8F [6:4] section. Table 98. P15–P0 Output/Input Pin Mapping Format, and Mode Video Out, 8-Bit, 4:2:2 Video Out, 16-Bit, 4:2:2 15 14 13 12 11 YCrCb[7:0]OUT Y[7:0]OUT Data Port Pins P[15:0] 10 9 8 7 6 5 4 3 2 1 0 CrCb[7:0] OUT Table 99. Standard Definition Pixel Port Modes OF_SEL[3:0] 0010 0011 (default) 0110-1111 Format 16-Bit at LLC2 4:2:2 8-Bit at LLC1 4:2:2 (default) Reserved Pixel Port Pins P[15: 0] P[15:8] P[7: 0] Y[7:0] CrCb[7:0] YCrCb[7:0] (default) Three-State Reserved. Do not use. Rev. 0 | Page 71 of 108 ADV7184 MPU PORT DESCRIPTION The ADV7184 supports a 2-wire (I2C-compatible) serial interface. Two inputs, serial data (SDA) and serial clock (SCLK), carry information between the ADV7184 and the system I2C master controller. Each slave device is recognized by a unique address. The ADV7184’s I2C port allows the user to set up and configure the decoder and to read back captured VBI data. The ADV7184 has two possible slave addresses for both read and write operations, depending on the logic level on the ALSB pin. These four unique addresses are shown in Table 100. The ALSB pin controls Bit 1 of the slave address. By altering the ALSB, it is possible to control two ADV7184s in an application without having a conflict with the same slave address. The LSB (Bit 0) sets either a read or write operation. Logic 1 corresponds to a read operation; Logic 0 corresponds to a write operation. Table 100. I2C Address ALSB 0 0 1 1 R/W 0 1 0 1 Slave Address 0x40 0x41 0x42 0x43 The ADV7184 acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit. The ADV7184 has 249 subaddresses to enable access to the internal registers. It therefore interprets the first byte as the device address and the second byte as the starting subaddress. The subaddresses auto-increment, allowing data to be written to or read from the starting subaddress. A data transfer is always terminated by a stop condition. The user can also access any unique subaddress register on a one-by-one basis without updating all the registers. Stop and start conditions can be detected at any stage during the data transfer. If these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. During a given SCLK high period, the user should issue only one start condition, one stop condition, or a single stop condition followed by a single start condition. If an invalid subaddress is issued by the user, the ADV7184 does not issue an acknowledge and returns to the idle condition. If in autoincrement mode the highest subaddress is exceeded, the following action is taken: 1. In read mode, the highest subaddress register contents continue to be output until the master device issues a no acknowledge. This indicates the end of a read. In a no acknowledge condition the SDA line is not pulled low on the ninth pulse. In write mode, the data for the invalid byte is not loaded into any subaddress register, a no acknowledge is issued by the ADV7184, and the part returns to the idle condition. To control the device on the bus, a specific protocol must be followed. First, the master initiates a data transfer by establishing a start condition, which is defined by a high-to-low transition on SDA while SCLK remains high. This indicates that an address/data stream follows. All peripherals respond to the start condition and shift the next eight bits (7-bit address + R/W bit). The bits are transferred from MSB down to LSB. The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse; this is known as an acknowledge bit. All other devices withdraw from the bus at this point and maintain an idle condition. The idle condition is where the device monitors the SDA and SCLK lines, waiting for the start condition and the correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first byte means the master writes information to the peripheral. Logic 1 on the LSB of the first byte means the master reads information from the peripheral. 2. SDATA S 1–7 8 9 1–7 8 9 1–7 DATA 8 9 ACK P STOP START ADDR R/W ACK SUBADDRESS ACK Figure 44. Bus Data Transfer WRITE SEQUENCE S SLAVE ADDR A(S) LSB = 0 SUB ADDR A(S) DATA A(S) LSB = 1 DATA A(S) P S = START BIT P = STOP BIT A(S) = ACKNOWLEDGE BY SLAVE A(M) = ACKNOWLEDGE BY MASTER A(S) = NO-ACKNOWLEDGE BY SLAVE A(M) = NO-ACKNOWLEDGE BY MASTER Figure 45. Read and Write Sequence Rev. 0 | Page 72 of 108 05479-050 READ SEQUENCE S SLAVE ADDR A(S) SUB ADDR A(S) S SLAVE ADDR A(S) DATA A(M) DATA A(M) P 05479-049 SCLOCK ADV7184 REGISTER ACCESSES The MPU can write to or read from most of the ADV7184’s registers, excepting the registers that are read only or write only. The subaddress register determines which register the next read or write operation accesses. All communications with the part through the bus start with an access to the subaddress register. A read/write operation is then performed from/to the target address, which then increments to the next address until a stop command on the bus is performed. USER MAP COMMON I2C SPACE ADDRESS 0x00 ≥ 0x3F USER SUB MAP ADDRESS 0x0E BIT 5 = 0b ADDRESS 0x0E BIT 5 = 1b REGISTER PROGRAMMING The I2C Register Maps section describes each register in terms of its configuration. After the part has been accessed over the bus and a read/write operation is selected, the subaddress is set up. The subaddress register determines to/from which register the operation takes place. Table 103and Table 104 list the various operations under the control of the subaddress register. As can be seen in Figure 46, the registers in the ADV7184 are arranged into two maps: the User Map (enabled by default) and the User Sub Map. The User Sub Map has controls for the interrupt and VDP functionality on the ADV7184 and the User Map controls everything else. The User Map and the User Sub Map consist of a common space from address 0x00 to 0x3F. Depending on how Bit 5 in register 0x0E (SUB_USR_EN) is set, the register map then splits in two sections. SUB_USR_EN, Address 0x0E [5] NORMAL REGISTER SPACE INTERRUPT AND VDP REGISTER SPACE Figure 46: Register Access —User Map and User Sub Map I2C SEQUENCER An I2C sequencer is used when a parameter exceeds eight bits, and is therefore distributed over two or more I2C registers, for example, HSB [11:0]. When such a parameter is changed using two or more I2C write operations, the parameter may hold an invalid value for the time between the first and last I2C being completed. In other words, the top bits of the parameter may already hold the new value while the remaining bits of the parameter still hold the previous value. To avoid this problem, the I2C sequencer holds the already updated bits of the parameter in local memory; all bits of the parameter are updated together once the last register write operation has completed. The correct operation of the I2C sequencer relies on the following: • All I2C registers for the parameter in question must be written to in order of ascending addresses. For example, for HSB[10:0], write to Address 0x34 first, followed by 0x35. No other I2C taking place between the two (or more) I2C writes for the sequence. For example, for HSB[10:0], write to Address 0x34 first, immediately followed by 0x35. This bit splits the register map at register 0x40. 0 (default)—The register map does not split and the User Map is enabled. 1—The register map splits and the User Sub Map is enabled. • Rev. 0 | Page 73 of 108 05479-048 I2C SPACE ADDRESS 0x40 ≥ 0xFF I2C SPACE ADDRESS 0x40 ≥ 0x9C ADV7184 I2C REGISTER MAPS USER MAP The collective name for the registers in Table 101 below is the User Map. Table 101. User Map Register Details Address Dec Hex 0 00 1 01 3 03 4 04 7 07 8 08 10 0A 11 0B 12 13 14 15 16 18 19 19 20 21 23 24 25 29 39 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 61 65 72 73 74 75 76 77 78 80 81 0C 0D 0E 0F 10 12 13 13 14 15 17 18 19 1D 27 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3D 41 48 49 4A 4B 4C 4D 4E 50 51 Register Name Input Ctrl Video Selection Output Ctrl Ext Output Ctrl Autodetect Enable Contrast Brightness Hue Default Value Y Default Value C ADI Ctrl Power Mgmt Status 1 Status 2 Status 3 Analog Ctrl Internal Analog Clamp Ctrl Digital Clamp Ctrl 1 Shaping Filter Ctrl Shaping Filter Ctrl 2 Comb Filter Ctrl ADI Ctrl 2 Pixel Delay Ctrl Misc Gain Ctrl AGC Mode Ctrl Chroma Gain Ctrl 1 Chroma Gain Ctrl 2 Luma Gain Ctrl 1 Luma Gain Ctrl 2 VSYNC Field Ctrl 1 VSYNC Field Ctrl 2 VSYNC Field Ctrl 3 HSYNC Pos Ctrl 1 HSYNC Pos Ctrl 2 HSYNC Pos Ctrl 3 Polarity NTSC Comb Ctrl PAL Comb Ctrl ADC Ctrl Man Window Ctrl Resample Ctrl Gemstar Ctrl 1 Gemstar Ctrl 2 Gemstar Ctrl 3 Gemstar Ctrl 4 Gemstar Ctrl 5 CTI DNR Ctrl 1 CTI DNR Ctrl 2 CTI DNR Ctrl 4 Lock Count Free Run Line Length1 CCAP 1 CCAP 2 RW RW RW RW RW RW RW RW RW 7 VID_SEL.3 VBI_EN BT656-4 AD_SEC525_EN CON.7 BRI.7 HUE.7 6 VID_SEL.2 ENHSPLL TOD AD_SECAM_EN CON.6 BRI.6 HUE.6 DEF_Y.4 DEF_C.6 5 VID_SEL.1 BETACAM OF_SEL.3 AD_N443_EN CON.5 BRI.5 HUE.5 DEF_Y.3 DEF_C.5 SUB_USR_EN PWRDN AD_RESULT.1 FSC NSTD STD FLD LEN 4 VID_SEL.0 OF_SEL.2 AD_P60_EN CON.4 BRI.4 HUE.4 DEF_Y.2 DEF_C.4 3 INSEL.3 ENVSPROC OF_SEL.1 TIM_OE AD_PALN_EN CON.3 BRI.3 HUE.3 DEF_Y.1 DEF_C.3 2 INSEL.2 OF_SEL.0 BL_C_VBI AD_PALM_EN CON.2 BRI.2 HUE.2 DEF_Y.0 DEF_C.2 PDBP FSC_LOCK MV PS DET SD_OP_50Hz XTAL_TTL_SEL 1 INSEL.1 0 INSEL.0 SD_DUP_AV RANGE AD_PAL_EN CON.0 BRI.0 HUE.0 Reset Value 00000000 11001000 00001100 01xx0101 01111111 10000000 00000000 00000000 (Hex) 00 C8 0C 45 7F 80 00 00 RW DEF_Y.5 RW DEF_C.7 RW R R R W RW RW RW RW RW RW RW RW RW W W W W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW W R R RES COL_KILL EN_SFL_PIN AD_NTSC_EN CON.1 BRI.1 HUE.1 DEF_VAL_ AUTO_EN DEF_C.1 FB_PWRDN LOST_LOCK MVCS T3 GEMD AD_RESULT.2 PAL_SW_LOCK INTERLACE AD_RESULT.0 FOLLOW_PW LL NSTD MV AGC DET FREE_RUN_ACT CVBS CCLEN CSFM.2 WYSFMOVR TRI_LLC SWPC DCT.1 CSFM.1 DCT.0 CSFM.0 YSFM.4 WYSFM.4 YSFM.3 WYSFM.3 NSFSEL.1 CTA.0 YSFM.2 WYSFM.2 NSFSEL.0 YSFM.1 WYSFM.1 PSFSEL.1 LTA.1 CAGC.1 CMG.9 CMG.1 LMG.9 LMG.1 CAGT.1 CMG.7 LAGT.1 LMG.7 VSBHO VSEHO HSB.7 HSE.7 PHS CTAPSN.1 CTAPSP.1 EN28XTAL AUTO_PDC_EN CKE LAGC.2 CAGT.0 CMG.6 LGAT.0 LMG.6 VSBHE VSEHE HSB.10 HSB.6 HSE.6 CTAPSN.0 CTAPSP.0 CKILLTHR.2 SFL_INV GDECEL.14 GDECEL.6 GDECOL.14 GDECOL.6 CTA.2 LAGC.1 CMG.5 LMG.5 CTA.1 LAGC.0 CMG.4 LMG.4 NEWAVMODE CMG.11 CMG.3 LMG.11 LMG.3 HVSTIM CMG.10 CMG.2 LMG.10 LMG.2 HSB.9 HSB.5 HSE.5 PVS CCMN.2 CCMP.2 CKILLTHR.1 GDECEL.13 GDECEL.5 GDECOL.13 GDECOL.5 DNR_EN CTI_C_TH.5 DNR_TH.5 COL.2 LLC_PAD_ SEL.1 CCAP1.5 CCAP2.5 HSB.8 HSB.4 HSE.4 CCMN.1 CCMP.1 CKILLTHR.0 GDECEL.12 GDECEL.4 GDECOL.12 GDECOL.4 HSB.3 HSE.3 PF CCMN.0 CCMP.0 PDN_ADC0 HSE.10 HSB.2 HSE.2 YCMN.2 YCMP.2 PDN_ADC1 HSE.9 HSB.1 HSE.1 YCMN.1 YCMP.1 PDN_ADC2 GDECEL.15 GDECEL.7 GDECOL.15 GDECOL.7 GDECEL.11 GDECEL.3 GDECOL.11 GDECOL.3 CTI_AB.1 CTI_C_TH.3 DNR_TH.3 COL.0 GDECEL.10 GDECEL.2 GDECOL.10 GDECOL.2 CTI_AB.0 CTI_C_TH.2 DNR_TH.2 CIL.2 GDECEL.9 GDECEL.1 GDECOL.9 GDECOL.1 CTI_AB_EN CTI_C_TH.1 DNR_TH.1 CIL.1 CTI_C_TH.7 DNR_TH.7 FSCLE 143 8F 153 99 154 9A CCAP1.7 CCAP2.7 CTI_C_TH.6 DNR_TH.6 SRLS LLC_PAD_ SEL_MAN CCAP1.6 CCAP2.6 CTI_C_TH.4 DNR_TH.4 COL.1 LLC_PAD_ SEL.0 CCAP1.4 CCAP2.4 DEF_VAL_EN 00110110 36 DEF_C.0 01111100 7C 00000000 00 00000000 00 IN_LOCK ----MVCS DET ----INST_HLOCK ----00000000 00 00010010 12 0000xxxx 00 YSFM.0 00000001 01 WYSFM.0 10010011 93 PSFSEL.0 11110001 F1 00000xxx 00 LTA.0 01011000 58 PW_UPD 11100001 E1 CAGC.0 10101110 AE CMG.8 11110100 F4 CMG.0 00000000 00 LMG.8 1111xxxx F0 LMG.0 xxxxxxxx 00 00010010 12 01000001 41 10000100 84 HSE.8 00000000 00 HSB.0 00000010 02 HSE.0 00000000 00 PCLK 00000001 01 YCMN.0 10000000 80 YCMP.0 11000000 C0 PDN_ADC3 00010001 11 01000011 43 00000001 01 GDECEL.8 00000000 00 GDECEL.0 00000000 00 GDECOL.8 00000000 00 GDECOL.0 00000000 00 GDECAD xxxx0000 00 CTI_EN 11101111 EF CTI_C_TH.0 00001000 08 DNR_TH.0 00001000 08 CIL.0 00100100 24 00000000 00 --------- CCAP1.3 CCAP2.3 CCAP1.2 CCAP2.2 CCAP1.1 CCAP2.1 CCAP1.0 CCAP2.0 Rev. 0 | Page 74 of 108 ADV7184 Address Dec Hex 155 9B 156 9C 157 9D 195 C3 196 C4 220 DC 221 DD 222 DE 223 DF 225 E1 226 E2 227 E3 228 E4 229 E5 230 E6 231 E7 232 E8 233 E9 234 EA 235 EB 236 EC 237 ED 237 ED 238 EE 239 240 241 243 244 248 EF F0 F1 F3 F4 F8 Register Name Letterbox 1 Letterbox 2 Letterbox 3 ADC Switch 1 ADC Switch 2 Letterbox Ctrl1 Letterbox Ctrl2 ST Noise Readback 1 ST Noise Readback 2 SD Offset Cb SD Offset Cr SD Saturation CB SD Saturation Cr NTSC V bit begin NTSC V bit end NTSC F bit toggle PAL V bit begin PAL V bit end PAL F bit toggle Vblank Ctrl 1 Vblank Ctrl2 FB_STATUS FB_CONTROL1 FB_CONTROL 2 FB_CONTROL 3 FB_CONTROL 4 FB_CONTROL 5 AFE_CONTROL 1 Drive Strength IF Comp Ctrl VS Mode Ctrl Peaking Ctrl Coring Threshold 2 RW R R R RW RW RW RW R R RW RW RW RW RW RW RW RW RW RW RW RW R W 7 LB_LCT.7 LB_LCM.7 LB_LCB.7 ADC1_SW.3 ADC_SW_MAN LB_SL.3 ST_NOISE.7 SD_OFF_CB.7 SD_OFF_CR.7 SD_SAT_CB.7 SD_SAT_CR.7 NVBEGDELO NVENDDELO NFTOGDELO PVBEGDELO PVENDDELO PFTOGDELO NVBIOLCM.1 NVBIOCCM.1 FB_STATUS.3 6 LB_LCT.6 LB_LCM.6 LB_LCB.6 ADC1_SW.2 5 LB_LCT.5 LB_LCM.5 LB_LCB.5 ADC1_SW.1 4 LB_LCT.4 LB_LCM.4 LB_LCB.4 ADC1_SW.0 LB_TH.4 LB_SL.0 ST_NOISE.4 SD_OFF_CB.4 SD_OFF_CR.4 SD_SAT_CB.4 SD_SAT_CR.4 NVBEG.4 NVEND.4 NFTOG.4 PVBEG.4 PVEND.4 PFTOG.4 NVBIELCM.0 NVBIECCM.0 FB_STATUS.0 MAN_ALPHA_ VAL.4 FB_SP_ ADJUST.0 FB_LEVEL.0 ADC3_SW.0 DR_STR.0 3 LB_LCT.3 LB_LCM.3 LB_LCB.3 ADC0_SW.3 ADC2_SW.3 LB_TH.3 LB_EL.3 ST_NOISE_VLD ST_NOISE.3 SD_OFF_CB.3 SD_OFF_CR.3 SD_SAT_CB.3 SD_SAT_CR.3 NVBEG.3 NVEND.3 NFTOG.3 PVBEG.3 PVEND.3 PFTOG.3 PVBIOLCM.1 PVBIOCCM.1 FB_INV MAN_ALPHA_ VAL.3 CNTR_ ENABLE FB_DELAY.3 CNTR_MODE.1 AA_FILT_EN.3 DR_STR_C VS_COAST_ MODE.1 PEAKING_ GAIN.3 DNR_TH2.3 2 LB_LCT.2 LB_LCM.2 LB_LCB.2 ADC0_SW.2 ADC2_SW.2 LB_TH.2 LB_EL.2 ST_NOISE.10 ST_NOISE.2 SD_OFF_CB.2 SD_OFF_CR.2 SD_SAT_CB.2 SD_SAT_CR.2 NVBEG.2 NVEND.2 NFTOG.2 PVBEG.2 PVEND.2 PFTOG.2 PVBIOLCM.0 PVBIOCCM.0 CVBS_RGB_SEL MAN_ALPHA_ VAL.2 FB_EDGE_ SHAPE..2 FB_DELAY.2 CNTR_MODE.0 AA_FILT_EN.2 DR_STR_C.0 IFFILTSEL.2 VS_COAST_ MODE.0 PEAKING_ GAIN.2 DNR_TH2.2 1 LB_LCT.1 LB_LCM.1 LB_LCB.1 ADC0_SW.1 ADC2_SW.1 LB_TH.1 LB_EL.1 ST_NOISE.9 ST_NOISE.1 SD_OFF_CB.1 SD_OFF_CR.1 SD_SAT_CB.1 SD_SAT_CR.1 NVBEG.1 NVEND.1 NFTOG.1 PVBEG.1 PVEND.1 PFTOG.1 PVBIELCM.1 PVBIECCM.1 FB_MODE.1 MAN_ALPHA_ VAL.1 FB_EDGE_ SHAPE.1 FB_DELAY.1 AA_FILT_EN.1 DR_STR_S IFFILTSEL.1 EXTEND_VS_ MIN_FREQ PEAKING_ GAIN.1 DNR_TH2.1 0 LB_LCT.0 LB_LCM.0 LB_LCB.0 ADC0_SW.0 ADC2_SW.0 LB_TH.0 LB_EL.0 ST_NOISE.8 ST_NOISE.0 SD_OFF_CB.0 SD_OFF_CR.0 SD_SAT_CB.0 SD_SAT_CR.0 NVBEG.0 NVEND.0 NFTOG.0 PVBEG.0 PVEND.0 PFTOG.0 PVBIELCM.0 PVBIECCM.0 FB_MODE.0 MAN_ALPHA_ VAL.0 FB_EDGE_ SHAPE.0 FB_DELAY.0 RGB_IP_SEL AA_FILT_EN.0 DR_STR_S.0 IFFILTSEL.0 EXTEND_VS_ MAX_FREQ PEAKING_ GAIN.0 DNR_TH2.0 Reset Value ------xxxxxxxx 0xxxxxxx 10101100 01001100 ----10000000 10000000 10000000 10000000 00100101 00000100 01100011 01100101 00010100 01100011 01010101 01010101 --00010000 (Hex) ------00 00 AC 4C ----80 80 80 80 25 04 63 65 14 63 55 55 --10 LB_SL.2 ST_NOISE.6 SD_OFF_CB.6 SD_OFF_CR.6 SD_SAT_CB.6 SD_SAT_CR.6 NVBEGDELE NVENDDELE NFTOGDELE PVBEGDELE PVENDDELE PFTOGDELE NVBIOLCM.0 NVBIOCCM.0 FB_STATUS.2 MAN_ALPHA_ VAL.6 FB_SP_ ADJUST.2 LB_SL.1 ST_NOISE.5 SD_OFF_CB.5 SD_OFF_CR.5 SD_SAT_CB.5 SD_SAT_CR.5 NVBEGSIGN NVENDSIGN NFTOGSIGN PVBEGSIGN PVENDSIGN PFTOGSIGN NVBIELCM.1 NVBIECCM.1 FB_STATUS.1 MAN_ALPHA_ VAL.5 FB_SP_ ADJUST.1 RW FB_CSC_MAN FB_SP_ RW ADJUST.3 RW RW CNTR_LEVEL.1 CNTR_LEVEL.0 FB_LEVEL.1 RW ADC3_SW.3 ADC3_SW.2 ADC3_SW.1 RW DR_STR RW RW PEAKING_ RW GAIN.7 RW DNR_TH2.7 PEAKING_ GAIN.6 DNR_TH2.6 PEAKING_ GAIN.5 DNR_TH2.5 00000000 00 01001010 01000100 00001100 00000000 xx010101 00000000 4A 44 0C 00 15 00 249 F9 251 FB 252 FC 00000000 00 01000000 40 00000100 04 PEAKING_ GAIN.4 DNR_TH2.4 Rev. 0 | Page 75 of 108 ADV7184 Table 102 provides a detailed description of the registers located in the User Map. Table 102. User Map Detailed Description Bit Address 0x00 Register Input Control Bit Description INSEL [3:0]. The INSEL bits allow the user to select an input channel as well as the input format. 765432 00 1 0 0 Comments 0 CVBS in on AIN1, SCART: G on AIN6/AIN9, B on AIN4/AIN7, R on AIN5/AIN8 1 CVBS in on AIN2, SCART: G on AIN6/AIN9, B on AIN4/AIN7, R on AIN5/AIN8 0 CVBS in on AIN3, SCART: G on AIN6/AIN9, B on AIN4/AIN7, R on AIN5/AIN8 1 CVBS in on AIN4, SCART: G on AIN9, B on AIN7, R on AIN8 0 CVBS in on AIN5, SCART: G on AIN9, B on AIN7, R on AIN8 1 CVBS in on AIN6, SCART: G on AIN9, B on AIN7, R on AIN8 0 Y on AIN1, C on AIN4 1 Y on AIN2, C on AIN5 0 Y on AIN3, C on AIN6 1 Y on AIN1, Pb on AIN4, Pr on AIN5 0 Y on AIN2, Pb on AIN3, Pr on AIN6 1 CVBS in on AIN7, SCART: G on AIN6, B on AIN4, R on AIN5 0 CVBS in on AIN8, SCART: G on AIN6, B on AIN4, R on AIN5 1 CVBS in on AIN9, SCART: G on AIN6, B on AIN4, R on AIN5 0 CVBS in on AIN10, SCART: G on AIN6/AIN9, B on AIN4/AIN7, R on AIN5/AIN8 1 CVBS in on AIN11, SCART: G on AIN6/AIN9, B on AIN4/AIN7, R on AIN5/AIN8 Auto-detect PAL (BGHID), NTSC (without pedestal), SECAM Auto-detect PAL (BGHID), NTSC (M) (with pedestal), SECAM Auto-detect PAL (N), NTSC (M) (without pedestal), SECAM Auto-detect PAL (N), NTSC (M) (with pedestal), SECAM NTSC(J) NTSC(M) PAL 60 NTSC 4.43 PAL BGHID PAL N (BGHID without pedestal) PAL M (without pedestal) PAL M PAL combination N PAL combination N SECAM (with pedestal) SECAM (with pedestal) 0 Set to default Disable VSYNC processor Enable VSYNC processor Set to default Standard video input Betacam input enable Disable HSYNC processor Enable HSYNC processor Set to default Notes Composite and SCART RGB (RGB analog input options selectable via RGB_IP_SEL) 00 0 00 1 00 01 01 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 S-Video YPbPr Composite and SCART RGB (RGB analog input options selectable via RGB_IP_SEL) 11 11 11 11 1 VID_SEL [7:3]. The VID_SEL bits allow the user to select the input video standard. 0000 0001 0010 0011 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 0 1 0 1 1 0 0x01 Video Selection Reserved. ENVSPROC Reserved. BETACAM ENHSPLL Reserved. Rev. 0 | Page 76 of 108 ADV7184 Address 0x03 Register Output Control Bit Description SD_DUP_AV. Duplicates the AV codes from the luma into the chroma path. Bit 765432 1 0 Comments 0 AV codes to suit 8-bit interleaved data output 1 AV codes duplicated (for 16-bit interfaces) Set as default Reserved Reserved 16-bit @ LLC1 4:2:2 8-bit @ LLC1 4:2:2 ITU-R BT.656 Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Not used Output pins enabled Drivers three-stated All lines filtered and scaled Only active video region filtered 0 1 0 1 0 1 0 1 xx 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 100000 BT656-3-complatible BT656-4-compatible Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Disable Enable Luma gain = 1 16 < Y < 235, 16 < C < 240 1 < Y < 254, 1 < C < 254 SFL output is disabled SFL information output on the SFL pin Decode and output color Blank Cr and Cb HS, VS, F three-stated HS, VS, F forced active ITU-R BT.656 Extended range SFL output enables connecting encoder and decoder directly During VBI Notes Reserved. OF_SEL [3:0]. Allows the user to choose from a set of output formats. 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0x04 Extended Output Control TOD. Three-state output drivers. This bit 0 allows the user to three-state the output 1 drivers: P[19:0], HS, VS, FIELD, and SFL. VBI_EN. Allows VBI data (Lines 1 to 21) to be 0 passed through with only a minimum 1 amount of filtering performed. RANGE. Allows the user to select the range of output values. Can be BT656 compliant, or can fill the whole accessible number range. EN_SFL_PIN See also TIM_OE and TRI_LLC BL_C_VBI. Blank chroma during VBI. If set, enables data in the VBI region to be passed through the decoder undistorted. TIM_OE. Timing signals output enable. Reserved. Reserved. BT656-4. Allows the user to select an output mode-compatible with ITU- R BT656-3/4. AD_PAL_EN. PAL B/G/I/H autodetect enable. AD_NTSC_EN. NTSC autodetect enable. AD_PALM_EN. PAL M autodetect enable. AD_PALN_EN. PAL N autodetect enable. AD_P60_EN. PAL 60 autodetect enable. AD_N443_EN. NTSC443 autodetect enable. AD_SECAM_EN. SECAM autodetect enable. AD_SEC525_EN. SECAM 525 autodetect enable. 0x08 Contrast Register CON[7:0]. Contrast adjust. This is the user control for contrast adjustment. Reserved. Controlled by TOD 0x07 Autodetect Enable 0 0 0x00 Gain = 0; 0x80 Gain = 1; 0xFF Gain = 2 0x09 Reserved. 100000 0 0 Rev. 0 | Page 77 of 108 ADV7184 Address 0x0A Register Brightness Register Bit Description BRI[7:0]. This register controls the brightness of the video signal. Bit 765432 000000 1 0 0 0 Comments Notes 0x00 = 0mV 0x7F = +204mV 0x80 = -204mV Hue range =–90° to +90° 0x0B 0x0C Hue Register Default Value Y HUE[7:0]. This register contains the value for 0 0 0 0 0 0 the color hue adjustment. DEF_VAL_EN. Default value enable. 0 0 0 1 Free-run mode dependent on DEF_VAL_AUTO_EN Force free-run mode on and output blue screen Disable free-run mode Enable automatic free-run mode (blue screen) Y[7:0] = {DEF_Y[5:0],0, 0} DEF_VAL_AUTO_EN. Default value. 0 1 001101 011111 0 0 DEF_Y[5:0]. Default value Y. This register holds the Y default value. 0x0D Default Value C DEF_C[7:0]. Default value C. The Cr and Cb default values are defined in this register. Reserved.. SUB_USR_EN. Enables the user to access the User Sub Map Reserved. Reserved. FB_PWRDN PDBP. Power-down bit priority selects between PWRDN bit or pin. Reserved. PWRDN. Power-down places the decoder in a full power-down mode. When lock is lost, free-run mode can be enabled to output stable timing, clock, and a set color. Default Y value output in freerun mode. Default Cb/Cr value output in free-run mode. Default values give blue screen output. See Figure 46. Cr[7:0] = DEF_C[7:4],0, 0, 0, 0} Cb[7:0] = DEF_C[3:0], 0, 0, 0, 0} Set as default Access User Map Access User Sub Map Set as default Set to default FB input operational FB input in power save mode Chip power-down controlled by pin Bit has priority (pin disregarded) Set to default System functional Powered down Set to default Normal operation Start reset sequence In lock (right now) = 1 Lost lock (since last read) = 1 Fsc lock (right now) = 1 Peak white AGC mode active = 1 NTSM-MJ NTSC-443 PAL-M PAL-60 PAL-BGHID SECAM PAL combination N SECAM 525 Color kill is active = 1 MV color striping detected MV color striping type MV pseudo Sync detected MV AGC pulses detected Nonstandard line length Fsc frequency nonstandard 1 = horizontal lock achieved 1 = Gemstar Data detected 0x0E ADI Control 000 0 1 00 0 0 0x0F Power Management 0 0 1 0 1 00 0 1 See PDBP, 0x0F Bit 2. Reserved. 0 RES. Chip Reset loads all I2C bits with default 0 values. 1 0x10 Status Register 1 (Read Only) IN_LOCK LOST_LOCK FSC_LOCK FOLLOW_PW AD_RESULT[2:0]. Autodetection result reports the standard of the Input video. x x x x 0 0 0 0 1 1 1 1 x x x x x x x xx x x 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Executing reset takes approx. 2 ms. Self-clearing. Provides information about the internal status of the decoder. Detected standard 0x12 Status Register 2 (Read Only) 0x13 Status Register 3 (Read only) COL_KILL MVCS DET MVCS T3 MV_PS DET MV_AGC DET LL_NSTD FSC_NSTD Reserved. INST_HLOCK GEMD Color Kill 1 = Detected 0 = Type 2; 1 = Type 3 1 = Detected 1 = Detected 1 = Detected 1 = Detected Unfiltered When GEMD bit goes HIGH, it will remain HIGH until end of active video lines in that field. 0 = SD 60 Hz detected; 1 = SD 50 Hz detected. 0 = Y/C; 1 = CVBS Blue screen output Correct field length found Field sequence found SD_OP_50HZ CVBS FREE_RUN_ACT STD FLD_LEN INTERLACED x x x x x SD field rate detect Result of CVBS/YC autodetection 1 = Free-run mode active 1 = Field length standard 1 = Interlaced video detected Rev. 0 | Page 78 of 108 ADV7184 Address Register Bit Description PAL_SW_LOCK Bit 765432 x 1 0 Comments 1 = Swinging burst detected Notes Reliable swinging burst sequence 0x13 Analogue Control Internal Reserved. (Write Only) XTAL_TTL_SEL 0 0 1 00000 00 0 1 000 0xx 0 0 1 1 0 000 0 0 1 0 1 x 0 Crystal used to derive 28.63636 MHz clock External TTL level clock supplied 0x14 Analog Clamp Control 0x15 Digital Clamp Control 1 Reserved. Reserved. CCLEN. Current clamp enable allows the user to switch off the current sources in the analog front. Reserved. Reserved. DCT[1:0]. Digital clamp timing determines the time constant of the digital fine clamp circuitry. 1 0 Set to default Current sources switched off Current sources enabled Set to default Set to default Slow (TC = 1 sec) Medium (TC = 0.5 sec) Fast (TC = 0.1 sec) TC dependent on video Set to default Auto wide notch for poor quality sources or wide-band filter with Comb for good quality input Auto narrow notch for poor quality sources or wideband filter with comb for good quality input SVHS 1 SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR601) PAL NN1 PAL NN2 PAL NN3 PAL WN 1 PAL WN 2 NTSC NN1 NTSC NN2 NTSC NN3 NTSC WN1 NTSC WN2 NTSC WN3 Reserved Auto selection 15 MHz Auto selection 2.17 MHz SH1 SH2 SH3 SH4 SH5 Wideband mode Reserved. Do not use. Reserved. Do not use. SVHS 1 x 0x17 Shaping Filter Control Reserved. YSFM[4:0]. Selects Y-shaping filter mode when in CVBS only mode. Allows the user to select a wide range of low-pass and notch filters. If either auto mode is selected, the decoder selects the optimum Y filter depending on the CVBS video source quality (good vs. bad). 0 Decoder selects optimum Yshaping filter depending on CVBS quality. 000 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 000 001 0 0 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 If one of these modes is selected, the decoder does not change filter modes. Depending on video quality, a fixed filter response (the one selected) is used for good and bad quality video. 0x17 Shaping Filter Control (cont.) CSFM[2:0]. C-shaping filter mode allows the selection from a range of low-pass chrominance filters. If either auto mode is selected, the decoder selects the optimum C filter depending on the CVBS video source quality (good vs. bad). Non-auto settings force a C filter for all standards and quality of CVBS video. WYSFM[4:0]. Wideband Y-shaping filter mode allows the user to select which Y shaping filter is used for the Y component Automatically selects a C filter based on video standard and quality. Selects a C filter for all video standards and for good and bad video. 0x18 Shaping Filter Control 2 000 000 000 0 0 1 0 1 0 Rev. 0 | Page 79 of 108 ADV7184 Address Register Bit Description of Y/C, YPbPr, B/W input signals; it is also used when a good quality input CVBS signal is detected. For all other inputs, the Y- shaping filter chosen is controlled by YSFM[4:0]. 7654 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 ~ 1 00 0 1 Bit 3 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 ~ 1 2 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 ~ 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 ~ 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ~ 1 Comments SVHS 2 SVHS 3 SVHS 4 SVHS 5 SVHS 6 SVHS 7 SVHS 8 SVHS 9 SVHS 10 SVHS 11 SVHS 12 SVHS 13 SVHS 14 SVHS 15 SVHS 16 SVHS 17 SVHS 18 (CCIR 601) Reserved. Do not use. Reserved. Do not use. Reserved. Do not use. Set to default Auto selection of best filter Manual select filter using WYSFM[4:0] Narrow Medium Wide Widest Narrow Medium Medium Wide Set as default Set to default Use 27 MHz crystal Use 28..63636 MHz crystal LLC pin active LLC pin three-stated No Delay Luma 1 clk (37 nS) delayed Luma 2 clk (74 nS) early Luma 1 clk (37 nS) early Set to Zero Not valid setting Chroma + 2 pixels (early) Chroma + 1 pixel (early) No delay Chroma − 1 pixel (late) Chroma − 2 pixels (late) Chroma − 3 pixels (late) Not valid setting Use values in LTA[1:0] and CTA[2:0] for delaying luma/chroma LTA and CTA values determined automatically No Swapping Swap the Cr and Cb O/P samples Update once per video line Update once per field Set to default Color kill disabled Notes Reserved. WYSFMOVR. Enables the use of automatic WYSFN filter. 0x19 Comb Filter Control PSFSEL[1:0]. Controls the signal bandwidth that is fed to the comb filters (PAL). 0 0 1 1 0 0 1 1 0 1 0 1 x 0 1 0 1 NSFSEL[1:0]. Controls the signal bandwidth that is fed to the comb filters (NTSC). 0x1D ADI Control 2 Reserved. Reserved. EN28XTAL TRI_LLC 1111 000x 0 1 0 1 x 0x27 Pixel Delay Control LTA[1:0]. Luma timing adjust allows the user to specify a timing difference between chroma and luma samples. 0 1 1 1 0 0 0 0 0 1 1 1 1 0 1 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 1 CVBS mode LTA[1:0] = 00b S-Video mode LTA[1:0]= 01b YPrPb mode LTA[1:0] = 01b Reserved. CTA[2:0]. Chroma timing adjust allows a specified timing difference between the luma and chroma samples. CVBS mode CTA[2:0] = 011b S-Video mode CTA[2:0] = 101b YPrPb mode CTA[2:0] = 110b AUTO_PDC_EN. Automatically programs the LTA/CTA values to align luma and chroma at the output for all modes of operation. SWPC. Allows the Cr and Cb samples to be swapped. 0x2B Misc Gain Control PW_UPD. Peak white update determines the rate of gain. Reserved. CKE. Color kill enable allows the color kill 0 1 1000 0 0 Peak white must be enabled. See LAGC[2:0] For SECAM color kill, threshold Rev. 0 | Page 80 of 108 ADV7184 Address Register Bit Description function to be switched on and off. Reserved. CAGC[1:0]. Chroma automatic gain control selects the basic mode of operation for the AGC in the chroma path. Bit 765432 1 1 1 0 Comments Color kill enabled Set to default Manual fixed gain Use luma gain for chroma Automatic gain Freeze chroma gain Set to 1 Manual fixed gain AGC peak white algorithm off AGC peak white algorithm on Reserved Reserved Reserved Reserved Freeze gain Set to 1 Notes is set at 8%. See CKILLTHR[2:0] Use CMG[11:0] Based on color burst 0x2C AGC Mode Control 0 0 1 1 11 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 01 0 0 1 0 1 Reserved. LAGC[2:0]. Luma automatic gain control selects the mode of operation for the gain control in the luma path. Use LMG[11:0] Blank level to sync tip Blank level to sync tip 0x2D Chroma Gain Control 1 0x2E 0x2F Chroma Gain Control 2 Luma Gain Control 1 0x30 Luma Gain Control 2 1 Reserved. CMG[11:8]. Chroma manual gain can be used to program a desired manual chroma gain. Reading back from this register in AGC mode gives the current gain. Reserved. CAGT[1:0]. Chroma automatic gain timing 00 allows adjustment of the chroma AGC 01 tracking speed. 10 11 CMG[7:0]. Chroma manual gain lower 8 bits. 0 0 See CMG[11:8] for description. LMG[11:8]. Luma manual gain can be used to program a desired manual chroma gain, or to read back the actual gain value used. Reserved. LAGT[1:0]. Luma automatic gain timing 00 allows adjustment of the luma AGC tracking 0 1 speed. 10 11 LMG[7:0]. Luma manual gain can be used to x x program a desired manual chroma gain or read back the actual used gain value. 0 CAGC[1:0] settings decide in which mode CMG[11:0] operates Set to 1 Slow (TC = 2 s) Medium (TC = 1 s) Fast (TC = 0.2 s) Adaptive CMG[11:0] = 750d; gain is 1 in NTSC CMG[11:0] = 741d; gain is 1 in PAL LAGC[1:0] settings decide in which mode LMG[11:0] operates Set to 1 Slow (TC = 2 s) Medium (TC = 1 s) Fast (TC = 0.2 s) Adaptive LMG[11:0] = 1128dec; gain is 1 in NTSC LMG[11:0] = 1222d; gain is 1 in PAL 11 Has an effect only if CAGC[1:0] is set to auto gain (10) 0000 xx 0 x 0 x Min value is 0d (G = –60 dB) Max value is 3750 (G = 5) 11 Only has an effect if LAGC[1:0] is set to auto gain (001, 010, 011,or 100) xxxx x x Min value NTSC 1024 (G = 0.90); PAL (G = 0.84) Max value NTSC 4095 (G = 3.63); PAL (G = 3.35) HSE = HSYNC end HSB = HSYNC begin 0x31 VS and FIELD Control 1 Reserved. HVSTIM. Selects where within a line of video the VS signal is asserted. NEWAVMODE. Sets the EAV/SAV mode. 0 1 0 0 1 1 0 0x32 VSYNC Field Control 2 Reserved. Reserved. VSBHE 000 0000 0 1 0 1 Set to default Start of line relative to HSE Start of line relative to HSB EAV/SAV codes generated to suit ADI encoders Manual VS/Field position controlled by Registers 0x32, 0x33, and 0xE5– 0xEA Set to default VSBHO 0 1 0x33 VSYNC Field Control 3 Reserved. VSEHE 0001 0 1 0 0 NEWAVMODE bit must be set high. Set to default VS goes high in the middle of the line (even field) VS changes state at the start of the line (even field) VS goes high in the middle of the line (odd field) VS changes state at the start of the line (odd field) Set to default VS goes low in the middle of the line NEWAVMODE bit must be set high. (even field) VS changes state at the start of the line (even field) Rev. 0 | Page 81 of 108 ADV7184 Address Register Bit Description VSEHO Bit 765432 0 1 0x34 HS Position Control 1 HSE[10:8]. HS end allows the positioning of the HS output within the video line. Reserved. HSB[10:8]. HS begin allows the positioning of the HS output within the video line. Reserved. HSB[7:0]. See above, using HSB[10:0] and HSE[10:0], the user can program the position and length of HS output signal. HSE[7:0]. See above. PCLK. Sets the polarity of LLC1. 0 000 0 000000 0 0 0 1 0 Comments Notes VS goes low in the middle of the line (odd field) VS changes state at the start of the line odd field HS output ends HSE[10:0] pixels Using HSB and HSE the user after the falling edge of HSYNC can program the position and length of the output HSYNC Set to 0 HS output starts HSB[10:0] pixels after the falling edge of HSYNC Set to 0 0x35 HS Position Control 2 1 0 0x36 0x37 HS Position Control 3 Polarity 000000 0 0 0 1 Reserved. PF. Sets the FIELD polarity. Reserved. PVS. Sets the VS Polarity. Reserved. PHS. Sets HS Polarity. 0x38 NTSC Comb Control YCMN[2:0]. Luma Comb Mode, NTSC. 0 0 1 0 0 1 0 0 1 0 0 1 1 1 1 000 0 0 0 1 1 0 0 1 0 1 CCMN[2:0]. Chroma Comb Mode, NTSC. 100 101 110 111 CTAPSN[1:0]. Chroma Comb Taps, NTSC. 0 0 1 1 0 1 0 1 0 1 1 1 1 000 0 0 1 1 1 0 0 0 0 1 0x39 PAL Comb Control YCMP[2:0]. Luma Comb mode, PAL. CCMP[2:0]. Chroma Comb mode, PAL. 100 101 110 111 Invert polarity Normal polarity as per the timing diagrams Set to 0 Active high Active low Set to 0 Active high Active low Set to 0 Active high Active low Adaptive 3-line, 3-tap luma Use low-pass notch Fixed luma comb (2-line) Fixed luma comb (3-Line) Fixed luma comb (2-line) 3-line adaptive for CTAPSN = 01 4-line adaptive for CTAPSN = 10 5-line adaptive for CTAPSN = 11 Disable chroma comb Fixed 2-line for CTAPSN = 01 Fixed 3-line for CTAPSN = 10 Fixed 4-line for CTAPSN = 11 Fixed 3-line for CTAPSN = 01 Fixed 4-line for CTAPSN = 10 Fixed 5-line for CTAPSN = 11 Fixed 2-line for CTAPSN = 01 Fixed 3-line for CTAPSN = 10 Fixed 4-line for CTAPSN = 11 Not used Adapts 3 lines – 2 lines Adapts 5 lines – 3 lines Adapts 5 lines – 4 lines Adaptive 5-line, 3-tap luma comb Use low-pass notch Fixed luma comb Fixed luma comb (5-line) Fixed luma comb (3-line) 3-line adaptive for CTAPSP = 01 4-line adaptive for CTAPSP = 10 5-line adaptive for CTAPSP = 11 Disable chroma comb Fixed 2-line for CTAPSP = 01 Fixed 3-line for CTAPSP = 10 Fixed 4-line for CTAPSP = 11 Fixed 3-line for CTAPSP = 01 Fixed 4-line for CTAPSP = 10 Fixed 5-line for CTAPSP = 11 Fixed 2-line for CTAPSP = 01 Fixed 3-line for CTAPSP = 10 Fixed 4-line for CTAPSP = 11 Top lines of memory All lines of memory Bottom lines of memory Top lines of memory All lines of memory Bottom lines of memory Top lines of memory All lines of memory Bottom lines of memory Top lines of memory All lines of memory Bottom lines of memory Rev. 0 | Page 82 of 108 ADV7184 Address Register Bit Description CTAPSP[1:0]. Chroma comb taps, PAL. 7 0 0 1 1 Bit 65432 0 1 0 1 1 0 Comments Not used Adapts 5-lines – 2 lines (2 taps) Adapts 5 lines – 3 lines (3 taps) Adapts 5 lines – 4 lines (4 taps) ADC3 normal operation Power down ADC3 ADC2 normal operation Power down ADC2 ADC1 normal operation Power down ADC1 ADC0 normal operation Power down ADC0 Set as default Set to default Kill at 0.5% Kill at 1.5% Kill at 2.5% Kill at 4% Kill at 8.5% Kill at 16% Kill at 32% Reserved Set to default Set to default SFL compatible with ADV7190/ADV7191/ ADV7194 & ADV73xx encoders SFL compatible with ADV717x encoders Set to default GDECEL[15:0]. 16 individual enable bits that select the lines of video (even field Lines 10–25) that the decoder checks for Gemstarcompatible data. GDECOL[15:0]. 16 individual enable bits that select the lines of video (odd field Lines 10–25) that the decoder checks for Gemstarcompatible data. Split data into half byte Output in straight 8-bit format Undefined Disable CTI Enable CTI Disable CTI alpha blender Enable CTI alpha blender Sharpest mixing Sharp mixing Smooth Smoothest Set to default Bypass the DNR block Enable the DNR block Set to default Set to 0x04 for A/V input; set to 0x0A for tuner input Notes 0x3A ADC Control PWRDN_ADC_3. Enables power-down of ADC3. PWRDN_ADC_2. Enables power-down of ADC2. PWRDN_ADC_1. Enables power-down of ADC1. PWRDN_ADC_0. Enables power-down of ADC0. 0 1 0001 00 0 0 0 0 1 1 1 1 0 0000 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0x3D Manual Window Control Reserved. Reserved. CKILLTHR[2:0]. 1 CKE = 1 enables the color kill function and must be enabled for CKILLTHR[2:0] to take effect. 0x41 Resample Control Reserved. Reserved. SFL_INV. Controls the behavior of the PAL switch bit. 1 1 Reserved. GDECEL[15:8]. See the Comments column. GDECEL[7:0]. See above. 0 000000 000000 0x48 0x49 Gemstar Control 1 Gemstar Control 2 0 0 0 0 LSB = Line 10; MSB = Line 25 Default = Do not check for Gemstar-compatible data on any lines [10–25] in even fields LSB = Line 10; MSB = Line 25 Default = Do not check for Gemstar-compatible data on any lines [10–25] in odd fields To avoid 00/FF code. 0x4A 0x4B Gemstar Control 3 Gemstar Control 4 GDECOL[15:8]. See the Comments column. GDECOL[7:0]. See above. 000000 000000 0 0 0 0 0x4C Gemstar Control 5 0x4D CTI DNR Control 1 GDECAD. Controls the manner in which decoded Gemstar data is inserted into the horizontal blanking period. Reserved. CTI_EN. CTI enable CTI_AB_EN. Enables the mixing of the transient improved chroma with the original signal. CTI_AB[1:0]. Controls the behavior of the alpha-blend circuitry. 0 1 xxxx00 0 0 1 0 1 0 0 1 1 0 0 1 0 0 0 1 0 1 Reserved. DNR_EN. Enable or bypass the DNR block. 0x4E CTI DNR Control 2 0x50 CTI DNR Control 4 0x51 Lock Count Reserved. 11 CTI_CTH[7:0]. Specifies how big the 000010 amplitude step must be to be steepened by the CTI block. DNR_TH[7:0]. Specifies the maximum edge 0 0 0 0 1 0 that is interpreted as noise and is therefore blanked. CIL[2:0]. Count-into-lock determines the 0 number of lines the system must remain in 0 0 0 0 0 0 1 1 line of video 2 lines of video Rev. 0 | Page 83 of 108 ADV7184 Address Register Bit Description lock before showing a locked status. Bit 765432 0 0 1 1 1 1 000 001 010 011 100 101 110 111 0 1 0 1 0x69 Config 1 SDM_SEL[1:0] 0 0 1 1 0 1 0 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 Comments 5 lines of video 10 lines of video 100 lines of video 500 lines of video 1000 lines of video 100000 lines of video 1 line of video 2 lines of video 5 lines of video 10 lines of video 100 lines of video 500 lines of video 1000 lines of video 100000 lines of video Over field with vertical info Line-to-line evaluation Lock status set only by horizontal lock Lock status set by horizontal lock and subcarrier lock. INSEL selects Analog I/P Muxing CVBS – AIN11 S-Video – Y on AIN10 and C on AIN12 CVBS/S-Video autodetect CVBS on AIN11 Y on AIN11 C on AIN12 Set to default LLC1 (nominal 27 MHz) selected out on LLC1 pin LLC2 (nominally 13.5 MHz) selected out on LLC1 pin Set to default CCAP1[7] contains parity bit for byte 0 CCAP2[7] contains parity bit for byte 0 Reports the number of black lines detected at the top of active video. Reports the number of black lines detected in the bottom half of active video if subtitles are detected. Reports the number of black lines detected at the bottom of active video. No connection AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 No connection No connection AIN7 AIN8 AIN9 AIN10 AIN11 AIN12 No connection No connection Notes COL[2:0]. Count-out-of-lock determines the number of lines the system must remain out-of-lock before showing a lost-locked status. SRLS. Select raw lock signal. Selects the determination of the lock status. FSCLE. Fsc lock enable. 0x8F Free Run Line Length 1 Reserved. Reserved. LLC_PAD_SEL [2:0]. Enables manual selection of clock for LLC1 pin. 00000x 00 000 101 0 0 For 16-bit 4:2:2 out, OF_SEL[3:0 = 0010 Only for use with VBI System 2 Only for use with VBI System 2 This feature examines the active video at the start and at the end of each field. It enables format detection even if the video is not accompanied by a CGMS or WSS sequence. SETADC_SW_MAN_EN = 1 0x99 0x9A 0x9B 0x9C CCAP1 (Read Only) CCAP2 (Read Only) Letterbox 1 (Read Only) Letterbox 2 (Read Only) Letterbox 3 (Read Only) ADC SWITCH 1 Reserved. CCAP1[7:0]. Closed caption data register. CCAP2[7:0]. Closed caption data register. LB_LCT[7:0]. Letterbox data register. LB_LCM[7:0]. Letterbox data register. 0 xxxxxx xxxxxx xxxxxx xxxxxx x x x x x x x x 0x9D LB_LCB[7:0]. Letterbox data register. xxxxxx x x 0xC3 ADC0_SW[3:0]. Manual muxing control for ADC0. 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0000 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0xC3 ADC SWITCH 1 ADC1_SW[3:0]. Manual muxing control for SETADC_SW_MAN_EN = 1 Rev. 0 | Page 84 of 108 ADV7184 Address Register (cont.) Bit Description ADC1. 7 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 43 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 xxx 6 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 5 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 2 1 0 Comments No connection No connection AIN3 AIN4 AIN5 AIN6 No connection No connection No connection No connection AIN9 AIN10 AIN11 AIN12 No connection No connection No connection AIN2 No connection No connection AIN5 AIN6 No connection No connection No connection AIN8 No connection No connection AIN11 AIN12 No connection Disable Enable Default threshold for the detection of black lines. Set as default LB detection ends with the last line of active video on a field, 1100b: 262/525. Letterbox detection aligned with the start of active video, 0100b: 23/286 NTSC. Notes 0xC4 ADC SWITCH 2 ADC2_SW[3:0]. Manual muxing control for ADC2. 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SETADC_SW_MAN_EN = 1 0xDC Letterbox Control 1 0xDD Letterbox Control 2 0xDE ST Noise Readback 1 (Read Only) Reserved. ADC_SW_MAN_EN. Enables manual setting 0 of the input signal muxing. 1 LB_TH [4:0]. Sets the threshold value that 011 determines if a line is black. 101 Reserved. LB_EL[3:0]. Programs the end line of the 11 activity window for LB detection (end of field). LB_SL[3:0]. Programs the start line of the 0100 activity window for LB detection (start of field). ST_NOISE[10:0] Sync Tip noise Measurement ST_NOISE[10:8] x ST_NOISE_VLD x 0 0 0 0 x x 1 = ST_NOISE[10:0] measurement valid 0 = ST_NOISE[10:0] measurement invalid 0xDF 0xE1 0xE2 0xE3 ST Noise Readback 2 (Read Only) SD Offset Cb SD Offset Cr SD Saturation Cb Reserved. ST_NOISE[7:0] See ST_NOISE[10:0] above SD_OFF_CB [7:0]. Adjusts the hue by selecting the offset for the Cb channel. SD_OFF_CR [7:0]. Adjusts the hue by selecting the offset for the Cr channel. SD_SAT_CB [7:0]. Adjusts the saturation of the picture by affecting gain on the Cb channel. SD_SAT_CR [7:0]. Adjusts the saturation of the picture by affecting gain on the Cr channel. NVBEG[4:0]. How many lines after lCOUNT rollover to set V high. xxxx xxxxxx 100000 100000 100000 x 0 0 0 x 0 0 0 Chroma gain = 0 dB 0xE4 SD Saturation Cr 100000 0 0 Chroma gain = 0 dB 0xE5 NTSC V Bit Begin 001 0 1 NTSC default (BT.656) Rev. 0 | Page 85 of 108 ADV7184 Address Register Bit Description NVBEGSIGN Bit 765432 0 1 NVBEGDELE. Delay V bit going high by one line relative to NVBEG (even field). NVBEGDELO. Delay V bit going high by one line relative to NVBEG (odd field). 0xE6 NTSC V Bit End NVEND[4:0]. How many lines after lCOUNT rollover to set V low. NVENDSIGN 0 1 001 0 1 NVENDDELE. Delay V bit going low by one line relative to NVEND (even field). NVENDDELO. Delay V bit going low by one line relative to NVEND (odd field). 0xE7 NTSC F Bit Toggle NFTOG[4:0]. How many lines after lCOUNT rollover to toggle F signal. NFTOGSIGN 0 1 000 0 1 NFTOGDELE. Delay F transition by one line relative to NFTOG (even field). NFTOGDELO. Delay F transition by one line relative to NFTOG (odd field). 0xE8 PAL V Bit Begin PVBEG[4:0]. How many lines after lCOUNT rollover to set V high. PVBEGSIGN 0 1 001 0 1 PVBEGDELE. Delay V bit going high by one line relative to PVBEG (even field). PVBEGDELO. Delay V bit going high by one line relative to PVBEG (odd field). 0xE9 PAL V Bit End PVEND[4:0]. How many lines after lCOUNT rollover to set V low. PVENDSIGN 0 1 101 0 1 PVENDDELE. Delay V bit going low by one line relative to PVEND (even field). PVENDDELO. Delay V bit going low by one line relative to PVEND (odd field). 0xEA PAL F Bit Toggle PFTOG[4:0]. How many lines after lCOUNT rollover to toggle F signal. PFTOGSIGN 0 1 000 0 1 PFTOGDELE. Delay F transition by one line relative to PFTOG (even field). PFTOGDELO. Delay F transition by one line relative to PFTOG (odd field). 0xEB V Blank Control 1 PVBIELCM[1:0]. PAL VBI even field line control. 0 1 0 0 1 1 0 0 1 1 00 01 10 0 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 1 1 1 0 1 0 0 0 1 1 0 Comments Set to low when manual programming Not suitable for user programming No delay Additional delay by 1 line No delay Additional delay by 1 line NTSC default (BT.656) Set to low when manual programming Not suitable for user programming No delay Additional delay by 1 line No delay Additional delay by 1 line NTSC default Set to low when manual programming Not suitable for user programming No delay Additional delay by 1 line No delay Additional delay by 1 line PAL default (BT.656) Set to low when manual programming Not suitable for user programming No delay Additional delay by 1 line No delay Additional delay by 1 line PAL default (BT.656) Set to low when manual programming Not suitable for user programming No delay Additional delay by 1 line No delay Additional delay by 1 line PAL default (BT.656) Set to low when manual programming Not suitable for user programming No delay Additional delay by 1 line No delay Additional delay by 1 line VBI ends 1 line earlier (line 335) ITU-R BT.470 compliant (Line 336) VBI ends 1 line later (line 337) VBI ends 2 lines later (line 338) VBI ends 1 line earlier (line 22) ITU-R BT.470 compliant (Line 23) VBI ends 1 line later (line 24) VBI ends 2 lines later (line 25) VBI ends 1 line earlier (line 282) ITU-R BT.470 compliant (Line 283) VBI ends 1 line later (line 284) Notes Controls position of first active (comb filtered) line after VBI on even field in PAL PVBIOLCM[1:0]. PAL VBI odd field line control. Controls position of first active (comb filtered) line after VBI on odd field in PAL NVBIELCM[1:0]. NTSC VBI even field line control. Controls position of first active (comb filtered) line after VBI on even field in NTSC Rev. 0 | Page 86 of 108 ADV7184 Address Register Bit Description PVBIOLCM[1:0]. NTSC VBI odd field line control. Bit 765432 11 00 01 10 11 1 0 Comments VBI ends 2 lines later (line 285) VBI ends 1 line earlier (line 20) ITU-R BT.470 compliant (Line 21) VBI ends 1 line later (line 22) VBI ends 2 lines later (line 23) Color output beginning line 335 ITU-R BT.470 compliant color output beginning Line 336 Color output beginning line 337 Color output beginning line 338 Color output beginning line 22 ITU-R BT.470 compliant color output beginning Line 23 Color output beginning line 24 Color output beginning line 25 Color output beginning line 282 ITU-R BT.470 compliant color output beginning Line 283 VBI ends 1 line later (line 284) Color output beginning line 285 Color output beginning line 20 ITU-R BT.470 compliant color output beginning Line 21 Color output beginning line 22 Color output beginning line 23 FB_RISE, 1 = There has been a rising edge on FB pin since last I2C read FB_FALL, 1 = there has been a falling edge on FB pin since last I2C read FB_STAT, Instantaneous value of FB signal at time of I2C read FB_HIGH, Indicates that the FB signal has gone high since the last I2C read Static switch mode – full RGB or full CVBS data Fixed alpha blending, See MAN_ALPHA_VAL[6:0] Dynamic switching (fast mux) Dynamic switching with edge enhancement CVBS source RGB source FB pin active high FB pin active low Notes Controls position of first active (comb filtered) line after VBI on odd field in NTSC 0xEC V Blank Control 2 PVBIECCM[1:0]. PAL VBI even field color control. 0 0 1 1 0 1 0 1 Controls the position of first line that outputs color after VBI on even field in PAL PVBIOCCM[1:0]. PAL VBI odd field color control. 00 01 10 11 Controls the position of first line that outputs color after VBI on odd field in PAL NVBIECCM[1:0]. NTSC VBI even field color control. 00 01 10 11 Controls the position of first line that outputs color after VBI on even field in NTSC NVBIOCCM[1:0]. NTSC VBI odd field color control. 00 01 10 11 Controls the position of first line that outputs color after VBI on odd field in NTSC 0xED FB_STATUS (Read Only) Reserved. FB_STATUS[3:0]. Provides information about the status of the FB pin. FB_STATUS.0 FB_STATUS.1 xx x x x Self-clearing bit x Self-clearing bit FB_STATUS.2 FB_STATUS.3 x x Self-clearing bit 0xED FB_CONTROL 1 (Write Only) FB_MODE[1:0]. Selects FB mode. 0 0 1 1 0 1 0 1 0 1 0 1 Selects either CVBS or RGB to be O/P 0xEE FB_CONTROL 2 MAN_ALPHA_VAL[6:0]. Determines in what proportion the video from the CVBS source and the RGB source are blended. FB_CSC_MAN 0001 00000 0 0 0 1 Automatic configuration of the CSC for SCART support Enable manual programming of CSC 0 0 0 0 1 0 0 0 1 1 0 0 1 0 1 0 Contrast reduction mode disabled – FB signal interpreted as Bi-level signal CSC is used to convert RGB portion of SCART signal to YCrCb Improves picture transition for high speed fast blank switching 0xEF FB_CONTROL 3 FB_EDGE_SHAPE[2:0] CNTR_ENABLE Rev. 0 | Page 87 of 108 ADV7184 Address Register Bit Description Bit 765432 1 1 0 Comments Notes Contrast reduction mode enabled – FB signal interpreted as Tri-level signal Adjusts FB timing in reference to the Each LSB corresponds to 1/8 sampling clock of a clock cycle Delay on FB signal in 28.63636 MHz clock cycles SD RGB input for FB on AIN7, AIN8 and AIN9 SD RGB input for FB on AIN4, AIN5 and AIN6 Set to Zero 25% 50% 75% 100% CNTR_ENABLE = 0, FB threshold = 1.4 V CNTR_ENABLE – 1, FB threshold = 1.6 V CNTR_ENABLE = 0, FB threshold = 1.6 V CNTR_ENABLE – 1, FB threshold = 1.8 V CNTR_ENABLE = 0, FB threshold = 1.8 V CNTR_ENABLE – 1, FB threshold = 2V CNTR_ENABLE = 0, FB threshold = 2V CNTR_ENABLE – 1, FB threshold = Not Used 0.4 V contrast reduction threshold 0.6 V contrast reduction threshold 0.8 V contrast reduction threshold Not used Disables the internal antialiasing filter on Channel 0 Enables the internal antialiasing filter on Channel 0 Disables the internal antialiasing filter on Channel 1 Enables the internal antialiasing filter on Channel 1 Disables the internal antialiasing filter on Channel 2 Enables the internal antialiasing filter on Channel 2 Disables the internal antialiasing filter on Channel 3 Enables the internal antialiasing filter on Channel 3 No connection No connection No connection No connection AIN4 No connection No connection No connection No connection AIN7 No connection No connection No connection FB_SP_ADJUST 0xF0 FB_CONTROL 4 FB_DELAY[3:0] Reserved. RGB_IP_SEL 0100 01 0100 0 1 0 0 0xF1 FB_CONTROL 5 Reserved. CNTR_MODE[1:0]. Allows adjustment of contrast level in the contrast reduction box. 0 0 0 1 1 00 0 1 0 1 FB_LEVEL[1:0]. Controls reference level for fast blank comparator. 01 10 11 CNTR_LEVEL[1:0]. Controls reference level for contrast reduction comparator. 0 0 1 1 0 1 0 1 0 1 CNTR_ENABLE = 1 0xF3 AFE_ CONTROL 1 AA_FILT_EN[0] AA_FILT_EN[1] 0 1 AA_FILT_EN[2] 0 1 AA_FILT_EN[3] 0 1 ADC3_SW[3:0] 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 Rev. 0 | Page 88 of 108 ADV7184 Address Register Bit Description 7 1 1 1 6 1 1 1 5 0 1 1 Bit 432 1 0 1 1 0 Comments No connection No connection No connection Reserved Medium-low drive strength (2x) Medium-high drive strength (3x) High drive strength (4x) Reserved Medium-low drive strength (2x) Medium-high drive strength (3x) High drive strength (4x) Reserved Medium-low drive strength (2x) Medium-high drive strength (3x) High drive strength (4x) No delay Bypass mode 2 MHz 5 MHz −3 dB +2 dB −6 dB +3.5 dB −10 dB +5 dB Reserved 3 MHz 6 MHz −2 dB +2 dB −5 dB +3 dB −7 dB +5 dB Notes 0xF4 Drive Strength DR_STR_S[1:0]. Selects the drive strength for the sync output signals. 0 0 1 1 0 0 1 1 0 0 1 1 xx 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 DR_STR_C[1:0]. Selects the drive strength for the clock output signal. DR_STR[1:0]. Selects the drive strength for the data output signals. Can be increased or decreased for EMC or crosstalk reasons. 0xF8 IF Comp Control Reserved. IFFILTSEL[2:0] IF filter selection for PAL and NTSC 0 1 0 1 0 1 0 1 0 1 0dB NTSC Filters PAL Filters 0xF9 VS Mode Control Reserved. EXTEND_VS_MAX_FREQ 00000 Limit maximum VSYNC frequency to 66.25 Hz (475 lines/frame) Limit maximum VSYNC frequency to 70.09 Hz (449 lines/frame) Limit minimum VSYNC frequency to 42.75 Hz (731 lines/frame) Limit minimum VSYNC frequency to 39.51 Hz (791 lines/frame) Auto coast mode This value sets up the output coast frequency. 50 Hz coast mode 60 Hz coast mode Reserved Increases/decreases the gain for high frequency portions of the video signal Specifies the max. edge that is interpreted as noise and therefore blanked EXTEND_VS_MIN_FREQ 0 1 VS_COAST_MODE[1:0] 0 0 1 1 0 1 0 1 0 0 0xFB Peaking Control Reserved. PEAKING_GAIN[7:0] 0000 010000 0xFC Coring Threshold 2 DNR_TH2[7:0] 000001 0 0 Rev. 0 | Page 89 of 108 ADV7184 USER SUB MAP The collective name for the subaddress registers in Table 103 is User Sub Map. To access the User Sub Map, SUB_USR_EN in Register Address 0x0E (User Map) must be programmed to 1. Table 103. User Sub Map Register Details Address Dec Hex Register Name 64 66 67 68 69 70 71 40 42 43 44 45 46 47 Interrupt Configuration 0 Interrupt Status 1 Interrupt Clear 1 Interrupt Mask 1 Raw Status 2 Interrupt Status 2 Interrupt Clear 2 R W 7 6 INTRQ_DUR_ SEL.0 MV_PS_CS_Q 5 MV_INTRQ_ SEL.1 SD_FR_ HNG_Q 4 MV_INTRQ_ SEL.0 3 2 MPU_STIM_I NTRQ 1 INTRQ_OP_ SEL.1 0 INTRQ_OP_ SEL.0 Reset Value (Hex) INTRQ_DUR_ RW SEL.1 R W RW R R W MPU_STIM_ INTRQ MPU_STIM_I NTRQ_Q MPU_STIM_ INTRQ_CLR 0001x000 10 ----- SD_UNLOCK_Q SD_LOCK_Q SD_UNLOCK_ CLR SD_UNLOCK_ MSKB EVEN_FIELD SD_FIELD_ CHNGD_Q SD_FIELD_ CHNGD_CLR SD_FIELD_ CHNGD_ MSKB SCM_LOCK SD_H_LOCK SD_H_LOCK_ SD_AD_CHNG_Q CHNG_Q SD_AD_CHNG_ CLR SD_AD_CHNG_ MSKB SD_H_LOCK_ CHNG_CLR SD_H_LOCK_ CHNG_MSKB VDP_ CGMS_WSS_ CHNGD_Q VDP_CGMS_WSS_ CHNGD_CLR VDP_CGMS_WSS_ CHNGD_MSKB WST_PKT_ VDP_TTXT_TYPE_ VDP_TTXT_ DECOD_DISABLE MAN_ENABLE TYPE_MAN.1 AUTO_DETECT_ GS_TYPE SD_FR_ MV_PS_CS_CLR CHNG_CLR MV_PS_CS _MSKB SD_FR_ CHNG_MSKB SD_LOCK_CLR x0000000 00 SD_LOCK_ MSKB CCAPD x0000000 00 --------- GEMD_Q GEMD_CLR CCAPD_Q CCAPD_CLR 0xx00000 00 72 73 74 75 76 48 49 4A 4B 4C Interrupt Mask 2 Raw Status 3 Interrupt Status 3 Interrupt Clear 3 Interrupt Mask 3 MPU_STIM_ RW INTRQ_MSKB R R W RW VDP_ VITC_Q VDP_ VITC_CLR VDP_ VITC_MSKB PAL_SW_LK_ CHNG_Q PAL_SW_LK_ CHNG_CLR PAL_SW_LK_ CHNG_MSKB GEMD_MSKB SD_V_LOCK SD_V_LOCK_ CHNG_Q SD_V_LOCK_ CHNG_CLR SD_V_LOCK_ CHNG_MSKB CCAPD_MSKB 0xx00000 00 SD_OP_50Hz SD_OP_ CHNG_Q SD_OP_ CHNG_CLR SD_OP_ CHNG_MSKB --------- SCM_LOCK_ CHNG_Q SCM_LOCK_ CHNG_CLR SCM_LOCK_ CHNG_MSKB VDP_GS_ VPS_PDC_ UTC_CHNG_Q VDP_GS_VPS_ PDC_UTC_ CHNG_CLR VDP_GS_VPS_ PDC_UTC_ CHNG_MSKB xx000000 00 xx000000 00 78 4E Interrupt Status 4 R VDP_CCAPD_ --Q --- 79 4F Interrupt Clear 4 W VDP_CCAPD_ 00x0x0x0 00 CLR VDP_CCAPD_ 00x0x0x0 00 MSKB VDP_TTXT_ TYPE_MAN.0 10001000 88 0001xx00 10 80 96 97 98 99 50 60 61 62 63 Interrupt Mask 4 VDP_Config_1 VDP_Config_2 VDP_ADF_Config_1 VDP_ADF_Config_2 VDP_LINE_00E VDP_LINE_00F VDP_LINE_010 VDP_LINE_011 VDP_LINE_012 VDP_LINE_013 VDP_LINE_014 VDP_LINE_015 VDP_LINE_016 VDP_LINE_017 VDP_LINE_018 VDP_LINE_019 VDP_LINE_01A RW RW RW RW ADF_ENABLE RW DUPLICATE ADF RW MAN_LINE_PGM VBI_DATA_P6_ RW N23.3 VBI_DATA_P7_ RW N24.3 VBI_DATA_P8_ RW N25.3 ADF_MODE.1 ADF_MODE.0 ADF_SDID.5 ADF_DID.4 ADF_SDID.4 ADF_DID.3 ADF_SDID.3 VBI_DATA_ P318.3 ADF_DID.2 ADF_SDID.2 VBI_DATA_ P318.2 ADF_DID.1 ADF_SDID.1 VBI_DATA_ P318.1 ADF_DID.0 ADF_SDID.0 VBI_DATA_ P318.0 VBI_DATA_ P319_N286.0 VBI_DATA_ P320_N287.0 VBI_DATA_ P321_N288.0 VBI_DATA_ P322.0 VBI_DATA_ P323.0 VBI_DATA_ P324_N272.0 VBI_DATA_ P325_N273.0 VBI_DATA_ P326_N274.0 VBI_DATA_ P327_N275.0 VBI_DATA_ P328_N276.0 VBI_DATA_ P329_N277.0 VBI_DATA_ P330_N278.0 00010101 15 0x101010 2A 0xxx0000 00 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 100 64 101 65 102 66 103 67 104 68 105 69 106 6A 107 6B 108 6C 109 6D 110 6E 111 6F 112 70 VBI_DATA_ P6_N23.2 VBI_DATA_ P7_N24.2 VBI_DATA_ P8_N25.2 VBI_DATA_ P6_N23.1 VBI_DATA_ P7_N24.1 VBI_DATA_ P8_N25.1 VBI_DATA_ P9.1 VBI_DATA_ P10.1 VBI_DATA_ P11.1 VBI_DATA_ P12_N10.1 VBI_DATA_ P13_N11.1 VBI_DATA_ P14_N12.1 VBI_DATA_ P6_N23.0 VBI_DATA_ P7_N24.0 VBI_DATA_ P8_N25.0 VBI_DATA_ P9.0 VBI_DATA_ P10.0 VBI_DATA_ P11.0 VBI_DATA_ P12_N10.0 VBI_DATA_ P13_N11.0 VBI_DATA_ P14_N12.0 VBI_DATA_P319_ VBI_DATA_P319_ VBI_DATA_ N286.3 N286.2 P319_N286.1 VBI_DATA_P320_ VBI_DATA_P320_ VBI_DATA_ N287.3 N287.2 P320_N287.1 VBI_DATA_P321_ VBI_DATA_P321_ VBI_DATA_ N288.3 N288.2 P321_N288.1 VBI_DATA_ P322.3 VBI_DATA_ VBI_DATA_P322.2 P322.1 VBI_DATA_ RW VBI_DATA_P9.3 P9.2 VBI_DATA_P10. VBI_DATA_ RW 3 P10.2 VBI_DATA_P11. VBI_DATA_ RW 3 P11.2 VBI_DATA_P12_ VBI_DATA_ RW N10.3 P12_N10.2 VBI_DATA_P13_ VBI_DATA_ RW N11.3 P13_N11.2 VBI_DATA_P14_ VBI_DATA_ RW N12.3 P14_N12.2 VBI_DATA_ VBI_DATA_P323.3 VBI_DATA_P323.2 P323.1 VBI_DATA_P324_ VBI_DATA_P324_ VBI_DATA_ N272.3 N272.2 P324_N272.1 VBI_DATA_P325_ VBI_DATA_P325_ VBI_DATA_ N273.3 N273.2 P325_N273.1 VBI_DATA_P326_ VBI_DATA_P326_ VBI_DATA_ N274.3 N274.2 P326_N274.1 VBI_DATA_P327_ VBI_DATA_P327_ VBI_DATA_ N275.3 N275.2 P327_N275.1 VBI_DATA_P15_ VBI_DATA_P15_ VBI_DATA_ RW N13.3 N13.2 P15_N13.1 VBI_DATA_P16_ VBI_DATA_P16_ VBI_DATA_ RW N14.3 N14.2 P16_N14.1 VBI_DATA_P17_ VBI_DATA_P17_ VBI_DATA_ RW N15.3 N15.2 P17_N15.1 VBI_DATA_P15_ VBI_DATA_P328_ VBI_DATA_P328_ VBI_DATA_ N13.0 N276.3 N276.2 P328_N276.1 VBI_DATA_P16_ VBI_DATA_P329_ VBI_DATA_P329_ VBI_DATA_ N14.0 N277.3 N277.2 P329_N277.1 VBI_DATA_P17_ VBI_DATA_P330_ VBI_DATA_P330_ VBI_DATA_ N15.0 N278.3 N278.2 P330_N278.1 Rev. 0 | Page 90 of 108 ADV7184 Address Dec Hex Register Name 113 71 114 72 115 73 116 74 117 75 118 76 119 77 120 78 120 78 121 79 122 7A 125 7D 126 7E 127 7F 132 84 133 85 134 86 135 87 136 88 137 89 138 8A 139 8B 140 8C 141 8D 142 8E 143 8F 144 90 146 92 147 93 148 94 149 95 150 96 151 97 152 98 153 99 154 9A 155 9B 156 9C VDP_LINE_01B VDP_LINE_01C VDP_LINE_01D VDP_LINE_01E VDP_LINE_01F VDP_LINE_020 VDP_LINE_021 R W 7 6 5 4 3 2 1 0 VBI_DATA_ P331_N279.0 VBI_DATA_ P332_N280.0 VBI_DATA_ P333_N281.0 VBI_DATA_ P334_N282.0 VBI_DATA_ P335_N283.0 VBI_DATA_ P336_N284.0 VBI_DATA_ P337_N285.0 CC_CLEAR CC_EVEN_FIELD CC_AVL CCAP_ CCAP_BYTE_1.1 BYTE_1.0 CCAP_ CCAP_BYTE_2.1 BYTE_2.0 CGMS_CRC.3 CGMS_WSS.9 CGMS_WSS.1 GS_VPS_PDC_ UTC_BYTE_0.1 GS_VPS_PDC_ UTC_BYTE_1.1 GS_VPS_PDC_ UTC_BYTE_2.1 GS_VPS_PDC_ UTC_BYTE_3.1 CGMS_CRC.2 CGMS_WSS.8 CGMS_WSS.0 GS_VPS_PDC_ UTC_BYTE_0.0 GS_VPS_PDC_ UTC_BYTE_1.0 GS_VPS_PDC_ UTC_BYTE_2.0 GS_VPS_PDC_ UTC_BYTE_3.0 Reset Value (Hex) VBI_DATA_P18_ VBI_DATA_P18_ VBI_DATA_ RW N16.3 N16.2 P18_N16.1 VBI_DATA_P19_ VBI_DATA_ RW N17.3 P19_N17.2 VBI_DATA_P20_ VBI_DATA_ RW N18.3 P20_N18.2 VBI_DATA_P21_ VBI_DATA_ RW N19.3 P21_N19.2 VBI_DATA_P22_ VBI_DATA_ RW N20.3 P22_N20.2 VBI_DATA_P23_ VBI_DATA_ RW N21.3 P23_N21.2 VBI_DATA_P24_ VBI_DATA_ RW N22.3 P24_N22.2 VITC_CLEAR TTXT_AVL VITC_AVL VBI_DATA_P18_ VBI_DATA_P331_ VBI_DATA_P331_ VBI_DATA_ N16.0 N279.3 N279.2 P331_N279.1 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 00000000 00 --------------------------------------------------------------------------------------------------------------------- VBI_DATA_P19_ VBI_DATA_P19_ VBI_DATA_P332_ VBI_DATA_P332_ VBI_DATA_ N17.1 N17.0 N280.3 N280.2 P332_N280.1 VBI_DATA_P20_ VBI_DATA_P20_ VBI_DATA_P333_ VBI_DATA_P333_ VBI_DATA_ N18.1 N18.0 N281.3 N281.2 P333_N281.1 VBI_DATA_P21_ VBI_DATA_P21_ VBI_DATA_P334_ VBI_DATA_P334_ VBI_DATA_ N19.1 N19.0 N282.3 N282.2 P334_N282.1 VBI_DATA_P22_ VBI_DATA_P22_ VBI_DATA_P335_ VBI_DATA_P335_ VBI_DATA_ N20.1 N20.0 N283.3 N283.2 P335_N283.1 VBI_DATA_P23_ VBI_DATA_P23_ VBI_DATA_P336_ VBI_DATA_P336_ VBI_DATA_ N21.1 N21.0 N284.3 N284.2 P336_N284.1 VBI_DATA_P24_ VBI_DATA_P24_ VBI_DATA_P337_ VBI_DATA_P337_ VBI_DATA_ N22.1 N22.0 N285.3 N285.2 P337_N285.1 GS_PDC_VPS_ UTC_CLEAR GS_PDC_VPS_ GS_DATA_TYPE UTC_AVL CCAP_BYTE_1.5 CCAP_BYTE_1.4 CCAP_BYTE_1.3 CCAP_BYTE_2.5 CCAP_BYTE_2.4 CCAP_BYTE_2.3 zero CGMS_WSS.13 CGMS_WSS.5 GS_VPS_PDC_ UTC_BYTE_0.5 GS_VPS_PDC_ UTC_BYTE_1.5 GS_VPS_PDC_ UTC_BYTE_2.5 GS_VPS_PDC_ UTC_BYTE_3.5 zero CGMS_WSS.12 CGMS_WSS.4 GS_VPS_PDC_ UTC_BYTE_0.4 GS_VPS_PDC_ UTC_BYTE_1.4 GS_VPS_PDC_ UTC_BYTE_2.4 GS_VPS_PDC_ UTC_BYTE_3.4 CGMS_CRC.5 CGMS_WSS.11 CGMS_WSS.3 GS_VPS_PDC_ UTC_BYTE_0.3 GS_VPS_PDC_ UTC_BYTE_1.3 GS_VPS_PDC_ UTC_BYTE_2.3 GS_VPS_PDC_ UTC_BYTE_3.3 CGMS_WSS_ CLEAR CGMS_WSS_AVL CCAP_BYTE_1.2 CCAP_BYTE_2.2 CGMS_CRC.4 CGMS_WSS.10 CGMS_WSS.2 GS_VPS_PDC_ UTC_BYTE_0.2 GS_VPS_PDC_ UTC_BYTE_1.2 GS_VPS_PDC_ UTC_BYTE_2.2 GS_VPS_PDC_ UTC_BYTE_3.2 VPS_PDC_UTC_ BYTE_4.2 VPS_PDC_UTC_ BYTE_5.2 VPS_PDC_UTC_ BYTE_6.2 VPS_PDC_UTC_ BYTE_7.2 VPS_PDC_UTC_ BYTE_8.2 VPS_PDC_UTC_ BYTE_9.2 VPS_PDC_UTC_ BYTE_10.2 VPS_PDC_UTC_ BYTE_11.2 VPS_PDC_UTC_ BYTE_12.2 VITC_DATA_1.2 VITC_DATA_2.2 VITC_DATA_3.2 VITC_DATA_4.2 VITC_DATA_5.2 VITC_DATA_6.2 VITC_DATA_7.2 VITC_DATA_8.2 VITC_DATA_9.2 VITC_CRC.2 VDP_STATUS_CLEAR W VDP_STATUS VDP_CCAP_DATA_0 VDP_CCAP_DATA_1 R R R CCAP_ CCAP_BYTE_1.7 BYTE_1.6 CCAP_ CCAP_BYTE_2.7 BYTE_2.6 zero CGMS_CRC.1 CGMS_WSS.7 GS_VPS_PDC_ UTC_BYTE_0.7 GS_VPS_PDC_ UTC_BYTE_1.7 GS_VPS_PDC_ UTC_BYTE_2.7 GS_VPS_PDC_ UTC_BYTE_3.7 zero CGMS_CRC.0 CGMS_WSS.6 GS_VPS_PDC_ UTC_BYTE_0.6 GS_VPS_PDC_ UTC_BYTE_1.6 GS_VPS_PDC_ UTC_BYTE_2.6 GS_VPS_PDC_ UTC_BYTE_3.6 CGMS_WSS_DATA_0 R CGMS_WSS_DATA_1 R CGMS_WSS_DATA_2 R VDP_GS_VPS_ PDC_UTC_0 VDP_GS_VPS_ PDC_UTC_1 VDP_GS_VPS_ PDC_UTC_2 VDP_GS_VPS_ PDC_UTC_3 VDP_VPS_PDC_ UTC_4 VDP_VPS_PDC_ UTC_5 VDP_VPS_PDC_ UTC_6 VDP_VPS_PDC_ UTC_7 VDP_VPS_PDC_ UTC_8 VDP_VPS_PDC_ UTC_9 VDP_VPS_PDC_ UTC_10 VDP_VPS_PDC_ UTC_11 VDP_VPS_PDC_ UTC_12 VDP_VITC_DATA_0 VDP_VITC_DATA_1 VDP_VITC_DATA_2 VDP_VITC_DATA_3 VDP_VITC_DATA_4 VDP_VITC_DATA_5 VDP_VITC_DATA_6 VDP_VITC_DATA_7 VDP_VITC_DATA_8 R R R R R R R R R R R R R R R R R R R R R R VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ BYTE_4.7 BYTE_4.6 BYTE_4.5 BYTE_4.4 BYTE_4.3 VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ BYTE_5.7 BYTE_5.6 BYTE_5.5 BYTE_5.4 BYTE_5.3 VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ BYTE_6.7 BYTE_6.6 BYTE_6.5 BYTE_6.4 BYTE_6.3 VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ BYTE_7.7 BYTE_7.6 BYTE_7.5 BYTE_7.4 BYTE_7.3 VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ BYTE_8.7 BYTE_8.6 BYTE_8.5 BYTE_8.4 BYTE_8.3 VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ BYTE_9.7 BYTE_9.6 BYTE_9.5 BYTE_9.4 BYTE_9.3 VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ BYTE_10.7 BYTE_10.6 BYTE_10.5 BYTE_10.4 BYTE_10.3 VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ BYTE_11.7 BYTE_11.6 BYTE_11.5 BYTE_11.4 BYTE_11.3 VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ VPS_PDC_UTC_ BYTE_12.7 BYTE_12.6 BYTE_12.5 BYTE_12.4 BYTE_12.3 VITC_DATA_1.7 VITC_DATA_1.6 VITC_DATA_1.5 VITC_DATA_1.4 VITC_DATA_1.3 VITC_DATA_2.7 VITC_DATA_2.6 VITC_DATA_2.5 VITC_DATA_2.4 VITC_DATA_2.3 VITC_DATA_3.7 VITC_DATA_3.6 VITC_DATA_3.5 VITC_DATA_3.4 VITC_DATA_3.3 VITC_DATA_4.7 VITC_DATA_4.6 VITC_DATA_4.5 VITC_DATA_4.4 VITC_DATA_4.3 VITC_DATA_5.7 VITC_DATA_5.6 VITC_DATA_5.5 VITC_DATA_5.4 VITC_DATA_5.3 VITC_DATA_6.7 VITC_DATA_6.6 VITC_DATA_6.5 VITC_DATA_6.4 VITC_DATA_6.3 VITC_DATA_7.7 VITC_DATA_7.6 VITC_DATA_7.5 VITC_DATA_7.4 VITC_DATA_7.3 VITC_DATA_8.7 VITC_DATA_8.6 VITC_DATA_8.5 VITC_DATA_8.4 VITC_DATA_8.3 VITC_DATA_9.7 VITC_DATA_9.6 VITC_DATA_9.5 VITC_DATA_9.4 VITC_DATA_9.3 VITC_CRC.7 VITC_CRC.6 I2C_GS_VPS_ PDC_UTC.0 VITC_CRC.5 VITC_CRC.4 VITC_CRC.3 WSS_CGMS_ GS_VPS_PDC_ UTC_CB_CHANGE CB_CHANGE VPS_PDC_UTC_ VPS_PDC_ BYTE_4.1 UTC_BYTE_4.0 VPS_PDC_UTC_ VPS_PDC_ BYTE_5.1 UTC_BYTE_5.0 VPS_PDC_UTC_ VPS_PDC_ BYTE_6.1 UTC_BYTE_6.0 VPS_PDC_UTC_ VPS_PDC_ BYTE_7.1 UTC_BYTE_7.0 VPS_PDC_UTC_ VPS_PDC_ BYTE_8.1 UTC_BYTE_8.0 VPS_PDC_UTC_ VPS_PDC_ BYTE_9.1 UTC_BYTE_9.0 VPS_PDC_UTC_ VPS_PDC_ BYTE_10.1 UTC_BYTE_10.0 VPS_PDC_UTC_ VPS_PDC_ BYTE_11.1 UTC_BYTE_11.0 VPS_PDC_UTC_ VPS_PDC_ BYTE_12.1 UTC_BYTE_12.0 VITC_DATA_1.1 VITC_DATA_1.0 VITC_DATA_2.1 VITC_DATA_2.0 VITC_DATA_3.1 VITC_DATA_3.0 VITC_DATA_4.1 VITC_DATA_4.0 VITC_DATA_5.1 VITC_DATA_5.0 VITC_DATA_6.1 VITC_DATA_6.0 VITC_DATA_7.1 VITC_DATA_7.0 VITC_DATA_8.1 VITC_DATA_8.0 VITC_DATA_9.1 VITC_DATA_9.0 VITC_CRC.1 VITC_CRC.0 VDP_VITC_CALC_CRC R VDP_OUTPUT_SEL I2C_GS_VPS_ RW PDC_UTC.1 00110000 30 Rev. 0 | Page 91 of 108 ADV7184 Table 104 provides a detailed description of the registers located in the User Sub Map. Table 104. User Sub Map Detailed Description User Sub Map Address Register 0x40 Interrupt Configuration 1 Bit Description INTRQ_OP_SEL[1:0]. Interrupt Drive Level Select Bit 7654321 0 0 1 1 0 1 x 00 01 10 11 00 01 10 11 Comments Open drain Drive low when active Drive high when active Reserved Manual interrupt mode disabled Manual interrupt mode enabled Not used Reserved Pseudo sync only Color stripe only Pseudo sync or color stripe 3 XTAL periods 15 XTAL periods 63 XTAL periods Active until cleared 0 No change 1 SD input has caused the decoder to go from an unlocked state to a locked state 0 No change 1 SD input has caused the decoder to go from a locked state to an unlocked state 0 0 1 0 1 Notes MPU_STIM_INTRQ[1:0]. Manual Interrupt Set Mode Reserved MV_INTRQ_SEL[1:0]. Macrovision Interrupt Select INTRQ_DUR_SEL[1:0]. Interrupt duration Select 0x42 Interrupt Status 1 (Read Only) SD_LOCK_Q These bits can be cleared or masked in Registers 0x43 and 0x44, respectively. SD_UNLOCK_Q Reserved Reserved Reserved SD_FR_CHNG_Q x x x 0 1 0 1 No Change Denotes a change in the free-run status No Change Pseudo sync/color striping detected. See Reg 0x40 MV_INTRQ_SEL[1:0] for selection 0 Do not clear 1 Clears SD_LOCK_Q bit Do not clear Clears SD_UNLOCK_Q bit Not used Not used Not used Do not clear Clears SD_FR_CHNG_Q bit Do not clear Clears MV_PS_CS_Q bit Not used 0 Masks SD_LOCK_Q bit 1 Unmasks SD_LOCK_Q bit Masks SD_UNLOCK_Q bit Unmasks SD_UNLOCK_Q bit Not used Not used Not used Masks SD_FR_CHNG_Q bit Unmasks SD_FR_CHNG_Q bit Masks MV_PS_CS_Q bit Unmasks MV_PS_CS_Q bit Not used MV_PS_CS_Q 0x43 Interrupt Clear 1 (Write Only) Reserved SD_LOCK_CLR SD_UNLOCK_CLR Reserved Reserved Reserved SD_FR_CHNG_CLR MV_PS_CS_CLR Reserved SD_LOCK_MSKB SD_UNLOCK_MSKB Reserved Reserved Reserved SD_FR_CHNG_MSKB MV_PS_CS_MSKB Reserved x 0 1 0 0 0 0 1 0 1 x 0x44 Interrupt Mask 1 (Read/Write) 0 1 0 0 0 0 1 0 1 x Rev. 0 | Page 92 of 108 ADV7184 User Sub Map Address Register 0x45 Raw Status 2 (Read Only) Bit Description CCAPD Bit 7 6 5 4 3 2 1 0 Comments 0 No CCAPD data detected – VBI system 2 1 CCAPD data detected – VBI system 2 xxx 0 Current SD Field is Odd Numbered 1 Current SD Field is Even Numbered xx 0 MPU_STIM_INT = 0 1 MPU_STIM_INT = 1 0 Closed captioning not detected in the input video signal – VBI system 2 1 Closed captioning data detected in the video input signal – VBI system 2 0 Gemstar data not detected in the input video signal– VBI system 2 1 Gemstar data detected in the input video signal– VBI system 2 xx 0 SD signal has not changed Field from ODD to Even or Vice versa 1 SD signal has changed Field from ODD to Even or Vice versa x Not used x Not used 0 Manual interrupt not Set 1 Manual interrupt Set 0 Do not clear – VBI system 2 1 Clears CCAPD_Q bit – VBI system 2 0 Do not clear 1 Clears GEMD_Q bit xx 0 Do not Clear 1 Clears SD_FIELD_CHNGD_Q bit x Not used x Not used 0 Do not clear 1 Clears MPU_STIM_INTRQ_Q bit 0 Masks CCAPD_Q bit – VBI system 2 1 Unmasks CCAPD_Q bit – VBI system 2 0 Masks GEMD_Q bit – VBI system 2 1 Unmasks GEMD_Q bit – VBI system 2 00 Not used 0 Masks SD_FIELD_CHNGD_Q bit 1 Unmasks SD_FIELD_CHNGD_Q bit 00 Not used 0 Masks MPU_STIM_INTRQ_Q bit 1 Unmasks MPU_STIM_INTRQ_Q bit 0 SD 60 Hz signal output 1 SD 50 Hz signal output 0 SD vertical sync lock not established 1 SD vertical sync lock established 0 SD horizontal sync lock not established 1 SD horizontal sync lock established x Not used 0 SECAM lock not established 1 SECAM lock established x Not used x Not used x Not used Notes These bits are status bits only. They cannot be cleared or masked. Register 0x46 is used for this purpose. Reserved EVEN_FIELD Reserved MPU_STIM_INTRQ 0x46 Interrupt Status 2 (Read Only) CCAPD_Q These bits can be cleared or masked by registers 0x47 and 0x48, respectively. Note that interrupt in register 0x46 for the CCAP, Gemstar, CGMS and WSS data is using the Mode 1 data slicer. GEMD_Q Reserved SD_FIELD_CHNGD_Q Reserved Reserved MPU_STIM_INTRQ_Q 0x47 Interrupt Clear 2 (Write Only) CCAPD_CLR GEMD_CLR Reserved SD_FIELD_CHNGD_CLR Reserved Reserved MPU_STIM_INTRQ_CLR 0x48 Interrupt Mask 2 (Read/Write) CCAPD_MSKB Note that interrupt in register 0x46 for the CCAP, Gemstar, CGMS and WSS data is using the Mode 1 data slicer. GEMD_MSKB Note that interrupt in register 0x46 for the CCAP, Gemstar, CGMS and WSS data is using the Mode 1 data slicer. Reserved SD_FIELD_CHNGD_MSKB Reserved MPU_STIM_INTRQ_MSKB 0x49 Raw Status 3 (Read Only) SD_OP_50Hz. SD 60/50Hz frame rate at output SD_V_LOCK SD_H_LOCK These bits are status bits only. They cannot be cleared or masked. Register 0x4A is used for this purpose. Reserved SCM_LOCK Reserved Reserved Reserved Rev. 0 | Page 93 of 108 ADV7184 User Sub Map Address Register 0x4A Interrupt Status 3 (Read Only) Bit 7 6 5 4 3 2 1 0 Comments 0 No Change in SD signal standard detected at the output 1 A Change in SD signal standard is detected at the output SD_V_LOCK_CHNG_Q 0 No change in SD vertical sync lock status 1 SD vertical sync lock status has changed SD_H_LOCK_CHNG_Q 0 No change in SD horizontal sync lock status 1 SD horizontal sync lock status has changed SD_AD_CHNG_Q. SD autodetect changed x No change in AD_RESULT[2:0] bits in Status Register 1 AD_RESULT[2:0] bits in Status Register 1 have changed SCM_LOCK_CHNG_Q. SECAM Lock 0 No change in SECAM Lock status 1 SECAM lock status has changed PAL_SW_LK_CHNG_Q x No change in PAL swinging burst lock status PAL swinging burst lock status has changed Reserved x Not used Reserved x Not used SD_OP_CHNG_CLR 0 Do not clear 1 Clears SD_OP_CHNG_Q bit SD_V_LOCK_CHNG_CLR 0 Do not clear 1 Clears SD_V_LOCK_CHNG_Q bit SD_H_LOCK_CHNG_CLR 0 Do not clear 1 Clears SD_H_LOCK_CHNG_Q bit SD_AD_CHNG_CLR 0 Do not clear 1 Clears SD_AD_CHNG_Q bit SCM_LOCK_CHNG_CLR 0 Do not clear 1 Clears SCM_LOCK_CHNG_Q bit PAL_SW_LK_CHNG_CLR 0 Do not clear 1 Clears PAL_SW_LK_CHNG_Q bit Reserved x Not used Reserved x Not used SD_OP_CHNG_MSKB 0 Masks SD_OP_CHNG_Q bit 1 Unmasks SD_OP_CHNG_Q bit SD_V_LOCK_CHNG_ MSKB 0 Masks SD_V_LOCK_CHNG_Q bit 1 Unmasks SD_V_LOCK_CHNG_Q bit SD_H_LOCK_CHNG_ MSKB 0 Masks SD_H_LOCK_CHNG_Q bit 1 Unmasks SD_H_LOCK_CHNG_Q bit SD_AD_CHNG_ MSKB 0 Masks SD_AD_CHNG_Q bit 1 Unmasks SD_AD_CHNG_Q bit SCM_LOCK_CHNG_ MSKB 0 Masks SCM_LOCK_CHNG_Q bit 1 Unmasks SCM_LOCK_CHNG_Q bit PAL_SW_LK_CHNG_ MSKB 0 Masks PAL_SW_LK_CHNG_Q bit 1 Unmasks PAL_SW_LK_CHNG_Q bit Reserved x Not used x Not used Reserved VDP_CCAPD_Q 0 Closed captioning not detected 1 Closed captioning detected Reserved x VDP_CGMS_WSS_CHNGD_Q. See 0x9C Bit 0 CGMS/WSS data is not changed/not 4of User Sub Map to determine whether available interrupt is issued for a change in 1 CGMS/WSS data is detected data or for when data is changed/available detected regardless of content Reserved x VDP_GS_VPS_PDC_UTC_CHNG_Q. See 0 Gemstar/PDC/VPS/UTC data is not 0x9C Bit 5of User Sub Map to determine changed/available Bit Description SD_OP_CHNG_Q. SD 60/50 Hz frame rate at output Notes These bits can be cleared and masked by Registers 0x4B and 0x4C, respectively. 0x4B Interrupt Clear 3 (Write Only) 0x4C Interrupt Mask 2 (Read/Write) 0x4E Interrupt Status 4 (Read Only) These bits can be cleared and masked by Registers 0x4F and 0x50, respectively. Note that interrupt in register 0x4E for the CCAP, Gemstar, CGMS, WSS,VPS,PDC, UTC and VITC data is using the VDP data slicer. Rev. 0 | Page 94 of 108 ADV7184 User Sub Map Address Register Bit Bit Description 76543210 whether interrupt is issued for a change in 1 detected data or for when data is detected regardless of content Reserved x VDP_VITC_Q 0 1 Reserved x VDP_CCAPD_CLR 0 1 Reserved x VDP_CGMS_WSS_CHNGD_CLR 0 1 Reserved x VDP_GS_VPS_PDC_UTC_ 0 CHNG_CLR 1 Reserved VDP_VITC_CLR Reserved VDP_CCAPD_MSKB Reserved VDP_CGMS_WSS_CHNGD_MSKB x 0 Masks VDP_CCAPD_Q 1 Unmasks VDP_CCAP_D_Q x 0 1 x 0 1 Reserved VDP_VITC_MSKB Reserved VDP_TTXT_TYPE_MAN[1:0] x 0 0 PAL: Teletext-ITU-BT.653-625/50-A NTSC: Reserved 0 1 PAL: Teletext-ITU-BT.653-625/50-B (WST) NTSC: Teletext-ITU-BT.653-525/60-B 1 0 PAL: Teletext-ITU-BT.653-625/50-C NTSC: Teletext-ITU-BT.653-525/60-C OR EIA516 (NABTS) 1 1 PAL: Teletext-ITU-BT.653-625/50-D NTSC: Teletext-ITU-BT.653-525/60-D 0 User programming of teletext type disabled 1 User programming of teletext type enabled 0 Enable hamming decoding of WST packets 1 Disable hamming decoding of WST packets 1000 xx00 0 1 Reserved ADF_DID[4:0] 000 1 0 1 0 1 User specified DID sent in the ancillary data stream with VDP decoded data 00 Nibble mode 01 Byte mode, no code restrictions Disable autodetection of Gemstar type Enable autodetection of Gemstar type x 0 1 Masks VDP_VITC_Q Unmasks VDP_VITC_Q Masks VDP_GS_VPS_PDC_UTC_CHNG_Q Unmasks VDP_GS_VPS_PDC_UTC_CHNG_Q Masks VDP_CGMS_WSS_CHNGD_Q Unmasks VDP_CGMS_WSS_CHNGD_Q Note that interrupt in register 0x4E for the CCAP, Gemstar, CGMS, WSS,VPS,PDC, UTC and VITC data is using the VDP data slicer. x 0 1 Do not clear Clears VDP_VITC_Q Comments Gemstar/PDC/VPS/UTC data is changed/available Notes VITC data is not available in the VDP VITC data is available in the VDP Do not clear Clears VDP_CCAPD_Q Do not clear Clears VDP_CGMS_WSS_CHNGD_Q Do not clear Clears VDP_GS_VPS_PDC_UTC_CHNG_Q Note that interrupt in register 0x4E for the CCAP, Gemstar, CGMS, WSS,VPS,PDC, UTC and VITC data is using the VDP data slicer. 0x4F Interrupt Clear 4 (Write Only) 0x50 Interrupt Mask 4 Reserved VDP_GS_VPS_PDC_UTC_ CHNG_MSKB 0x60 VDP_Config_1 VDP_TTXT_TYPE_MAN_ENABLE WST_PKT_DECOD_DISABLE 0x61 VDP_Config_2 Reserved Reserved AUTO_DETECT_GS_TYPE 0x62 VDP_ADF_Config_1 ADF_MODE[1:0] Rev. 0 | Page 95 of 108 ADV7184 User Sub Map Address Register Bit Description Bit 7 6 5 4 3 2 1 0 Comments 10 Byte mode with 0x00 and 0xFF prevented 11 Reserved 0 Disable insertion of VBI decoded data into ancillary 656 stream 1 Enable insertion of VBI decoded data into ancillary 656 stream 1 0 1 0 1 0 User-specified SDID sent in the ancillary data stream with VDP decoded data x 0 Ancillary data packet is spread across the Y and C data streams 1 Ancillary data packet is duplicated on the Y and C data streams 0 0 0 0 Sets VBI standard to be decoded from line 318 (PAL). NTSC – N/A 000 0 Decode default standards on the lines indicated in Table 64. 1 Manually program the VBI standard to be decoded on each line. See Table 65 0 0 0 0 Sets VBI standard to be decoded from line 319 (PAL), 286 (NTSC) 0000 Sets VBI standard to be decoded from line 6 (PAL), 23 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 320 (PAL), 287 (NTSC) 0000 Sets VBI standard to be decoded from line 7 (PAL), 24 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 321 (PAL), 288 (NTSC) 0000 Sets VBI standard to be decoded from line 8 (PAL), 25 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 322 (PAL), NTSC – N/A 0000 Sets VBI standard to be decoded from line 9 (PAL), NTSC – N/A 0 0 0 0 Sets VBI standard to be decoded from line 323 (PAL), NTSC –N/A 0000 Sets VBI standard to be decoded from line 10 (PAL), NTSC – N/A 0 0 0 0 Sets VBI standard to be decoded from line 324 (PAL), 272 (NTSC) 0000 Sets VBI standard to be decoded from line 11 (PAL), NTSC – N/A 0 0 0 0 Sets VBI standard to be decoded from line 325 (PAL), 273(NTSC) 0000 Sets VBI standard to be decoded from line 12 (PAL), 10 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 326 (PAL), 274 (NTSC) 0000 Sets VBI standard to be decoded from line 13 (PAL), 11 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 327 (PAL), 275 (NTSC) 0000 Sets VBI standard to be decoded from line 14 (PAL), 12 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 328 (PAL), 276 (NTSC) 0000 Sets VBI standard to be decoded from line 15 (PAL), 13 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 329 (PAL), 277 (NTSC) 0000 Sets VBI standard to be decoded from line 16 (PAL), 14 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 330 (PAL), 278 (NTSC) Notes ADF_ENABLE 0x63 VDP_ADF_Config_2 ADF_SDID[5:0] Reserved DUPLICATE_ADF 0x64 VDP_LINE_00E VBI_DATA_P318[3:0] Reserved MAN_LINE_PGM If set to 1, all VBI_DATA_Px_Ny bits must set as desired. MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be 0x65 VDP_LINE_00F VBI_DATA_P319_N286[3:0] VBI_DATA_P6_N23[3:0] 0x66 VDP_LINE_010 VBI_DATA_P320_N287[3:0] VBI_DATA_P7_N24[3:0] 0x67 VDP_LINE_011 VBI_DATA_P321_N288[3:0] VBI_DATA_P8_N25[3:0] 0x68 VDP_LINE_012 VBI_DATA_P322[3:0] VBI_DATA_P9[3:0] 0x69 VDP_LINE_013 VBI_DATA_P323[3:0] VBI_DATA_P10[3:0] 0x6A VDP_LINE_014 VBI_DATA_P324_N272[3:0] VBI_DATA_P11[3:0] 0x6B VDP_LINE_015 VBI_DATA_P325_N273[3:0] VBI_DATA_P12_N10[3:0] 0x6C VDP_LINE_016 VBI_DATA_P326_N274[3:0] VBI_DATA_P13_N11[3:0] 0x6D VDP_LINE_017 VBI_DATA_P327_N275[3:0] VBI_DATA_P14_N12[3:0] 0x6E VDP_LINE_018 VBI_DATA_P328_N276[3:0] VBI_DATA_P15_N13[3:0] 0x6F VDP_LINE_019 VBI_DATA_P329_N277[3:0] VBI_DATA_P16_N14[3:0] 0x70 VDP_LINE_01A VBI_DATA_P330_N278[3:0] Rev. 0 | Page 96 of 108 ADV7184 User Sub Map Address Register Bit Description VBI_DATA_P17_N15[3:0] VBI_DATA_P331_N279[3:0] VBI_DATA_P18_N16[3:0] 0x72 VDP_LINE_01C VBI_DATA_P332_N280[3:0] VBI_DATA_P19_N17[3:0] 0x73 VDP_LINE_01D VBI_DATA_P333_N281[3:0] VBI_DATA_P20_N18[3:0] 0x74 VDP_LINE_01E VBI_DATA_P334_N282[3:0] VBI_DATA_P21_N19[3:0] 0x75 VDP_LINE_01F VBI_DATA_P335_N283[3:0] VBI_DATA_P22_N20[3:0] 0x76 VDP_LINE_020 VBI_DATA_P336_N284[3:0] VBI_DATA_P23_N21[3:0] 0x77 VDP_LINE_021 VBI_DATA_P337_N285[3:0] VBI_DATA_P24_N22[3:0] 0x78 VDP_STATUS (Read Only) CC_AVL CC_EVEN_FIELD Bit 7 6 5 4 3 2 1 0 Comments 0000 Sets VBI standard to be decoded from line 17 (PAL), 15 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 331 (PAL), 279 (NTSC) 0000 Sets VBI standard to be decoded from line 18 (PAL), 16 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 332 (PAL), 280 (NTSC) 0000 Sets VBI standard to be decoded from line 19 (PAL), 17 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 333 (PAL), 281 (NTSC) 0000 Sets VBI standard to be decoded from line 20 (PAL), 18 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 334 (PAL), 282 (NTSC) 0000 Sets VBI standard to be decoded from line 21 (PAL), 19 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 335 (PAL), 283 (NTSC) 0000 Sets VBI standard to be decoded from line 22 (PAL), 20 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 336 (PAL), 284 (NTSC) 0000 Sets VBI standard to be decoded from line 23 (PAL), 21 (NTSC) 0 0 0 0 Sets VBI standard to be decoded from line 337 (PAL), 285 (NTSC) 0000 Sets VBI standard to be decoded from line 24 (PAL), 22 (NTSC) 0 Closed captioning not detected 1 Closed captioning detected 0 Closed captioning decoded from odd field 1 Closed captioning decoded from even field 0 CGMS/WSS not detected 1 CGMS/WSS detected 0 0 VPS not detected 1 VPS detected 0 1 0 1 0 1 Gemstar 1x detected Gemstar 2x detected VITC not detected VITC detected Teletext not detected Teletext detected 0 Do not re-initialize the CCAP registers 1 Re-initializes the CCAP readback registers 0 0 1 Reserved GS_PDC_VPS_UTC_CLEAR 0 0 1 Reserved VITC_CLEAR 0 0 1 0 Do not re-initialize the VITC registers This is a self-clearing bit Re-initializes the VITC readback registers Do not re-initialize the GS/PDC/VPS/ UTC registers Refreshes the GS/PDC/VPS/UTC readback registers This is a self-clearing bit Do not re-initialize the CGMS/WSS registers Re-initializes the CGMS/WSS readback registers This is a self-clearing bit Notes effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective MAN_LINE_PGM must be set to 1 for these bits to be effective CC_CLEAR resets the CC_AVL bit 0x71 VDP_LINE_01B CGMS_WSS_AVL Reserved GS_PDC_VPS_UTC_AVL CGMS_WSS_CLEAR resets the CGMS_WSS_AVL bit GS_PDC_VPS_UTC_CLEAR resets the GS_PDC_VPS_UTC_AVL bit GS_DATA_TYPE VITC_AVL TTXT_AVL 0x78 VDP_STATUS_CLEAR (Write Only) CC_CLEAR VITC_CLEAR resets the VITC_AVL bit This is a self-clearing bit Reserved CGMS_WSS_CLEAR Reserved Rev. 0 | Page 97 of 108 ADV7184 User Sub Map Address Register 0x79 VDP_CCAP_DATA_0 (Read Only) 0x7A VDP_CCAP_DATA_1 (Read Only) 0x7D VDP_CGMS_WSS_DATA_0 (Read Only) 0x7E 0x7F 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F 0x90 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C Bit Description CCAP_BYTE_1[7:0] CCAP_BYTE_2[7:0] Bit 7 6 5 4 3 2 1 0 Comments x x x x x x x x Decoded Byte 1 of CCAP x x x x x x x x Decoded Byte 2 of CCAP x x x x Decoded CRC sequence for CGMS 0000 x x x x x x Decoded CGMS/WSS data xx Decoded CRC sequence for CGMS x x x x x x x x Decoded CGMS/WSS data x x x x x x x x Decoded Gemstar/VPS/PDC/UTC data x x x x x x x x Decoded Gemstar/VPS/PDC/UTC data x x x x x x x x Decoded Gemstar/VPS/PDC/UTC data x x x x x x x x Decoded Gemstar/VPS/PDC/UTC data x x x x x x x x Decoded VPS/PDC/UTC data x x x x x x x x Decoded VPS/PDC/UTC data x x x x x x x x Decoded VPS/PDC/UTC data x x x x x x x x Decoded VPS/PDC/UTC data x x x x x x x x Decoded VPS/PDC/UTC data x x x x x x x x Decoded VPS/PDC/UTC data x x x x x x x x Decoded VPS/PDC/UTC data x x x x x x x x Decoded VPS/PDC/UTC data x x x x x x x x Decoded VPS/PDC/UTC data x x x x x x x x Decoded VITC data x x x x x x x x Decoded VITC data x x x x x x x x Decoded VITC data x x x x x x x x Decoded VITC data x x x x x x x x Decoded VITC data x x x x x x x x Decoded VITC data x x x x x x x x Decoded VITC data x x x x x x x x Decoded VITC data x x x x x x x x Decoded VITC data x x x x x x x x Decoded VITC CRC data 0000 0 1 GS_VPS_PDC_UTC_CB_CHANGE 0 1 I2C_GS_VPS_PDC_UTC[1:0] 0 0 1 1 0 1 0 1 Disable content-based updating of CGMS and WSS data Enable content-based updating of CGMS and WSS data Disable content-based updating of Gemstar, VPS, PDC and UTC data Enable content-based updating of Gemstar, VPS, PDC and UTC data Gemstar 1x/2x VPS PDC UTC The AVAILABLE bit shows the availability of data only when its content has changed. Notes CGMS_CRC[5:2] Reserved VDP_CGMS_WSS_DATA_1 CGMS_WSS[13:8] (Read Only) CGMS_CRC[1:0] VDP_CGMS_WSS_DATA_2 CGMS_WSS[7:0] (Read Only) VDP_GS_VPS_PDC_UTC_0 GS_VPS_PDC_UTC_BYTE_0[7:0] (Read Only) VDP_GS_VPS_PDC_UTC_1 GS_VPS_PDC_UTC_BYTE_1[7:0] (Read Only) VDP_GS_VPS_PDC_UTC_2 GS_VPS_PDC_UTC_BYTE_2[7:0] (Read Only) VDP_GS_VPS_PDC_UTC_3 GS_VPS_PDC_UTC_BYTE_3[7:0] (Read Only) VDP_VPS_PDC_UTC_4 VPS_PDC_UTC_BYTE_4[7:0] (Read Only) VDP_VPS_PDC_UTC_5 VPS_PDC_UTC_BYTE_5[7:0] (Read Only) VDP_VPS_PDC_UTC_6 VPS_PDC_UTC_BYTE_6[7:0] (Read Only) VDP_VPS_PDC_UTC_7 VPS_PDC_UTC_BYTE_7[7:0] (Read Only) VDP_VPS_PDC_UTC_8 VPS_PDC_UTC_BYTE_8[7:0] (Read Only) VDP_VPS_PDC_UTC_9 VPS_PDC_UTC_BYTE_9[7:0] (Read Only) VDP_VPS_PDC_UTC_10 VPS_PDC_UTC_BYTE_10[7:0] (Read Only) VDP_VPS_PDC_UTC_11 VPS_PDC_UTC_BYTE_11[7:0] (Read Only) VDP_VPS_PDC_UTC_12 VPS_PDC_UTC_BYTE_12[7:0] (Read Only) VDP_VITC_DATA_0 VITC_DATA_0[7:0] (Read Only) VDP_VITC_DATA_1 VITC_DATA_1[7:0] (Read Only) VDP_VITC_DATA_2 VITC_DATA_2[7:0] (Read Only) VDP_VITC_DATA_3 VITC_DATA_3[7:0] (Read Only) VDP_VITC_DATA_4 VITC_DATA_4[7:0] (Read Only) VDP_VITC_DATA_5 VITC_DATA_5[7:0] (Read Only) VDP_VITC_DATA_6 VITC_DATA_6[7:0] (Read Only) VDP_VITC_DATA_7 VITC_DATA_7[7:0] (Read Only) VDP_VITC_DATA_8 VITC_DATA_8[7:0] (Read Only) VDP_VITC_CALC_CRC VITC_CRC[7:0] (Read Only) VDP_OUTPUT_SEL Reserved WSS_CGMS_CB_CHANGE Standard expected to be decoded Rev. 0 | Page 98 of 108 ADV7184 I2C PROGRAMMING EXAMPLES Note: These scripts are applicable to a system with the analog inputs arranged as shown in Figure 50. The input selection registers change in accordance with how the PCB is laid out. MODE 1 CVBS INPUT Composite video on AIN10. All standards are supported through autodetect, 8-bit, 4:2:2, ITU-R BT.656 output on P15 to P8. Table 105. Mode 1 CVBS Input Register Address 0x00 0x17 0x19 0x1D 0x3A 0x3B 0x3D 0x3E 0x3F 0xF3 0xF9 0x0E 0x52 0x54 0x7F 0x81 0x90 0x91 0x92 0x93 0x94 0xB1 0xB6 0xC0 0xCF 0xD0 0xD1 0xD6 0xD7 0xE5 0x0E Register Value 0x0E 0x41 0xFA 0x47 0x17 0x71 0xA2 0x6A 0xA0 0x01 0x03 0x80 0x46 0x00 0xFF 0x30 0xC9 0x40 0x3C 0xCA 0xD5 0xFF 0x08 0x9A 0x50 0x4E 0xB9 0xDD 0xE2 0x51 0x00 Notes CVBS on AIN 10. Set CSFM to SH1. Split filter control. Enable 28.63636 MHz crystal mode. Power down ADC1, ADC2 and ADC3. Recommended setting. MWE enable manual window, color kill threshold to 2. BLM optimization. BGB optimization Enable antialias filter on ADC0. Set maximum v lock range. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev. 0 | Page 99 of 108 ADV7184 MODE 2 S-VIDEO INPUT Y on AIN2 and C on AIN3. All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 106. Mode 2 S-Video Input Register Address 0x1D 0x3A 0x3B 0x3D 0x3E 0x3F 0x69 0xC3 0xC4 0xF3 0xF9 0x0E 0x52 0x54 0x7F 0x81 0x90 0x91 0x92 0x93 0x94 0xB1 0xB6 0xC0 0xCF 0xD0 0xD1 0xD6 0xD7 0xE5 0x0E Register Value 0x47 0x13 0x71 0xA2 0x6A 0xA0 0x03 0x32 0xFF 0x03 0x03 0x80 0x46 0x00 0xFF 0x30 0xC9 0x40 0x3C 0xCA 0xD5 0xFF 0x08 0x9A 0x50 0x4E 0xB9 0xDD 0xE2 0x51 0x00 Notes Enable 28.63636 MHz crystal mode. Power down ADC2 and ADC3. Recommended setting. MWE enable manual window, color kill threshold to 2. BLM optimization. BGB optimization. Set SDM_SEL to 03 for YC/CVBS auto AIN11, AIN12. Manually mux Y signal on AIN2 to ADC0 and C signal on AIN3 to ADC1. Manual mux enable. Enable anti-alias filter on ADC0 and ADC1. Set maximum v lock range. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev. 0 | Page 100 of 108 ADV7184 MODE 3 525I/625I YPRPB INPUT Y on AIN6, Pr on AIN4, and Pb on AIN5. All standards are supported through autodetect, 8-bit, ITU-R BT.656 output on P15 to P8. Table 107. Mode 3 YPrPb Input 525i/625i Register Address 0x8D 0x00 0x1D 0x27 0x3A 0x3B 0x3D 0x3E 0x3F 0xB4 0xB5 0xC3 0xC4 0xF3 0xF9 0x0E 0x52 0x54 0x7F 0x81 0x90 0x91 0x92 0x93 0x94 0x7E 0xB1 0xB6 0xC0 0xCF 0xD0 0xD1 0xD6 0xE5 0x0E Register Value 0x83 0x09 0x47 0x98 0x11 0x71 0xA2 0x6A 0xA0 0xF9 0x00 0x46 0xB5 0x07 0x03 0x80 0x46 0x00 0xFF 0x30 0xC9 0x40 0x3C 0xCA 0xD5 0x73 0xFF 0x08 0x9A 0x50 0x4E 0xB9 0xDD 0x51 0x00 Notes Recommended setting. Set YPrPb mode. Note: Writes below to registers 0xC3 and 0xC4, overrides INSEL YPrPb setting. Enable 28.63636 MHz crystal mode. Swap Cr and Cb, Y/C delay correction. Power down ADC3. Recommended setting. MWE enable manual window, color kill threshold to 2. BLM optimization. BGB optimization. Recommended setting. Recommended setting. Manually mux Y signal on AIN6 to ADC0, Pr signal on AIN4 to ADC1. Manual mux enable, Pb signal on AIN5 to ADC2. Enable anti-alias filter on ADC0, ADC1 and ADC2. Set maximum v lock range. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev. 0 | Page 101 of 108 ADV7184 MODE 4 SCART—S-VIDEO OR CVBS AUTODETECT Y/CVBS Input on AIN11, C INPUT on AIN12, 8-bit, ITU-R BT.656 output on P15 to P8. Table 108. Mode 4 SCART CVBS/S-Video Autodetect on AIN 11/ AIN12 Register Address 0x1D 0x3A 0x3B 0x3D 0x3E 0x3F 0x69 0xF3 0xF9 0x0E 0x52 0x54 0x7F 0x81 0x90 0x91 0x92 0x93 0x94 0xB1 0xB6 0xC0 0xCF 0xD0 0xD1 0xD6 0xD7 0xE5 0x0E Register Value 0x47 0x13 0x71 0xA2 0x6A 0xA0 0x03 0x03 0x03 0x80 0x46 0x00 0xFF 0x30 0xC9 0x40 0x3C 0xCA 0xD5 0xFF 0x08 0x9A 0x50 0x4E 0xB9 0xDD 0xE2 0x51 0x00 Notes Enable 28.63636 MHz crystal mode. Power down ADC2 and ADC3. Recommended Setting MWE enable manual window, color kill threshold to 2. BLM optimization. BGB optimization. Set SDM_SEL to 03 for YC/CVBS auto AIN11, AIN12. Enable anti-alias filter on ADC0 and ADC1. Set maximum v lock range Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev. 0 | Page 102 of 108 ADV7184 MODE 5 SCART FAST BLANK—CVBS AND RGB CVBS Input on AIN11, B INPUT on AIN7, R INPUT on AIN8, G INPUT on AIN9; 8-bit, ITU-R BT.656 output on P15 to P8. Table 109. Mode 5 SCART CVBS/S-Video Autodetect on AIN 11/ AIN12 Register Address 0x00 0x17 0x19 0x1D 0x3A 0x3B 0x3D 0x3E 0x3F 0x4D 0x67 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0xC5 0xED 0xF3 0xF9 0x0E 0x49 0x52 0x54 0x7F 0x81 0x90 0x91 0x92 0x93 0x94 0xB1 0xB6 0xC0 0xCF 0xD0 0xD1 0xD6 0xD7 0xE5 0x0E Register Value 0x0F 0x41 0xFA 0x47 0x10 0x71 0xA2 0x6A 0xA0 0xEE 0x01 0xD0 0x04 0x01 0x00 0x04 0x08 0x02 0x00 0x00 0x12 0x0F 0x03 0x80 0x01 0x46 0x00 0xFF 0x30 0xC9 0x40 0x3C 0xCA 0xD5 0xFF 0x08 0x9A 0x50 0x4E 0xB9 0xDD 0xE2 0x51 0x00 Notes CVBS on AIN11. Set CSFM to SH1. Split filter control. Enable 28.63636 MHz crystal mode. Power up all four ADCs. Recommended setting. MWE enable manual window, color kill threshold to 2. BLM optimization. BGB optimization. Disable CTI Format 422. Manual gain channels A, B, C. Manual gain channels A, B, C. Manual gain channels A, B, C. Manual gain channels A, B, C. Manual offsets A to 64d, B and C to 512d. Manual offsets A to 64d, B and C to 512d. Manual offsets A to 64d, B and C to 512d. Manual offsets A to 64d, B and C to 512d. Recommended write. Enable dynamic fast blank mode. Enable anti-alias filter on all ADCs. Set maximum v lock range. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev. 0 | Page 103 of 108 ADV7184 MODE 6 SCART RGB INPUT (STATIC FAST BLANK)—CVBS AND RGB CVBS Input on AIN11, B INPUT on AIN7, R INPUT on AIN8, G INPUT on AIN9, 8-bit, ITU-R BT.656 output on P15 to P8. Table 110. Mode 6 SCART CVBS/S-Video Autodetect on AIN 11/ AIN12 Register Address 0x00 0x1D 0x3A 0x3B 0x3D 0x3E 0x3F 0x4D 0x67 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x93 0x94 0x95 0x96 0xC5 0xED 0xF3 0xF9 0x0E 0x52 0x54 0x7F 0x81 0x90 0x91 0x92 0x93 0x94 0xB1 0xB6 0xC0 0xCF 0xD0 0xD1 0xD6 0xD7 0xE5 0x0E Register Value 0x0F 0x47 0x10 0x71 0xA2 0x6A 0xA0 0xEE 0x01 0xD0 0x04 0x01 0x00 0x04 0x08 0x02 0x00 0x78 0x23 0x11 0xC0 0x00 0xC4 0x0F 0x03 0x80 0x46 0x00 0xFF 0x30 0xC9 0x40 0x3C 0xCA 0xD5 0xFF 0x08 0x9A 0x50 0x4E 0xB9 0xDD 0xE2 0x51 0x00 Notes CVBS on AIN11. Enable 28.63636 MHz crystal mode. Power up all four ADCs. Recommended setting. MWE enable manual window, color kill threshold to 2. BLM optimization. BGB optimization. Disable CTI. Format 422. Manual gain channels A, B, C. Manual gain channels A, B, C. Manual gain channels A, B, C. Manual gain channels A, B, C. Manual offsets A to 64d, B and C to 512d. Manual offsets A to 64d, B and C to 512d. Manual offsets A to 64d, B and C to 512d. Manual offsets A to 64d, B and C to 512d. Clamp optimization Clamp optimization Clamp optimization Clamp optimization Recommended write. Enable static switching mode and select RGB input. Enable anti-alias filter on all ADCs. Set maximum v lock range. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Recommended setting. Rev. 0 | Page 104 of 108 ADV7184 PCB LAYOUT RECOMMENDATIONS The ADV7184 is a high precision, high speed mixed-signal device. To achieve the maximum performance from the part, it is important to have a well laid out PCB board. The following is a guide for designing a board using the ADV7184. It is also recommended to use a single ground plane for the entire board. This ground plane should have a space between the analog and digital sections of the PCB (see Figure 48). ADV7184 05479-052 ANALOG INTERFACE INPUTS Care should be taken when routing the inputs on the PCB. Track lengths should be kept to a minimum, and 75 Ω trace impedances should be used when possible. Trace impedances other than 75 Ω increase the chance of reflections. ANALOG SECTION DIGITAL SECTION Figure 48. PCB Ground Layout POWER SUPPLY DECOUPLING It is recommended to decouple each power supply pin with 0.1 μF and 10 nF capacitors. The fundamental idea is to have a decoupling capacitor within about 0.5 cm of each power pin. Also, avoid placing the capacitor on the opposite side of the PC board from the ADV7184, as doing so interposes resistive vias in the path. The decoupling capacitors should be located between the power plane and the power pin. Current should flow from the power plane to the capacitor to the power pin. Do not make the power connection between the capacitor and the power pin. Placing a via underneath the 100 nF capacitor pads, down to the power plane, is generally the best approach (see Figure 47). VDD 10nF GND 100nF VIA TO GND 05479-051 Experience has repeatedly shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result. In some cases, using separate ground planes is unavoidable. For those cases, it is recommended to place a single ground plane under the ADV7184. The location of the split should be under the ADV7184. For this case, it is even more important to place components wisely because the current loops are much longer (current takes the path of least resistance). An example of a current loop: power plane to ADV7184 to digital output trace to digital data receiver to digital ground plane to analog ground plane. PLL Place the PLL loop filter components as close as possible to the ELPF pin. Do not place any digital or other high frequency traces near these components. Use the values suggested in Figure 50 with tolerances of 10% or less. VIA TO SUPPLY DIGITAL OUTPUTS (BOTH DATA AND CLOCKS) Try to minimize the trace length that the digital outputs have to drive. Longer traces have higher capacitance, which requires more current, which causes more internal digital noise. Shorter traces reduce the possibility of reflections. Adding a 30 Ω to 50 Ω series resistor can suppress reflections, reduce EMI, and reduce the current spikes inside the ADV7184. If series resistors are used, place them as close as possible to the ADV7184 pins. However, try not to add vias or extra length to the output trace to make the resistors closer. If possible, limit the capacitance that each of the digital outputs drives to less than 15 pF. This can easily be accomplished by keeping traces short and by connecting the outputs to only one device. Loading the outputs with excessive capacitance increases the current transients inside the ADV7184, creating more digital noise on its power supplies. Figure 47. Recommended Power Supply Decoupling It is particularly important to maintain low noise and good stability of PVDD. Careful attention must be paid to regulation, filtering, and decoupling. It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups (AVDD, DVDD, DVDDIO, and PVDD). Some graphic controllers use substantially different levels of power when active (during active picture time) and when idle (during horizontal and vertical sync periods). This can result in a measurable change in the voltage supplied to the analog supply regulator, which can, in turn, produce changes in the regulated analog supply voltage. This can be mitigated by regulating the analog supply, or at least PVDD, from a different, cleaner power source, for example, from a 12 V supply. Rev. 0 | Page 105 of 108 ADV7184 DIGITAL INPUTS The digital inputs on the ADV7184 are designed to work with 3.3 V signals, and are not tolerant of 5 V signals. Extra components are needed if 5 V logic signals are required to be applied to the decoder. Use the following guidelines to ensure correct operation: • • • Use the correct, 28.63636 MHz, frequency crystal. Tolerance should be 50 ppm or better. User a parallel-resonant crystal. Know the Cload for the crystal part selected. The values of the C1 and C2 capacitors must be calculated using this Cload value. XTAL AND LOAD CAPACITOR VALUES SELECTION Figure 49 shows an example reference clock circuit for the ADV7184. Special care must be taken when using a crystal circuit to generate the reference clock for the ADV7184. Small variations in reference clock frequency may cause autodetection issues and impair the ADV7184 performance. XTAL 28.63636MHz To find C1 and C2, use the following formula: C = 2(Cload − Cstray) − Cpg where Cstray is usually 2 pF to 3 pF, depending on board traces, and Cpg (pin-to-ground capacitance) is 4 pF for the ADV7184. C1 = 47pF C2 = 47pF 05479-054 R = 1MΩ Example: Figure 49. Crystal Circuit Cload = 30 pF. C1 = 50 pF, C2 = 50 pF (in this case 47 pF is the nearest real-life cap value to 50 pF) Rev. 0 | Page 106 of 108 ADV7184 TYPICAL CIRCUIT CONNECTION An example of how to connect the ADV7184 video decoder is shown in Figure 50. For a detailed schematic diagram for the ADV7184, refer to the ADV7184 evaluation note, which can be obtained from a local ADI representative. DVDDIO (3.3V) FERRITE BEAD 33μF 10μF 0.1μF DGND 0.01μF POWER SUPPLY DECOUPLING FOR EACH POWER PIN DGND PVDD (1.8V) DGND DGND FERRITE BEAD 33μF 10μF 0.1μF AGND AGND DGND AVDD (3.3V) AGND AGND FERRITE BEAD 33μF 10μF 0.01μF POWER SUPPLY DECOUPLING FOR EACH POWER PIN AGND 0.1μF AGND DVDD (1.8V) 19Ω CVBS1 S-VIDEO Y C AGND AGND AGND FERRITE BEAD 33μF DGND 10μF DGND DVDDIO DVDD AVDD PVDD 0.01μF POWER SUPPLY DECOUPLING FOR EACH POWER PIN AGND 0.1μF DGND P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 0.01μF POWER SUPPLY DECOUPLING FOR EACH POWER PIN DGND FB 100nF AIN1 100nF AIN7 100nF AIN2 100nF AIN8 100nF AIN3 100nF AIN9 100nF AIN4 F_BLNK BLUE RED/C GREEN CVBS/Y 19Ω MULTIFORMAT PIXEL PORT P15–P8 8-BIT ITU-R BT.656 PIXEL DATA @ 27MHz P7–P0 Cb AND Cr 16-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz P15–P8 Y 16-BIT ITU-R BT.656 PIXEL DATA @ 13.5MHz ADV7184 Pr Pb Y 19Ω CVBS0 100nF AIN10 100nF AIN5 100nF AIN11 100nF AIN6 100nF 75Ω 56Ω 75Ω 75Ω 56Ω 75Ω 75Ω 75Ω 75Ω 75Ω 56Ω AIN12 LLC1 LLC2 27MHz OUTPUT CLOCK 13.5MHz OUTPUT CLOCK AGND 0.1μF 0.1μF + CAPY1 10μF 0.1μF 1nF CAPY2 OE OUTPUT ENABLE I/P AGND + AGND + 10μF 0.1μF 10μF + 0.1μF 28.6363MHz AGND 10μF 0.1μF 1nF CAPC1 CAPC2 CML REFOUT INT SFL HS VS FIELD INTERRUPT O/P SFL O/P HS O/P VS O/P FIELD O/P XTAL DVDDIO SELECT I2C ADDRESS DVSS DVDDIO 2kΩ MPU INTERFACE CONTROL LINES DVDDIO 2kΩ 100Ω SCLK 100Ω SDA DVDDIO 4.7kΩ RESET 100nF DGND AGND DGND RESET AGND DGND 1LOAD 47pF1 DGND 1MΩ XTAL1 47pF1 DGND ALSB PVDD ELPF 1.7kΩ 82nF 10nF CAP VALUES ARE DEPENDENT ON CRYSTAL ATTRIBUTES. Figure 50. Typical Connection Diagram Rev. 0 | Page 107 of 108 05479-053 ADV7184 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.60 MAX 80 1 PIN 1 16.20 16.00 SQ 15.80 61 60 TOP VIEW (PINS DOWN) 14.20 14.00 SQ 13.80 1.45 1.40 1.35 0.15 0.05 SEATING PLANE 0.20 0.09 7° 3.5° 0° 0.10 MAX COPLANARITY 20 21 40 41 VIEW A VIEW A ROTATED 90° CCW 0.65 BSC LEAD PITCH 0.38 0.32 0.22 COMPLIANT TO JEDEC STANDARDS MS-026-BEC Figure 51. 80-Lead Low Profile Quad Flat Package [LQFP] (ST-80-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADV7184BSTZ 2 EVAL-ADV7184EB 1 Temperature Range –40°C to +85°C Package Description Low Profile Quad Flat Package (LQFP) Evaluation Board Package Option ST-80-2 The ADV7184 is a Pb-free, environmentally friendly product. It is manufactured using the most up-to-date materials and processes. The coating on the leads of each device is 100% pure Sn electroplate. The device is suitable for Pb-free applications, and is able to withstand surface-mount soldering at up to 255°C (±5°C). In addition, it is backward-compatible with conventional SnPb soldering processes. This means that the electroplated Sn coating can be soldered with SnPb solder pastes at conventional reflow temperatures of 220°C to 235°C. 2 Z = Pb-free part. Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. © 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05479–0–7/05(0) Rev. 0 | Page 108 of 108