Low Power HDMI to LVDS Display Bridge
ADV7613
Data Sheet
FEATURES
Dedicated, flexible audio output port
Dolby® TrueHD DTS-HD Master Audio™
General
Internal EDID RAM
Integrated consumer electronics control (CEC) controller
Standard identification (STDI) circuit
Any to any, 3 × 3 color space conversion (CSC) matrix
100-ball, 9 mm × 9 mm CSP_BGA package
Qualified for automotive applications
Single-input HDMI receiver with dual channel LVDS
transmitter outputs
HDMI receiver support
148.5 MHz maximum TMDS clock frequency
High-bandwidth Digital Content Protection (HDCP) 1.4
support with internal HDCP keys
Adaptive HDMI equalizer
5 V detect and hot plug assert for HDMI port
Extended colorimetry, including sYCC601, Adobe RGB,
Adobe YCC 601, xvYCC extended gamut color
LVDS transmitters
Dual channel 24-bit OpenLDI interface
Supports 6-bit and 8-bit nonbalanced OpenLDI or 8-bit
video electronics standards association (VESA) formats
Audio support including high bit rate (HBR) and Direct
Stream Digital (DSD)
S/PDIF (IEC 60958-compatible) digital audio support
APPLICATIONS
Projectors
Automotive infotainment headunits
Automotive infotainment displays
Digital signage
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
CLOCK
DIGITAL
CLOCK
SYNTHESIS
PACKET
INFOFRAME
MEMORY
AUDIO
PACKET
PROCESSOR
AUDIO
INTERFACE
AUDIO
OUTPUT
INT
DDC
CABLE
EQUALIZER
EDID
CONTROL
HDMI
PROCESSOR
HDCP
KEYS
COMPONENT
PROCESSOR
HOST I/F
CONFIGURATION
AND CONTROL
OpenLDI
ENCODER
LVDS Tx
LVDS Tx
DUAL
LVDS Tx
OUTPUT
I2C SLAVE
RESET
13676-001
HDMI
Figure 1.
Rev. C
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ADV7613
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power Supply Recommendations ................................................. 11
Applications ....................................................................................... 1
Power-Up Sequence ................................................................... 11
Functional Block Diagram .............................................................. 1
Power-Down Sequence.............................................................. 11
Revision History ............................................................................... 2
Theory of Operation ...................................................................... 12
General Description ......................................................................... 3
HDMI Receiver........................................................................... 12
Detailed Functional Block Diagram .......................................... 3
HDCP Repeater Functionality ................................................. 12
Specifications..................................................................................... 4
Component Processor (CP) ...................................................... 12
Electrical Characteristics ............................................................. 4
LVDS Transmitter Features ....................................................... 12
LVDS Transmitter (OpenLDI Mapping) ................................... 5
I2C Interface ................................................................................ 12
Data and I2C Timing Characteristics ......................................... 5
Other Features ............................................................................ 12
Absolute Maximum Ratings............................................................ 7
Audio Output Data .................................................................... 12
Thermal Resistance ...................................................................... 7
Outline Dimensions ....................................................................... 13
ESD Caution .................................................................................. 7
Ordering Guide .......................................................................... 13
Pin Configuration and Function Descriptions ............................. 8
Automotive Products ................................................................. 13
REVISION HISTORY
9/2018—Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 13
5/2017—Rev. A to Rev. B
Changes to LVDS Transmitter Features Section ........................ 12
Changes to Ordering Guide .......................................................... 13
12/2015—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 13
10/2015—Revision 0: Initial Version
Rev. C | Page 2 of 13
Data Sheet
ADV7613
GENERAL DESCRIPTION
The ADV7613 is a high quality, low power, single-input HDMI
to LVDS display bridge. It incorporates an HDMI capable
receiver that supports up to 1080p, 60 Hz.
STDI detection block, free run, and synchronization alignment
controls.
The LVDS encoder can package data into 6-bit or 8-bit non-dc
balanced OpenLDI mapping or 8-bit VESA mapping. The
ADV7613 can output 24-bit OpenLDI data via dual-channel
LVDS transmitters, up to a maximum resolution of 1080p,
60 Hz received at the input. The maximum output clock
supported by a single LVDS output port is 92 MHz.
The HDMI port has dedicated 5 V detect and hot plug assert
pins. The HDMI receiver also includes an integrated equalizer
that ensures the robust operation of the interface with long
cables.
The ADV7613 has an audio output port for the audio data
extracted from the HDMI stream. HDMI audio formats include
super audio CD (SACD) via Direct Stream Digital® (DSD) and
HBR. The HDMI receiver has an advanced mute controller that
prevents audible extraneous noise in the audio output.
The ADV7613 is offered in an automotive grade and a consumer grade. The operating temperature range is −40°C to
+85°C.
Fabricated in an advanced CMOS process, the ADV7613 is
provided in a 9 mm × 9 mm, 100-ball CSP_BGA, RoHScompliant package.
The ADV7613 contains a component processor (CP) that
processes the video signals from the HDMI receiver. It provides
features such as contrast, brightness and saturation adjustments,
DETAILED FUNCTIONAL BLOCK DIAGRAM
ADV7613
DPLL
RXA_5V
HPA_A
A
B
C
BACK‐END
COLOR SPACE
CONVERSION
CEC
CONTROLLER
DATA
PREPROCESSOR
AND COLOR SPACE
CONVERSION
5V DETECT AND
HPD CONTROLLER
HDMI
PROCESSOR
DDCA_SDA
DDCA_SCL
RXA_C±
RXA_0±
RXA_1±
RXA_2±
EDID REPEATER
CONTROLLER
LTX2_0+
LTX2_0–
LTX2_1+
LTX2_1–
LTX2_2+
LTX2_2–
LTX2_3+
LTX2_3–
LTX2_C+
LTX2_C–
INT
AP0
PACKET/INFOFRAME
MEMORY
HDCP
KEYS
PLL
EQUALIZER
INTERRUPT
CONTROLLER
SAMPLER
HDCP
ENGINE
PACKET
PROCESSOR
Figure 2. Detailed Functional Block Diagram
Rev. C | Page 3 of 13
AUDIO
PROCESSOR
AUDIO OUTPUT
FORMATTER
CEC
COMPONENT
PROCESSOR
CONTROL
INTERFACE
I2 C
CS
LVDS FORMATTER
SCL
SDA
AP1
AP2
AP3
AP4
AP5
SCLK
MCLKOUT
13676-002
XTALP
XTALN
LTX1_0+
LTX1_0–
LTX1_1+
LTX1_1–
LTX1_2+
LTX1_2–
LTX1_3+
LTX1_3–
LTX1_C+
LTX1_C–
ADV7613
Data Sheet
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
DVDD = 1.71 V to 1.89 V, DVDDIO = 3.135 V to 3.465 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to
1.89 V, LTX_VDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
DIGITAL INPUTS
Input High Voltage
Symbol
Test Conditions/Comments
Min
VIH
1.2
2
Input Low Voltage
VIL
Input Current
IIN
XTALN and XTALP pins
Other digital inputs
XTALN and XTALP pins
Other digital inputs
CS pin
XTALN and XTALP pins
Other digital inputs
Input Capacitance1
DIGITAL INPUTS (5 V TOLERANT)2
Input High Voltage
Input Low Voltage
Input Current
Input Leakage Current
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage
Current
Output Capacitance4
POWER REQUIREMENTS
Termination Power Supply
Digital Input/Output (I/O)
Power Supply
Digital Core Power Supply
Phase-Locked Loop (PLL)
Power Supply
Comparator Power Supply
LVDS Power Supply
CURRENT CONSUMPTION4
Configuration 1
Typ
Max
10
V
V
V
V
µA
µA
µA
pF
0.8
+80
+100
V
V
µA
µA
0.4
+100
V
V
µA
+10
20
µA
pF
0.4
0.8
+60
−60
±15
±10
CIN
Unit
DDCA_SCL, DDCA_SDA
VIH
VIL
IIN
IIN
VOH
VOL
ILEAK
2.6
−80
−100
RXA_5V
2.4
HPA_A3
−100
Other digital outputs
−10
COUT
TVDD
DVDDIO
3.135
3.135
3.3
3.3
3.465
3.465
V
V
DVDD
PVDD
1.71
1.71
1.8
1.8
1.89
1.89
V
V
CVDD
LTX_VDD
1.71
1.71
1.8
1.8
1.89
1.89
V
V
Pseudorandom test pattern; 1360 × 768p at 60 Hz input
resolution; 85 MHz pixel clock; 25°C operating temperature;
DVDD, PVDD, CVDD, and LTX_DVDD = 1.8 V; DVDDIO and
TVDD = 3.3 V; LVDS Port 2 used
Termination Power Supply
Digital I/O Power Supply
Digital Core Power Supply
PLL Power Supply
Comparator Power Supply
LVDS Power Supply
Configuration 2
ITVDD
IDVDDIO
IDVDD
IPVDD
ICVDD
ILTX_VDD
Termination Power Supply
Digital I/O Power Supply
Digital Core Power Supply
ITVDD
IDVDDIO
IDVDD
50
6
68
29
65
45
mA
mA
mA
mA
mA
mA
58
6
102
mA
mA
mA
Checker one-dot × one-dot test pattern; 1920 × 720p at
60 Hz input resolution; 92 MHz pixel clock; 25°C operating
temperature; DVDD, PVDD, CVDD, and LTX_DVDD = 1.8 V;
DVDDIO and TVDD = 3.3 V; LVDS Port 2 used
Rev. C | Page 4 of 13
Data Sheet
ADV7613
Parameter
PLL Power Supply
Comparator Power Supply
LVDS Power Supply
Configuration 3
Symbol
IPVDD
ICVDD
ILTX_VDD
Termination Power Supply
Digital I/O Power Supply
Digital Core Power Supply
PLL Power Supply
Comparator Power Supply
LVDS Power Supply
POWER-DOWN CURRENT⁴
Terminator Power Supply
Digital I/O Power Supply
Digital Core Power Supply
PLL Power Supply
Comparator Power Supply
LVDS Power Supply
ITVDD
IDVDDIO
IDVDD
IPVDD
ICVDD
ILTX_VDD
Test Conditions/Comments
Min
Typ
29
66
43
Max
Unit
mA
mA
mA
70
15
147
44
96
88
mA
mA
mA
mA
mA
mA
Pseudorandom test pattern; 1920 × 1080p at 60 Hz input
resolution; 148.5 MHz pixel clock; 85°C operating temperature;
DVDD, PVDD, CVDD, and LTX_DVDD = 1.89 V; DVDDIO and
TVDD = 3.465 V; LVDS Port 1 and LVDS Port 2 used
ITVDD_PD
IDVDDIO_PD
IDVDD_PD
IPVDD_PD
ICVDD_PD
ILTX_VDD_PD
327
387
102
223
74
323
µA
µA
µA
µA
µA
µA
Data characterized by evaluation.
The following pins are 5 V tolerant inputs: DDCA_SCL, DDCA_SDA, and RXA_5V.
3
The HPA_A pin is a 5 V tolerant output.
4
Data characterized by evaluation.
1
2
LVDS TRANSMITTER (OpenLDI MAPPING)
Table 2.
Parameter
OpenLDI OUTPUTS1
Differential Output Voltage
Offset Output Voltage
Change in VOD Mismatch
Change in VOS Mismatch
OpenLDI TRANSMITTER2
OpenLDI Output Rise Time
OpenLDI Output Fall Time
1
2
Symbol
Min
Typ
Max
Unit
VOD
VOS
247
1.125
350
1.2
454
1.375
50
50
mV
V
mV
mV
0.21 × UI
0.21 × UI
0.3 × UI
0.3 × UI
ps
ps
tR
tF
Measurement performed using a 100 Ω termination resistor.
Data characterized by evaluation, using a 100 Ω source termination resistor. UI is unit interval, that is, the bit width.
DATA AND I2C TIMING CHARACTERISTICS
Table 3.
Parameter
CLOCK AND CRYSTAL
Crystal (XTAL) Frequency
XTAL Frequency Stability
Input Clock Range (TMDS)
OpenLDI Output Clock Range
I2C PORTS
SCL Frequency
SCL Minimum Pulse Width High
SCL Minimum Pulse Width Low
Start Condition Hold Time
Symbol
Min
Typ
Max
Unit
±50
148.5
92
MHz
ppm
MHz
MHz
28.63636
25
25
400
t1
t2
t3
Rev. C | Page 5 of 13
600
1.3
600
kHz
ns
µs
ns
ADV7613
Data Sheet
Parameter
Start Condition Setup Time
SDA Setup Time
SCL and SDA Rise Time
SCL and SDA Fall Time
Stop Condition Setup Time
RESET FEATURE
Reset Pulse Width
Reset Pulse to First I2C Transaction
I2S PORT, MASTER MODE
SCLK Mark to Space Ratio
Left/Right Clock (LRCLK) Data Transition Time
Symbol
t4
t5
t6
t7
t8
Min
600
100
Max
0.6
Unit
ns
ns
ns
ns
µs
5
5
ms
ms
300
300
t15:t16
t17
t18
t19
t20
I2Sx1 Data Transition Time
Typ
45:55
55:45
10
10
5
5
% Duty Cycle
ns
ns
ns
ns
I Sx signals (where x = 0, 1, 2, or 3) are available on the AP1 to AP4 pins (see Table 6).
1 2
Timing Diagrams
t3
t3
t5
SDA
t1
t6
t2
t7
13676-003
SCL
t8
t4
Figure 3. I C Timing
2
t15
SCLK
t16
t17
LRCLK
t18
t19
I2 Sx
LEFT JUSTIFIED
MODE
MSB
MSB – 1
t20
I2 Sx
I2S MODE
t19
MSB
MSB – 1
t20
I2 Sx
RIGHT JUSTIFIED
MODE
t19
MSB
LSB
t20
13676-004
NOTES
1. THE LRCLK SIGNAL IS AVAILABLE ON THE AP5 PIN.
2. I2Sx SIGNALS (WHERE x = 0, 1, 2, OR 3) ARE AVAILABLE
ON THE FOLLOWING PINS:AP1, AP2, AP3, AND AP4.
Figure 4. I2S Timing
Rev. C | Page 6 of 13
Data Sheet
ADV7613
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter
DVDD to GND
PVDD to GND
DVDDIO to GND
CVDD to GND
TVDD to GND
LTX_VDD to GND
Digital Inputs to GND
5 V Tolerant Digital Inputs to
GND1
Digital Outputs to GND
XTALP, XTALN
SCL, SDA Data Pins to
DVDDIO
Maximum Junction
Temperature (TJ MAX)
Storage Temperature Range
Infrared Reflow Soldering
(20 sec)
Operating Temperature
Range
1
Rating
2.2 V
2.2 V
4.0 V
2.2 V
4.0 V
2.2 V
GND − 0.3 V to DVDDIO + 0.3 V
5.3 V
GND − 0.3 V to DVDDIO + 0.3 V
−0.3 V to PVDD + 0.3 V
DVDDIO − 0.3 V to DVDDIO + 3.6 V
125°C
To reduce power consumption when using the ADV7613, turn
off the unused sections of the device.
Due to printed circuit board (PCB) metal variation and,
therefore, variation in PCB heat conductivity, the value of θJA
may differ for various PCBs.
It is possible to obtain the most efficient measurement solution
by using the package surface temperature to estimate the die
temperature because this solution eliminates the variance
associated with the θJA value.
When using the device, the maximum junction temperature
(TJ MAX) must not go above 125°C. The following equation
calculates the junction temperature using the measured package
surface temperature and applies only when no heat sink is used
on the device under test (DUT):
TJ = TS + (ΨJT × WTOTAL).
−60°C to +150°C
260°C
−40°C to +85°C
The following inputs are 3.3 V inputs but are 5 V tolerant: DDCA_SCL and
DDCA_SDA.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
where:
TJ is the junction temperature.
TS is the package surface temperature (°C).
ΨJT = 0.81°C/W for the 100-ball CSP_BGA (based on a 2s2p test
board defined in the JEDEC specification).
WTOTAL = ((PVDD × IPVDD) + (0.2 × TVDD × ITVDD) +
(CVDD × ICVDD) + (DVDD × IDVDD) + (DVDDIO ×
IDVDDIO) + (LTX_VDD × ITLX_VDD)).
where 0.2 is 20% of the TVDD power that is dissipated on the
device itself.
ESD CAUTION
Rev. C | Page 7 of 13
ADV7613
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
A
GND
DDCA_SD A
DDCA_SCL
GND
XTALP
PVDD
RESET
SCL
AP5
GND
A
B
RXA_5V
HPA_A
CEC
GND
XTALN
CS
INT
SDA
AP4
AP3
B
C
RXA_C+
RXA_C–
CVDD
GND
GND
DVDD
TEST0
TEST1
AP2
AP1
C
D
RXA_0+
RXA_0–
CVDD
GND
GND
DVDD
TEST2
TEST3
MCLKOUT
SCLK
D
E
RXA_1+
RXA_1–
CVDD
GND
GND
DVDD
DVDD
TEST4
TEST5
AP0
E
F
RXA_2+
RXA_2–
TVDD
GND
GND
GND
DVDDIO
TEST6
TEST7
TEST8
F
G
CVDD
CVDD
TVDD
GND
GND
GND
DVDDIO
TEST9
TEST10
TEST11
G
H
LTX2_3–
LTX_VDD
LTX_VDD
GND
GND
LTX_VDD
LTX_VDD
TEST12
TEST13
LTX1_0–
H
J
LTX2_3+
LTX2_C–
LTX2_2–
LTX2_1–
LTX2_0–
LTX1_3–
LTX1_C–
LTX1_2–
LTX1_1–
LTX1_0+
J
K
GND
LTX2_C+
LTX2_2+
LTX2_1+
LTX2_0+
LTX1_3+
LTX1_C+
LTX1_2+
LTX1_1+
GND
K
1
2
3
4
5
6
7
8
9
10
13676-005
DATA LINES (INPUT AND OUTPUT)
POWER SUPPLIES
GND
TEST PINS
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No
A1, A4, A10, B4, C4, C5, D4,
D5, E4, E5, F4 to F6, G4 to
G6, H4, H5, K1, K10
A2
A3
A5
Mnemonic
GND
Type
Ground
Description
Ground.
DDCA_SDA
DDCA_SCL
XTALP
A6
A7
PVDD
RESET
A8
SCL
HDCP Slave Serial Data for HDMI Port A.
HDCP Slave Serial Clock for HDMI Port A.
Input for 28.63636 MHz Crystal or an External 1.8 V, 28.63636 MHz Clock
Oscillator Source to Clock the ADV7613.
Digital PLL Supply Voltage (1.8 V).
System Reset Input, Active Low. A minimum low reset pulse width of 5
ms is required to reset the ADV7613 circuitry.
I2C Port Serial Clock Input. SCL is the clock line for the control port.
A9
AP5
HDMI Rx DDC
HDMI Rx DDC
Miscellaneous
analog
Power
Miscellaneous
digital
Miscellaneous
digital
Audio output
B1
RXA_5V
HDMI input
Audio Output Pin 5. This pin is configurable to output S/PDIF digital
audio, HBR or DSD. The AP5 pin typically provides the LRCLK signal for
the I2S modes.
5 V Detect Pin for HDMI Port A.
Rev. C | Page 8 of 13
Data Sheet
ADV7613
Pin No
B2
Mnemonic
HPA_A
Type
Miscellaneous
digital
Digital
input/output
Miscellaneous
analog
Miscellaneous
digital
B3
CEC
B5
XTALN
B6
CS
B7
INT
Miscellaneous
digital
B8
SDA
B9
AP4
Miscellaneous
digital
Audio output
B10
AP3
Audio output
C1
C2
C3, D3, E3, G1, G2
C6, D6, E6, E7
C7, C8, D7, D8, E8, E9, F8 to
F10, G8 to G10, H8, H9
C9
RXA_C+
RXA_C−
CVDD
DVDD
TEST0 to
TEST13
AP2
HDMI input
HDMI input
Power
Power
Miscellaneous
C10
AP1
Audio output
D1
D2
D9
RXA_0+
RXA_0−
MCLKOUT
HDMI input
HDMI input
Audio output
D10
E1
E2
E10
SCLK
RXA_1+
RXA_1−
AP0
Audio output
HDMI input
HDMI input
Audio Output
F1
F2
F3, G3
F7, G7
H1
H2, H3, H6, H7
H10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K2
K3
RXA_2+
RXA_2−
TVDD
DVDDIO
LTX2_3−
LTX_VDD
LTX1_0−
LTX2_3+
LTX2_C−
LTX2_2−
LTX2_1−
LTX2_0−
LTX1_3−
LTX1_C−
LTX1_2−
LTX1_1−
LTX1_0+
LTX2_C+
LTX2_2+
HDMI input
HDMI input
Power
Power
LVDS output
Power
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
Audio output
Description
Hot Plug Assert. This pin can be configured to output the hot plug assert
signal for HDMI Port A.
Consumer Electronics Control Channel.
Crystal Output.
Chip Select. This pin must be set low for the ADV7613 to process I2C
messages. Pulling this line up causes the I2C state machine to ignore I2C
transmission.
Interrupt. This pin can be active low or active high, open drain or
transistor to transistor logic (TTL). The events that trigger an interrupt are
under user configuration.
I2C Port Serial Data Input/Output. SDA is the data line for the control port.
Audio Output 4. This pin is configurable to output S/PDIF digital audio,
HBR, or I2S.
Audio Output 3. This pin is configurable to output S/PDIF digital audio,
HBR, or I2S.
Digital Input Clock True of HDMI Port A.
Digital Input Clock Complement of HDMI Port A.
HDMI Analog Block Supply Voltage (1.8 V).
Digital Core Supply Voltage (1.8 V).
Test Pins. Connect these pins to ground via 1 kΩ resistors.
Audio Output 2. This pin is configurable to output S/PDIF digital audio,
HBR, DSD, or I2S mode.
Audio Output 1. This pin is configurable to output S/PDIF digital audio,
HBR, or DSD.
Digital Input Channel 0 True of HDMI Port A.
Digital Input Channel 0 Complement of HDMI Port A.
Master Clock. This pin is configurable to output the audio master clock
signal.
Serial Clock. This pin is configurable to output the audio serial clock.
Digital Input Channel 1 True of HDMI Port A.
Digital Input Channel 1 Complement HDMI Port A.
Audio Output 0. This pin is configurable to output S/PDIF digital audio,
HBR, DSD, or I2S.
Digital Input Channel 2 True of HDMI Port A.
Digital Input Channel 2 Complement of HDMI Port A.
Termination Supply Voltage (3.3 V).
Digital I/O Supply Voltage (3.3 V).
LVDS Output Channel 3 Complement of LVDS Output Port 2.
LVDS Supply Voltage (1.8 V).
LVDS Output Channel 0 Complement of LVDS Output Port 1.
LVDS Output Channel 3 True of LVDS Output Port 2.
LVDS Clock Complement of LVDS Output Port 2.
LVDS Output Channel 2 Complement of LVDS Output Port 2.
LVDS Output Channel 1 Complement of LVDS Output Port 2.
LVDS Output Channel 0 Complement of LVDS Output Port 2.
LVDS Output Channel 3 Complement of LVDS Output Port 1.
LVDS Clock Complement of LVDS Output Port 1.
LVDS Output Channel 2 Complement of LVDS Output Port 1.
LVDS Output Channel 1 Complement of LVDS Output Port 1.
LVDS Output Channel 0 True of LVDS Output Port 1.
LVDS Clock True of LVDS Output Port 2.
LVDS Output Channel 2 True of LVDS Output Port 2.
Rev. C | Page 9 of 13
ADV7613
Pin No
K4
K5
K6
K7
K8
K9
Data Sheet
Mnemonic
LTX2_1+
LTX2_0+
LTX1_3+
LTX1_C+
LTX1_2+
LTX1_1+
Type
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
LVDS output
Description
LVDS Output Channel 1 True of LVDS Output Port 2.
LVDS Output Channel 0 True of LVDS Output Port 2.
LVDS Output Channel 3 True of LVDS Output Port 1.
LVDS Clock True of LVDS Output Port 1.
LVDS Output Channel 2 True of LVDS Output Port 1.
LVDS Output Channel 1 True of LVDS Output Port 1.
Rev. C | Page 10 of 13
Data Sheet
ADV7613
POWER SUPPLY RECOMMENDATIONS
POWER-UP SEQUENCE
POWER-DOWN SEQUENCE
The recommended power-up sequence for the ADV7613 is to
power up the 3.3 V supplies first, followed by the 1.8 V supplies.
Hold the RESET line low for at least 5 ms after the supplies have
powered up. Allow a minimum additional 5 ms before carrying
out the first I2C transaction.
The ADV7613 power supplies can be deasserted simultaneously
as long as a higher rated supply (for example, TVDD/DVDDIO)
does not fall to a voltage level less than a lower rated supply (for
example, DVDD), and the absolute maximum ratings
specifications are followed.
Alternatively, power up the ADV7613 by asserting all supplies
simultaneously. In this case, take care while the supplies are
being established to ensure that a lower voltage supply does not
go above a higher voltage supply level. Hold the RESET line low
for at least 5 ms after the supplies have powered up. Allow a
minimum additional 5 ms before carrying out the first I2C
transaction.
1.8V
3.3V
SUPPLIES
1.8V
SUPPLIES
RESET
5ms
I2C
TRANSACTION
5ms
13676-006
POWER SUPPLY (V)
3.3V
Figure 6. Recommended Power-Up Sequence
Rev. C | Page 11 of 13
ADV7613
Data Sheet
THEORY OF OPERATION
HDMI RECEIVER
The HDMI receiver supports HDTV formats of up to 1080p.
The HDMI-compatible receiver on the ADV7613 allows active
equalization of the HDMI data signals. This equalization
compensates for the high frequency losses inherent in HDMI
and DVI cabling, especially at longer cable lengths and higher
frequencies. The HDMI-compatible receiver is capable of
equalizing for cable lengths up to 20 meters to achieve robust
receiver performance.
The HDMI receiver offers advanced audio functionality. The
receiver contains an audio mute controller that can detect a
variety of conditions that may result in audible extraneous noise
in the audio output. Upon detection of these conditions, the
audio signal can be ramped down or muted to prevent audio
clicks or pops. The HDMI receiver supports the reception of all
types of audio data described in the HDMI specifications,
including the following:
•
•
•
•
•
•
LPCM (uncompressed audio)
IEC 61937 (compressed audio)
DSD audio (1-bit audio)
HBR audio (high bit rate compressed audio)
Audio sample, HBR, DSD packet support
Support for EDID RAM
two LVDS transmitters up to a maximum input resolution of
1080p at 60 Hz.
The two LVDS output ports (Port 1 and Port 2) can drive two
identical LVDS display panels with video streams from a single
video data stream received by the HDMI receiver block.
In the dual LVDS transmitter mode of the ADV7613, the OpenLDI
encoder splits the single video stream received by the HDMI block
into two video streams; the odd video stream and the even video
stream. LVDS Output Port 1 outputs the even video stream and
LVDS Output Port 2 outputs the odd video stream.
When connected to the dual LVDS receiver panel, LVDS Output
Port 1 must be connected to the even LVDS receiver port of the
LVDS panel. LVDS Output Port 2 must be connected to the odd
receiver port of the LVDS panel.
In the single LVDS transmitter mode, the video is output on
either LVDS Output Port 1 or LVDS Output Port 2.
The maximum video resolution supported by a single LVDS
output port must have a clock frequency of 92 MHz or less.
I2C INTERFACE
The ADV7613 supports a 2-wire serial (I2C-compatible)
interface.
OTHER FEATURES
There is no Deep Color support in the ADV7613.
Other features of the ADV7613 include the following:
HDCP REPEATER FUNCTIONALITY
•
•
With the inclusion of HDCP, displays can receive encrypted
video content. The HDMI interface of the ADV7613 allows
authentication of a video receiver, decryption of encoded data at
the receiver, and renewability of that authentication during
transmission, as specified by the HDCP 1.4 specification.
Programmable interrupt output pin, INT
Chip select, CS
AUDIO OUTPUT DATA
The audio output pins (AP0 to AP5) can output audio data in a
number of formats as described in Table 6.
COMPONENT PROCESSOR (CP)
Table 6. Description of Audio Formats Supported
The ADV7613 has two any to any, 3 × 3 color space conversion
(CSC) matrices. The first CSC block is located in front of the
CP section. The second CSC block is located at the back of the
CP section. Each CSC enables YCrCb to RGB and RGB to
YCrCb conversions.
Pin No.
E10
Mnemonic
AP0
I2S/SPDIF Interface
SPDIF0
C10
AP1
I2S0/SPDIF0
C9
AP2
I2S1/SPDIF1
B10
AP3
I2S2/SPDIF2
B9
AP4
I2S3/SPDIF3
A9
AP5
D9
MCLKOUT
D10
SCLK
LRCLK (left/right
channel clock
output)
Master clock output
(MCLK)
Bit or serial clock
output (SCLK)
CP features include
•
•
•
•
Support for 525p, 625p, 720p, 1080p, as well as some
graphics standard (WVGA, WXGA)
Manual adjustments including gain (contrast), offset
(brightness), hue, and saturation
Free run output mode that provides stable timing when no
video input is present
Standard identification enabled by the STDI block
LVDS TRANSMITTER FEATURES
The LVDS or OpenLDI encoder can package data into 6-bit or
8-bit non-dc balanced OpenLDI mapping, or 8-bit VESA
mapping. The ADV7613 can output 24-bit OpenLDI data over
Rev. C | Page 12 of 13
DSD Interface
DSD0A (first
DSD channel)
DSD0B (second
DSD channel)
DSD1A (third
DSD channel)
DSD1B (fourth
DSD channel)
DSD2A (fourth
DSD channel)
DSD2B (fifth
DSD channel)
Not applicable
Not applicable
Data Sheet
ADV7613
OUTLINE DIMENSIONS
A1 BALL
CORNER
9.10
9.00 SQ
8.90
A1 BALL
CORNER
10 9 8
7 6 5 4
3 2
1
A
B
C
7.20
BSC SQ
D
E
F
0.80
BSC
G
H
J
K
*1.400
DETAIL A
1.253
1.173
BOTTOM VIEW
0.90
REF
0.383
0.343
0.303
0.26
REF
SEATING
PLANE
DETAIL A
0.975
0.910
0.845
0.50
0.45
0.40
BALL DIAMETER
COPLANARITY
0.12
*COMPLIANT TO JEDEC STANDARDS MO-275-DDAB-1
WITH THE EXCEPTION OF THE PACKAGE HEIGHT
03-14-2013-A
TOP VIEW
Figure 7. 100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-100-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADV7613BBCZ
ADV7613BBCZ-RL
ADV7613WBBCZ
ADV7613WBBCZ-RL
ADV7613WBBCZ-P
ADV7613WBBCZ-P-RL
EVAL-ADV7613FEBZ
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
100-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board
Package Option
BC-100-4
BC-100-4
BC-100-4
BC-100-4
BC-100-4
BC-100-4
AUTOMOTIVE PRODUCTS
The ADV7613W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2015–2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13676-0-9/18(C)
Rev. C | Page 13 of 13
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