Intermediate Frequency Transmitter,
800 MHz to 4000 MHz
HMC8200LP5ME
Data Sheet
FUNCTIONAL BLOCK DIAGRAM
LO_N
VCC_IRM
VCC_ENV
ENV_P
28
26
25
29
27
SEN
LO_P
30
SDI
SCLK
HMC8200
31
SDO
1
APPLICATIONS
DVDD
2
RST
3
22
VCC_D2S
Point to point communications
Satellite communications
Wireless microwave backhaul systems
BB_IP
4
21
VVA_IN
SPI
24
ENV_N
23
D2S_OUT
BB_IN
5
20
VGA_VCTRL
VCC_DGA
6
19
VCC_VGA
BB_QN
7
BB_QP
8
LOG_RF 15
VCC_LOG 16
14
VCC_BG
SLPD_OUT 13
11
LOG_IF 12
DGA_S2_IN
9
TX_IFIN
DGA_S1_OUT
10
BAND
GAP
18
TX_OUT
17
VCC_AMP
PACKAGE
BASE
13868-001
High linearity: supports modulations to 1024 QAM
Tx IF range: 200 MHz to 700 MHz
Tx RF range: 800 MHz to 4000 MHz
Tx power control: 25 dB
SPI controlled interface
32-lead, 5 mm × 5 mm LFCSP package
32
FEATURES
Figure 1.
GENERAL DESCRIPTION
The HMC8200LP5ME is a highly integrated intermediate
frequency (IF) transmitter chip that converts the industry
standard 300 MHz to 400 MHz IF input signals to an 800 MHz to
4000 MHz single-ended radio frequency (RF) signal at its output.
The IF transmitter chip is housed in a compact 5 mm × 5 mm
LFCSP package and supports complex modulations up to
1024 QAM. The HMC8200LP5ME simultaneously reduces the
design complexity of traditional microwave radios while realizing
significant size and cost improvements.
Rev. D
With IF input power ranges from −31 dBm to +4 dBm, the
HMC8200LP5ME provides 35 dB of digital gain control in 1 dB
steps and an analog voltage gain amplifier (VGA) continuously
controls the transmitter output power from −20 dBm to +5 dBm.
The device also features three integrated power detectors. The
first detector (LOG_IF) can be utilized to monitor the IF input
power. The second detector (SLPD_OUT) is a square law power
detector that monitors the power entering the mixer. The third
power detector (LOG_RF) is used to monitor the output power,
which can be used for fine output power adjustment.
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Technical Support
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HMC8200LP5ME
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................6
Applications ....................................................................................... 1
Pin Configuration and Function Descriptions..............................7
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ..............................................8
General Description ......................................................................... 1
Theory of Operation ...................................................................... 18
Revision History ............................................................................... 2
Register Array Assignments and Serial Interface .................. 18
Specifications..................................................................................... 3
Register Descriptions ..................................................................... 20
Electrical Characteristics: 800 MHz to 1800 MHz RF
Frequency Range .......................................................................... 3
Register Array Assignments...................................................... 20
Electrical Characteristics: 1800 MHz to 2800 MHz RF
Frequency Range .......................................................................... 4
Electrical Characteristics: 2800 MHz to 4000 MHz RF
Frequency Range .......................................................................... 5
Evaluation Printed Circuit Board (PCB) ..................................... 23
Evaluation PCB Schematic ........................................................ 24
Outline Dimensions ....................................................................... 25
Ordering Guide .......................................................................... 25
Absolute Maximum Ratings ............................................................ 6
REVISION HISTORY
6/2017—Rev. C to Rev. D
Changes to Table 5 ............................................................................ 7
Changes to Read Example Section ............................................... 18
Changes to Figure 61 and Figure 62............................................. 19
2/2017—Rev. B to Rev. C
Changes to Figure 60 ...................................................................... 18
Updated Outline Dimensions ....................................................... 25
This Hittite Microwave Products data sheet has been reformatted
to meet the styles and standards of Analog Devices, Inc.
6/2016—v01.0216 to Rev. B
Updated Format .................................................................. Universal
Added Pin Configuration Diagram; Renumbered Sequentially ......7
Added Ordering Guide .................................................................. 22
Rev. D | Page 2 of 25
Data Sheet
HMC8200LP5ME
SPECIFICATIONS
TA = 25°C, IF frequency = 350 MHz, local oscillator (LO) input signal level = 0 dBm, RF input signal level = −31 dBm per tone, DGA
setting (dec) = 35 (maximum gain), VGA setting = 3.3 V (maximum gain), sideband select = lower sideband, unless otherwise noted.
ELECTRICAL CHARACTERISTICS: 800 MHz TO 1800 MHz RF FREQUENCY RANGE
Table 1.
Parameter
OPERATING CONDITIONS
LO Frequency Range
IF Frequency Range
IF INPUT INTERFACE
Input Impedance
Return Loss
LOG IF Power Detector1 dB Dynamic Range
LOG IF Power Detector Range
LOG IF Power Detector Slope
Square Log Power Detector Range
RF OUTPUT INTERFACE
Input Impedance
Return Loss
LOG Power Detector1 dB Dynamic Range
LOG Power Detector Range
LOG Power Detector Slope
LO INPUT INTERFACE
Input Impedance
Return Loss
DYNAMIC PERFORMANCE
Conversion Gain
Digital VGA Dynamic Range
Analog VGA Dynamic Range
Sideband Rejection1
Noise Figure
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (OP1dB)
LO to RF Rejection1
IF to RF Rejection
POWER SUPPLY
Supply Voltage
VCCx
VCC_VGA2
Supply Current
VCCx
VCC_VGA2
1
2
Min
Typ
300
200
Max
Unit
2300
700
MHz
MHz
50
20
50
−30
+10
37
17
7
50
13
50
37
Ω
dB
dB
dBm
mV/dB
50
12
Ω
dB
34
35
27
32
6
31
15
30
63
dB
dB
dB
dBc
dB
dBm
dBm
dBc
dBc
3.3
3.3
V
V
540
11
mA
μA
−25
7
30
30
23
28
28
11
56
Measurement was taken uncalibrated.
VCC_VGA can be adjusted from 3.3 V (maximum gain) to 0 V (minimum gain) to control the RF VGA.
Rev. D | Page 3 of 25
Ω
dB
dB
dBm
mV/dB
dB
+10
HMC8200LP5ME
Data Sheet
ELECTRICAL CHARACTERISTICS: 1800 MHz TO 2800 MHz RF FREQUENCY RANGE
Table 2.
Parameter
OPERATING CONDITIONS
LO Frequency Range
IF Frequency Range
IF INPUT INTERFACE
Input Impedance
Return Loss
LOG IF Power Detector1 dB Dynamic Range
LOG IF Power Detector Range
LOG IF Power Detector Slope
Square Log Power Detector Range
RF OUTPUT INTERFACE
Input Impedance
Return Loss
LOG Power Detector1 dB Dynamic Range
LOG Power Detector Range
LOG Power Detector Slope
LO INPUT INTERFACE
Input Impedance
Return Loss
DYNAMIC PERFORMANCE
Conversion Gain
Digital VGA Dynamic Range
Analog VGA Dynamic Range
Sideband Rejection1
Noise Figure
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (OP1dB)
LO to RF Rejection1
IF to RF Rejection
POWER SUPPLY
Supply Voltage
VCCx
VCC_VGA2
Supply Current
VCCx
VCC_VGA2
1
2
Min
Typ
1300
200
Max
Unit
3300
700
MHz
MHz
50
20
50
−30
+10
37
17
12
50
15
50
37
Ω
dB
dB
dBm
mV/dB
50
15
Ω
dB
32
35
26
32
5.5
28
15
34
58
dB
dB
dB
dBc
dB
dBm
dBm
dBc
dBc
3.3
3.3
V
V
540
11
mA
μA
−25
8
28
30
22
28
25
10
55
Measurement was taken uncalibrated.
VCC_VGA can be adjusted from 3.3 V (maximum gain) to 0 V (minimum gain) to control the RF VGA.
Rev. D | Page 4 of 25
Ω
dB
dB
dBm
mV/dB
dB
+10
Data Sheet
HMC8200LP5ME
ELECTRICAL CHARACTERISTICS: 2800 MHz TO 4000 MHz RF FREQUENCY RANGE
Table 3.
Parameter
OPERATING CONDITIONS
LO Frequency Range
IF Frequency Range
IF INPUT INTERFACE
Input Impedance
Return Loss
LOG IF Power Detector1 dB Dynamic Range
LOG IF Power Detector Range
LOG IF Power Detector Slope
Square Log Power Detector Range
RF OUTPUT INTERFACE
Input Impedance
Return Loss
LOG Power Detector1 dB Dynamic Range
LOG Power Detector Range
LOG Power Detector Slope
LO INPUT INTERFACE
Input Impedance
Return Loss
DYNAMIC PERFORMANCE
Conversion Gain
Digital VGA Dynamic Range
Analog VGA Dynamic Range
Sideband Rejection1
Noise Figure
Output Third-Order Intercept (OIP3)
Output 1 dB Compression Point (OP1dB)
LO to RF Rejection1
IF to RF Rejection
POWER SUPPLY
Supply Voltage
VCCx
VCC_VGA2
Supply Current
VCCx
VCC_VGA2
1
2
Min
Typ
2300
200
Max
Unit
4500
700
MHz
MHz
50
20
50
−30
+10
37
17
15
50
23
50
37
Ω
dB
dB
dBm
mV/dB
50
17
Ω
dB
30
35
25
30
5.5
26
14
32
55
dB
dB
dB
dBc
dB
dBm
dBm
dBc
dBc
3.3
3.3
V
V
540
11
mA
μA
−25
12
22
30
20
22
20
7
50
Measurement was taken uncalibrated.
VCC_VGA can be adjusted from 3.3 V (maximum gain) to 0 V (minimum gain) to control the RF VGA.
Rev. D | Page 5 of 25
Ω
dB
dB
dBm
mV/dB
dB
+10
HMC8200LP5ME
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter
IF Input
LO Input
VCCx
Digital Input/Output
Maximum Junction Temperature to
Maintain 1 Million Hour MTTF
Thermal Resistance (RTH), Junction to
Ground Paddle
Temperature
Operating
Storage
Maximum Peak Reflow Temperature
(MSL3)
ESD Sensitivity (Human Body Model)
Rating
10 dBm
10 dBm
−0.5 V to +5.5 V
−0.3 V to +3.6 V
150°C
11°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
−40°C to +85°C
−65°C to +150°C
260°C
2000 V (Class 2)
Rev. D | Page 6 of 25
Data Sheet
HMC8200LP5ME
32
31
30
29
28
27
26
25
SDI
SCLK
SEN
LO_P
LO_N
VCC_IRM
VCC_ENV
ENV_P
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
HMC8200
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
ENV_N
D2S_OUT
VCC_D2S
VVA_IN
VGA_VCTRL
VCC_VGA
TX_OUT
VCC_AMP
NOTES
1. CONNECT EXPOSED GROUND PADDLE TO RF/DC GROUND.
13868-100
TX_IFIN
DGA_S1_OUT
DGA_S2_IN
LOG_IF
SLPD_OUT
VCC_BG
LOG_RF
VCC_LOG
9
10
11
12
13
14
15
16
SDO
DVDD
RST
BB_IP
BB_IN
VCC_DGA
BB_QN
BB_QP
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4, 5
6
Mnemonic
SDO
DVDD
RST
BB_IP, BB_IN
VCC_DGA
7, 8
9
10
BB_QN, BB_QP
TX_IFIN
DGA_S1_OUT
11
12
13
14
DGA_S2_IN
LOG_IF
SLPD_OUT
VCC_BG
15
16
17
18
19
20
21
22
23
24, 25
26
27
28, 29
30
31
32
LOG_RF
VCC_LOG
VCC_AMP
TX_OUT
VCC_VGA
VGA_VCTRL
VVA_IN
VCC_D2S
D2S_OUT
ENV_N, ENV_P
VCC_ENV
VCC_IRM
LO_N, LO_P
SEN
SCLK
SDI
EPAD
Description
SPI Serial Data Output.
SPI Digital Supply (3.3 VDC). Refer to Figure 64 for the required external components.
SPI Reset. Connect to logic high for normal operation.
Positive and Negative Filter Baseband IF I Inputs.
Power Supply for the Digital Variable Gain Amplifier (3.3 VDC). Refer to Figure 64 for the required external
components.
Negative and Positive Filter Baseband IF Q Inputs.
Transmit (Tx) IF Input, Intermediate Frequency Input Port. This pin is matched to 50 Ω.
Power Supply for the First Stage Digital Gain Amplifier (3.3 VDC). This pin is matched to 50 Ω. Refer to Figure 64
for the required external components.
Second Stage Digital Gain Amplifier Input.
IF Log Detector Output.
Square Law Detector Output.
Band Gap Supply. Power Supply Voltage for the Bias Controller (3.3 VDC). Refer to Figure 64 for the required
external components.
RF Log Detector Output.
RF Log Detector Supply (3.3 VDC). Refer to Figure 64 for the required external components.
Power Supply for the RF Output Amplifier (3.3 VDC). Refer to Figure 64 for the required external components.
Tx Chip Output.
Power Supply for the Variable Gain Amplifier (3.3 VDC). Refer to Figure 64 for the required external components.
VGA Control Voltage. Refer to Figure 64 for the required external components.
VVA Intermediate Frequency Input Port. This pin is matched to 50 Ω.
Differential to Single Amplifier Supply. Refer to Figure 64 for the required external components.
Differential to Single Amplifier Intermediate Frequency Output Port. This pin is matched to 50 Ω.
Envelope Detector Outputs.
Envelope Detector Supply (3.3 VDC). Refer to Figure 64 for the required external components.
Power Supply for the Mixer Output (3.3 VDC). Refer to Figure 64 for the required external components.
Local Oscillator Inputs. These pins are ac-coupled and matched to 50 Ω.
SPI Serial Enable.
SPI Clock Digital Input.
SPI Serial Data Input.
Exposed Pad. Connect exposed ground paddle to RF/dc ground.
Rev. D | Page 7 of 25
HMC8200LP5ME
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
50
DGAMIN,
DGAMIN,
DGAMIN,
TA = +85°C
TA = +25°C
TA = –40°C
TA = +85°C
TA = +25°C
TA = –40°C
40
CONVERSION GAIN (dB)
30
20
10
0
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
Figure 6. Conversion Gain vs. RF Frequency
over Temperature, Upper Sideband
90
+85°C
+25°C
–40°C
80
35
SIDEBAND REJECTION (dBc)
30
25
20
15
10
5
70
60
50
40
30
20
10
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
0
0.8
13868-003
1.2
Figure 4. Sideband Rejection vs. RF Frequency over Temperature, Lower
Sideband
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
13868-006
SIDEBAND REJECTION (dBc)
TA = +85°C
TA = +25°C
TA = –40°C
RF FREQUENCY (GHz)
+85°C
+25°C
–40°C
40
Figure 7. Sideband Rejection vs. RF Frequency over Temperature, Upper
Sideband
40
40
+85°C
+25°C
–40°C
35
30
25
25
IP3 (dBm)
30
20
20
15
15
10
10
5
5
1.2
1.6
2.0
2.4
2.8
RF FREQUENCY (GHz)
3.2
3.6
+85°C
+25°C
–40°C
35
4.0
0
0.8
13868-004
IP3 (dBm)
DGAMIN,
DGAMIN,
DGAMIN,
0
–20
0.8
45
0
0.8
TA = +85°C
TA = +25°C
TA = –40°C
10
Figure 3. Conversion Gain vs. RF Frequency
over Temperature, Lower Sideband
0
0.8
DGAMAX,
DGAMAX,
DGAMAX,
–10
13868-002
–20
0.8
20
13868-005
–10
30
Figure 5. Output IP3 vs. RF Frequency over Temperature, Lower Sideband
1.2
1.6
2.0
2.4
2.8
RF FREQUENCY (GHz)
3.2
3.6
4.0
13868-007
CONVERSION GAIN (dB)
40
50
DGAMAX,
DGAMAX,
DGAMAX,
Figure 8. Output IP3 vs. RF Frequency over Temperature, Upper Sideband
Rev. D | Page 8 of 25
Data Sheet
HMC8200LP5ME
0
0
–10
–15
–20
–20
–25
–25
IM3 (dBc)
–15
–30
–35
–40
–45
–50
–50
–55
–55
–60
–60
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
–65
0.8
2.0
2.4
2.8
3.2
3.6
4.0
20
16
14
14
P1dB (dBm)
16
12
10
8
12
10
8
6
6
4
4
2
2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
0
0.8
13868-009
1.2
+85°C
+25°C
–40°C
18
Figure 10. Output P1dB vs. RF Frequency over Temperature, Lower Sideband
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
13868-012
+85°C
+25°C
–40°C
18
Figure 13. Output P1dB vs. RF Frequency over Temperature, Upper Sideband
16
16
+85°C
+25°C
–40°C
14
+85°C
+25°C
–40°C
14
12
8
6
10
8
6
4
4
2
2
1.6
2.0
2.4
2.8
RF FREQUENCY (GHz)
3.2
3.6
4.0
0
0.8
13868-010
1.2
Figure 11. Noise Figure vs. RF Frequency over Temperature, Lower Sideband
1.2
1.6
2.0
2.4
2.8
RF FREQUENCY (GHz)
3.2
3.6
4.0
13868-013
NOISE FIGURE (dB)
12
10
0
0.8
1.6
Figure 12. IM3 vs. RF Frequency over Temperature, Upper Sideband
20
0
0.8
1.2
RF FREQUENCY (GHz)
Figure 9. IM3 vs. RF Frequency over Temperature, Lower Sideband
P1dB (dBm)
–35
–45
–65
0.8
NOISE FIGURE (dB)
–30
–40
13868-008
IM3 (dBc)
–10
+85°C
+25°C
–40°C
–5
13868-011
+85°C
+25°C
–40°C
–5
Figure 14. Noise Figure vs. RF Frequency over Temperature, Upper Sideband
Rev. D | Page 9 of 25
Data Sheet
45
40
40
35
35
30
25
20
15
10
5
0
0.8
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
1.2
1.6
30
25
20
15
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
10
5
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
0
0.8
Figure 15. Conversion Gain vs. RF Frequency at Various LO Powers
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
13868-017
SIDEBAND REJECTION (dBc)
45
13868-014
CONVERSION GAIN (dB)
HMC8200LP5ME
Figure 18. Sideband Rejection vs. RF Frequency at Various LO Powers
40
0
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
–5
35
–10
–15
30
–20
IM3 (dBc)
IP3 (dBm)
25
20
–25
–30
–35
–40
15
–45
1.2
1.6
–55
–60
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
–65
0.8
2.8
3.2
3.6
4.0
40
CONVERSION GAIN (dB)
35
8
6
4
30
25
20
15
2.95V
3.13V
3.30V
3.46V
3.63V
10
2
5
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
13868-016
NOISE FIGURE (dB)
2.4
45
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
10
0
0.8
2.0
Figure 19. IM3 vs. RF Frequency at Various LO Powers
16
12
1.6
RF FREQUENCY (GHz)
Figure 16. Output IP3 vs. RF Frequency at Various LO Powers
14
1.2
13868-018
0
0.8
–50
Figure 17. Noise Figure vs. RF Frequency at Various LO Powers
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
Figure 20. Conversion Gain vs. RF Frequency at Various VCCx
Rev. D | Page 10 of 25
13868-019
5
–4dBm
–2dBm
0dBm
+2dBm
+4dBm
13868-015
10
Data Sheet
HMC8200LP5ME
40
0
35
–5
+85°C
+25°C
–40°C
RETURN LOSS (dB)
30
20
15
0
0.8
1.2
1.6
–20
–30
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
–35
0.8
13868-020
5
–15
–25
2.95V
3.13V
3.30V
3.46V
3.63V
10
–10
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
Figure 21. Output IP3 vs. RF Frequency at Various VCCx
13868-023
IP3 (dBm)
25
Figure 24. RF Return Loss vs. RF Frequency over Temperature
45
0
+85°C
+25°C
–40°C
40
RETURN LOSS (dB)
30
25
20
15
2.95V
3.13V
3.30V
3.46V
3.63V
5
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
–15
–20
–25
4.0
RF FREQUENCY (GHz)
–30
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
IF FREQUENCY (GHz)
Figure 25. IF Return Loss vs. RF Frequency over Temperature
Figure 22. Sideband Rejection vs. RF Frequency at Various VCCx
80
0
2.95V
3.13V
3.30V
3.46V
3.63V
–5
–10
–15
70
60
REJECTION (dBc)
–20
–25
–30
–35
–40
–45
50
40
30
20
–50
–55
10
–65
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
RF FREQUENCY (GHz)
4.0
0
0.8
1.2
1.6
2.0
2.4
2.8
3.2
3.6
RF FREQUENCY (GHz)
Figure 26. IF to RF Rejection vs. RF Frequency at 25°C
Figure 23. IM3 vs. RF Frequency at Various VCCx
Rev. D | Page 11 of 25
4.0
13868-025
–60
13868-022
IM3 (dBc)
–10
13868-024
10
13868-021
SIDEBAND REJECTION (dBc)
–5
35
HMC8200LP5ME
Data Sheet
0
40
+85°C
+25°C
–40°C
35
30
–10
–15
–20
25
20
15
10
5
0
–5
DGA = 0
DGA = 5
DGA = 10
DGA = 15
–10
–15
0.9
1.5
2.1
2.7
3.3
3.9
4.5
LO FREQUENCY (GHz)
–20
0.8
13868-026
Figure 27. LO Return Loss vs. RF Frequency over Temperature
1.6
2.0
2.4
2.8
3.2
3.6
Figure 30. Conversion Gain vs. RF Frequency over DGA Word, Measurement
Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA
40
+85°C
+25°C
–40°C
50
35
CONVERSION GAIN (dB)
30
40
30
20
25
20
15
10
5
0
10
+85°C
+25°C
–40°C
–5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
LO FREQUENCY (GHz)
–10
13868-027
0
0.5
Figure 28. LO to RF Rejection vs. LO Frequency over Temperature,
Measurement Uncalibrated for LO Leakage
0
5
10
15
20
25
30
35
DGA (Word)
Figure 31. Conversion Gain vs. DGA Word over Temperature, Measurement
Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA, RF = 2 GHz
70
1.5
+85°C
+25°C
–40°C
0.8GHz
1.0GHz
2.0GHz
3.0GHz
4.0GHz
1.4
DGA CONVERSION GAIN STEP (dB)
60
50
REJECTION (dBc)
4.0
RF FREQUENCY (GHz)
60
REJECTION (dBc)
1.2
13868-030
–25
0.3
DGA = 20
DGA = 25
DGA = 30
DGA = 35
13868-029
CONVERSION GAIN (dB)
RETURN LOSS (dB)
–5
40
30
20
10
1.3
1.2
1.1
1.0
0.9
0.8
0.7
1.6
2.0
2.4
2.8
RF FREQUENCY (GHz)
3.2
3.6
4.0
Figure 29. IF to RF Rejection vs. RF Frequency over Temperature, Measured at
the Input of the External Low-Pass Filter After C55, see Figure 64
Rev. D | Page 12 of 25
0.5
0
5
10
15
20
25
30
35
DGA (Word)
Figure 32. Conversion Gain Step vs. DGA Word over RF Frequency
13868-031
1.2
13868-028
0.6
0
0.8
Data Sheet
HMC8200LP5ME
1.5
35
1.4
DGA CONVERSION GAIN STEP (dB)
40
25
20
15
10
5
0
+85°C
+25°C
–40°C
5
10
15
20
25
30
35
DGA (Word)
0.9
0.8
0.7
0
5
15
10
30
25
20
35
DGA (Word)
Figure 36. Conversion Gain Step vs. DGA Word over Temperature,
RF = 2 GHz
40
35
35
30
25
30
DGA = 35
25
DGA = 30
20
20
15
15
IP3 (dBm)
10
5
DGA = 25
10
DGA = 20
5
DGA = 15
0
0
–5
–5
–10
DGA = 10
DGA = 5
–15
–10
–20
+85°C
+25°C
–40°C
–20
0
5
10
15
20
25
30
DGA = 0
–25
35
DGA (Word)
–30
0.8
13868-033
–15
Figure 34. Conversion Gain vs. DGA Word over Temperature, RF = 4 GHz,
Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
13868-036
CONVERSION GAIN (dB)
1.0
0.5
Figure 33. Conversion Gain vs. DGA Word over Temperature, RF = 1 GHz,
Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA
Figure 37. Output IP3 vs. RF Frequency over DGA Word, Measurement
Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA
1.5
40
+85°C
+25°C
–40°C
1.4
35
30
1.3
25
1.2
20
15
1.1
IP3 (dBm)
DGA CONVERSION GAIN STEP (dB)
1.1
13868-035
–10
0
1.2
0.6
13868-032
–5
1.3
1.0
0.9
10
5
0
–5
0.8
–10
0.7
–15
–20
0.6
+85°C
+25°C
–40°C
–25
0
5
10
15
20
DGA (Word)
25
30
35
–30
13868-034
0.5
Figure 35. Conversion Gain Step vs. DGA Word over Temperature, RF =
1 GHz, Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on
RF VGA
0
5
10
15
20
DGA (Word)
25
30
35
13868-037
CONVERSION GAIN (dB)
30
+85°C
+25°C
–40°C
Figure 38. Output IP3 vs. DGA Word over Temperature, RF = 2 GHz,
Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA
Rev. D | Page 13 of 25
HMC8200LP5ME
Data Sheet
0
1.5
+85°C
+25°C
–40°C
–15
1.3
DGA = 20
DGA = 25
DGA = 30
DGA = 35
–20
1.2
–25
1.1
1.0
0.9
–30
–35
–40
–35
–50
0.8
–55
–60
0.7
–65
0.6
5
10
15
20
25
30
35
DGA (Word)
–75
0.8
13868-038
0
Figure 39. Conversion Gain Step vs. DGA Word over Temperature, RF = 4 GHz
1.2
1.6
2.0
2.4
2.8
3.2
4.0
Figure 42. IM3 vs. RF Frequency over DGA Word, Measurement Conducted
with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA
40
0
35
–5
30
–10
25
–15
+85°C
+25°C
–40°C
–20
20
–25
IM3 (dBc)
15
10
5
0
–30
–35
–40
–35
–5
–50
–10
–55
–15
–60
+85°C
+25°C
–40°C
–65
–70
–30
0
5
10
15
20
25
30
35
DGA (Word)
–75
13868-039
–25
Figure 40. Output IP3 vs. DGA Word over Temperature, RF = 1 GHz,
Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA
0
5
10
15
20
25
30
35
DGA (Word)
13868-042
–20
Figure 43. IM3 vs. DGA Word over Temperature, RF = 2 GHz, Measurement
Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA
40
55
35
50
DGA = 0
DGA = 9
DGA = 18
DGA = 27
DGA = 35
30
45
25
20
NOISE FIGURE (dB)
40
15
10
5
0
–5
–10
35
30
25
20
15
–15
–20
10
+85°C
+25°C
–40°C
–30
5
–35
0
5
10
15
20
DGA (Word)
25
30
35
0
0.8
13868-040
–25
Figure 41. Output IP3 vs. DGA Word over Temperature, RF = 4 GHz,
Measurement Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA
1.2
1.6
2.0
2.4
2.8
RF FREQUENCY (GHz)
3.2
3.6
4.0
13868-043
IP3 (dBm)
3.6
RF FREQUENCY (GHz)
13868-041
–70
0.5
IP3 (dBm)
DGA = 0
DGA = 5
DGA = 10
DGA = 15
–10
IM3 (dBm)
DGA CONVERSION GAIN STEP (dB)
1.4
–5
Figure 44. Noise Figure vs. RF Frequency over DGA Word at VCC_VGA = 3.3 V
Rev. D | Page 14 of 25
Data Sheet
HMC8200LP5ME
55
0
–5
50
+85°C
+25°C
–40°C
–10
–15
45
–20
IM3 (dBc)
–30
–35
–40
–35
–50
35
30
25
20
–55
15
–60
10
–65
0
5
10
20
15
25
30
35
DGA (Word)
0
0.8
13868-044
–75
Figure 45. IM3 vs. DGA Word over Temperature, RF = 1 GHz, Measurement
Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA
1.2
1.6
2.0
2.4
2.8
3.2
3.6
4.0
RF FREQUENCY (GHz)
Figure 48. Noise Figure vs. RF Frequency over DGA Word at VCC_VGA = 0 V
0.050
0
–5
0.045
–15
IF LOG OUT SENSITIVITY (V/dB)
+85°C
+25°C
–40°C
–10
–20
–25
IM3 (dBc)
DGA = 27
DGA = 35
DGA = 0
DGA = 9
DGA = 18
5
–70
13868-047
NOISE FIGURE (dB)
40
–25
–30
–35
–40
–35
–50
–55
–60
–65
0.040
0.035
0.030
0.025
RF
RF
RF
RF
RF
RF
RF
RF
RF
0.020
0.015
0.010
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
0.005
0
5
10
15
20
25
30
35
DGA (Word)
0
–50
13868-045
–75
Figure 46. IM3 vs. DGA Word over Temperature, RF = 4 GHz, Measurement
Conducted with VCC_VGA = 3.3 V (Maximum Gain) on RF VGA
–36
–29
–15
–22
INPUT POWER (dBm)
Figure 49. Log IF Detector Sensitivity vs. Input Power over Temperature and
RF Frequency
2.8
55
DGA = 0
DGA = 9
DGA = 18
DGA = 27
DGA = 35
50
45
2.6
2.4
RF LOG OUT (V)
40
NOISE FIGURE (dB)
–43
13868-048
–70
35
30
25
20
0.8GHz
1GHz
2GHz
3GHz
4GHz
2.2
2.0
1.8
1.6
15
1.4
10
1.2
1.6
2.0
2.4
2.8
RF FREQUENCY (GHz)
3.2
3.6
4.0
13868-046
0
0.8
Figure 47. Noise Figure vs. RF Frequency over DGA Word at VCC_VGA = 1.5 V
Rev. D | Page 15 of 25
1.0
–30 –27 –24 –21 –18 –15 –12
–9
–6
–3
0
3
6
OUTPUT POWER (dBm)
Figure 50. Log RF Detector vs. Output Power over RF Frequency
13868-049
1.2
5
HMC8200LP5ME
Data Sheet
2.5
2.8
IF LOG OUT (V)
1.5
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
2.6
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
2.4
RF LOG OUT (V)
RF
RF
RF
RF
RF
RF
RF
RF
RF
2.0
1.0
+85°C
+25°C
–40°C
2.2
2.0
1.8
1.6
1.4
0.5
–35
–40
–30
–15
–20
–25
INPUT POWER (dBm)
Figure 51. Log IF Detector Output vs. Input Power over Temperature and RF
Frequency
1.0
–30 –27 –24 –21 –18 –15 –12
RF
RF
RF
RF
RF
RF
RF
RF
RF
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
= 1GHz AT
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
1.0
0.5
30
25
20
15
10
–29
–22
–15
0
0.5
1.0
1.5
2.0
2.5
3.0
CONTROL VOLTAGE (V)
13868-054
–36
13868-051
–43
Figure 52. Square Law Detector Output vs. Input Power over Temperature
and RF Frequency
Figure 55. Conversion Gain vs. VGA Control Voltage over RF Frequency,
Measurement Conducted with DGA = 35 (Maximum Gain) on IF DGA
2.8
40
2.6
35
+85°C
+25°C
–40°C
CONVERSION GAIN (dB)
RF LOG OUT (V)
6
5
INPUT POWER (dBm)
2.4
3
0.8GHz
1.0GHz
2.0GHz
3.0GHz
4.0GHz
35
1.5
0
–50
0
2.2
2.0
1.8
1.6
1.4
30
+85°C
+25°C
–40°C
25
20
15
10
5
1.2
–9
–6
OUTPUT POWER (dBm)
–3
0
3
6
0
0.5
13868-052
1.0
–30 –27 –24 –21 –18 –15 –12
Figure 53. Log RF Detector vs. Output Power over Temperature, RF = 0.8 GHz
1.0
1.5
2.0
CONTROL VOLTAGE (V)
2.5
3.0
13868-055
2.0
–3
40
CONVERSION GAIN (dB)
SLPD OUT (V)
2.5
–6
Figure 54. Log RF Detector vs. Output Power over Temperature, RF = 2 GHz
3.5
3.0
–9
OUTPUT POWER (dBm)
13868-053
–45
13868-050
1.2
0
–50
Figure 56. Conversion Gain vs. VGA Control Voltage over Temperature, RF =
2 GHz, Measurement Conducted with DGA = 35 (Maximum Gain) on IF DGA
Rev. D | Page 16 of 25
Data Sheet
HMC8200LP5ME
40
2.8
35
+85°C
+25°C
–40°C
2.2
2.0
1.8
1.6
1.4
–9
–6
–3
0
3
6
OUTPUT POWER (dBm)
Figure 57. Log RF Detector vs. Output Power over Temperature, RF = 4 GHz
20
15
10
+85°C
+25°C
–40°C
25
20
15
10
1.5
2.0
2.5
3.0
13868-057
5
CONTROL VOLTAGE (V)
1.5
2.0
2.5
3.0
Figure 59. Conversion Gain vs. VGA Control Voltage over Temperature, RF =
4 GHz, Measurement Conducted with DGA = 35 (Maximum Gain) on IF DGA
35
1.0
1.0
CONTROL VOLTAGE (V)
40
CONVERSION GAIN (dB)
25
0
0.5
13868-056
1.0
–30 –27 –24 –21 –18 –15 –12
0
0.5
+85°C
+25°C
–40°C
5
1.2
30
30
13868-058
RF LOG OUT (V)
2.4
CONVERSION GAIN (dB)
2.6
Figure 58. Conversion Gain vs. VGA Control Voltage over Temperature, RF =
1 GHz, Measurement Conducted with DGA = 35 (Maximum Gain) on IF DGA
Rev. D | Page 17 of 25
HMC8200LP5ME
Data Sheet
THEORY OF OPERATION
The single-ended input of the HMC8200LP5MEutilizes an input
digital gain amplifier (DGA) that is controlled via SPI, which feeds
the IF signals to an image reject mixer. At the input of the device
before the DGA, an intermediate log power detector can be used to
monitor input power levels into the device. A square law detector
follows the DGA to monitor the power entering the mixer. See the
Register Array Assignments and Serial Interface section for more
information regarding the DGA.
The baseband differential inputs of the HMC8200LP5ME feed
the intermediate frequency directly into the image reject mixer.
It is recommended that when using the single-ended input, do
not leave the baseband differential inputs connected. The local
oscillator port can either be driven single ended through LO_N
or differentially through the combination of LO_N and LO_P. If
Driving the local oscillator port differentially improves the LO
to RF rejection.
The IF is then converted to RF, which is followed by an amplifier.
Next, the amplified RF signal is fed off chip to a low-pass filter. The
external filter path feeds back into a variable gain amplifier (VGA)
that is voltage controlled. The output of the VGA drives a final
amplifier that is the output of the device. An RF log detector is
connected to the output of the final amplifier to monitor the output
power of the HMC8200LP5ME.
The HMC8200LP5ME utilizes an input low noise amplifier
(LNA) cascaded with a VGA, which can either be controlled by
the internal AGC or external voltages, that feeds the RF signals
to an image reject mixer. The local oscillator port can either be
driven single ended through LO_N or differentially through the
combination of LO_N and LO_P.
The radio frequency is then converted to intermediate
frequencies, which can either feed off chip via baseband
differential outputs or feed on chip into a programmable bandpass filter. It is recommended during IF mode operation that
the baseband outputs be unconnected.
The programmable band-pass filter on chip has four programmable bandwidths (14 MHz, 28 MHz, 56 MHz, and 112 MHz).
The programmable band-pass filter has the capability to adjust
the center frequency.
This calibration can be recalled via SPI control or the customer
can adjust the center frequency, but the calibration value must
be stored off chip (see the Register Array Assignments section).
An external filter option can be utilized to allow the customer
to select other filter bandwidths/responses that are not available
on chip. The external filter path coming from the image reject
mixer feeds into an amplifier that has differential outputs. The
output of the external filter can be fed back into the chip, which
is then connected to another amplifier.
A VGA follows immediately after the band-pass filter. Control
the IF VGA either by the AGC or external voltages. The output
of the variable gain amplifier is the output of the device.
REGISTER ARRAY ASSIGNMENTS AND SERIAL
INTERFACE
The register arrays for the HMC8200LP5ME are organized into
seven registers of 16 bits. Using the serial interface, the arrays
are written or read one row at a time, as shown in Figure 61 and
Figure 62. Figure 61 shows the sequence of signals on the enable
(SEN), CLK, and data (SDI) lines to write one 16-bit array of data
to a single register. The enable line goes low, the first of 24 data
bits is placed on the data line, and the data is sampled on the
rising edge of the clock. The data line should remain stable for
at least 2 ns after the rising edge of CLK. The device supports a
serial interface running up to 10 MHz, the interface is 3.3 V
CMOS logic.
A write operation requires 24 data bits and 24 clock pulses, as
shown in Figure 61. The 24 data bits contain the 3-bit chip
address, followed by the 5-bit register array number, and finally
the 16-bit register data. After the 24th clock pulses of the write
operation, the enable line returns high to load the register array
on the IC.
A read operation requires 24 data bits and 48 clock pulses, as
shown in Figure 62. For every register read operation, a write to
Register 7 is required first. The data written should contain the
3-bit chip address, followed by the 5-bit register number for
Register 7, and finally the 5-bit number of the register to be
read. The remaining 11 bits should be logic zeroes. When the
read operation is initiated, the data is available on the data
output (SDO) pin.
Read Example
If reading Register 2, write the following 24 bits to initiate the
read operation. The output data bits are placed on the data line
during the rising edge of the clock.
From the factory, a filter calibration is conducted and the center
frequency of the filter is set to 140 MHz.
00000000000 00010 00111 101
ZERO BITS (11 BITS)
REGISTER 7 ADDRESS (5 BITS)
REGISTER TO BE READ (5 BITS)
CHIP ADDRESS (3 BITS)
Figure 60. Sample Bits to Initiate Read
Rev. D | Page 18 of 25
13868-059
The HMC8200LP5ME is a highly integrated intermediate
frequency (IF) transceiver chip that converts intermediate
frequency to a single-ended radio frequency (RF) signal at its
output. The intermediate frequency (IF) can be supplied to the
HMC8200LP5ME singled ended or through the baseband
differential inputs.
Data Sheet
HMC8200LP5ME
24 CLOCK CYCLES
SEN
1
24
CLK
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
REGISTER
ADDRESS
LSB
MSB
MSB
WRITE DATA
CHIP
ADDRESS
13868-060
2
LSB
1
LSB
0
MSB
SDI
Figure 61. Timing Diagram, SPI Register Write
24 CLOCK CYCLES
SEN
24 CLOCK CYCLES
1
24
1
24
CLK
0 1 2 3 4 5 6 7 8 9 1011121314151617181920212223
READ DATA
MSB
LSB
LSB
MSB
LSB
MSB
CHIP
READ
REGISTER
REG 7 ADDRESS
ADDRESS ADDRESS
LSB
MSB
MSB
ALL ZEROS
Figure 62. Timing Diagram, SPI Register Read
Rev. D | Page 19 of 25
13868-061
0 1 2 3 4 5 6 7 8 9 101112131415
SDO
LSB
SDI
HMC8200LP5ME
Data Sheet
REGISTER DESCRIPTIONS
REGISTER ARRAY ASSIGNMENTS
In the Access columns (Table 6 through Table 12), R means read, W means write, and R/W means read/write.
Enable Bits
Table 6. Enable Register, (Address 0x01)
Bit No.
[15:13]
12
Bit Name
Reserved
LOG_IF_EN
11
D2SE_EN
10
9
Factory diagnostics
CM_BUFFER_EN
8
7
Factory Diagnostics
LOG_DET_EN
6
MS_EN
5
ENVELOPE_EN
4
VGA_EN
3
IRM_EN
2
IRM_IQ_EN
1
DGA_EN
0
LPF_EN
Description
Not used
Log intermediate frequency (IF) detector enable
0 = disable
1 = enable
Differential to single (after mixer) enable
0 = disable
1 = enable
0 = Logic 0 for normal operation
Common-mode buffer enable
0 = disable
1 = enable
1 = Logic 1 for normal operation
Log detector enable
0 = disable
1 = enable
Square detector enable
0 = disable
1 = enable
Envelope detector enable
0 = enable
1 = disable
Variable gain amplifier (VGA) enable
0 = disable
1 = enable
Image reject mixer enable
0 = disable
1 = enable
IQ line enable
0 = disable
1 = enable
Digital gain amplifier (DGA) enable
0 = disable
1 = enable
Low-pass filter enable
0 = disable
1 = enable
Rev. D | Page 20 of 25
Reset
0x6
0x1
Access
R/W
R/W
0x1
R/W
0x0
0x0
R/W
R/W
0x1
0x1
R/W
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x1
R/W
0x0
R/W
0x1
R/W
0x0
R/W
Data Sheet
HMC8200LP5ME
Digital Gain Amplifier: DGA Control
Table 7. Digital Gain Amplifier (Address 0x03)
Bit No.
15
[14:9]
Bit Name
Reserved
DGA_CTRL
[8:0]
Reserved
Description
Not used
Override SPI FIL2_FRQ_SET and use 8-bit word from OTP
0 = minimum gain
1=…
100011 = maximum gain
Not used
Reset
0x0
0x0
Access
R/W
R/W
0x0
R/W
Reset
0000111
11
11100
10
Access
R/W
R/W
R/W
R/W
Reset
0010
Access
1
R/W
01
R/W
0
0x0
R/W
R/W
Reset
1111000
0
0x0
Access
R/W
R/W
R/W
Digital Gain Amplifier: Amplifier Current, Envelope Level, and VGA Attenuation Bias
Table 8. Digital Gain Amplifier, (Address 0x04)
Bit No.
[15:9]
[8:7]
[6:2]
[1:0]
Bit Name
Reserved
AMP_CUR
ENV_LVL
VGA_ATT_BIAS
Description
Not used
Amplifier current
Envelope level
VGA attenuation bias
Image Reject Mixer: Sideband, and Polarity and Offset for I
Table 9. Image Reject Mixer Register, (Address 0x05)
Bit No.
[15:12]
Bit Name
Reserved
11
IRM_IS
[10:9]
Reserved
8
[7:0]
OFFSET_POLARITY_I
IRM_OFFSET_I
Description
Reserved
Logic 0010 for normal operation
Image sideband
0 = upper sideband
1 = lower sideband
Reserved
Logic 01 for normal operation
Offset Polarity I
Image reject mixer offset for I
Image Reject Mixer: Polarity and Offset for Q
Table 10. Image Reject Mixer Register, (Address 0x06)
Bit No.
[15:9]
8
[7:0]
Bit Name
Reserved
OFFSET_POLARITY_Q
IRM_OFFSET_Q
Description
Not used
Offset Polarity Q
Image reject mixer offset for Q
Rev. D | Page 21 of 25
HMC8200LP5ME
Data Sheet
Phase I: Adjust
Table 11. Phase I Register, (Address 0x08)
Bit No.
[15:9]
[8:0]
Bit Name
Reserved
I_PHASE_ADJ
Description
Not used
I phase adjust
Reset
1111000
0x0
Access
R/W
R/W
Description
Not used
Q phase adjust
Reset
1111000
0x0
Access
R/W
R/W
Phase Q: Adjust
Table 12. Phase Q Register, (Address 0x09)
Bit No.
[15:9]
[8:0]
Bit Name
Reserved
Q_PHASE_ADJ
Rev. D | Page 22 of 25
Data Sheet
HMC8200LP5ME
EVALUATION PRINTED CIRCUIT BOARD (PCB)
ENV P
ENV N
GND
SLPD OUT
LOP
C31
LOG RF
GND
VGA CTRL
U2
LOG IF
C4
J3
F1
C6
3
C11
C24
C32
C33
C49
R7
C55
C3
C5
C40
C10
C26
C27
C54 R13
C56
JP1
C29
C21
TX_OUT
C37
C38
C47
C44
C45
C65
C43
600-00663-00-2
C18
C19
C42
R3
C28
L1
R1
4
R1
6
C17
C20
C22
C23
C25
L2
C57
C61
C58
C1
4
C2
0
C3
0
C6 62 9
C C5
BB IN
C1
C50
J15
C64
C1
5
R15
R17
C36
C34
C35
R4
R6
C6
BB IP
R5
C46
C48
LON
GND
TX IF IN
VCC_3P3V
13868-063
BB QP
J1
BB QN
C16
GND
Figure 63. Evaluation PCB
Rev. D | Page 23 of 25
HMC8200LP5ME
Data Sheet
EVALUATION PCB SCHEMATIC
VCC3
LO_N
C5
100pF
LO_P
C6
10nF
SEN
C55
100pF
SCLK
VCTRL
C11
100pF
25
26
27
28
20
6
19
7
18
8
17
C27
10nF
VCC8
C28
100pF
R3
24.9Ω
C29
10nF
C48
10µF
VCC6
C25
10nF
C46
10µF
VCC7
C22
100pF
VCC1/DGA_S1
C23
10nF
C45
10µF
DET1
DET3
VCC_AGC
VCC10
DET2
C20
100pF
C33
10nF
C32
100pF
R7
10kΩ
C34
100pF
R6
10kΩ
R5
10kΩ
DET3
3
Rev. D | Page 24 of 25
C33
10nF
C50
10µF
5
V
1
V
4
R5
10kΩ
Figure 64. PCB Schematic/Typical Applications Circuit
C49
10µF
2
C31
100pF
13868-062
C18
100pF
C26
100pF
C30
L2
5pF
15nH
C24
100pF
C19
10nF
JP1
VCC5
C17
1000pF
C43
10µF
R13
1kΩ
RF OUT
IF IN
L1
330nH
C64
10nF
C54
100pF
16
21
5
15
4
14
22
9
C15
100pF
C63
100pF
23
3
13
VCC2
C56
100pF
VCC4
24
SPI
12
RST
C14
10nF
29
1
2
11
C10
10nF
10
C40
10µF
30
32
SDO
VCC9
31
SDI
Data Sheet
HMC8200LP5ME
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
PIN 1
INDICATOR
0.31
0.25
0.19
25
32
24
1
0.50
BSC
3.20
3.10 SQ
3.00
EXPOSED
PAD
8
17
0.50
0.40
0.30
TOP VIEW
1.00
0.85
0.80
16
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PKG-000000
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
9
BOTTOM VIEW
3.50 REF
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
01-26-2017-A
5.10
5.00 SQ
4.90
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 65. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body, 0.85 mm Package Height
(CP-32-27)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
HMC8200LP5ME
Temperature Range
−40°C to +85°C
MSL Rating3
MSL3
Package Description
32-Lead LFCSP, Tape and Reel
Package
Option
CP-32-27
HMC8200LP5METR
−40°C to +85°C
MSL3
32-Lead LFCSP, Tape and Reel
CP-32-27
EK1HMC8200LP5M
Evaluation Kit
1
All products listed in the ordering guide are RoHS compliant.
The HMC8200LP5ME lead finish is NiPdAu.
3
See the Absolute Maximum Ratings section.
4
XXXX is the 4-digit lot number.
2
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13868-0-6/17(D)
Rev. D | Page 25 of 25
Branding4
H8200
XXXX
H8200
XXXX
Quantity
50
500
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湘ICP备2023018690号
