16-Channel High Performance
Differential Output, 192 kHz, 24-Bit DAC
ADAU1966
Data Sheet
FEATURES
GENERAL DESCRIPTION
118 dB DAC dynamic range and SNR
−98 dB THD + N
Differential voltage DAC output
2.5 V digital, 5 V analog and 3.3 V or 5 V I/O supplies
521 mW total (32.6 mW/channel) quiescent power
PLL generated or direct MCLK master clock
Low EMI design
Linear regulator driver to generate digital supply
Supports 24-bit and 32 kHz to 192 kHz sample rates
Low propagation 192 kHz sample rate mode
Log volume control with autoramp function
Temperature sensor with digital readout ±3°C accuracy
SPI and I2C controllable for flexibility
Software-controllable clickless mute
Software power-down
Right-justified, left-justified, I2S, and TDM modes
Master and slave modes with up to 16-channel input/output
80-lead LQFP package
Qualified for automotive applications
The ADAU1966 is a high performance, single-chip DAC that
provides 16 digital-to-analog converters (DACs) with differential output using the Analog Devices, Inc., patented multibit
sigma-delta (Σ-Δ) architecture. An SPI/I2C port is included,
allowing a microcontroller to adjust volume and many other
parameters. The ADAU1966 operates from 2.5 V digital, 5 V
analog and 3.3 V or 5 V input/output supplies. A linear regulator
is included to generate the digital supply voltage from the analog
supply voltage. The ADAU1966 is available in an 80-lead LQFP
package.
The ADAU1966 is designed for low EMI. This consideration is
apparent in both the system and circuit design architectures.
By using the on-board PLL to derive the internal master clock
from an external LRCLK, the ADAU1966 can eliminate the
need for a separate high frequency master clock and can be
used with or without a bit clock. The DACs are designed using
the latest Analog Devices continuous time architectures to
further minimize EMI. By using 2.5 V digital supplies, power
consumption is minimized, and the digital waveforms are a
smaller amplitude, further reducing emissions.
APPLICATIONS
Automotive audio systems
Home theater systems
Digital audio effects processors
FUNCTIONAL BLOCK DIAGRAM
DIGITAL AUDIO
INPUT
ADAU1966
SERIAL DATA PORT
DAC
DAC
DAC
DAC
DAC
DAC
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
SDATA
IN
CLOCKS
TIMING MANAGEMENT
AND CONTROL
(CLOCK AND PLL)
DAC
DAC
DIGITAL
FILTER
AND
VOLUME
CONTROL
DAC
DAC
DIFFERENTIAL
ANALOG
AUDIO
OUTPUTS
DAC
DAC
DAC
DAC
PRECISION
VOLTAGE
REFERENCE
SPI/I2C
CONTROL PORT
CONTROL DATA
INPUT/OUTPUT
INTERNAL
TEMP
SENSOR
09434-001
DIFFERENTIAL
ANALOG
AUDIO
OUTPUTS
SDATA
IN
Figure 1.
Rev. E
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 ©2011–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADAU1966
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Block Power-Down and Thermal Sensor Control 1 Register27
Applications ....................................................................................... 1
Power-Down Control 2 Register .............................................. 28
General Description ......................................................................... 1
Power-Down Control 3 Register .............................................. 29
Functional Block Diagram .............................................................. 1
Thermal Sensor Temperature Readout Register .................... 30
Revision History ............................................................................... 3
DAC Control 0 Register ............................................................ 31
Specifications..................................................................................... 4
DAC Control 1 Register ............................................................ 32
Analog Performance Specifications ........................................... 4
DAC Control 2 Register ............................................................ 33
Crystal Oscillator Specifications................................................. 5
DAC Individual Channel Mutes 1 Register ............................ 34
Digital Input/Output Specifications........................................... 5
DAC Individual Channel Mutes 2 Register ............................ 35
Power Supply Specifications........................................................ 6
Master Volume Control Register.............................................. 36
Digital Filters ................................................................................. 6
DAC 1 Volume Control Register .............................................. 36
Timing Specifications .................................................................. 7
DAC 2 Volume Control Register .............................................. 37
Absolute Maximum Ratings............................................................ 9
DAC 3 Volume Control Register .............................................. 37
Thermal Resistance ...................................................................... 9
DAC 4 Volume Control Register .............................................. 38
ESD Caution .................................................................................. 9
DAC 5 Volume Control Register .............................................. 38
Pin Configuration and Function Descriptions ........................... 10
DAC 6 Volume Control Register .............................................. 39
Typical Performance Characteristics ........................................... 13
DAC 7 Volume Control Register .............................................. 39
Application Circuits ....................................................................... 14
DAC 8 Volume Control Register .............................................. 40
Theory of Operation ...................................................................... 15
DAC 9 Volume Control Register .............................................. 40
Digital-to-Analog Converters (DACs) .................................... 15
DAC 10 Volume Control Register............................................ 41
Clock Signals ............................................................................... 15
DAC 11 Volume Control Register............................................ 41
Power-Up and RST ..................................................................... 16
DAC 12 Volume Control Register............................................ 42
Standalone Mode ........................................................................ 17
DAC 13 Volume Control Register............................................ 42
I2C Control Port .......................................................................... 17
DAC 14 Volume Control Register............................................ 43
Serial Control Port: SPI Control Mode ................................... 19
DAC 15 Volume Control Register............................................ 43
Power Supply and Voltage Reference ....................................... 20
DAC 16 Volume Control Register............................................ 44
Serial Data Ports—Data Format ............................................... 20
Common Mode and Pad Strength Register ............................ 44
Time-Division Multiplexed (TDM) Modes ............................ 20
DAC Power Adjust 1 Register ................................................... 45
Temperature Sensor ................................................................... 20
DAC Power Adjust 2 Register ................................................... 46
Additional Modes ....................................................................... 22
DAC Power Adjust 3 Register ................................................... 47
Register Summary .......................................................................... 24
DAC Power Adjust 4 Register ................................................... 48
Register Details ............................................................................... 25
Outline Dimensions ....................................................................... 52
PLL and Clock Control 0 Register ........................................... 25
Ordering Guide .......................................................................... 52
PLL and Clock Control 1 Register ........................................... 26
Automotive Products ................................................................. 52
Rev. E | Page 2 of 52
Data Sheet
ADAU1966
REVISION HISTORY
3/16—Rev. D to Rev. E
Changes to Table 4 ............................................................................ 5
12/13—Rev. C to Rev. D
Changes to Features Section ............................................................ 1
Changes to General Description ..................................................... 1
Changes to Specifications Section................................................... 4
Deleted Table 3 and Table 4; Renumbered Sequentially .............. 5
Changes to Table 5 ............................................................................ 6
Changes to Theory of Operation Section ....................................15
Changes to Table 11 ........................................................................15
Changes to Table 13 ........................................................................17
Changes to Serial Control Port: SPI Control Mode Section......19
Added Figure 14, Figure 15, and Figure 16; Renumbered
Sequentially ......................................................................................19
Moved, Changes to Figure 17 ........................................................20
Changes to Power Supply and Voltage Reference Section and
Serial Data Ports—Data Format Section ......................................20
Changes to Figure 18 ......................................................................21
Change to Address 0x01C, Table 23 .............................................24
Changes to Table 52, Common Mode and Pad Strength
Register .............................................................................................44
3/13—Rev. B to Rev. C
Changes to Table 2 and Table 3 ....................................................... 5
Changes to Table 4 ............................................................................ 6
Changes to I2C Control Port Section ............................................ 18
Changes to Figure 13, Table 19, Table 20, Table 21, and
Table 22 ............................................................................................. 19
Changes to Serial Control Port: SPI Control Mode Section ..... 20
8/12—Rev. A to Rev. B
Change to Table 10 .......................................................................... 10
7/12—Rev. 0 to Rev. A
Changed Output Resistance at Each Pin Parameter from 100 Ω
to 33 Ω ................................................................................................ 4
Changes to Figure 13 ...................................................................... 19
Added Figure 14 .............................................................................. 20
Updated Outline Dimensions........................................................ 52
9/11—Revision 0: Initial Version
Rev. E | Page 3 of 52
ADAU1966
Data Sheet
SPECIFICATIONS
Performance of all channels is identical, exclusive of the interchannel gain mismatch and interchannel phase deviation specifications.
Master clock = 12.288 MHz (48 kHz fS, 256 × fS mode), input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word
width = 24 bits, load capacitance (digital output) = 20 pF, load current (digital output) = ±1 mA or 1.5 kΩ to ½ DVDD supply, input
voltage high = 2.0 V, input voltage low = 0.8 V, analog audio output resistive load = 3100 Ω per pin, unless otherwise noted.
ANALOG PERFORMANCE SPECIFICATIONS
Specifications guaranteed at AVDDx = 5 V and an ambient temperature of 25°C. Supply voltages = AVDDx = 5 V, DVDD = 2.5 V,
ambient temperature1 (TA) = 25°C, unless otherwise noted.
Table 1.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Differential Output Voltage
Gain Error
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE VOLTAGES
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
TEMPERATURE SENSOR
Temperature Accuracy
Temperature Readout Range
Temperature Readout Step Size
Temperature Sample Rate
REGULATOR
Input Supply Voltage
Regulated Output Voltage
1
Test Conditions/Comments
Min
Typ
105
108
115.5
118
−90
−98
−98
3.00 (±8.49)
Max
Unit
20 Hz to 20 kHz, −60 dB input
0 dBFS
Two channels running, −1 dBFS
16 channels running, −1 dBFS
−10
−25
−30
−6
−85
+10
+25
+30
100
0
0.375
95.25
±0.6
33
TS_REF pin
CM pin
CM pin
2.14
1.50
2.25
2.25
−3
−60
2.29
+3
+140
VSUPPLY pin
VSENSE pin
3.0
2.26
Functionally guaranteed at −40°C to +125°C case temperature.
Rev. E | Page 4 of 52
5
2.50
V
V
V
6
°C
°C
°C
Hz
5.5
2.59
V
V
1
0.25
dB
dB
dB
dB
dB
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
Data Sheet
ADAU1966
Specifications guaranteed at AVDDx = 5 V and an ambient temperature of 105°C. Supply voltages = AVDDx = 5 V, DVDD = 2.5 V,
ambient temperature1 (TA) = 105°C, unless otherwise noted.
Table 2.
Parameter
DIGITAL-TO-ANALOG CONVERTERS
Dynamic Range
No Filter (RMS)
With A-Weighted Filter (RMS)
Total Harmonic Distortion + Noise
Full-Scale Differential Output Voltage
Gain Error
Offset Error
Gain Drift
Interchannel Isolation
Interchannel Phase Deviation
Volume Control Step
Volume Control Range
De-emphasis Gain Error
Output Resistance at Each Pin
REFERENCE
Temperature Sensor Reference Voltage
Common-Mode Reference Output
External Reference Voltage Source
REGULATOR
Input Supply Voltage
Regulated Output Voltage
1
Test Conditions/Comments
Min
Typ
Max
109
110.5
113.5
116
−85
−92.5
−92.5
3.00 (±8.49)
Unit
20 Hz to 20 kHz, −60 dB input
0 dBFS
Two channels running −1 dBFS
Eight channels running −1 dBFS
−10
−25
−30
−85
+10
+25
+30
−6
100
0
0.375
95.25
±0.6
33
dB
dB
dB
dB
dB
V rms (V p-p)
%
mV
ppm/°C
dB
Degrees
dB
dB
dB
Ω
TS_REF pin
CM pin
CM pin
2.14
1.50
2.25
2.25
2.29
V
V
V
VSUPPLY pin
VSENSE pin
3.0
2.25
5
2.50
5.5
2.55
V
V
Functionally guaranteed at −40°C to +125°C case temperature.
CRYSTAL OSCILLATOR SPECIFICATIONS
Table 3.
Parameter
Transconductance, TA = 25°C
Transconductance, TA = 105°C
Min
6.4
5.2
Typ
7 to 10
7.5 to 8.5
Max
14
12
Unit
mmhos
mmhos
DIGITAL INPUT/OUTPUT SPECIFICATIONS
−40°C < TA < +105°C, IOVDD = 5.0 V and 3.3 V ± 10%.
Table 4.
Parameter
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
Input Leakage
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Input Capacitance
Test Conditions/Comments
IOVDD = 5.0 V
IIH at VIH = 3.3 V
IIL at VIL = 0 V
IOH = 1 mA
IOL = 1 mA
Rev. E | Page 5 of 52
Min
0.7 × IOVDD
Typ
Max
0.3 × IOVDD
10
10
0.8 × IOVDD
0.1 × IOVDD
5
Unit
V
V
μA
μA
V
V
pF
ADAU1966
Data Sheet
POWER SUPPLY SPECIFICATIONS
Table 5.
Parameter
SUPPLIES
Voltage
Analog Current—AVDD = 5.0 V
Normal Operation
Power-Down
Digital Current—DVDD = 2.5 V
Normal Operation
Power-Down
PLL Current—PLLVDD = 2.5 V
Normal Operation
Power-Down
IO Current—IOVDD = 3.3 V
Normal Operation
Power-Down
QUIESCENT DISSIPATION—DITHER INPUT
Operation
All Supplies
Analog Supply
Digital Supply
PLL Supply
I/O Supply
Power-Down, All Supplies
POWER SUPPLY REJECTION RATIO
Signal at Analog Supply Pins
Test Conditions/Comments
Min
Typ
Max
Unit
AVDD
DVDD
PLLVDD
IOVDD
VSUPPLY
4.5
2.25
2.25
3.0
3.0
5.0
2.5
2.5
5.0
5.0
5.5
3.6
3.6
5.5
5.5
V
V
V
V
V
84
1
mA
μA
fS = 48 kHz to 192 kHz
No MCLK or I2S
30
4
mA
μA
fS = 48 kHz to 192 kHz
5
1
mA
μA
4
1
mA
μA
521
420
75
13
13
0
mW
mW
mW
mW
mW
mW
85
85
dB
dB
MCLK = 256 × fS, 48 kHz
AVDDx = 5.0 V, DVDD/PLLVDD = 2.5 V, IOVDD = 3.3 V
AVDDx = 5.0 V
DVDD = 2.5 V
PLLVDD= 2.5 V
IOVDD = 3.3 V
1 kHz, 200 mV p-p
20 kHz, 200 mV p-p
DIGITAL FILTERS
Table 6.
Parameter
DAC INTERPOLATION FILTER
Pass Band
Pass-Band Ripple
Transition Band
Stop Band
Stop-Band Attenuation
Mode
Factor
Min
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
0.4535 × fS
0.3646 × fS
0.3646 × fS
35
Rev. E | Page 6 of 52
Typ
Max
22
70
±0.01
±0.05
±0.1
0.5 × fS
0.5 × fS
0.5 × fS
0.5465 × fS
0.6354 × fS
0.6354 × fS
24
48
96
26
61
122
68
68
68
Unit
kHz
kHz
kHz
dB
dB
dB
kHz
kHz
kHz
kHz
kHz
kHz
dB
dB
dB
Data Sheet
Parameter
Propagation Delay
ADAU1966
Mode
48 kHz mode, typical at 48 kHz
96 kHz mode, typical at 96 kHz
192 kHz mode, typical at 192 kHz
192 kHz low delay mode, typical at 192 kHz
Factor
25/fS
11/fS
8/fS
2/fS
Min
Typ
521
115
42
10
Max
Unit
μs
μs
μs
μs
TIMING SPECIFICATIONS
−40°C < TA < +105°C, DVDD = 2.5 V ± 10%.
Table 7.
Parameter
INPUT MASTER CLOCK (MCLK) AND RESET
tMH
tMH
fMCLK
fMCLK
fBCLK
tPDR
tPDRR
PLL
Lock Time
Lock Time
256 × fS VCO Clock, Output Duty Cycle, MCLKO Pin
SPI PORT
tCCH
tCCL
fCCLK
tCDS
tCDH
tCLS
tCLH
tCLHIGH
tCOE
tCOD
tCOH
tCOTS
I2C
fSCL
tSCLL
tSCLH
tSCS
tSCH
tSSH
tDS
tSR
tSF
tBFT
Description
Min
MCLK duty cycle, DAC clock source = PLL clock at
256 × fS, 384 × fS, 512 × fS, and 768 × fS
DAC clock source = direct MCLK at 512 × fS (bypass
on-chip PLL)
MCLKI frequency, PLL mode
Direct MCLK 512 × fS mode
DBCLK frequency, PLL mode
Low
Recovery, reset to active output
Max
Unit
40
60
%
40
60
%
6.9
40.5
27.1
27.0
MHz
MHz
MHz
ns
ms
10
50
60
ms
ms
%
15
300
MCLK input
DLRCLK input
40
See Figure 17
CCLK high
CCLK low
CCLK frequency, fCCLK = 1/tCCP; only tCCP shown in Figure 17
CDATA setup, time to CCLK rising
CDATA hold, time from CCLK rising
CLATCH setup, time to CCLK rising
CLATCH hold, time from CCLK falling
CLATCH high, not shown in Figure 17
COUT enable from CCLK falling
COUT delay from CCLK falling
COUT hold from CCLK falling, not shown in Figure 17
COUT tristate from CCLK falling
See Figure 2 and Figure 13
SCL clock frequency
SCL low
SCL high
Setup time (start condition), relevant for repeated start
condition
Hold time (start condition), first clock generated after
this period
Setup time (stop condition)
Data setup time
SDA and SCL rise time
SDA and SCL fall time
Bus-free time between stop and start
Rev. E | Page 7 of 52
Typ
35
35
10
10
10
10
10
10
30
30
30
30
400
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
1.3
0.6
0.6
kHz
μs
μs
μs
0.6
μs
0.6
100
μs
ns
ns
ns
μs
300
300
1.3
ADAU1966
Data Sheet
Parameter
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDLS
tDDS
tDDH
Description
See Figure 19
DBCLK high, slave mode
DBCLK low, slave mode
DLRCLK setup, time to DBCLK rising, slave mode
DLRCLK hold from DBCLK rising, slave mode
DLRCLK skew from DBCLK falling, master mode
DSDATAx setup to DBCLK rising
DSDATAx hold from DBCLK rising
tDS
tSCH
Min
10
10
10
5
−8
10
5
tSCH
SDA
SCL
tSCLH
tBFT
tSCLL
tSF
tSCS
Figure 2. I2C Timing Diagram
Rev. E | Page 8 of 52
tSSH
09434-002
tSR
Typ
Max
+8
Unit
ns
ns
ns
ns
ns
ns
ns
Data Sheet
ADAU1966
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 8.
Parameter
Analog (AVDD)
Input/Output (IOVDD)
Digital (DVDD)
PLL (PLLVDD)
VSUPPLY
Input Current (Except Supply Pins)
Analog Input Voltage (Signal Pins)
Digital Input Voltage (Signal Pins)
Operating Temperature Range (Case)
Storage Temperature Range
Rating
−0.3 V to +5.5 V
−0.3 V to +5.5 V
−0.3 V to +3.6 V
−0.3 V to +3.6 V
−0.3 V to +6.0 V
±20 mA
–0.3 V to AVDD + 0.3 V
−0.3 V to IOVDD + 0.3 V
−40°C to +125°C
−65°C to +150°C
θJA represents junction-to-ambient thermal resistance; θJC represents the junction-to-case thermal resistance. All characteristics
are for a 4-layer board with a solid ground plane.
Table 9. Thermal Resistance
Package Type
80-Lead LQFP
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. E | Page 9 of 52
θJA
42.3
θJC
10.0
Unit
°C/W
ADAU1966
Data Sheet
DAC8N
DAC8P
DAC7N
72
71
70
69
DAC_BIAS3 1
68
67
66
65
64
63
62
61
60
DAC_BIAS2
59
DAC_BIAS1
AVDD3 3
58
AVDD2
DAC13P 4
57
DAC4N
DAC13N 5
56
DAC4P
DAC14P 6
55
DAC3N
DAC14N 7
54
DAC3P
DAC15P 8
53
DAC2N
DAC15N 9
52
DAC2P
PIN 1
INDICATOR
DAC_BIAS4 2
43
MISO/SDA/SA
MCLKO 19
42
MOSI/ADDR1/SA
DVDD 20
41
DVDD
22
23
24
25
26
27
28
DLRCLK
21
29
30
31
32
33
34
35
36
37
38
39
40
DGND
SCLK/SCL
XTALO 18
IOVDD
44
DSDATA1
SS/ADDR0/SA
MCLKI/XTALI 17
DSDATA2
45
DSDATA3
SA_MODE
PLLVDD 16
DSDATA4
46
DSDATA5
PU/RST
LF 15
DSDATA6
47
SA2
AGND1
PLLGND 14
SA1
48
DGND
AVDD1
AGND4 13
DVDD
49
DBCLK
DAC1P
AVDD4 12
DGND
50
VSUPPLY
TOP VIEW
(Not to Scale)
VDRIVE
DAC1N
DAC16N 11
VSENSE
51
DGND
ADAU1966A
IOVDD
DAC16P 10
NOTES
1. SEE THE STANDALONE MODE SECTION (TABLE 13 AND TABLE 14) FOR THE SA_MODE SETTINGS
FOR PIN 31, PIN 32, PIN 42, PIN 43, AND PIN 45.
Figure 3. Pin Configuration
Table 10. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Type1
I
I
PWR
O
O
O
O
O
O
O
O
PWR
GND
GND
O
PWR
I
O
O
Mnemonic
DAC_BIAS3
DAC_BIAS4
AVDD3
DAC13P
DAC13N
DAC14P
DAC14N
DAC15P
DAC15N
DAC16P
DAC16N
AVDD4
AGND4
PLLGND
LF
PLLVDD
MCLKI/XTALI
XTALO
MCLKO
Description
DAC Bias 3. AC couple with 470 nF to AGND3.
DAC Bias 4. AC couple with 470 nF to AVDD3.
Analog Power.
DAC13 Positive Output.
DAC13 Negative Output.
DAC14 Positive Output.
DAC14 Negative Output.
DAC15 Positive Output.
DAC15 Negative Output.
DAC16 Positive Output.
DAC16 Negative Output.
Analog Power.
Analog Ground.
PLL Ground.
PLL Loop Filter, Reference to PLLVDD.
Apply 2.5 V to Power PLL.
Master Clock Input, Input to Crystal Inverter.
Output from Crystal Inverter.
Master Clock Output.
Rev. E | Page 10 of 52
11298-003
DAC9P
73
AGND2
DAC9N
74
CM
DAC10P
75
TS_REF
DAC10N
76
DAC5P
DAC11P
77
DAC5N
DAC11N
78
DAC6P
DAC12P
79
DAC7P
DAC12N
80
DAC6N
AGND3
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
ADAU1966
Pin No.
20, 29, 41
21, 26, 30, 40
22, 39
23
Type1
PWR
GND
PWR
I
Mnemonic
DVDD
DGND
IOVDD
VSENSE
24
25
O
I
VDRIVE
VSUPPLY
27
28
31
I/O
I/O
I
DBCLK
DLRCLK
DSDATA8/SA
32
I
DSDATA7/SA
33
34
35
36
37
38
42
I
I
I
I
I
I
I
DSDATA6
DSDATA5
DSDATA4
DSDATA3
DSDATA2
DSDATA1
CDATA/ADDR1/SA
43
I/O
COUT/SDA/SA
44
I
CCLK/SCL/SA
45
I
CLATCH/ADDR0/SA
46
I
SA_MODE
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
I
GND
PWR
O
O
O
O
O
O
O
O
PWR
I
I
GND
O
PU/RST
AGND1
AVDD1
DAC1P
DAC1N
DAC2P
DAC2N
DAC3P
DAC3N
DAC4P
DAC4N
AVDD2
DAC_BIAS1
DAC_BIAS2
AGND2
CM
63
O
TS_REF
64
65
66
67
O
O
O
O
DAC5P
DAC5N
DAC6P
DAC6N
Description
Digital Power, 2.5 V.
Digital Ground.
Power for Digital Input and Output Pins, 3.3 V to 5 V.
2.5 V Output of Regulator, Collector of Pass Transistor. Bypass with 10 μF in parallel
with 100 nF.
Drive for Base of Pass Transistor.
5 V Input to Voltage Regulator, Emitter of Pass Transistor. Bypass with 10 μF in parallel
with 100 nF.
Bit Clock for DACs.
Frame Clock for DACs.
DAC15 and DAC 16 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 13, and Table 14).
DAC13 and DAC 14 Serial Data Input/SA_MODE TDM State (see the Standalone Mode
section, Table 13, and Table 14).
DAC11 and DAC 12 Serial Data Input.
DAC9 and DAC 10 Serial Data Input.
DAC7 and DAC 8 Serial Data Input.
DAC5 and DAC 6 Serial Data Input.
DAC3 and DAC 4 Serial Data Input.
DAC1 and DAC 2 Serial Data Input.
Control Data Input (SPI)/Address 1 (I2C)/SA_MODE State (see the Standalone Mode
section and Table 13).
Control Data Output (SPI)/Control Data Input (I2C)/SA_MODE State (see the
Standalone Mode section and Table 13).
Control Clock Input (SPI)/Control Clock Input (I2C)/SA_MODE State (see the Standalone
Mode section and Table 13).
Control Chip Select (SPI) (Low Active)/Address 0 (I2C)/SA_MODE State (see the
Standalone Mode section and Table 13).
Standalone Mode. This pin allows mode control of ADAU1966 using Pin 42 to Pin 45,
Pin 31, and Pin 32 (high active, see Table 13 and Table 14).
Power-Up/Reset (Low Active).
Analog Ground.
Analog Power.
DAC1 Positive Output.
DAC1 Negative Output.
DAC2 Positive Output.
DAC2 Negative Output.
DAC3 Positive Output.
DAC3 Negative Output.
DAC4 Positive Output.
DAC4 Negative Output.
Analog Power.
DAC Bias 1. AC couple with 470 nF to AVDD2.
DAC Bias 2. AC couple with 470 nF to AGND2.
Analog Ground.
Common-Mode Reference Filter Capacitor Connection. Bypass with 10 μF in parallel
with 100 nF to AGND2. This reference can be shut off in the PLL_CLK_CTRL1 register
and the pin can be driven with an outside voltage source.
Voltage Reference Filter Capacitor Connection. Bypass with 10 μF in parallel with
100 nF to AGND2.
DAC5 Positive Output.
DAC5 Negative Output.
DAC6 Positive Output.
DAC6 Negative Output.
Rev. E | Page 11 of 52
ADAU1966
Pin No.
68
69
70
71
72
73
74
75
76
77
78
79
80
1
Type1
O
O
O
O
O
O
O
O
O
O
O
O
GND
Data Sheet
Mnemonic
DAC7P
DAC7N
DAC8P
DAC8N
DAC9P
DAC9N
DAC10P
DAC10N
DAC11P
DAC11N
DAC12P
DAC12N
AGND3
Description
DAC7 Positive Output.
DAC7 Negative Output.
DAC8 Positive Output.
DAC8 Negative Output.
DAC9 Positive Output.
DAC9 Negative Output.
DAC10 Positive Output.
DAC10 Negative Output.
DAC11 Positive Output.
DAC11 Negative Output.
DAC12 Positive Output.
DAC12 Negative Output.
Analog Ground.
I = input, O = output, I/O = input/output, PWR = power, GND = ground.
Rev. E | Page 12 of 52
Data Sheet
ADAU1966
TYPICAL PERFORMANCE CHARACTERISTICS
0.05
0.20
0.04
0.15
0.03
0.10
MAGNITUDE (dB)
MAGNITUDE (dB)
0.02
0.01
0
–0.01
0.05
0
–0.05
–0.02
–0.10
–0.03
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
FREQUENCY (FACTORED TO fS)
–0.20
0
0.15
0.20
0.25
0.30
0.35
0.40
1.0
Figure 6. DAC Pass-Band Filter Response, 96 kHz
0
–10
–10
–20
–20
–30
–30
MAGNITUDE (dB)
0
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
–90
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FREQUENCY (FACTORED TO fS)
0.9
1.0
09434-005
MAGNITUDE (dB)
0.10
FREQUENCY (FACTORED TO fS)
Figure 4. DAC Pass-Band Filter Response, 48 kHz
–100
0.05
09434-006
0
09434-004
–0.05
09434-007
–0.15
–0.04
–100
Figure 5. DAC Stop-Band Filter Response, 48 kHz
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
FREQUENCY (FACTORED TO fS)
Figure 7. DAC Stop-Band Filter Response, 96 kHz
Rev. E | Page 13 of 52
0.9
ADAU1966
Data Sheet
APPLICATION CIRCUITS
Typical application circuits are shown in Figure 8 to Figure 11. Recommended loop filters for DLRCLK and MCLKI/XTALI modes of the
PLL reference are shown in Figure 8. Output filters for the DAC outputs are shown in Figure 9 and Figure 10, and an external regulator
circuit is shown in Figure 11.
LF
DLRCLK
MCLKI/XTALI
LF
39nF
5.6nF
2.2nF
390pF
562Ω
PLLVDD
09434-008
3.32kΩ
PLLVDD
Figure 8. Recommended Loop Filters for DLRCLK or MCLKI/XTALI PLL Reference Modes
DACP
10µF
+
237Ω
OUTP
2.7nF
DACN
10µF
+
237Ω
OUTN
49.9kΩ
09434-009
49.9kΩ
Figure 9. Typical DAC Output Passive Filter Circuit (Differential)
1.1nF
AD8672ARZ
DAC1P
1.50kΩ
1.54kΩ
5
100Ω
7
4.7µF
+
OUTPUT1P
6
+12V DC
422Ω
2.49kΩ
100kΩ
8
0.1µF
4.7µF
0.1µF
4.7µF
+
1nF
4.7µF
1nF
4.7µF
+
V+
V–
4
+
+
100kΩ
–12V DC
1.54kΩ
422Ω
100Ω
1
3
4.7µF
+
OUTPUT1N
09434-010
AD8672ARZ
1.1nF
Figure 10. Typical DAC Output Active Filter Circuit (Differential)
100nF
+
10µF
VSUPPLY
5V
1kΩ
B
VDRIVE
E
FZT953
C
VSENSE
2.5V
100nF
+
10µF
09434-011
DAC1N
2
1.50kΩ
2.49kΩ
Figure 11. Recommended 2.5 V Regulator Circuit
Rev. E | Page 14 of 52
Data Sheet
ADAU1966
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTERS (DACS)
The 16 ADAU1966 digital-to-analog converter (DAC) channels
are differential for improved noise and distortion performance
and are voltage output for simplified connection. The DACs
include on-chip digital interpolation filters with 68 dB stop-band
attenuation and linear phase response, operating at an oversampling ratio of 256× (48 kHz range), 128× (96 kHz range), or
64× (192 kHz range). Each channel has its own independently
programmable attenuator, adjustable in 255 steps in increments
of 0.375 dB. Digital inputs are supplied through eight serial data
input pins (two channels on each pin), a common frame clock
(DLRCLK), and a bit clock (DBCLK). Alternatively, any one of the
TDM modes can be used to access up to 16 channels on a single
TDM data line.
The ADAU1966 has a low propagation delay mode; this mode
is an option for an fS of 192 kHz and is enabled in Register DAC_
CTRL0[2:1]. By setting these bits to b11, the propagation delay
is reduced by the amount shown in Table 6. The shorter delay is
achieved by reducing the amount of digital filtering; the negative
impact of selecting this mode is reduced audio frequency response
and increased out-of-band energy.
When AVDD is supplied with 5 V, each analog output pin has a
nominal common-mode (CM) dc level of 2.25 V and swings
±2.12 V above and below the 2.25 V for a for a 1.5 V rms signal
on each pin. Differentially, the signal is 3 V rms, 8.48 V p-p,
from a 0 dBFS digital input signal.
The differential analog outputs require only a single-order
passive differential RC filter to provide the specified DNR
performance; see Figure 9 for an example filter. The outputs can
easily drive differential inputs on a separate PCB through
cabling as well as differential inputs on the same PCB.
If more signal level is required or if a more robust filter is needed, a
single op amp gain stage designed as a second-order, low-pass
Bessel filter can be used to remove the high frequency out-ofband noise present on each pin of the differential outputs. The
choice of components and design of this circuit is critical to yield
the full DNR of the DACs (see the recommended passive and
active circuits in Figure 9 and Figure 10). This filter can be built
into an active difference amplifier to provide a single-ended output
with gain, if necessary. Note that the use of op amps with low
slew rate or low bandwidth can cause high frequency noise and
tones to fold down into the audio band; exercise care when
selecting these components.
The ADAU1966 offers control over the analog performance
of the DACs; it is possible to program the registers to reduce
the power consumption with the trade-off of lower SNR and
THD + N. The reduced power consumption is the result of
changing the internal bias current to the analog output
amplifiers.
Register DAC_POWER1 to Register DAC_POWER4 present
four basic settings for the DAC power vs. performance in each
of the 16 channels: best performance, good performance, low
power, and lowest power. Alternatively, in Register PLL_CLK_
CTRL1[7:6], the LOPWR_MODE bits offer global control over
the power and performance for all 16 channels. The default
setting is b00. This setting allows the channels to be controlled
individually using the DAC_POWERx registers. Setting b10
and Setting b11 select the low power and lowest power settings.
The data presented in Table 11 shows the result of setting all
16 channels to each of the four settings. The SNR and THD + N
specifications are shown in relation to the measured performance of a device at the best performance setting.
The voltage at CM, the common-mode reference pin, can be
used to bias the external op amps that buffer the output signals
(see the Power Supply and Voltage Reference section).
CLOCK SIGNALS
Upon powering the ADAU1966 and asserting the PU/RST pin
high, the device starts in either standalone mode (SA_MODE)
or program mode, depending on the state of SA_MODE (Pin 46).
The clock functionality of SA_MODE is described in the
Standalone Mode section. In program mode, the default for the
ADAU1966 is for the MCLKO pin to feed a buffered output of
the MCLKI signal. The default for the DLRCLK and DBCLK
ports is slave mode; the DAC must be driven with a coherent set
of MCLK, LRCLK, and BCLK signals to function.
The MCLKO pin can be programmed to provide different clock
signals using Register Bits PLL_CLK_CTRL1[5:4]. The default,
b10, provides a buffered copy of the clock signal that is driving
the MCLKI pin. Two modes, b00 and b01, provide low jitter
clock signals. The b00 setting yields a clock rate between 4 MHz
and 6 MHz, and b01 yields a clock rate between 8 MHz and
12 MHz. Both of these clock frequencies are scaled as ratios of
MCLK automatically inside the ADAU1966. As an example, an
MCLK of 8.192 MHz and a setting of b00 yield an MCLKO of
(8.192/2) = 4.096 MHz. Alternatively, an MCLK of 36.864 MHz
and a setting of b01 yield an MCLKO frequency of (36.864/3) =
12.288 MHz. The setting b11 shuts off the MCLKO pin.
Table 11. DAC Power vs. Performance
Register Setting
Total AVDD Current
SNR
THD + N (−1 dBFS signal)
Best Performance
84 mA
Reference
Reference
Good Performance
75 mA
−0.2 dB
−1.8 dB
Rev. E | Page 15 of 52
Low Power
66 mA
−1.5 dB
−3.0 dB
Lowest Power
56 mA
−14.2 dB
−5.8 dB
ADAU1966
Data Sheet
After the PU/RST pin has been asserted high, the PLL_CLK_
CTRLx registers (Register 0x00 and Register 0x01) can be
programmed. The on-chip phase-locked loop (PLL) can be
selected to use the clock appearing at the MCLKI/XTALI pin at
a frequency of 256, 384, 512, or 768 times the sample rate (fS),
referenced to the 48 kHz mode from the master clock select
(MCS) setting, as described in Table 12. In 96 kHz mode, the
master clock frequency stays at the same absolute frequency;
therefore, the actual multiplication rate is divided by 2. In
192 kHz mode, the actual multiplication rate is divided by 4.
For example, if the ADAU1966 is programmed in 256 × fS mode,
the frequency of the master clock input is 256 × 48 kHz =
12.288 MHz. If the ADAU1966 is then switched to 96 kHz
operation (by writing to DAC_CTRL0 [2:1]), the frequency of
the master clock remains at 12.288 MHz, which is 128 × fS in this
example. In 192 kHz mode, MCS becomes 64 × fS.
bit in the DAC_CTRL1 register. With the BCLK_GEN bit set to
b1 (internal) and the SAI_MS bit set to b0 (slave), the ADAU1966
generate its own DBCLK; this works with the PLL input set to
either MCLKI/XTALI or DLRCLK. DLRCLK is the only required
clock in DLRCLK PLL mode.
The internal clock for the digital core varies by mode: 512 × fS
(48 kHz mode), 256 × fS (96 kHz mode), or 128 × fS (192 kHz
mode). By default, the on-board PLL generates this internal
master clock from an external clock.
Driving the PU/RST pin low puts the device into a very low power
state (
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