ADV7280/ADV7281/ADV7282/ADV7283 Hardware
Reference Manual
UG-637
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
ADV7280/ADV7281/ADV7282/ADV7283 Functionality and Features
OVERVIEW
This user guide provides a detailed description of the
functionality and features of the ADV7280, ADV7280-M,
ADV7281, ADV7281-M, ADV7281-MA, ADV7282,
ADV7282-M, and ADV7283 video decoders. Table 1 list the
shorthand notations used for these decoders in this user guide.
The ADV7280, ADV7280-M, ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, ADV7282-M, and ADV7283
automatically detect and convert standard composite analog
baseband video signals compatible with worldwide NTSC, PAL,
and SECAM standards. These video recorders accept composite
video signals (CVBS) as well as S-Video (YC) and YPbPr video
signals, supporting a wide range of consumer and automotive video
sources. The ADV7281, ADV7281-M, ADV7281-MA,
ADV7282, ADV7282-M, and ADV7283 models can also accept
pseudo differential and true differential CVBS inputs.
The ADV728x-T models (ADV7280, ADV7281, ADV7282, and
ADV7283) convert the analog video inputs into a YCrCb 4:2:2
component video data stream that is compatible with the 8-bit
ITU-R BT.656 interface standard.
The ADV728x-M models (ADV7280-M, ADV7281-M,
ADV7281-MA, and ADV7282-M) convert the analog video
inputs into an 8-bit YcrCb 4:2:2 video stream, and that is output
over an MIPI CSI-2 interface. This MIPI CSI-2 output interface
connects to a wide range of video processors and FPGAs.
The AGC and clamp-restore circuitry allow an input video signal
peak-to-peak range to 1.0 V at the analog video input pin of the
ADV728x. Alternatively, these can be bypassed for manual
settings.
AC coupling of the input video signals provides STB protection.
On the ADV7281, ADV7281-M, ADV7282, and ADV7282-M
models, short-to-battery (STB) diagnostics can be carried out on
two input video signals.
The ADV728x is programmed via a two-wire, serial,
bidirectional port (I2C® compatible). The ADV728x supports a
number of functions including 8-bit to 6-bit down dither mode
and adaptive contrast enhancement (ACE).
The advanced interlaced-to-progressive (I2P) function allows
the ADV7280, ADV7280-M, ADV7282, ADV7282-M, and
ADV7283 to convert an interlaced video input into a
progressive video output. This function is performed without
the need for external memory. Edge adaptive technology is used
to minimize video defects on low angle lines.
The ADV728x is fabricated in a 1.8 V CMOS process. Its
monolithic CMOS construction ensures greater functionality
with lower power dissipation. The ADV728x are available in
−40°C to +85°C temperature range models. This makes the
ADV728x ideal for automotive applications.
See Table 6 for a descriptive list of these video decoder models.
Rev. A | Page 1 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
TABLE OF CONTENTS
Overview ............................................................................................ 1
Identification ............................................................................... 28
Revision History ............................................................................... 3
Status 1 ......................................................................................... 28
Using this Hardware Reference Guide ........................................... 4
Status 2 ......................................................................................... 28
Generic Shorthand Notations ..................................................... 4
Status 3 ......................................................................................... 28
Number Notations ........................................................................ 4
Autodetection Result ................................................................. 29
Register Access Conventions ...................................................... 4
Video Processor .............................................................................. 30
Acronyms and Abbreviations ..................................................... 4
SD Luma Path ............................................................................. 30
Field Function Descriptions........................................................ 5
SD Chroma Path ......................................................................... 30
Video Decoder Models .................................................................... 6
ACE, I2P, and Dither Processing Blocks ................................. 30
Video Input Pins Column ........................................................... 7
Sync Processing .......................................................................... 31
Differential AFE Column ............................................................ 7
VBI Data Recovery ..................................................................... 31
Output Format Column .............................................................. 7
General Setup .............................................................................. 31
Diagnostic Pins Column ............................................................. 7
Color Controls ............................................................................ 34
GPO Pins Column........................................................................ 7
Free-Run Operation ................................................................... 35
Sync Output Pins Column .......................................................... 7
Clamp Operation ........................................................................ 36
ACE Column ................................................................................. 7
Luma Filter .................................................................................. 37
I2P Column ................................................................................... 7
Chroma Filter.............................................................................. 40
Package Column ........................................................................... 7
Gain Operation ........................................................................... 41
Functional Block Diagrams......................................................... 8
Chroma Transient Improvement (CTI) .................................. 44
General Description ....................................................................... 11
Digital Noise Reduction (DNR) and Luma Peaking Filter ... 45
Overview of Analog Front End ................................................ 11
Comb Filters................................................................................ 46
Overview of Standard Definition Processor ........................... 11
IF Filter Compensation ............................................................. 48
Input Networks ............................................................................... 12
Adaptive Contrast Enhancement (ACE)................................. 49
Single-Ended Input Network .................................................... 12
Dither Function .......................................................................... 50
Differential Input Network ....................................................... 12
I2P Function ............................................................................... 50
Short-to-Battery Protection ...................................................... 13
Output Video Format..................................................................... 51
Short-to-Battery (STB) Diagnostics ............................................. 14
Swap Color output...................................................................... 51
Programming Diagnostic Slice Levels ..................................... 15
Output Format Control ............................................................. 51
Programming Diagnostic Interrupt ......................................... 16
ITU-R BT.656 Output .................................................................... 52
Programming INTRQ Hardware Interrupt ............................ 17
ITU-R BT.656 Output Control Registers ................................ 53
Analog Front End ........................................................................... 18
MIPI CSI-2 Tx Output ................................................................... 55
Input Configuration ................................................................... 18
Ultralow Power State.................................................................. 55
Manual Muxing Mode ............................................................... 21
I C Port Description ....................................................................... 57
Antialiasing Filters.......................................................................... 25
Register Maps .............................................................................. 59
Antialiasing Filter Configuration ............................................. 25
PCB Layout Recommendations.................................................... 61
Global Control Registers ............................................................... 26
Analog Interface Inputs ............................................................. 61
Power Saving Mode and Reset Control ................................... 26
Power Supply Decoupling ......................................................... 61
Global Pin Control ..................................................................... 26
VREFN and VREFP Pins .......................................................... 61
General-Purpose Output Controls .......................................... 27
Digital Outputs ........................................................................... 61
Global Status Register .................................................................... 28
Exposed Metal Pad ..................................................................... 61
2
Rev. A| Page 2 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
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Digital Inputs ...............................................................................61
Interrupt/VDP Sub Map Description ...................................... 90
MIPI Outputs (D0P, D0N, CLKP, CLKN) ...............................61
VPP Map Description ................................................................ 99
Power Supply Requirements ..........................................................62
CSI Map Description ................................................................100
I C Register Maps ............................................................................63
References ......................................................................................103
2
User Sub Map Description .........................................................70
User Sub Map 2 Description ......................................................88
REVISION HISTORY
9/14—Rev. 0 to Rev. A
Added ADV7283 (Throughout)...................................................... 1
Changes to Single-Ended Input Network Section and
Differential Input Network Section ..............................................12
Added Short-to-Battery Protection Section ................................13
Changes to Short-to-Battery (STB) Diagnostics Section ...........14
Changes to Table 9 and Table 11 ...................................................15
Added Programming Diagnostic Interrupt Section ...................16
Added Programming INTRQ Hardware Interrupt Section ......17
Changes to Table 27 ........................................................................26
Added Output Format Control Section and Table 75 ................51
Changes to Table 86 and Table 87 .................................................54
Changes to Analog Interface Inputs Section and Digital Outputs
Section ..............................................................................................61
Added Register 0x53 to Register 0x55; Table 106 .......................94
Changes to Register 0x5B; Table 107 ............................................99
5/14—Revision 0: Initial Version
Rev. A | Page 3 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
USING THIS HARDWARE REFERENCE GUIDE
GENERIC SHORTHAND NOTATIONS
REGISTER ACCESS CONVENTIONS
Table 1. Shorthand Notations
Table 3. Register Access Conventions
Notation
ADV728x
Mode
R/W
R
ADV728x-T
ADV728x-M
Description
Refers to the ADV7280, ADV7280-M, ADV7281,
ADV7281-M, ADV7281-MA, ADV7282, ADV7282-M,
and ADV7283 models
Refers to the ADV7280, ADV7281, ADV7282, and
ADV7283 models
Refers to the ADV7280-M, ADV7281-M,
ADV7281-MA, and ADV7282-M models
Table 2. Number Notations
V[X:Y]
0xNN
0bNN
NN
ACRONYMS AND ABBREVIATIONS
Table 4. Acronyms and Abbreviations
NUMBER NOTATIONS
Notation
Bit N
W
Description
Memory location has read and write access.
Memory location is read access only. A read
always returns 0 unless otherwise specified.
Memory location is write access only.
Description
Bits are numbered in little endian format, that is,
the least significant bit of a number is referred to
as Bit 0.
Bit field representation covering Bit X to Bit Y of a
value or a field (V).
Hexadecimal (Base 16) numbers are preceded by
the prefix 0x.
Binary (Base 2) numbers are preceded by the
prefix 0b.
Decimal (Base 10) are represented using no
additional prefixes or suffixes.
Acronym/
Abbreviation
AA
ACE
ADC
AFE
AGC
AIN
CMR
CVBS
AVI
DE
GPO
HS
I2P
IC
I2 C
LLC
LSB
Mbps
ms
MSB
MIPI CSI-2
NC
PLL
Rx
SAV
SFL
SHA
SNR
STB
TTL
Tx
VBI
VS
XTAL
Rev. A | Page 4 of 104
Description
Anti-alias
Adaptive contrast enhancement
Analog-to-digital converter
Analog front end
Automatic gain control
Analog video input pin
Common-mode rejection
Composite video baseband signal
Auxiliary video information
Data enable
General-purpose output
Horizontal synchronization
Interlaced-to-progressive converter (that is,
deinterlacer)
Integrated circuit
Inter integrated circuit
Line locked clock
Least significant bit
Megabits per second
Millisecond
Most significant bit
Mobile industry processor interface camera
serial interface, version 2
No connect
Phase-locked loop
Receiver
Start of active video
Color subcarrier frequency lock
Sample-and-hold
Signal-to-noise ratio
Short-to-battery
Transistor-to-transistor level
Transmitter
Vertical blanking interval
Vertical synchronization
Crystal oscillator
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
FIELD FUNCTION DESCRIPTIONS
In this example
Throughout this reference manual, a series of function tables
are provided. The function of a field is described in a table
preceded by the bit name, a short function description, the I2C
map, the register location within the I2C map, and a detailed
description of the field.
•
The name of the field is DIAG1_SLICE_LEVEL and it is
three bits long.
•
User Sub Map indicates which I2C map or sub map the
field is located in.
•
Address 0x5D is the I2C location of the field within the I2C
Map or Sub Map. The address is stated in a big endian
format (MSB first, LSB last).
•
The address is followed by a description of the field.
•
The first column of the table lists values the field can take
or can be set to. These values are in binary format if not
preceded by 0x or in hexadecimal format if preceded by 0x.
•
The second column of the table describes the operation of
the field (such as DIAG1_SLICE_LEVEL) for each value
the field can be set to.
The detailed description consists of:
•
•
the values the field can take (for a readable field)
the values the field can be set to (for a writable field)
Example Field Function Description
This section provides an example of a field function table
followed by a description of each part of the table.
DIAG1_SLICE_LEVEL[2:0], User Sub Map,
Address 0x5D[4:2]
The DIAG1_SLICE_LEVEL[2:0] bits allow the user to set the
diagnostic slice level for the DIAG1 pin.
Table 5. DIAG1_SLICE_LEVEL[2:0] Settings
DIAG1_SLICE_LEVEL[2:0]
000
001
010
011 (default)
100
101
110
111
Diagnostic Slice Level
75 mV
225 mV
375 mV
525 mV
675 mV
825 mV
975 mV
1.125 V
Rev. A | Page 5 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
VIDEO DECODER MODELS
Table 6 lists the Analog Devices, Inc., video decoders described in this reference manual. Select columns are described in full in the
sections that follow.
Table 6. Description of ADV728x Models
Model
Number
ADV7280
Generic
Shorthand
Notation
ADV728x-T
Video
Input
Pins
4
Differential
AFE
No
Output
Format
TTL
Diagnostic
Pins
No
GPO
Pins
No
Sync
Output
Pins
Yes (2)
ACE
Yes
I2P
Yes
ADV7281
ADV728x-T
4
Yes
TTL
Yes (2)
No
No
Yes
No
ADV7282
ADV728x-T
4
Yes
TTL
Yes (2)
No
No
Yes
Yes
ADV7283
ADV728x-T
6
Yes
TTL
No
No
No
Yes
Yes
ADV7280-M
ADV728x-M
8
No
MIPI CSI-2
No
Yes (3)
No
Yes
Yes
ADV7281-M
ADV728x-M
6
Yes
MIPI CSI-2
Yes (2)
Yes (3)
No
Yes
No
ADV7281-MA
ADV728x-M
8
Yes
MIPI CSI-2
No
Yes (3)
No
Yes
No
ADV7282-M
ADV728x-M
6
Yes
MIPI CSI-2
Yes (2)
Yes (3)
No
Yes
Yes
Rev. A | Page 6 of 104
Package
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
32-lead LFCSP,
5 mm × 5 mm
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
VIDEO INPUT PINS COLUMN
DIAGNOSTIC PINS COLUMN
Indicates how many analog video inputs pins are available on
each ADV728x model.
Indicates if the ADV728x model has diagnostic pins and, if so,
how many. Diagnostic pins are used to monitor analog video
input lines for short-to-battery (STB) events.
•
One analog video input pin is required for single-ended
CVBS inputs.
•
Two analog video input pins are required for pseudo
differential and fully differential CVBS inputs.
•
Two analog video input pins are required for S-Video (YC)
inputs.
•
Three analog video input pins are required for component
(YPbPr) inputs.
DIFFERENTIAL AFE COLUMN
Indicates if the ADV728x model has a differential analog front
end (AFE). A differential AFE is needed to process pseudo
differential and fully differential CVBS inputs.
OUTPUT FORMAT COLUMN
Indicates the digital video output format output from each
ADV728x model.
•
TTL means that the ADV728x model outputs 8-bit YUV
video data over a TTL bus.
•
MIPI CSI-2 indicates that the ADV728x model outputs
8-bit YUV video data over a MIPI CSI-2 bus. This MIPI
CSI-2 bus consists of one differential data channel (D0P,
D0N) and one differential clock channel (CLKP, CLKN).
GPO PINS COLUMN
Indicates if the ADV728x model has general-purpose output
(GPO) pins and, if so, how many. GPO pins are outputs from
the ADV728x that can be used to control other external devices.
SYNC OUTPUT PINS COLUMN
Indicates if the video decoder has synchronization output pins
and, if so, how many. Examples of synchronization output pins
include horizontal synchronization (HS), vertical
synchronization(VS), and subcarrier frequency lock (SFL).
ACE COLUMN
Indicates if the ADV728x model has the ability to perform the
adaptive contrast enhancement (ACE) function.
The ACE function allows dark areas of the video to be
brightened up without saturating bright areas. This is useful for
automotive applications.
I2P COLUMN
Indicates if the ADV728x model has an in-built interlaced-toprogressive converter (I2P). This is also known as a
deinterlacer. The I2P core converts the interlaced video formats
of NTSC (480i) or PAL (576i) into progressive standards (480p,
576p).
PACKAGE COLUMN
Indicates the package in which the video decoder is available.
Rev. A | Page 7 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
FUNCTIONAL BLOCK DIAGRAMS
ADV7280
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
LLC
XTALN
+
SHA
AA
FILTER
VBI SLICER
ADC
–
COLOR
DEMOD
AA
FILTER
I2P
FIFO
HS
ACE
DOWN
DITHER
I2C/CONTROL
REFERENCE
8-BIT
PIXEL DATA
P7 TO P0
INTRQ
11935-001
AIN3
AIN4
AA
FILTER
2D COMB
VS/FIELD/SFL
OUTPUT BLOCK
ANALOG VIDEO
INPUTS
MUX BLOCK
AIN1
AIN2
AA
FILTER
SCLK SDATA ALSB RESET PWRDWN
Figure 1. ADV7280 Functional Block Diagram
ADV7280-M
CLKP
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
MIPI
Tx
XTALN
CLKN
D0P
2D COMB
+
SHA
AA
FILTER
ADC
–
VBI SLICER
COLOR
DEMOD
AA
FILTER
I2P
ACE
DOWN
DITHER
I2C/CONTROL
REFERENCE
SCLK SDATA ALSB RESET PWRDWN
Figure 2. ADV7280-M Functional Block Diagram
Rev. A | Page 8 of 104
GPO0
GPO1
GPO2
INTRQ
11935-002
AA
FILTER
OUTPUT BLOCK
AA
FILTER
MUX BLOCK
ANALOG VIDEO
INPUTS
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
FIFO
D0N
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
ADV7281
UG-637
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
LLC
2D COMB
+
SHA
AA
FILTER
ADC
VBI SLICER
–
COLOR
DEMOD
AA
FILTER
DIAGNOSTICS
DIAG1
ACE
DOWN
DITHER
I2C/CONTROL
REFERENCE
DIAG2
8-BIT
PIXEL DATA
P7 TO P0
INTRQ
11935-003
AA
FILTER
OUTPUT BLOCK
AIN3
AIN4
AA
FILTER
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
FIFO
XTALN
SCLK SDATA ALSB RESET PWRDWN
Figure 3. ADV7281 Functional Block Diagram
ADV7281-M
CLKP
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
MIPI
Tx
XTALN
CLKN
D0P
2D COMB
+
SHA
AA
FILTER
ADC
VBI SLICER
–
COLOR
DEMOD
AA
FILTER
DIAGNOSTICS
DIAG1
ACE
DOWN
DITHER
GPO0
GPO1
GPO2
I2C/CONTROL
REFERENCE
INTRQ
11935-004
AIN5
AIN6
AA
FILTER
OUTPUT BLOCK
AIN3
AIN4
AA
FILTER
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
FIFO
D0N
SCLK SDATA ALSB RESET PWRDWN
DIAG2
Figure 4. ADV7281-M Functional Block Diagram
ADV7281-MA
CLKP
CLOCK PROCESSING BLOCK
XTALP
PLL
MIPI
Tx
ADLLT PROCESSING
XTALN
CLKN
D0P
AA
FILTER
2D COMB
+
SHA
AA
FILTER
DIGITAL
PROCESSING
BLOCK
ADC
–
VBI SLICER
COLOR
DEMOD
AA
FILTER
ACE
DOWN
DITHER
I2C/CONTROL
REFERENCE
SCLK SDATA ALSB RESET PWRDWN
Figure 5. ADV7281-MA Functional Block Diagram
Rev. A | Page 9 of 104
GPO0
GPO1
GPO2
INTRQ
11935-005
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AA
FILTER
OUTPUT BLOCK
10-BIT ADC
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
FIFO
D0N
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
ADV7282
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
LLC
AIN3
AIN4
AA
FILTER
2D COMB
+
AA
FILTER
VBI SLICER
ADC
SHA
–
COLOR
DEMOD
AA
FILTER
DIAGNOSTICS
I2P
DOWN
DITHER
I2C/CONTROL
REFERENCE
DIAG2
DIAG1
ACE
8-BIT
PIXEL DATA
P7 TO P0
INTRQ
11935-006
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
OUTPUT BLOCK
AA
FILTER
AIN1
AIN2
FIFO
XTALN
SCLK SDATA ALSB RESET PWRDWN
Figure 6. ADV7282 Functional Block Diagram
ADV7282-M
CLKP
CLOCK PROCESSING BLOCK
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
MIPI
Tx
XTALN
CLKN
D0P
AIN5
AIN6
+
SHA
AA
FILTER
ADC
–
VBI SLICER
COLOR
DEMOD
AA
FILTER
DIAGNOSTICS
DIAG1
I2P
ACE
DOWN
DITHER
GPO0
GPO1
GPO2
INTRQ
I2C/CONTROL
REFERENCE
11935-007
AIN3
AIN4
2D COMB
AA
FILTER
OUTPUT BLOCK
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AA
FILTER
AIN1
AIN2
FIFO
D0N
SCLK SDATA ALSB RESET PWRDWN
DIAG2
Figure 7. ADV7282-M Functional Block Diagram
ADV7283
CLOCK PROCESSING BLOCK
LLC
XTALP
PLL
ADLLT PROCESSING
10-BIT ADC
DIGITAL
PROCESSING
BLOCK
2D COMB
+
SHA
AA
FILTER
ADC
–
VBI SLICER
COLOR
DEMOD
AA
FILTER
I2P
REFERENCE
ACE
DOWN
DITHER
I2C/CONTROL
SCLK SDATA ALSB RESET PWRDWN
NOTES
1. SHA IS A SAMPLE-AND-HOLD AMPLIFIER CIRCUIT.
Figure 8. ADV7283 Functional Block Diagram
Rev. A | Page 10 of 104
8-BIT
PIXEL DATA
P0 TO P7
INTRQ
11935-108
AIN5
AIN6
AA
FILTER
OUTPUT BLOCK
AIN3
AIN4
AA
FILTER
MUX BLOCK
DIFFERENTIAL
OR
SINGLE-ENDED
ANALOG VIDEO
INPUTS
AIN1
AIN2
FIFO
XTALN
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
GENERAL DESCRIPTION
4.43, and SECAM B/D/G/K/L. The ADV728x can automatically
detect the video standard and process it accordingly.
OVERVIEW OF ANALOG FRONT END
The ADV728x has a five-line, adaptive, 2D comb filter that gives
superior chrominance and luminance separation when decoding
a composite video signal. This highly adaptive filter automatically
adjusts its processing mode according to the video standard and
signal quality without requiring user intervention. Video user
controls, such as brightness, contrast, saturation, and hue, are
also available with these video decoders.
The ADV728x AFE consists of a single high speed, 10-bit
analog-to-digital converter (ADC) that digitizes the analog
video signal before applying it to the standard definition
processor.
The front end also includes a four-channel input mux that
enables multiple composite video signals to be applied to the
ADV728x. Clamp restore circuitry is positioned in front of the
ADC to ensure that the video signal remains within the range of
the converter. An external resistor and capacitor circuit is
required before each analog input channel to ensure that the
input signal is kept within the range of the ADC (see the Input
Networks section). Fine clamping of the video signal is performed
downstream by digital fine clamping within the ADV728x.
The ADV728x implements a patented ADLLT™ algorithm to
track varying video line lengths from sources such as a VCR.
ADLLT enables the ADV728x to track and decode poor quality
video sources, such as VCRs and noisy sources, from tuner outputs
and camcorders. The ADV728x contains a chroma transient
improvement (CTI) processor that sharpens the edge rate of
chroma transitions, resulting in sharper vertical transitions.
Table 7 shows the three ADC clocking rates that are determined
by the video input format to be processed—that is, INSEL[4:0].
These clock rates ensure 4× oversampling per channel for
CVBS, Y/C, and YPbPr modes.
ACE offers improved visual detail using an algorithm to
automatically vary contrast levels in order to enhance picture
detail. This increases the brightness of dark regions of an image
without saturating bright areas of the image.
Table 7. ADC Clock Rates
Down dithering converts the output of the ADV728x from an
8-bit output to a 6-bit output.
Input Format
CVBS
Y/C (S-Video)
YPbPr
1
ADC Clock Rate (MHz)1
57.27
114
172
Oversampling
Rate per Channel
4×
4×
4×
Based on a 28.63636 MHz crystal between the XTAL and XTAL1 pins.
OVERVIEW OF STANDARD DEFINITION
PROCESSOR
The ADV728x is capable of decoding a large selection of baseband
video signals in composite, S-Video, and component formats.
The ADV7281, ADV7281-M, ADV7281-MA, ADV7282,
ADV7282-M, and ADV7283 are also capable of receiving
pseudo-differential and fully differential CVBS inputs. The
video standards supported by the video processor include PAL
B/D/I/G/H, PAL 60, PAL M, PAL N, PAL Nc, NTSC M/J, NTSC
The I2P block on the ADV7280, ADV7280-M, ADV7282,
ADV7282-M, and ADV7283 converts the interlaced video input
into a progressive video output. This is done without a need for
external memory.
The ADV728x can process a variety of vertical blanking interval
(VBI) data services, such as closed captioning (CCAP),
widescreen signaling (WSS), and copy generation management
systems (CGMS). VBI data is transmitted as ancillary data
packets.
The ADV728x is fully Rovi (previously Macrovision) compliant;
detection circuitry enables Type I, Type II, and Type III protection
levels to be identified and reported to the user. The decoder is
also fully robust to all Rovi signal inputs.
Rev. A | Page 11 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
INPUT NETWORKS
An input network (external resistor and capacitor circuit)
is required on the AINx input pins of the ADV728x. The
components of the input network depend on the video format
selected for the analog input.
POSITIVE
INPUT
CONNECTOR
1.3kΩ
SINGLE-ENDED INPUT NETWORK
24Ω
100nF
EXT
ESD
R1
1.3kΩ
430Ω
100nF
AIN2
NEGATIVE
INPUT
CONNECTOR
Figure 10. Differential Input Network
Fully differential video transmission involves transmitting
two complementary CVBS signals. Pseudo differential video
transmission involves transmitting a CVBS signal and a source
ground signal.
Differential video transmission has several key advantages over
single-ended transmission, including the following:
AIN3
51Ω
11935-008
EXT
ESD
VIDEO INPUT
FROM SOURCE
11935-009
• Single-ended CVBS
• YC (S-Video)
• YPrPb
It is recommended that the input network circuit shown in
Figure 9 be placed as close as possible to the AINx pins of the
ADV728x.
VIDEO INPUT
FROM SOURCE
AIN1
430Ω
Figure 9 shows the input network to use on each AINx input pin
of the ADV728x when any of the following video input formats
are used:
INPUT
CONNECTOR
100nF
Figure 9. Single-Ended Input Network
The 24 Ω and 51 Ω resistors supply the 75 Ω end termination
required for the analog video input. These resistors also create a
resistor divider with a gain of 0.68. The resistor divider attenuates
the amplitude of the input analog video and scales the input to the
ADC range of the ADV728x. This allows an input range to the
ADV728x of up to 1.47 V peak-to-peak. Note that amplifiers
within the ADC restore the amplitude of the input signal so that
signal-to-noise ratio (SNR) performance is maintained.
The 100 nF ac coupling capacitor removes the dc bias of the
analog input video before it is fed into the AINx pin of the
ADV728x. The clamping circuitry within the ADV728x restores
the dc bias of the input signal to the optimal level before it is fed
into the ADC of the ADV728x.
The 100 nF ac coupling capacitor limits the current flow into
the ADV728x during short-to-battery (STB) events. Note that
the 24 Ω and 51 Ω resistors can be damaged during STB events
unless high power resistors are used. To avoid the need for high
power resistors, use the differential input network described in
the Differential Input Network section.
DIFFERENTIAL INPUT NETWORK
•
•
•
Inherent small signal and large signal noise rejection
Improved EMI performance
Ability to absorb ground bounce
Resistor R1 provides the RF end termination for the differential
CVBS input lines. For a pseudo differential CVBS input, R1
should have a value of 75 Ω. For a fully differential CVBS input,
R1 should have a value of 150 Ω.
The 1.3 kΩ and 430 Ω resistors create a resistor divider with a
gain of 0.25. The resistor divider attenuates the amplitude of the
input analog video, but increases the input common-mode range
to 4 V peak-to-peak. Note that amplifiers within the ADC
restore the amplitude of the input signal so that SNR
performance is maintained.
The 100 nF ac coupling capacitor removes the dc bias of the analog
input video before it is fed into the AINx pin. The clamping
circuitry within the part restores the dc bias of the input signal
to the optimal level before it is fed into the ADC of the part.
The 100 nF ac coupling capacitors limit the current flow into
the ADV7281, ADV7281-M, ADV7281-MA, ADV7282,
ADV7282-M, and ADV7283 during STB events. See the Shortto-Battery Protection section.
To achieve optimal performance, the 1.3 kΩ and 430 Ω resistors
should be closely matched; that is, all 1.3 kΩ and 430 Ω resistors
should have the same resistance tolerance, and this tolerance
should be as low as possible.
This section applies to the ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, ADV7282-M, and ADV7283
models only.
Figure 10 shows the input network to use when pseudo
differential or fully differential CVBS video is input on the AINx
input pins. It is recommended that the input network circuit
shown in Figure 10 be placed as close as possible to the AINx
pins of the ADV728x.
Rev. A | Page 12 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
SHORT-TO-BATTERY PROTECTION
In differential mode, the ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, ADV7282-M, and ADV7283 are
protected against short-to-battery (STB) events by the external
100 nF ac-coupling capacitors (see Figure 10). The external input
network resistors are sized to be large enough to reduce the
current flow during a STB event, but to be small enough not to
effect the operation of the ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, ADV7282-M, and ADV7283.
UG-637
Choose the power rating of the input network resistors to
withstand the high voltages of STB events. Similarly, choose the
breakdown voltage of the ac-coupling capacitors to be robust to
STB events.
The R1 resistor is protected because no current or limited
current flows through it during an STB event.
In single-ended CVBS, YC, and YPbPr modes, the inputs
network resistors need to have high power ratings to be robust
to STB events
Rev. A | Page 13 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
SHORT-TO-BATTERY (STB) DIAGNOSTICS
Short-to-battery (STB) diagnostic pins are only available on the
ADV7281, ADV7281-M, ADV7282, and ADV7282-M models.
R5
DIAG1
INPUT
CONNECTOR
R4
1.3kΩ
100nF
Resistors R4 and R5 divide down the voltage at the input
connector to protect the DIAGx pin from an STB event. The
DIAGx pin circuitry compares this voltage to a programmable
reference voltage, known as the diagnostic slice level. When the
diagnostic slice level is exceeded, an STB event has occurred.
AIN1
430Ω
EXT
ESD
R1
1.3kΩ
430Ω
100nF
INPUT
CONNECTOR
Figure 11. Diagnostic Connections
AIN2
11935-010
VIDEO INPUT
FROM SOURCE
The ADV7281/ADV7281-M/ADV7282/ADV7282-M senses
an STB event via the DIAG1 and DIAG2 pins. The DIAG1 and
DIAG2 pins can sense an STB event on either the positive or
negative differential input because of the negligible voltage drop
across Resistor R1.
When the DIAGx pin voltage exceeds the diagnostic slice level
voltage, a hardware interrupt is triggered and indicated by the
INTRQ pin. A readback register is also provided, which allows
the user to determine the DIAGx pin on which the STB event
occurred (see the Programming Diagnostic Interrupt section
for more information).
Use Equation 1 to find the trigger voltage for a selected
diagnostic slice level.
VSTB _ TRIGGER
R5 R4
DIAGNOSTIC _SLICE_LEV EL
R5
where:
VSTB_TRIGGER is the minimum voltage required at the input
connector to trigger the STB interrupt on the
ADV7281/ADV7281-M/ADV7282/ADV7282-M.
DIAGNOSTIC_SLICE_LEVEL is the programmable
reference voltage.
Rev. A | Page 14 of 104
(1)
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
DIAG2 Pin
DIAG2_SLICER_PWRDN, User Sub Map,
Address 0x5E[6]
PROGRAMMING DIAGNOSTIC SLICE LEVELS
DIAG1 Pin
DIAG1_SLICER_PWRDN, User Sub Map,
Address 0x5D[6]
This bit powers up or powers down the diagnostic circuitry for
the DIAG1 pin.
Table 8. DIAG1_SLICER_PWRDN Function
DIAG1_SLICER_PWRDN
0
1 (default)
Diagnostic Slice Level
Power up the diagnostic circuitry
for the DIAG1 pin.
Power down the diagnostic
circuitry for the DIAG1 pin.
DIAG1_SLICE_LEVEL[2:0], User Sub Map,
Address 0x5D[4:2]
The DIAG1_SLICE_LEVEL[2:0] bits allow the user to set the
diagnostic slice level for the DIAG1 pin. When a voltage greater
than the diagnostic slice level is seen on the DIAG1 pin, an STB
interrupt is triggered.
For the diagnostic slice level to be set correctly, the diagnostic
circuitry for the DIAG1 pin must be powered up (see Table 8).
Table 9. DIAG1_SLICE_LEVEL[2:0] Settings
DIAG1_SLICE_LEVEL[2:0]
000
001
010
011 (default)
100
101
110
111
1
Diagnostic Slice Level
75 mV1
225 mV1
375 mV1
525 mV
675 mV
825 mV
975 mV
1.125 V
UG-637
This bit powers up or powers down the diagnostic circuitry for
the DIAG2 pin.
Table 10. DIAG2_SLICER_PWRDN Function
DIAG2_SLICER_PWRDN
0
1 (default)
Diagnostic Slice Level
Power up the diagnostic circuitry
for the DIAG2 pin.
Power down the diagnostic
circuitry for the DIAG2 pin.
DIAG2_SLICE_LEVEL[2:0], User Sub Map,
Address 0x5E[4:2]
The DIAG2_SLICE_LEVEL[2:0] bits allow the user to set the
diagnostic slice level for the DIAG2 pin. When a voltage greater
than the diagnostic slice level is seen on the DIAG2 pin, an STB
interrupt is triggered.
For the diagnostic slice level to be set correctly, the diagnostic
circuitry for the DIAG2 pin must be powered up (see Table 10).
Table 11. DIAG2_SLICE_LEVEL[2:0] Settings
DIAG2_SLICE_LEVEL[2:0]
000
001
010
011 (default)
100
101
110
111
1
Diagnostic Slice Level
75 mV1
225 mV1
375 mV1
525 mV
675 mV
825 mV
975 mV
1.125 V
This setting is not recommended for the optimal performance of the
ADV728x.
This setting is not recommended for the optimal performance of the
ADV728x.
Rev. A | Page 15 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
PROGRAMMING DIAGNOSTIC INTERRUPT
This section describes how to program software interrupt bits
to toggle when STB events are detected on the diagnostic pins.
A hardware interrupt indicated by the INTRQ pin will also
trigger when a software interrupt activates. Details on how to
control the INTRQ pin hardware interrupt are given in the
Programming INTRQ Hardwar Interrupt section.
Before programming the software diagnostic interrupts, the
diagnostic circuitry must first be activated and the diagnostic
slice level must be programmed (see Programming Diagnostic
Slice Levels section).
The diagnostic interrupts also need to be unmasked
(that is, activated) using the DIAG_TRI1_L1_MSK and
DIAG_TRI2_L1_MSK bits.
DIAG_TRI1_L1, Diagnostic Interrupt 1 Status,
Interrupt/VDP Sub Map, Address 0x53[1]
This read-only register, shows the status of the interrupt for
Diagnostic Pin 1, that is, if a STB event has occurred on the
DIAG1 pin. An STB event is deemed to have occurred when the
voltage on the DIAG1 pin exceeds the diagnostic slice level (see
the Programming Diagnostic Slice Levels section). When
triggered the DIAG_TRI1_L1 bit will remain high until cleared
(see the Clearing Diagnostic Interrupts).
Table 14. DIAG_TRI1_L1
DIAG_TRI1_L1
0
1
Description
Voltage higher than DIAG1_Slice_Level not
detected on DIAG1 pin
Voltage higher than DIAG1_Slice_Level
detected on DIAG1 pin
When a STB event is detected, the interrupt status bits
DIAG_TRI1_L1 and DIAG_TRI2_L1 will toggle from 0 to 1.
DIAG_TRI2_L1, Diagnostic Interrupt 2 Status,
Interrupt/VDP Sub Map, Address 0x53[3]
The DIAG_TRI1_L1 and DIAG_TRI2_L1 interrupts will
remain at 1 until they are cleared.
This read-only register, shows the status of the interrupt for
Diagnostic Pin 2, that is, if a STB event has occurred on the
DIAG2 pin. An STB event is deemed to have occurred when the
voltage on the DIAG2 pin exceeds the diagnostic slice level (see
the Programming Diagnostic Slice Levels section). When
triggered the DIAG_TRI2_L1 bit will remain high until cleared
(see the Clearing Diagnostic Interrupts).
DIAG_TRI1_L1 and DIAG_TRI2_L1 interrupts are
cleared by writing 1 to the DIAG_TRI1_L1_CLR and
DIAG_TRI2_L1_CLR bits.
Unmasking Diagnostic Interrupts
The DIAG_TRI1_L1_MSK and DIAG_TRI2_L1_MSK bits are
used to unmask (that is, to activate) the diagnostic interrupts.
Table 15. DIAG_TRI2_L1 Function
DIAG_TRI2_L1
0
DIAG_TRI1_L1_MSK, Unmask Diagnostic Interrupt 1,
Interrupt/VDP Sub Map, Address 0x55[1]
Description
Voltage higher than DIAG2_SLICE_LEVEL not
detected on the DIAG2 pin
Voltage higher than DIAG2_SLICE_LEVEL
detected on the DIAG2 pin
This unmasks (that is, activates) the STB interrupt for
Diagnostic Pin 1.
1
Table 12. DIAG_TRI1_L1_MSK Function
Clearing Diagnostic Interrupts
DIAG_TRI1_L1_MSK
Description
0 (default)
1
Mask DIAG_TRI1_L1 interrupt
Unmask DIAG_TRI1_L1 interrupt
The DIAG_TRI1_L1_CLR and DIAG_TRI2_L1_CLR bits are
used to clear the diagnostic interrupts.
DIAG_TRI1_L1_CLR, Clear Diagnostic Interrupt 1,
Interrupt/VDP Sub Map, Address 0x54[1]
DIAG_TRI2_L1_MSK, Unmask Diagnostic Interrupt 2,
Interrupt/VDP Sub Map, Address 0x55[3]
This bit clears the interrupt for Diagnostic Pin 1.
This unmasks (that is, activates) the STB interrupt for
Diagnostic Pin 2.
The DIAG_TRI1_L1_CLR is a self-clearing, write only bit.
Table 16. DIAG_TRI1_L1_CLR Function
Table 13. DIAG_TRI2_L1_MSK Function
DIAG_TRI2_L1_MSK
Description
0 (default)
1
Mask DIAG_TRI2_L1 interrupt
Unmask (that is, activate) DIAG_TRI2_L1
interrupt
Diagnostic Interrupt Status
The DIAG_TRI1_L1 and DIAG_TRI2_L1 bits give the status of
the diagnostic interrupt (that is, if a STB event has occurred or
not).
DIAG_TRI1_L1_CLR
0 (default)
1
Description
Do not clear DIAG_TRI1_L1
Clear DIAG_TRI1_L1
DIAG_TRI2_L1_CLR , Clear Diagnostic Interrupt 2,
Interrupt/VDP Sub Map, Address 0x54[3]
This bit clears the interrupt for Diagnostic Pin 2.
The DIAG_TRI2_L1_CLR is a self-clearing, write only bit.
Table 17. DIAG_TRI2_L1_CLR Function
DIAG_TRI2_L1_CLR
0 (default)
1
Rev. A | Page 16 of 104
Description
Do not clear DIAG_TRI2_L1
Clear DIAG_TRI2_L1
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
PROGRAMMING INTRQ HARDWARE INTERRUPT
When a software interrupt is unmasked and triggered, a
hardware interrupt indicated by the INTRQ pin will also
automatically trigger.
INTRQ_DUR_SEL[1:0], Interrupt/VDP Sub Map,
Address 0x40[7:6]
The INTRQ_DUR_SEL[1:0] bits are used to set the duration of
the INTRQ interrupt output.
An example on how to program a software interrupt is given in
the Programming Diagnostic Interrupt section. Other software
interrupts can be programmed in a similar manner. See
Table 106 for other software interrupts available on the
ADV728x.
The INTRQ_OP_SEL[1:0] bits are used to program the INTRQ
hardware interrupt to drive out in a number of different ways
(for example, drive the INTRQ pin high, drive the INTRQ pin
low, or make the INTRQ pin open drain).
The INTRQ_DUR_SEL[1:0] bits are used to set the duration of
the INTRQ interrupt output.
The duration of the INTRQ interrupt output is given in terms
of crystal clock periods. Because a 28.63636 MHz crystal is used
a clock period corresponds to approximately 35 ns.
The INTRQ interrupt output can also be set to be active until
cleared. In this mode of operation, the INTRQ pin will be active
until every active software interrupt has been cleared.
Table 19. INTRQ_DUR_SEL[1:0] Settings
INTRQ_DUR_SEL[1:0]
00 (default)
01
INTRQ_OP_SEL[1:0], Interrupt/VDP Sub Map,
Address 0x40[1:0]
10
The INTRQ_OP_SEL[1:0] bits are used to program the INTRQ
hardware interrupt to drive out in a number of different ways
when active.
11
In open-drain mode, the INTRQ is at DVDDIO voltage when
not active and drives low when active. In open-drain mode,
the INTRQ pin requires a pull-up resistor to DVDDIO in order
for the INTRQ interrupt to work correctly.
In drive low when active mode, the INTRQ is at DVDDIO
voltage when not active and drives low when active. In drive
low when active mode, the INTRQ pin does not require a pullup resistor to DVDDIO.
In drive high when active mode, the INTRQ is at GND when
not active and drives high to DVDDIO when active. In drive
high when active mode, the INTRQ pin does not require a pullup resistor to DVDDIO.
Table 18. INTRQ_OP_SEL[1:0] Settings
INTRQ_OP_SEL[1:0]
00 (default)
01
10
11
UG-637
Description
Open drain
Drive low when active
Drive high when active
Reserved
Rev. A | Page 17 of 104
Description
3 crystal periods ( approximately
0.105 µs)
15 crystal periods (approximately
0.525 µs)
63 crystal periods (approximately
2.205 µs)
Active until cleared
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
ANALOG FRONT END
INPUT CONFIGURATION
INSEL[4:0], Input Control, Address 0x00[4:0]
The following two steps are key for configuring the ADV728x to
correctly decode the input video.
The INSEL bits allow the user to select the input format. They also
configure the standard definition processor core to process CVBS,
differential CVBS, S-Video (Y/C), or component (YPrPb) format.
1.
2.
Use INSEL[4:0] to configure the routing and format decoding
(CVBS, Y/C, or YPrPb).
If the input requirements are not met using the INSEL[4:0]
options, the analog input muxing section must be configured
manually to correctly route the video from the analog
input pins to the ADC. The standard definition processor
block, which decodes the digital data, should be configured
to process the CVBS, Y/C, or YPrPb format. This is performed
by the INSEL[4:0] selection.
INSEL[4:0] has predefined analog input routing schemes that
do not require manual mux programming (see Table 20). This
allows the user to route the various video signal types to the
decoder and select them using INSEL[4:0] only. The added
benefit is that if, for example, the CVBS input is selected, the
remaining channels are powered down.
Rev. A | Page 18 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
Table 20. INSEL[4:0]
Analog Input for
ADV7281 and
ADV7282
CVBS input on AIN1
CVBS input on AIN2
Reserved
Reserved
Reserved
Reserved
CVBS input on AIN3
CVBS input on AIN4
Y input on AIN1,
C input on AIN2
Reserved
Analog Input for
ADV7281-M,
ADV7282-M, and
ADV7283
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
Reserved
Reserved
CVBS input on AIN5
CVBS input on AIN6
Y input on AIN1,
C input on AIN2
Y input on AIN3,
C input on AIN4
Reserved
INSEL
[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
Video
Format
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
CVBS
Y/C (S-Video)
01001
Y/C (S-Video)
01010
Y/C (S-Video)
Analog Input for
ADV7280
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
Reserved
Reserved
Reserved
Reserved
Y input on AIN1,
C input on AIN2
Y input on AIN3,
C input on AIN4
Reserved
01011
Y/C (S-Video)
Reserved
01100
YPrPb
01101
YPrPb
Y input on AIN1,
Pb input on AIN2,
Pr input on AIN3
Reserved
01110
Differential
CVBS
Differential
CVBS
Differential
CVBS
Differential
CVBS
Reserved
Analog Input for
ADV7280-M
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
CVBS input on AIN5
CVBS input on AIN6
CVBS input on AIN7
CVBS input on AIN8
Y input on AIN1,
C input on AIN2
Y input on AIN3,
C input on AIN4
Y input on AIN5,
C input on AIN6
Y input on AIN7,
C input on AIN8
Y input on AIN1,
Pb input on AIN2,
Pr input on AIN3
Y input on AIN4,
Pb input on AIN5,
Pr input on AIN6
Reserved
Reserved
Reserved
Positive on AIN1,
Negative on AIN2
Reserved
Reserved
Reserved
Reserved
Positive on AIN1,
Negative on AIN2
Positive on AIN3,
Negative on AIN4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Positive on AIN3,
Negative on AIN4
Reserved
Positive on AIN5,
Negative on AIN6
Reserved
01111
10000
10001
10010
to
11111
1
Reserved
Y input on AIN3,
C input on AIN4
Reserved1
Reserved1
Y input on AIN5,
C input on AIN6
Y input on AIN1,
Pb input on AIN2,
Pr input on AIN3
Reserved
Analog Input for
ADV7281-MA
CVBS input on AIN1
CVBS input on AIN2
CVBS input on AIN3
CVBS input on AIN4
CVBS input on AIN5
CVBS input on AIN6
CVBS input on AIN7
CVBS input on AIN8
Y input on AIN1,
C input on AIN2
Y input on AIN3,
C input on AIN4
Y input on AIN5,
C input on AIN6
Y input on AIN7,
C input on AIN8
Y input on AIN1,
Pb input on AIN2,
Pr input on AIN3
Y input on AIN4,
Pb input on AIN5,
Pr input on AIN6
Positive on AIN1,
Negative on AIN2
Positive on AIN3,
Negative on AIN4
Positive on AIN5,
Negative on AIN6
Positive on AIN7,
Negative on AIN8
Reserved
Note that it is possible for the ADV7281/ADV7282 to receive YPbPr formats; however, a manual muxing scheme is required. In this case luma(Y) is fed in on AIN1 or AIN3,
blue chroma (Pb) is fed in on AIN4 and red chroma (Pr) is fed in on AIN2. See the Manual Muxing Mode section for more information.
Rev. A | Page 19 of 104
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
MAN_MUX_EN
MAN_MUX_EN
AIN1
AIN2
AIN3
AIN4
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
MUX_0[3:0]
AIN2
AIN4
AIN6
AIN2
AIN4
MUX_0[3:0]
MUX_0N[3:0]
MUX_1[3:0]
ADC
ADC
AIN2
AIN4
AIN6
MUX_1[3:0]
AIN2
AIN3
MUX_2[3:0]
MUX_2[3:0]
11935-011
AIN2
AIN3
11935-014
Figure 12. Manual Muxing Scheme for ADV7280
MAN_MUX_EN
AIN2
AIN3
AIN6
MAN_MUX_EN
MUX_0[3:0]
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
MUX_1[3:0]
ADC
AIN2
AIN4
AIN6
AIN8
MUX_2[3:0]
MUX_0[3:0]
MUX_0N[3:0]
Figure 13. Manual Muxing Scheme for ADV7280-M
MAN_MUX_EN
AIN1
AIN2
AIN3
AIN4
AIN2
AIN4
AIN2
AIN4
MUX_0[3:0]
ADC
AIN2
AIN4
AIN5
AIN6
AIN8
MUX_1[3:0]
AIN2
AIN3
AIN6
MUX_2[3:0]
Figure 16. Manual Muxing Scheme for ADV7281-MA
MUX_ON[3:0]
ADC
MUX_1[3:0]
AIN2
11935-013
MUX_2[3:0]
Figure 14. Manual Muxing Scheme for ADV7281 and ADV7282
Rev. A | Page 20 of 104
11935-015
AIN2
AIN4
AIN5
AIN6
AIN8
Figure 15. Manual Muxing Scheme for ADV7281-M, ADV7282-M, and ADV7283
11935-012
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
MANUAL MUXING MODE
UG-637
Note that MUX0N cannot be powered down independently.
MUX0N can only be powered down when MUX0, MUX1, and
MUX2 are all powered down.
In manual muxing mode, the user selects the analog input pin
(for example, AIN1, AIN2, and so on) that is to be processed by
the ADC of the ADV728x. MAN_MUX_EN (User Map,
Register 0xC4, Bit 7) must be set to 1 to enable the following
muxing blocks:
Manual Muxing of the ADV7280
MAN_MUX_EN must be set to 1 (User Map,
Register 0xC4, Bit 7).
CVBS can only be processed by MUX0.
Y/C can only be processed by MUX0 and MUX1. MUX0
processes the luma (Y) and MUX1 processes the chroma
(C).
Component (YPbPr) signals can only be processed by
MUX0(Y), MUX1(Pb), and MUX2(Pr).
MUX0[3:0], ADC mux configuration, Address 0xC3[3:0]
MUX0N[3:0], ADC mux configuration, Address 0x60[3:0]
(MUX0N[3:0] applies only to the ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, and ADV7282-M models)
MUX1[3:0], ADC mux configuration, Address 0xC3[7:4]
MUX2[3:0], ADC mux configuration, Address 0xC4[3:0]
The four mux sections are controlled by the signal buses,
MUX0/MUX0N/MUX2/MUX3[2:0].
The tables in this section explain the control words used.
The input signal that contains the timing information (HS and VS)
must be processed by MUX0. For example, in a Y/C input
configuration, connect MUX0 to the Y channel and MUX1 to
the C channel.
MUX0N is only used to process the negative input for fully
differential or pseudo differential CVBS inputs.
When one or more muxes are not used to process video, such as
the CVBS input, the idle mux and associated channel clamps and
buffers should be powered down (see the description of
Register 0x3A in the User Map in Table 104).
Table 21 shows the settings for manual muxing of the
ADV7280.
Manual Muxing of the ADV7280-M
Table 22 shows the settings for manual muxing of the
ADV7280-M.
MAN_MUX_EN must be set to 1 (User Map, Register 0xC4,
Bit 7).
CVBS can only be processed by MUX0.
Y/C can only be processed by MUX0 and MUX1. MUX0
processes the luma (Y) and MUX1 processes the chroma
(C).
Component (YPbPr) signals can only be processed by
MUX0(Y), MUX1(Pb), and MUX2(Pr).
Table 21. Manual Mux Settings for ADC of ADV7280
MUX0[3:0]
0000
0001
0010
0011
0100
0101 to 1111
ADC Connection
No connect
AIN1
AIN2
AIN3
AIN4
No connect
MUX1[3:0]
0000
0001
0010
0011
0100
0101 to 1111
ADC Connected To
No connect
No connect
AIN2
No connect
AIN4
No connect
MUX2[3:0]
0000
0001
0010
0011
0100
0101 to 1111
ADC Connection
No connect
No connect
AIN2
AIN3
No connect
No connect
ADC Connection
No connect
No connect
AIN2
No connect
AIN4
AIN5
AIN6
No connect
AIN8
No connect
MUX2[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
ADC Connection
No connect
No connect
AIN2
AIN3
No connect
No connect
AIN6
No connect
No connect
No connect
Table 22. Manual Mux Settings for ADC of ADV7280-M
MUX0[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
ADC Connection
No connect
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
No connect
MUX1[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
Rev. A | Page 21 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Manual Muxing of the ADV7281 and ADV7282
•
Table 24 shows the settings for manual muxing of the ADV7281
and ADV7282.
•
•
•
•
MAN_MUX_EN must be set to 1 (User Map, Register
0xC4, Bit 7)
CVBS can only be processed by MUX0.
Differential CVBS can only be processed by MUX0
(positive channel) and MUX0N (negative channel).
UG-637
Y/C can only be processed by MUX0 and MUX1. MUX0
processes the luma (Y) and MUX1 processes the chroma
(C).
Component (YPbPr) signals can only be processed by
MUX0(Y), MUX1(Pb), and MUX2(Pr). For example, Y
can be fed in on AIN1 or AIN3 for MUX0. Pb can be fed in
on AIN4 for MUX1. Pr can be fed in on AIN2 for MUX2.
Table 23 gives an example of how to program the
ADV7281/ADV7282 to accept YPrPb inputs.
Table 23. Register Writes to Program the ADV7281 or ADV7282 to Accept YPbPr Input
Register Map
User Map (0x40 or 0x42)
Register Address
0x00
0xC3
Register Write
0x0C
0x87
0xC4
0x82
Description
Program INSEL for YPbPr input.
Program manual muxing. Y is fed in on AIN3 for MUX0. Pb is fed in
on AIN4 for MUX1.
Enable manual muxing. Pr is fed in on AIN2 for MUX2.
Table 24. Manual Mux Settings for ADC of ADV7281 and ADV7282
MUX0[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to
1111
ADC Connection
No connect
AIN1
AIN2
No connect
No connect
No connect
No connect
AIN3
AIN4
No connect
MUX0N[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to
1111
ADC Connection
No connect
No connect
AIN2
No connect
No connect
No connect
No connect
No connect
AIN4
No connect
MUX1[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to
1111
Rev. A | Page 22 of 104
ADC Connection
No connect
No connect
AIN2
No connect
No connect
No connect
No connect
No connect
AIN4
No connect
MUX2[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to
1111
ADC Connection
No connect
No connect
AIN2
No connect
No connect
No connect
No connect
No connect
No connect
No connect
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
Manual Muxing of the ADV7281-M, ADV7282-M, and ADV7283
Table 25 shows the settings for manual muxing of the ADV7281-M, ADV7282-M, and ADV7283.
•
•
•
•
•
MAN_MUX_EN must be set to 1 (User Map, Register 0xC4, Bit 7)
CVBS can only be processed by MUX0.
Differential CVBS can only be processed by MUX0 (positive channel) and MUX0N (negative channel).
Y/C can only be processed by MUX0 and MUX1. MUX0 processes the luma (Y) and MUX1 processes the chroma (C).
Component (YPbPr) signals can only be processed by MUX0(Y), MUX1(Pb), and MUX2(Pr).
Table 25. Manual Mux Settings for ADC of ADV7281-M, ADV7282-M, and ADV7283
MUX0[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC Connection
No connect
AIN1
AIN2
AIN3
AIN4
No connect
No connect
AIN5
AIN6
No connect
MUX0N[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC Connection
No connect
No connect
AIN2
No connect
AIN4
No connect
No connect
No connect
AIN6
No connect
MUX1[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
Rev. A | Page 23 of 104
ADC Connection
No connect
No connect
AIN2
No connect
AIN4
No connect
No connect
No connect
AIN6
No connect
MUX2[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC Connection
No connect
No connect
AIN2
AIN3
No connect
No connect
No connect
No connect
No connect
No connect
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Manual Muxing of the ADV7281-MA
Table 26 shows the settings for manual muxing of the ADV7281-MA.
•
•
•
•
•
MAN_MUX_EN must be set to 1 (User Map, Register 0xC4, Bit 7).
CVBS can only be processed by MUX0.
Differential CVBS can only be processed by MUX0 (positive channel) and MUX0N (negative channel).
Y/C can only be processed by MUX0 and MUX1. MUX0 processes the luma (Y) and MUX1 processes the chroma (C).
Component (YPbPr) signals can only be processed by MUX0(Y), MUX1(Pb), and MUX2(Pr).
Table 26. Manual Mux Settings for ADC of ADV7281-MA
MUX0[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC
Connection
No connect
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
No connect
MUX0N[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC
Connection
No connect
No connect
AIN2
No connect
AIN4
No connect
AIN6
No connect
AIN8
No connect
MUX1[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
Rev. A | Page 24 of 104
ADC
Connection
No connect
No connect
AIN2
No connect
AIN4
AIN5
AIN6
No connect
AIN8
No connect
MUX2[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001 to 1111
ADC
Connection
No connect
No connect
AIN2
AIN3
No connect
No connect
AIN6
No connect
No connect
No connect
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
ANTIALIASING FILTERS
The ADV728x has optional on-chip antialiasing (AA) filters
on each of the four channels that are multiplexed to the ADC
(see Figure 17).
AA_FILT_EN[1], Antialiasing Filter Enable,
Address 0xF3[1]
The filters are designed for standard definition video up to
10 MHz bandwidth. Figure 18 and Figure 19 show the filter
magnitude and phase characteristics.
When AA_FILT_EN[1] is set to 1, AA Filter 2 is enabled.
AA_FILT_EN[2], Antialiasing Filter Enable,
Address 0xF3[2]
The antialiasing filters are enabled by default and the selection
of INSEL[4:0] determines which filters are powered up at any
given time. For example, if CVBS mode is selected, the filter
circuits for the remaining input channels are powered down to
conserve power. However, the antialiasing filters can be disabled
or bypassed using the AA_FILT_MAN_OVR control.
AA
FILTER 1
MUX BLOCK
AA
FILTER 2
AA
FILTER 3
When AA_FILT_EN[2] is set to 0, AA Filter 3 is disabled.
When AA_FILT_EN[2] is set to 1, AA Filter 3 is enabled.
AA_FILT_EN[3], Antialiasing Filter Enable,
Address 0xF3[3]
When AA_FILT_EN[3] is set to 0, AA Filter 4 is disabled.
When AA_FILT_EN[3] is set to 1, AA Filter 4 is enabled.
10-BIT, 86MHz
ADC
0
+
SHA
–
–4
ADC
–8
NOTES
1. EIGHT ANALOG INPUTS ARE ONLY AVAILABLE ON THE
ADV7280-M AND ADV7281-MA MODELS.
SIX ANALOG INPUTS ARE AVAILABLE ON ADV7281-M,
ADV7282-M, AND ADV7283.
FOUR ANALOG INPUTS ARE AVAILABLE ON ADV7280,
ADV7281, AND ADV7282.
MAGNITUDE (dB)
AA
FILTER 4
11935-016
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN7
AIN8
When AA_FILT_EN[1] is set to 0, AA Filter 2 is disabled.
–12
–16
–20
–24
–28
Figure 17. Antialias Filter Configuration
–36
1k
AA_FILT_MAN_OVR, Antialiasing Filter Override,
Address 0xF3[4]
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 18. Antialiasing Filter Magnitude Response
This feature allows the user to override the antialiasing filters
on/off settings, which are automatically selected by INSEL[4:0].
0
–10
AA_FILT_EN[3:0], Antialiasing Filter Enable,
Address 0xF3[3:0]
–20
–30
–40
PHASE (Degrees)
These bits allow the user to enable or disable the antialiasing
filters on each of the three input channels multiplexed to the
ADC. When disabled, the analog signal bypasses the AA filters
and is routed directly to the ADC.
–50
–60
–70
–80
–90
–100
–110
–120
When AA_FILT_EN[0] is set to 0, AA Filter 1 is disabled.
–130
–140
When AA_FILT_EN[0] is set to 1, AA Filter 1 is enabled.
–150
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 19. Antialiasing Filter Phase Response
Rev. A | Page 25 of 104
100M
11935-018
AA_FILT_EN[0], Antialiasing Filter Enable,
Address 0xF3[0]
10k
11935-017
–32
ANTIALIASING FILTER CONFIGURATION
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
GLOBAL CONTROL REGISTERS
The register control bits listed in this section affect the entire
chip.
POWER SAVING MODE AND RESET CONTROL
Power Down
PWRDWN, Address 0x0F[5]
The ADV728x can be placed into a chip-wide, power-down mode
by setting the PWRDWN bit or by using the PWRDWN pin.
The power-down mode stops the clock from entering the digital
section of the chip, thereby freezing its operation. No I2C bits are
lost during power-down mode. The PWRDWN bit also affects
the analog blocks and switches them into low current modes.
The I2C interface is unaffected and remains operational in
power-down mode.
When PWRDWN is set to 0, the chip is operational. When
PWRDWN is set to 1 (default), the ADV728x is in a chip-wide,
power-down mode.
Reset, Chip Reset, Address 0x0F[7]
Setting this bit, which is equivalent to controlling the RESET
pin on the ADV728x, issues a full chip reset. All I2C registers
are reset to their default/power-up values. Note that some register
bits do not have a reset value specified; they keep their last
written value. Those bits are marked as having a reset value of
x in the register tables (see Table 104 and Table 106). After the
reset sequence, the part immediately starts to acquire the
incoming video signal.
After setting the reset bit (or initiating a reset via the RESET pin),
the part returns to the default for its primary mode of operation.
All I2C bits are loaded with their default values, making this bit
self-clearing. Executing a software reset takes approximately 2 ms.
However, it is recommended to wait 5 ms before any further I2C
writes are performed.
The I2C master controller receives a no acknowledge condition
on the ninth clock cycle when chip reset is implemented.
When the reset bit is set to 0 (default), operation is normal.
When the reset bit is set to 1, the reset sequence starts.
GLOBAL PIN CONTROL
Drive Strength Selection (I2C)
DR_STR_S[1:0], Address 0xF4[1:0]
The DR_STR_S[1:0] bits allow the user to select the strength of
the I2C signal output drivers. This affects the drive strength for
the SDA and SCL pins.
Table 27. DR_STR_S Function
DR_STR_S[1:0]
00
01 (default)
10
11
1
Description
Low drive strength (1×)1
Medium low drive strength (2×)
Medium high drive strength (3×)
High drive strength (4×)
The low drive strength setting is not recommended for the optimal
performance of the ADV728x.
Rev. A | Page 26 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
GENERAL-PURPOSE OUTPUT CONTROLS
When GPO[0] is set to 1, Logic 1 is output from the GPO0 pin.
The ADV7280-M, ADV7281-M, ADV7281-MA, and
ADV7282-M have three general-purpose outputs (GPO).
GPO[1]
When GPO[1] is set to 0 (default), Logic 0 is output from the
GPO1 pin.
Three GPOs
These outputs allow the user to control other devices in a
system via the I2C port of the device.
When GPO[1] is set to 1, Logic 1 is output from the GPO1 pin.
GPO[2]
GPO_ENABLE, General-Purpose Output Enable,
User Sub Map, Address 0x59[4]
When GPO[2] is set to 0 (default), Logic 0 is output from the
GPO2 pin.
When GPO_ENABLE is set to 0 (default), all GPO pins are
tristated.
When GPO[2] is set to 1, Logic 1 is output from the GPO2 pin.
When GPO_ENABLE is set to 1, all GPO pins are in a driven
state. The polarity output from each GPO is controlled by
GPO[3:0].
GPO[2:0], General-Purpose Outputs, User Sub Map,
Address 0x59[2:0]
Individual control of the four GPO ports is achieved using
GPO[2:0].
GPO_ENABLE must be set to 1 for the GPO pins to become active.
GPO[0]
When GPO[0] is set to 0 (default), Logic 0 is output from the
GPO0 pin.
Table 28. General-Purpose Output Truth Table
GPO_ENABLE
0
1
1
1
1
1
1
1
1
1
2
GPO[2:0]
XXX1
000
001
010
011
100
101
110
111
X indicates any value.
Z indicates high impedance.
Rev. A | Page 27 of 104
GPO2
Z2
0
0
0
0
1
1
1
1
GPO1
Z2
0
0
1
1
0
0
1
1
GPO0
Z2
0
1
0
1
0
1
0
1
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
GLOBAL STATUS REGISTER
Four registers provide summary information about the video
decoder. The IDENT register allows the user to identify the
revision code of the ADV728x. The other three registers
(Address 0x10, Address 0x12, and Address 0x13) contain
status bits from the ADV728x.
IDENTIFICATION
IDENT[7:0], Address 0x11[7:0]
This is the register identification of the ADV728x revision. Table 29
describes the various versions of the ADV728x.
Table 29. IDENT CODE
IDENT[7:0]
0x40
0x41
0x42
Description
Pre-release Silicon
Pre-release Silicon
Released Silicon
STATUS 2
Status 2[7:0], Address 0x12[7:0]
Table 31. Status 2 Function
Status 2[7:0]
0
Bit Name
MVCS DET
1
MVCS T3
2
MV PS DET
3
4
5
6
7
MV AGC DET
LL NSTD
FSC NSTD
Reserved
Reserved
Description
Detected Rovi (previously
Macrovision) color striping
Rovi color striping protection;
conforms to Type 3 if high, Type
2 if low
Detected Rovi pseudo sync
pulses
Detected Rovi AGC pulses
Line length is nonstandard
fSC frequency is nonstandard
STATUS 1
STATUS 3
Status 1[7:0], Address 0x10[7:0]
Status 3[7:0], Address 0x13[7:0]
Table 32. Status 3 Function
This read-only register provides information about the internal
status of the ADV728x.
See the CIL[2:0], Count into Lock, Address 0x51[2:0] section
and the COL[2:0], Count Out of Lock, Address 0x51[5:3] section
for details on timing.
Depending on the setting of the FSCLE bit, the status registers are
based solely on horizontal timing information or on the horizontal
timing and lock status of the color subcarrier. See the FSCLE,
fSC Lock Enable, Address 0x51[7] section.
Table 30. Status 1 Function
Status 1[7:0]
0
1
2
3
4
5
6
7
Bit Name
IN_LOCK
LOST_LOCK
FSC_LOCK
FOLLOW_PW
AD_RESULT[0]
AD_RESULT[1]
AD_RESULT[2]
COL_KILL
Description
In lock (now)
Lost lock (since last read)
fSC locked (now)
AGC follows peak white algorithm
Result of autodetection
Result of autodetection
Result of autodetection
Color kill active
Status 3[7:0]
0
Bit Name
INST_HLOCK
1
2
Reserved
SD_OP_50Hz
3
4
Reserved
FREE_RUN_ACT
5
STD FLD LEN
6
Interlaced
7
PAL_SW_LOCK
Rev. A | Page 28 of 104
Description
Horizontal lock indicator
(instantaneous)
Flags whether 50 Hz or 60 Hz is
present at output
Reserved
Flags if ADV728x has entered
free-run mode (see Free-Run
Operation section)
Field length is correct for
currently selected video
standard
Interlaced video detected
(field sequence found)
Reliable sequence of
swinging bursts detected
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
Table 33. AD_RESULT Function
AUTODETECTION RESULT
AD_RESULT[2:0], Address 0x10[6:4]
The AD_RESULT[2:0] bits report back on the findings from the
ADV728x autodetection block. See the General Setup section for
more information on enabling the autodetection block and the
Autodetection of SD Modes section for more information on
how to configure it.
AD_RESULT[2:0]
000
001
010
011
100
101
110
111
Rev. A | Page 29 of 104
Description
NTSC M/NTSC J
NTSC 4.43
PAL M
PAL 60
PAL B/PAL G/PAL H/PAL I/PAL D
SECAM
PAL Combination N
SECAM 525
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
VIDEO PROCESSOR
STANDARD DEFINITION PROCESSOR
DIGITIZED CVBS
DIGITIZED Y (YC)
DIGITIZED CVBS
DIGITIZED C (YC)
VBI DATA
RECOVERY
LUMA
DIGITAL
FINE
CLAMP
CHROMA
DIGITAL
FINE
CLAMP
CHROMA
DEMOD
STANDARD
AUTODETECTION
SLLC
CONTROL
LUMA
FILTER
LUMA
GAIN
CONTROL
LUMA
RESAMPLE
SYNC
EXTRACT
LINE
LENGTH
PREDICTOR
RESAMPLE
CONTROL
CHROMA
FILTER
CHROMA
GAIN
CONTROL
CHROMA
RESAMPLE
LUMA
2D COMB
AV
CODE
INSERTION
ACE
DITHER
I2P
SD PROCESSOR
OUTPUT
MEASUREMENT
BLOCK (≥ I2C)
CHROMA
2D COMB
VIDEO DATA
PROCESSING
BLOCK
INTERLACED TO
PROGRESSIVE
CONVERTER BLOCK,
ADV7280, ADV7280-M
ADV7282 AND
ADV7282-M ONLY
fSC
RECOVERY
11935-019
MACROVISION
DETECTION
Figure 20. Block Diagram of Video Processor
Figure 20 shows a block diagram of the video processor within the
ADV728x. The ADV728x can handle standard definition video
in CVBS, Y/C, and YPrPb formats. It can be divided into a
luminance and chrominance path. If the input video is of a
composite type (CVBS), both processing paths are fed with the
CVBS input. The output from the video processor is fed into
a MIPI CSI-2 Tx block in the ADV728x-M models. In the
ADV728x-T models, the output of the video processor is output
from the part in an ITU-R BT.656 video stream.
SD LUMA PATH
The input signal is processed by the following blocks:
Luma digital fine clamp. This block uses a high precision
algorithm to clamp the video signal.
Luma filter. This block contains a luma decimation filter
(YAA) with a fixed response and some shaping filters
(YSH) that have selectable responses.
Luma gain control. The AGC can operate on a variety of
different modes, including gain based on the depth of the
horizontal sync pulse, peak white mode, and fixed manual
gain.
Luma resample. To correct for line length errors as well as
dynamic line length changes, the data is digitally resampled.
Luma 2D comb. The 2D comb filter provides Y/C separation.
AV code insertion. At this point, the decoded luma (Y) signal
is merged with the retrieved chroma values. AV codes can
be inserted (as per ITU-R BT.656).
SD CHROMA PATH
ACE, I2P, AND DITHER PROCESSING BLOCKS
The input signal is processed by the following blocks:
Chroma demodulation. This block employs a color subcarrier
(fSC) recovery unit to regenerate the color subcarrier for
any modulated chroma scheme. The demodulation block
then performs an AM demodulation for PAL and NTSC,
and an FM demodulation for SECAM.
Chroma filter. This block contains a chroma decimation filter
(CAA) with a fixed response and some shaping filters (CSH)
that have selectable responses.
Chroma gain control. AGC can operate on several different
modes, including gain based on the color subcarrier
amplitude, gain based on the depth of the horizontal sync
pulse on the luma channel, or fixed manual gain.
Chroma resample. The chroma data is digitally resampled
to keep it perfectly aligned with the luma data. The
resampling is done to correct for static and dynamic line
length errors of the incoming video signal.
Chroma 2D comb. The 2D, five line, super adaptive comb
filter provides high quality Y/C separation if the input
signal is CVBS.
AV code insertion. At this point, the demodulated chroma
(Cr and Cb) signal is merged with the retrieved luma values.
AV codes can be inserted (as per ITU-R BT.656).
Chroma digital fine clamp. This block uses a high precision
algorithm to clamp the video signal.
Rev. A | Page 30 of 104
Adaptive contrast enhancement (ACE). This block offers
improved visual detail by using an algorithm to automatically vary the contrast levels to enhance picture detail.
See the Adaptive Contrast Enhancement section.
Dither. When enabled, this block converts the digital output
of the ADV728x from 8-bit pixel data down to 6-bit pixel
data. This function makes it easier for the ADV728x to
communicate with some LCD panels. See the Dither
Function section.
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
•
Interlaced-to-progressive converter (I2P). This block is
only available in the ADV7280, ADV7280-M, ADV7282,
ADV7282-M, and ADV7283 models. This block converts
interlaced video formats (480i and 576i) into progressive
video formats (480p and 576p).
SYNC PROCESSING
The ADV728x extracts syncs embedded in the analog input
video signal. The sync extraction is optimized to support
imperfect video sources, such as VCRs with head switches.
The actual algorithm used employs a coarse detection based on
a threshold crossing, followed by a more detailed detection using
an adaptive interpolation algorithm. The raw sync information
is sent to a line length measurement and prediction block. The
output of this is then used to drive the digital resampling
section to ensure that the ADV728x outputs 720 active pixels
per line.
The sync processing on the ADV728x also includes the following
specialized postprocessing blocks that filter and condition the
raw sync information retrieved from the digitized analog video:
•
•
VSYNC processor. This block provides extra filtering of the
detected VSYNCs to improve vertical lock.
HSYNC processor. The HSYNC processor is designed to
filter incoming HSYNCs that were corrupted by noise,
providing much improved performance for video signals
with a stable time base, but poor SNR.
VBI DATA RECOVERY
The ADV728x can retrieve the following information from the
input video:
•
•
•
•
•
Wide screen signaling (WSS)
Copy generation management system (CGMS)
Closed captioning (CCAP)
Rovi protection presence
Teletext
Autodetection of SD Modes
To guide the autodetect system of the ADV728x, individual
enable bits are provided for each of the supported video standards.
Setting the relevant bit to 0 inhibits the standard from being
detected automatically. Instead, the system chooses the closest of
the remaining enabled standards. The results of the autodetection
block can be read back via the status registers (see the Global
Status Register section for more information).
VID_SEL[3:0], Address 0x02[7:4]
Table 34. VID_SEL Function
VID_SEL[3:0]
0000 (default)
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Autodetect PAL B/PAL G/PAL H/PAL I/PAL D,
NTSC J (no pedestal), SECAM
Autodetect PAL B/PAL G/PAL H/PAL I/PAL D,
NTSC M (pedestal), SECAM
Autodetect PAL N (pedestal), NTSC J
(no pedestal), SECAM
Autodetect PAL N (pedestal), NTSC M
(pedestal), SECAM
NTSC J
NTSC M
PAL 60
NTSC 4.43
PAL B/PAL G/PAL H/PAL I/PAL D
PAL N = PAL B/PAL G/PAL H/PAL I/PAL D (with
pedestal)
PAL M (without pedestal)
PAL M
PAL Combination N
PAL Combination N (with pedestal)
SECAM
SECAM
AD_SEC525_EN, SECAM 525 Autodetect Enable,
Address 0x07[7]
Setting AD_SEC525_EN to 0 (default) disables the autodetection
of a 525-line system with a SECAM style, FM-modulated color
component.
The ADV728x is also capable of automatically detecting the
incoming video standard with respect to the following:
•
•
•
UG-637
Setting AD_SEC525_EN to 1 enables the detection of a SECAM
style, FM-modulated color component.
Color subcarrier frequency
Field rate
Line rate
The ADV728x can configure itself to support PAL B/PAL D/
PAL I/PAL G/PAL H, PAL M, PAL N, PAL Combination N,
NTSC M/NTSC J, SECAM 50 Hz/60 Hz, NTSC 4.43, and PAL 60.
GENERAL SETUP
Video Standard Selection
The VID_SEL[3:0] bits (Address 0x02[7:4]) allow the user to
force the digital core into a specific video standard. This is not
necessary under normal circumstances. The VID_SEL[3:0] bits
default to an autodetection mode that supports PAL, NTSC,
SECAM, and variants thereof.
AD_SECAM_EN, SECAM Autodetect Enable,
Address 0x07[6]
Setting AD_SECAM_EN to 0 (default) disables the autodetection
of SECAM.
Setting AD_SECAM_EN to 1 enables the detection of SECAM.
AD_N443_EN, NTSC 4.43 Autodetect Enable,
Address 0x07[5]
Setting AD_N443_EN to 0 disables the autodetection of NTSC
style systems with a 4.43 MHz color subcarrier.
Setting AD_N443_EN to 1 (default) enables the detection of
NTSC style systems with a 4.43 MHz color subcarrier.
Rev. A | Page 31 of 104
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
AD_P60_EN, PAL 60 Autodetect Enable, Address 0x07[4]
Setting AD_P60_EN to 0 disables the autodetection of PAL
systems with a 60 Hz field rate.
Setting AD_P60_EN to 1 (default) enables the detection of PAL
systems with a 60 Hz field rate.
AD_PALN_EN, PAL N Autodetect Enable,
Address 0x07[3]
Setting AD_PALN_EN to 0 (default) disables the detection of
the PAL N standard.
Setting AD_PALN_EN to 1 enables the detection of the PAL N
standard.
AD_PALM_EN, PAL M Autodetect Enable,
Address 0x07[2]
Setting AD_PALM_EN to 0 (default) disables the autodetection
of PAL M.
SFL_INV, Subcarrier Frequency Lock Inversion,
Address 0x41[6] (ADV7280 Only)
This bit controls the behavior of the PAL switch bit in the
SFL (genlock telegram) data stream. Implemented to solve
compatibility issues with video encoders, it solves two
problems.
First, the PAL switch bit is meaningful only in PAL. Some encoders
(including Analog Devices encoders) also look at the state of
this bit in NTSC.
Second, there was a design change in Analog Devices encoders
from ADV717x to ADV719x. The older versions used the SFL
(genlock telegram) bit directly, whereas the newer ones invert
the bit prior to using it. The reason for this is that the inversion
compensated for the one line delay of an SFL (genlock telegram)
transmission.
AD_NTSC_EN, NTSC Autodetect Enable,
Address 0x07[1]
As a result, for the ADV717x and ADV73xx encoders, the PAL
switch bit in the SFL (genlock telegram) must be set to 0 for NTSC
to work. For the older video encoders, the PAL switch bit in the
SFL must be set to 1 to work in NTSC. If the state of the PAL switch
bit is wrong, a 180° phase shift occurs.
Setting AD_NTSC_EN to 0 (default) disables the detection of
standard NTSC.
In a decoder/encoder back-to-back system in which SFL is used,
this bit must be set up properly for the specific encoder used.
Setting AD_NTSC_EN to 1 enables the detection of standard NTSC.
Setting SFL_INV to 0 (default) makes the part SFL compatible
with the ADV717x and ADV73xx video encoders.
Setting AD_PALM_EN to 1 enables the detection of PAL M.
AD_PAL_EN, PAL B/PAL D/PAL I/PAL G/PAL H
Autodetect Enable, Address 0x07[0]
Setting SFL_INV to 1 makes the part SFL compatible with the
older video encoders.
Setting AD_PAL_EN to 0 (default) disables the detection of
standard PAL.
Setting AD_PAL_EN to 1 enables the detection of standard PAL.
Rev. A | Page 32 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
SELECT THE RAW LOCK SIGNAL
SRLS
1
0
FILTER THE RAW LOCK SIGNAL
CIL[2:0], COL[2:0]
0
1
fSC LOCK
COUNTER INTO LOCK
COUNTER OUT OF LOCK
STATUS 1[0]
MEMORY
STATUS 1[1]
11935-020
TIME_WIN
FREE_RUN
UG-637
TAKE fSC LOCK INTO ACCOUNT
FSCLE
Figure 21. Lock Related Signal Path
Lock Related Controls
CIL[2:0], Count into Lock, Address 0x51[2:0]
Lock information is presented to the user through Bits[2:0] of the
Status 1 register (see the Status 1[7:0], Address 0x10[7:0] section).
Figure 21 outlines the signal flow and the controls that are available
to influence the way the lock status information is generated.
CIL[2:0] determines the number of consecutive lines for which
the lock condition must be true before the system switches into
the locked state and reports this via Status 1[1:0]. The bit counts
the value in lines of video.
SRLS, Select Raw Lock Signal, Address 0x51[6]
Table 35. CIL Function
Using the SRLS bit, the user can choose between two sources for
determining the lock status (per Bits[1:0] in the Status 1 register).
See Figure 21.
CIL[2:0]
000
001
010
011
100 (default)
101
110
111
•
•
The TIME_WIN signal is based on a line-to-line evaluation
of the horizontal synchronization pulse of the incoming
video. It reacts quickly.
The FREE_RUN signal evaluates the properties of the
incoming video over several fields, taking vertical
synchronization information into account.
Number of Video Lines
1
2
5
10
100
500
1000
100,000
COL[2:0], Count Out of Lock, Address 0x51[5:3]
Setting SRLS to 0 (default) selects the FREE_RUN signal (to
evaluate over several fields).
Setting SRLS to 1 selects the TIME_WIN signal (to evaluate on a
line-to-line basis).
FSCLE, fSC Lock Enable, Address 0x51[7]
The FSCLE bit allows the user to choose whether the status of
the color subcarrier loop is taken into account when the overall
lock status is determined and presented via Bits[1:0] in the
Status 1 register. This bit must be set to 0 when operating the
ADV728x in YPrPb component mode to generate a reliable
HLOCK status bit.
When FSCLE is set to 0 (default), the overall lock status is
dependent only on horizontal sync lock.
When FSCLE is set to 1, the overall lock status is dependent on
horizontal sync lock and fSC lock.
COL[2:0] determines the number of consecutive lines for which
the out-of-lock condition must be true before the system switches
into the unlocked state and reports this via Status 1[1:0]. It counts
the value in lines of video.
Table 36. COL Function
COL[2:0]
000
001
010
011
100 (default)
101
110
111
Rev. A | Page 33 of 104
Number of Video Lines
1
2
5
10
100
500
1000
100,000
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
COLOR CONTROLS
SD_OFF_Cr[7:0], SD Offset Cr Channel, Address 0xE2[7:0]
These registers allow the user to control picture appearance,
including control of active data in the event of video being lost.
These controls are independent of any other controls. For instance,
brightness control is independent of picture clamping, although
both controls affect the dc level of the signal.
This register allows the user to select an offset for the Cr channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register.
Table 41. SD_OFF_Cr Function
This register allows the user to control contrast adjustment of
the picture.
SD_OFF_Cr[7:0]
0x80 (default)
0x00
0xFF
Table 37. CON Function
BRI[7:0], Brightness Adjust, Address 0x0A[7:0]
CON[7:0], Contrast Adjust, Address 0x08[7:0]
CON[7:0]
0x80 (default)
0x00
0xFF
Description
Gain on luma channel = 1
Gain on luma channel = 0
Gain on luma channel = 2
This register controls the brightness of the video signal. It allows
the user to adjust the brightness of the picture.
Table 42. BRI Function
SD_SAT_Cb[7:0], SD Saturation Cb Channel,
Address 0xE3[7:0]
This register allows the user to control the gain of the Cb channel
only, which in turn adjusts the saturation of the picture.
Table 38. SD_SAT_Cb Function
SD_SAT_Cb[7:0]
0x80 (default)
0x00
0xFF
BRI[7:0]
0x00 (default)
0x7F
0x80
HUE[7:0], Hue Adjust, Address 0x0B[7:0]
HUE[7:0] has a range of ±90°, with 0x00 equivalent to an
adjustment of 0°. The resolution of HUE[7:0] is 1 bit = 0.7°.
This register allows the user to control the gain of the Cr channel
only, which in turn adjusts the saturation of the picture.
Table 39. SD_SAT_Cr Function
The hue adjustment value is fed into the AM color demodulation
block. Therefore, it applies only to video signals that contain
chroma information in the form of an AM-modulated carrier
(CVBS or Y/C in PAL or NTSC). It does not affect SECAM
and does not work on component video inputs (YPrPb).
Table 43. HUE Function
Description
Gain on Cr channel = 0 dB
Gain on Cr channel = −42 dB
Gain on Cr channel = +6 dB
HUE[7:0]
0x00 (default)
0x7F
0x80
SD_OFF_Cb[7:0], SD Offset Cb Channel, Address 0xE1[7:0]
This register allows the user to select an offset for the Cb channel
only and to adjust the hue of the picture. There is a functional
overlap with the HUE[7:0] register (Address 0x0B).
Table 40. SD_OFF_Cb Function
SD_OFF_Cb[7:0]
0x80 (default)
0x00
0xFF
Description
Offset of the luma channel = 0 IRE
Offset of the luma channel = +30 IRE
Offset of the luma channel = −30 IRE
This register contains the value for the color hue adjustment. It
allows the user to adjust the hue of the picture.
Description
Gain on Cb channel = 0 dB
Gain on Cb channel = −42 dB
Gain on Cb channel = +6 dB
SD_SAT_Cr[7:0], SD Saturation Cr Channel,
Address 0xE4[7:0]
SD_SAT_Cr[7:0]
0x80 (default)
0x00
0xFF
Description
0 mV offset applied to the Cr channel
−312 mV offset applied to the Cr channel
+312 mV offset applied to the Cr channel
Description
0 mV offset applied to the Cb channel
−312 mV offset applied to the Cb channel
+312 mV offset applied to the Cb channel
Rev. A | Page 34 of 104
Description (Adjust Hue of the Picture)
Phase of the chroma signal = 0°
Phase of the chroma signal = −90°
Phase of the chroma signal = +90°
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
DEF_Y[5:0], Default Value Y, Address 0x0C[7:2]
Single Color Test Pattern
When the ADV728x loses lock on the incoming video signal or
when there is no input signal, the DEF_Y[5:0] register allows
the user to specify a default luma value to be output. This value
is used under the following conditions:
In this mode, the ADV728x device can be set to output the
default luma and chroma data stored in DEF_Y and DEF_C
(see the Color Controls section).
In this mode, the ADV728x device outputs the 100% color bars
pattern.
If the DEF_VAL_AUTO_EN bit is set to 1 and the
ADV728x has lost lock to the input video signal, this is the
intended mode of operation (automatic mode).
If the DEF_VAL_EN bit is set to 1, regardless of the lock
status of the video decoder, this is a forced mode that may
be useful during configuration.
The DEF_Y[5:0] values define the six MSBs of the output video.
The remaining LSBs are padded with 0s. For example, in 8-bit
mode, the output is Y[7:0] = (DEF_Y[5:0], 0, 0).
For DEF_Y[5:0], 0x0D (blue) is the default value for Y.
Color Bars Test Pattern
Luma Ramp Test Pattern
In this mode, the ADV728x device outputs a series of vertical
bars. Each vertical bar is progressively brighter than the vertical
bar to its left.
Boundary Box Test Pattern
In this mode, the ADV728x device outputs a black screen with
a 1-pixel depth white border (see Figure 22).
Register 0x0C has a default value of 0x36.
DEF_C[7:0], Default Value C, Address 0x0D[7:0]
The DEF_C[7:0] register complements the DEF_Y[5:0] value. It
defines the four MSBs of Cr and Cb values to be output if:
The DEF_VAL_AUTO_EN bit is set to high and the
ADV728x cannot lock to the input video (automatic mode).
The DEF_VAL_EN bit is set to high (forced output).
11935-021
Figure 22. Boundary Box Free-Run Test Pattern
The data that is finally output from the ADV728x for the chroma
side is Cr[4:0] = (DEF_C[7:4]) and Cb[4:0] = (DEF_C[3:0]).
DEF_VAL_AUTO_EN, Default Value Automatic Enable,
User Map, Address 0x0C[1]
For DEF_C[7:0], 0x7C (blue) is the default value for Cr and Cb.
This bit enables the ADV728x to enter free-run mode if it
cannot decode the video signal that has been input.
FREE-RUN OPERATION
Table 44. DEF_VAL_AUTO_EN Function
Free-run mode provides the user with a stable clock and
predictable data if the input signal cannot be decoded, for
example, if input video is not present.
DEF_VAL_AUTO_EN
0
The ADV728x automatically enters free-run mode if the input
signal cannot be decoded. The user can prevent this operation
by setting the DEF_VAL_AUTO_EN to 0. When the DEF_VAL_
AUTO_EN bit is set to 0, the ADV728x outputs noise if it
cannot decode the input video. It is recommended that the user
keep DEF_VAL_AUTO_EN set to 1.
The user can force free-run mode by setting the DEF_VAL_EN
bit to 1. This can be a useful tool in debugging system level issues.
The VID_SEL[3:0] bits can be used to force the video standard
output in free-run mode (see the Video Standard Selection
section).
1 (default)
DEF_VAL_EN, Default Value Enable, User Map,
Address 0x0C[0]
This bit forces free-run mode.
Table 45. DEF_VAL_EN Function
DEF_VAL_EN
0 (default)
1
The user can also specify which data is output in free-run mode
with the FREE_RUN_PAT_SEL bits. The following test patterns
can be set using this function:
Description
The ADV728x outputs noise if it loses
lock with the inputted video signal.
The ADV728x enters free-run mode if it
loses lock with the inputted video signal.
Single color
Color bars
Luma ramp
Boundary box
Rev. A | Page 35 of 104
Description
Do not force free-run mode (that is, free-run
mode dependent on DEF_VAL_AUTO_EN)
Force free-run mode
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
The clamping can be divided into two sections.
FREE_RUN_PAT_SEL[2:0], Free Run Pattern Select, User
Map, Address 0x14[2:0]
This function selects what data is output in free-run mode.
Table 46. FREE_FUN_PAT_SEL Function
001
010
101
Description
Single color set by DEF_C and DEF_Y
controls; see the Color Controls section
100% color bars
Luma ramp. Note that to display
properly, the DEF_C register should be
set to 0x88; see the Color Controls
section
Boundary box
The primary task of the analog clamping circuits is to ensure that
the video signal stays within the valid 1.0 V ADC input window
so that the analog-to-digital conversion can take place. The current
sources in the AFE correct the dc level of the ac-coupled input
video signal before it is fed into the ADC. The digitized data from
the ADC is then fed into the video processor. The digital fine
clamp block within the video processor corrects for any remaining
variation in the dc level. The video processor also sends clamp
control signals to the current sources. This feedback loop fine
tunes the current clamp operation and compensates for any noise
on the input video signal. This maintains the dc level of the
video signal during normal operation.
CLAMP OPERATION
The input video is ac-coupled into the ADV728x. This has the
advantage of protecting the ADV728x from STB events. However,
the dc value of the input video needs to be restored. This process
is referred to as clamping the video. This section explains the
general process of clamping on the ADV728x in both singleended and differential modes. This section also shows the different
ways in which a user can configure clamp operation behavior.
Differential CVBS Clamping Operation
This section applies to the ADV7281, ADV7281-M,
ADV7281-MA, ADV7282, ADV7282-M, and ADV7283
models only.
Single-Ended CVBS Clamp Operation
The ADV728x uses a combination of current sources and a digital
processing block for clamping as shown in Figure 23.
The analog processing channel shown is replicated three times
inside the IC. While only a single channel is needed for a singleended CVBS signal, two independent channels are needed for
Y/C (SVHS) type signals, and three independent channels are
needed to allow component signals (YPrPb) to be processed.
The differential clamping operation works in a similar manner
to the single-ended clamping operation (see the Single-Ended
CVBS Clamp Operation section). In differential mode, a coarse
clamp pulls the positive and negative video input to a commonmode voltage VCML (see Figure 24). The feedback loop
between the current clamps and the video processor fine tunes
this coarse dc offset and makes the clamping robust to noise on the
video input. Note that the current clamps are controlled within
a feedback loop between the AFE and the video processor; the
coarse clamps are not.
ADV728x
ANALOG FRONT END (AFE)
EXTERNAL AC
COUPLING
CAPACITOR
CLAMP CONTROL
ADC
CURRENT
SOURCE
CLAMPS
DATA PREPROCESSOR
VIDEO PROCESSOR
WITH DIGITAL
FINE CLAMP
11935-022
SINGLE-ENDED
ANALOG
VIDEO INPUT
DIGITAL CORE
Figure 23. Single-Ended Clamping Overview
ADV728x
ANALOG FRONT END (AFE)
EXTERNAL AC
COUPLING
CAPACITOR
CLAMP CONTROL
COARSE
CLAMP
ADC
POSITIVE
DIFFERENTIAL ANALOG
VIDEO INPUT
NEGATIVE
DIFFERENTIAL ANALOG
VIDEO INPUT
EXTERNAL AC
COUPLING
CAPACITOR
VCML
DIGITAL CORE
DATA PREPROCESSOR
CURRENT
SOURCE
CLAMPS
VIDEO PROCESSOR
WITH DIGITAL
FINE CLAMP
CURRENT
SOURCE
CLAMPS
COARSE
CLAMP
CLAMP CONTROL
Figure 24. Differential Clamping Overview
Rev. A | Page 36 of 104
11935-023
FREE_RUN_PAT_SEL
000 (default)
Clamping before the ADC (analog domain): current sources
and voltage sources.
Clamping after the ADC (digital domain): digital processing
block.
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Clamp Operation Controls
•
The following sections describe the I2C signals that can be used
to influence the behavior of the clamping block.
CCLEN, Current Clamp Enable, Address 0x14[4]
The current clamp enable bit allows the user to switch off all the
current sources in the AFE simultaneously. This may be useful
if the incoming analog video signal is clamped externally.
When CCLEN is set to 0, the current sources are switched off.
When CCLEN is set to 1 (default), the current sources are
enabled.
DCT[1:0], Digital Clamp Timing, Address 0x15[6:5]
The clamp timing register determines the time constant of the
digital fine clamp circuitry. Note that the digital fine clamp reacts
quickly because it immediately corrects any residual dc level error
for the active line. The time constant from the digital fine clamp
must be much quicker than the one from the analog blocks.
By default, the time constant of the digital fine clamp is adjusted
dynamically to suit the currently connected input signal.
Table 47. DCT Function
DCT[1:0]
00 (default)
01
10
11
Description
Slow (TC = 1 sec)
Medium (TC = 0.5 sec)
Fast (TC = 0.1 sec)
Determined by ADV728x, depending on the
input video parameters
Luma shaping filters (YSH). The shaping filter block is a
programmable low-pass filter with a wide variety of responses.
It can be used to reduce selectively the luma video signal
bandwidth (needed prior to scaling, for example). For some
video sources that contain high frequency noise, reducing
the bandwidth of the luma signal improves visual picture
quality. If the video is low-pass filtered, a follow-on video
compression stage can work more efficiently.
The ADV728x has two responses for the shaping filter: one
that is used for good quality composite, component, and SVHS
type sources; and a second for nonstandard CVBS signals.
The YSH filter responses also include a set of notches for
PAL and NTSC. However, using the comb filters for Y/C
separation is recommended.
Digital resampling filter. This block allows dynamic
resampling of the video signal to alter parameters such as
the time base of a line of video. Fundamentally, the resampler
is a set of low-pass filters. The actual response is chosen by the
system with no requirement for user intervention.
Figure 26 through Figure 29 show the overall response of all filters
together. Unless otherwise noted, the filters are set into a typical
wideband mode.
Y Shaping Filter
DCFE, Digital Clamp Freeze Enable, Address 0x15[4]
This register bit allows users to freeze the digital clamp loop at
any time (do their own clamping). Users can disable the current
sources for analog clamping via the appropriate register bits,
wait until the digital clamp loop settles, and then freeze it via
the DCFE bit.
When DCFE is set to 0 (default), the digital clamp is operational.
When DCFE is set to1, the digital clamp loop is frozen.
LUMA FILTER
Data from the digital fine clamp block is processed by the three
sets of filters that follow. The data format at this point is CVBS
for CVBS input or luma only for Y/C and YPrPb input formats.
•
•
UG-637
Luma antialias filter (YAA). The ADV728x receives video at
a rate of 28.6363 MHz. (In the case of 4× oversampled video,
the ADC samples at 57.27 MHz, and the first decimation is
performed inside the DPP filters. Therefore, the data rate
into the ADV728x is always 28.6363 MHz.) The ITU-R
BT.601 recommends a sampling frequency of 13.5 MHz.
The luma antialias filter decimates the oversampled video
using a high quality linear phase, low-pass filter that preserves
the luma signal while, at the same time, attenuating out-ofband components. The luma antialias filter (YAA) has a
fixed response.
For input signals in CVBS format, the luma shaping filters play
an essential role in removing the chroma component from a
composite signal. Y/C separation must aim for the best possible
crosstalk reduction while still retaining as much bandwidth
(especially on the luma component) as possible. High quality
Y/C separation can be achieved by using the internal comb
filters of the ADV728x. Comb filtering, however, relies on the
frequency relationship of the luma component (multiples of the
video line rate) and the color subcarrier (fSC). For good quality
CVBS signals, this relationship is known; the comb filter algorithms
can be used to separate luma and chroma with high accuracy.
In the case of nonstandard video signals, the frequency relationship
may be disturbed, and the comb filters may not be able to remove
all crosstalk artifacts in the best fashion without the assistance
of the shaping filter block.
An automatic mode is provided that allows the ADV728x to
evaluate the quality of the incoming video signal and select the
filter responses in accordance with the signal quality and video
standard. YFSM, WYSFMOVR, and WYSFM allow the user to
manually override the automatic decisions in part or in full.
The luma shaping filter has the following control bits.
•
•
Rev. A | Page 37 of 104
YSFM[4:0] allows the user to manually select a shaping
filter mode (applied to all video signals) or to enable an
automatic selection (depending on video quality and video
standard).
WYSFMOVR allows the user to manually override the
WYSFM decision.
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
The Y-shaping filter mode operates as follows:
WYSFM[4:0] allows the user to select a different shaping
filter mode for good quality composite (CVBS), component
(YPrPb), and SVHS (Y/C) input signals.
In automatic mode, the system preserves the maximum possible
bandwidth for good CVBS sources (because they can be successfully
combed) as well as for luma components of YPrPb and Y/C
sources (because they need not be combed). For poor quality
signals, the system selects from a set of proprietary shaping
filter responses that complements comb filter operation to
reduce visual artifacts.
If the YSFM settings specify a filter (that is, YSFM is set
to values other than 00000 or 00001), the chosen filter is
applied to all video, regardless of its quality.
In automatic selection mode, the notch filters are only used
for bad quality video signals. For all other video signals,
wideband filters are used.
WYSFMOVR, Wideband Y Shaping Filter Override,
Address 0x18[7]
Setting the WYSFMOVR bit enables the use of the WYSFM[4:0]
settings for good quality video signals. For more information on
luma shaping filters, see the Y Shaping Filter section and the
flowchart shown in Figure 25.
The decisions of the control logic are shown in Figure 25.
YSFM[4:0], Y Shaping Filter Mode, Address 0x17[4:0]
The Y shaping filter mode bits allow the user to select from
a wide range of low-pass and notch filters. When switched in
automatic mode, the filter selection is based on other register
selections, such as detected video standard, as well as properties
extracted from the incoming video itself, such as quality and time
base stability. The automatic selection always selects the widest
possible bandwidth for the video input encountered (see Table 48).
When WYSFMOVR is set to 0, the shaping filter for good quality
video signals is selected automatically.
When WYSFMOVR is set to 1 (default), it enables manual
override via WYSFM[4:0].
SET YSFM
YES
YSFM IN AUTO MODE?
00000 OR 00001
NO
VIDEO
QUALITY
BAD
GOOD
AUTO SELECT LUMA
SHAPING FILTER TO
COMPLEMENT COMB
USE YSFM SELECTED
FILTER REGARDLESS OF
VIDEO QUALITY
WYSFMOVR
1
0
SELECT WIDEBAND
FILTER AS PER
WYSFM[4:0]
SELECT AUTOMATIC
WIDEBAND FILTER
Figure 25. YSFM and WYSFM Control Flowchart
Rev. A | Page 38 of 104
11935-024
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
Table 48. YSFM Function
YSFM[4:0]
00000
00001 (default)
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
Description
Automatic selection including a wide notch
response (PAL/NTSC/SECAM)
Automatic selection including a narrow notch
response (PAL/NTSC/SECAM)
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
PAL NN1
PAL NN2
PAL NN3
PAL WN1
PAL WN2
NTSC NN1
NTSC NN2
NTSC NN3
NTSC WN1
NTSC WN2
NTSC WN3
Reserved
UG-637
WYSFM[4:0], Wideband Y Shaping Filter Mode,
Address 0x18[4:0]
The WYSFM[4:0] bits allow the user to manually select a shaping
filter for good quality video signals, such as CVBS with stable
time base, luma component of YPrPb, and luma component of
Y/C. The WYSFM bits are active only if the WYSFMOVR bit is
set to 1. See the general discussion of the shaping filter settings in
the Y Shaping Filter section.
Table 49. WYSFM Function
WYSFM[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011 (default)
10100 to 11111
Rev. A | Page 39 of 104
Description
Reserved, do not use
Reserved, do not use
SVHS 1
SVHS 2
SVHS 3
SVHS 4
SVHS 5
SVHS 6
SVHS 7
SVHS 8
SVHS 9
SVHS 10
SVHS 11
SVHS 12
SVHS 13
SVHS 14
SVHS 15
SVHS 16
SVHS 17
SVHS 18 (CCIR 601)
Reserved, do not use
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
The filter plots in Figure 26 show the SVHS 1 (narrowest) to
SVHS 18 (widest) shaping filter settings. Figure 28 shows the PAL
notch filter responses. The NTSC notch filter responses are shown
in Figure 29.
0
–10
–20
–20
–30
–40
–60
–80
–100
–40
–120
0
2
4
–50
6
8
10
12
FREQUENCY (MHz)
11935-026
AMPLITUDE (dB)
0
AMPLITUDE (dB)
COMBINED Y ANTIALIAS, SVHS LOW-PASS FILTERS,
Y RESAMPLE
COMBINED Y ANTIALIAS, CCIR MODE SHAPING FILTER,
Y RESAMPLE
Figure 27. Combined Y Antialias, CCIR Mode Shaping Filter
–60
0
2
4
6
8
10
12
FREQUENCY (MHz)
COMBINED Y ANTIALIAS, PAL NOTCH FILTERS,
Y RESAMPLE
11935-025
–70
0
Figure 26. Y SVHS Combined Responses
–10
•
Figure 30 shows the overall response of all filters together.
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
FREQUENCY (MHz)
11935-027
•
Chroma antialias filter (CAA). The ADV728x oversamples the
CVBS by a factor of 4 and the chroma/YPrPb by a factor of 2.
A decimating filter (CAA) is used to preserve the active video
band and to remove any out-of-band components. The
CAA filter has a fixed response.
Chroma shaping filters (CSH). The shaping filter block
(CSH) can be programmed to perform a variety of low-pass
responses. It can be used to selectively reduce the bandwidth
of the chroma signal for scaling or compression.
Digital resampling filter. This block allows dynamic
resampling of the video signal to alter parameters,0 such as
the time base of a line of video. Fundamentally, the resampler
is a set of low-pass filters. The actual response is chosen by
the system without user intervention.
–20
Figure 28. Combined Y Antialias, PAL Notch Filters
COMBINED Y ANTIALIAS, NTSC NOTCH FILTERS,
Y RESAMPLE
0
–10
–20
–30
–40
–50
–60
–70
0
2
4
6
8
10
12
FREQUENCY (MHz)
Figure 29. Combined Y Antialias Filter, NTSC Notch Filters
Rev. A | Page 40 of 104
11935-028
•
AMPLITUDE (dB)
Data from the digital fine clamp block is processed by the three
sets of filters that follow. The data format at this point is CVBS for
CVBS (or differential CVBS) inputs, chroma only for Y/C, or U/V
interleaved for YPrPb input formats.
AMPLITUDE (dB)
CHROMA FILTER
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
As shown in Figure 33, the ADV728x can decode a video signal
as long as it fits into the ADC window. The components for this
are the amplitude of the input signal and the dc level it resides on.
The dc level is set by the clamping circuitry (see the Clamp
Operation section).
COMBINED C ANTIALIAS, C SHAPING FILTER,
C RESAMPLER
0
–10
–20
If the amplitude of the analog video signal is too high, clipping
may occur, resulting in visual artifacts. The analog input range
of the ADC, together with the clamp level, determines the
maximum supported amplitude of the video signal.
–40
–60
0
1
2
3
4
5
6
FREQUENCY (MHz)
11935-029
–50
Figure 30. Chroma Shaping Filter Responses
CSFM[2:0], C Shaping Filter Mode, Address 0x17[7:5]
The C shaping filter mode bits allow the user to select from a
range of low-pass filters for the chrominance signal. When
switched in automatic mode, the widest filter is selected based
on the video standard/format and user choice (see the 000 and
001 settings in Table 50).
Figure 31 and Figure 32 show the typical voltage divider networks
required to keep the input video signal within the allowed range of
the ADC, 0 V to 1 V. The circuit in Figure 31 should be placed
before all the single-ended analog inputs to the ADV728x, and
place the circuit in Figure 32 before all the differential inputs to
the ADV728x.
Note differential inputs can only be applied directly to the
ADV7281, ADV7281-M, ADV7281-MA, ADV7282, ADV7282-M,
and ADV7283 models.
ANALOG VIDEO
INPUT
AIN
24Ω
Table 50. CSFM Function
CSFM[2:0]
000 (default)
001
010
011
100
101
110
111
100nF
11935-030
–30
51Ω
Figure 31. Single-Ended Input Voltage Divider Network
Description
Autoselection 1.5 MHz bandwidth
Autoselection 2.17 MHz bandwidth
SH1
SH2
SH3
SH4
SH5
Wideband mode
ANALOG_INPUT
CVBS_1P
1.3kΩ
0.1µF
AINx
430Ω
75Ω
ANALOG_INPUT
CVBS_1N
1.3kΩ
430Ω
0.1µF
AINx
11935-031
ATTENUATION (dB)
UG-637
Figure 32. Differential Input Voltage Divider Network
Figure 30 shows the responses of SH1 (narrowest) to SH5
(widest) in addition to the wideband mode (shown in red).
The minimum supported amplitude of the input video is
determined by the ability of the ADV728x to retrieve horizontal
and vertical timing and to lock to the color burst, if present.
GAIN OPERATION
The gain control within the ADV728x is done on a purely digital
basis. The input ADC supports a 10-bit range mapped into a 1.0 V
analog voltage range. Gain correction takes place after the
digitization in the form of a digital multiplier.
There are separate gain control units for luma and chroma data.
Both can operate independently of each other. The chroma unit,
however, can also take its gain value from the luma path.
Advantages of this architecture over the commonly used
programmable gain amplifier (PGA) before the ADC include
the fact that the gain is now completely independent of supply,
temperature, and process variations.
Rev. A | Page 41 of 104
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
The possible AGC modes are shown in Table 51.
Table 51. AGC Modes
Input Video Type
Any
CVBS
Luma Gain
Manual gain luma
Dependent on
horizontal sync depth
Peak white
Y/C
Dependent on
horizontal sync depth
Peak white
YPrPb
Dependent on
horizontal sync depth
Chroma Gain
Manual gain chroma
Dependent on colorburst amplitude
taken from luma path
Dependent on colorburst amplitude
taken from luma path
Dependent on colorburst amplitude
taken from luma path
Dependent on colorburst amplitude
Taken from luma path
It is possible to freeze the automatic gain control loops. This causes
the loops to stop updating and the AGC determined gain at the
time of the freeze to stay active until the loop is either unfrozen
or the gain mode of operation is changed.
The currently active gain from any of the modes can be read
back. Refer to the description of the dual-function manual gain
registers, LG[11:0] luma gain and CG[11:0] chroma gain, in the
Luma Gain section and Chroma Gain section, respectively.
ANALOG VOLTAGE RANGE SUPPORTED BY ADC
(1V RANGE FOR ADV7182)
MAXIMUM
VOLTAGE
VIDEO PROCESSOR
(GAIN SELECTION ONLY)
ADC
DATA PREPROCESSOR
(DPP)
GAIN
CONTROL
MINIMUM
VOLTAGE
CLAMP
LEVEL
Figure 33. Gain Control Overview
Rev. A | Page 42 of 104
11935-032
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ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
UG-637
Luma Gain
LAGC[2:0], Luma Automatic Gain Control,
Address 0x2C[6:4]
LG[11:0], Luma Gain, Address 0x2F[3:0], Address 0x30[7:0]
The luma automatic gain control mode bits select the operating
mode for the gain control in the luma path.
Luma gain[11:0] is a dual-function register. If all of these bits
are written to, a desired manual luma gain can be programmed.
This gain becomes active if the LAGC[2:0] mode is switched to
manual fixed gain. Equation 1 shows how to calculate a desired
gain.
LMG[11:0], Luma Manual Gain, Address 0x2F[3:0],
Address 0x30[7:0]
The peak white algorithm is used to detect if the input video
amplitude exceeds the ADC input range of the ADV728x. If this
is so, then the ADV728x reduces its internal luma gain to
prevent the signal from becoming saturated.
Table 52. LAGC Function
LAGC[2:0]
000
001
010 (default)
011
100
101
110
111
Description
Manual fixed gain (use LMG[11:0])
AGC (blank level to sync tip), peak white algorithm off
AGC (blank level to sync tip), peak white algorithm on
Reserved
Reserved
Reserved
Reserved
Freeze gain
LAGT[1:0], Luma Automatic Gain Timing,
Address 0x2F[7:6]
•
•
Luma manual gain value (LAGC[2:0] set to luma manual
gain mode)
Luma automatic gain value (LAGC[2:0] set to either of the
automatic modes)
Table 54. LG/LMG Function
LG[11:0]/LMG[11:0]
LMG[11:0] = x
LG[11:0] = x
Luma Gain ≅
The luma automatic gain timing register allows the user to
influence the tracking speed of the luminance automatic gain
control. This register has an effect only if the LAGC[2:0] register
is set to 001 or 010 (automatic gain control modes).
If peak white AGC is enabled and active (see the Status 1[7:0],
Address 0x10[7:0] section), the actual gain update speed is dictated
by the peak white AGC loop and, as a result, the LAGT settings
have no effect. As soon as the part leaves peak white AGC, LAGT
becomes relevant again.
The update speed for the peak white algorithm can be customized
by the use of internal parameters.
Description
Slow (time constant = 2 sec)
Medium (time constant = 1 sec)
Fast (time constant = 0.2 sec)
Adaptive
Read/Write
Write
Read
Description
Manual gain for luma path
Actual used gain
LMG[11 : 0]
Luma Calibration Factor
(1)
where LMG[11:0] is a decimal value between 1024 and 4095.
Calculation of the Luma Calibration Factor
1.
2.
3.
4.
Table 53. LAGT Function
LAGT[1:0]
00
01
10
11 (default)
If read back, this register returns the current gain value.
Depending on the setting in the LAGC[2:0] bits, the value is
one of the following:
Using a video source, set the content to a gray field and
apply a standard CVBS signal to the CVBS input of
the board.
Using an oscilloscope, measure the signal at the CVBS input
to ensure that its sync depth, color burst, and luma are at
the standard levels.
Connect the output of the ADV728x to a backend system
that has unity gain and monitor the output voltage.
Measure the luma level correctly from the black level. Turn
off the luma AGC and manually change the value of the luma
manual gain control register, LMG[11:0], until the output
luma level matches the input measured in Step 2.
This value, in decimal, is the luma calibration factor.
PW_UPD, Peak White Update, Address 0x2B[0]
The peak white and average video algorithms determine the
gain based on measurements taken from the active video. The
PW_UPD bit determines the rate of gain change. LAGC[2:0] must
be set to the appropriate mode to enable the peak white or average
video mode in the first place. For more information, see the
LAGC[2:0], Luma Automatic Gain Control, Address 0x2C[6:4]
section.
Setting PW_UPD to 0 updates the gain once per video line.
Setting PW_UPD to 1 (default) updates the gain once per field.
Chroma Gain
CAGC[1:0], Chroma Automatic Gain Control,
Address 0x2C[1:0]
The two bits of the color automatic gain control mode select the
basic mode of operation for the automatic gain control in the
chroma path.
Table 55. CAGC Function
CAGC[1:0]
00
01
10 (default)
11
Rev. A | Page 43 of 104
Description
Manual fixed gain (use CMG[11:0])
Use luma gain for chroma
Automatic gain (based on color burst)
Freeze chroma gain
UG-637
ADV7280/ADV7281/ADV7282/ADV7283 Hardware Reference Manual
CAGT[1:0], Chroma Automatic Gain Timing,
Address 0x2D[7:6]
CKE, Color Kill Enable, Address 0x2B[6]
The color kill enable bit allows the optional color kill function
to be switched on or off.
The chroma automatic gain timing register allows the user to
influence the tracking speed of the chroma automatic gain
control. This register has an effect only if the CAGC[1:0] bits
are set to 10 (automatic gain).
For QAM-based video standards (PAL and NTSC), as well as
FM-based systems (SECAM), the threshold for the color kill
decision is selectable via the CKILLTHR[2:0] bits.
If color kill is enabled and the color carrier of the incoming
video signal is less than the threshold for 128 consecutive video
lines, color processing is switched off (black and white output).
To switch the color processing back on, another 128 consecutive
lines with a color burst greater than the threshold are required.
Table 56. CAGT Function
CAGT[1:0]
00
01
10
11 (default)
Description
Slow (time constant = 2 sec)
Medium (time constant = 1 sec)
Reserved
Adaptive
The color kill option works only for input signals with a modulated
chroma part. For component input (YPrPb), there is no color kill.
CG[11:0], Chroma Gain, Address 0x2D[3:0],
Address 0x2E[7:0];
CMG[11:0], Chroma Manual Gain, Address 0x2D[3:0],
Address 0x2E[7:0]
Set CKE to 0 to disable color kill.
Set CKE to 1 (default) to enable color kill.
CKILLTHR[2:0], Color Kill Threshold, Address 0x3D[6:4]
Chroma gain[11:0] is a dual-function register. If written to, a
desired manual chroma gain can be programmed. This gain
becomes active if the CAGC[1:0] function is switched to manual
fixed gain. See Equation 2 for calculating a desired gain.
The CKILLTHR[2:0] bits allow the user to select a threshold for
the color kill function. The threshold applies only to QAM-based
(NTSC and PAL) or FM-modulated (SECAM) video standards.
If read back, this register returns the current gain value. Depending
on the setting in the CAGC[1:0] bits, this is either:
•
•
The chroma manual gain value (CAGC[1:0] set to chroma
manual gain mode).
The chroma automatic gain value (CAGC[1:0] set to either
of the automatic modes).
Table 57. CG/CMG Function
CG[11:0]/CMG[11:0]
CMG[11:0]
CG[11:0]
Chroma_Gain ≅
Read/Write
Write
Read
Description
Manual gain for chroma path
Currently active gain
CMG[11 : 0]decimal
ChromaCalibrationFactor
(2)
where ChromaCalibrationFactor is a decimal value between 0
and 4095.
To enable the color kill function, the CKE bit must be set. For the
000, 001, 010, and 011 settings, chroma demodulation inside
the ADV728x may not work satisfactorily for poor input video
signals.
Table 58. CKILLTHR Function
CKILLTHR[2:0]
000
001
010 (default)
011
100
101
110
111
Description
NTSC, PAL
SECAM
Kill at